From 095677dfa38209f79c8541a5129d75b268faf337 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 11 Feb 2013 15:20:38 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5152
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/SPC56ELxx/hal_lld.c |  8 ++++--
 os/hal/platforms/SPC56ELxx/hal_lld.h | 53 +++++++++++++++++++++++++++++++++---
 2 files changed, 54 insertions(+), 7 deletions(-)

(limited to 'os/hal')

diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c
index a6bf31dc8..f3ba51399 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.c
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.c
@@ -127,9 +127,11 @@ void spc_early_init(void) {
   CGM.OSC_CTL.B.OSCBYP = TRUE;
 #endif /* SPC5_OSC_BYPASS */
 
-  /* Enable clocks to all peripherals: */
-/*  CGM.SC_DC0.R = 0x80;
-  CGM.AC0_DC0_3.R = 0x80808080;
+  /* Setting the various dividers and source selectors.*/
+  CGM.SC_SS.R  = SPC5_CGM_SC_SS;
+  CGM.SC_DC0.R = SPC5_CGM_SC_DC0;
+
+  /*CGM.AC0_DC0_3.R = 0x80808080;
   CGM.AC1_DC0_3.R = 0x80808080;
   CGM.AC2_DC0_3.R = 0x85808080;
   CGM.AC0_SC.R = 0x04000000;
diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.h b/os/hal/platforms/SPC56ELxx/hal_lld.h
index 3bb2a652d..f616d4827 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.h
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.h
@@ -122,6 +122,18 @@
 #define SPC5_FMPLL_ODF_DIV16        (3U << 24)
 /** @} */
 
+/**
+ * @name    Clock selectors used in the various GCM SC registers
+ * @{
+ */
+#define SPC5_CGM_SS_MASK            (15U << 24)
+#define SPC5_CGM_SS_IRC             (0U << 24)
+#define SPC5_CGM_SS_XOSC            (2U << 24)
+#define SPC5_CGM_SS_FMPLL0          (4U << 24)
+#define SPC5_CGM_SS_FMPLL1          (5U << 24)
+#define SPC5_CGM_SS_FMPLL1_DIV6     (8U << 24)
+/** @} */
+
 /**
  * @name    ME_GS register bits definitions
  * @{
@@ -291,6 +303,21 @@
 #define SPC5_FMPLL1_ODF             SPC5_FMPLL_ODF_DIV4
 #endif
 
+/**
+ * @brief   System clock source.
+ */
+#if !defined(SPC5_SYSCLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_SYSCLK_SRC             SPC5_CGM_SS_FMPLL0
+#endif
+
+/**
+ * @brief   System clock divider value.
+ * @note    Zero means disabled clock.
+ */
+#if !defined(SPC5_SYSCLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_SYSCLK_DIVIDER_VALUE   1
+#endif
+
 /**
  * @brief   Active run modes in ME_ME register.
  * @note    Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
@@ -668,13 +695,13 @@
 
 /* Check on SPC5_FMPLL1_ODF.*/
 #if (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV2)
-#define SPC5_FMPLL1_ODF_VALUE    2
+#define SPC5_FMPLL1_ODF_VALUE   2
 #elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV4)
-#define SPC5_FMPLL1_ODF_VALUE    4
+#define SPC5_FMPLL1_ODF_VALUE   4
 #elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV8)
-#define SPC5_FMPLL1_ODF_VALUE    8
+#define SPC5_FMPLL1_ODF_VALUE   8
 #elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV16)
-#define SPC5_FMPLL1_ODF_VALUE    16
+#define SPC5_FMPLL1_ODF_VALUE   16
 #else
 #error "invalid SPC5_FMPLL1_ODF value specified"
 #endif
@@ -702,6 +729,24 @@
 #error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
 #endif
 
+/* Check on the system clock selector settings.*/
+#if (SPC5_SYSCLK_SRC == SPC5_CGM_SS_IRC) ||                                 \
+    (SPC5_SYSCLK_SRC == SPC5_CGM_SS_XOSC) ||                                \
+    (SPC5_SYSCLK_SRC == SPC5_CGM_SS_FMPLL0)
+#define SPC5_CGM_SC_SS          SPC5_SYSCLK_SRC
+#else
+#error "invalid SPC5_SYSCLK_SRC value specified"
+#endif
+
+/* Check on the system divider settings.*/
+#if SPC5_SYSCLK_DIVIDER_VALUE == 0
+#define SPC5_CGM_SC_DC0         0
+#elif (SPC5_SYSCLK_DIVIDER_VALUE >= 1) && (SPC5_SYSCLK_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_SC_DC0         (0x80 | (SPC5_SYSCLK_DIVIDER_VALUE - 1))
+#else
+#error "invalid SPC5_SYSCLK_DIVIDER_VALUE value specified"
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
-- 
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