From d25139221ec71ed2fbd6a9e06aa3c039c6cf9551 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Mon, 21 Sep 2015 11:01:37 +0000 Subject: Fixed bug #609. Updated STM32F1xx headers. STM32F1xx, STM32F3xx and STM32F37x now use the common DMAv1 driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8319 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 37 +- os/hal/ports/STM32/STM32F0xx/platform.mk | 4 +- os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c | 13 +- os/hal/ports/STM32/STM32F1xx/hal_lld.h | 24 +- os/hal/ports/STM32/STM32F1xx/platform.mk | 5 +- os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk | 5 +- os/hal/ports/STM32/STM32F1xx/stm32_dma.c | 502 --------------------- os/hal/ports/STM32/STM32F1xx/stm32_dma.h | 406 ----------------- os/hal/ports/STM32/STM32F1xx/stm32_registry.h | 338 +++++++------- os/hal/ports/STM32/STM32F37x/platform.mk | 5 +- os/hal/ports/STM32/STM32F37x/stm32_dma.c | 449 ------------------ os/hal/ports/STM32/STM32F37x/stm32_dma.h | 406 ----------------- os/hal/ports/STM32/STM32F37x/stm32_registry.h | 62 ++- os/hal/ports/STM32/STM32F3xx/platform.mk | 5 +- os/hal/ports/STM32/STM32F3xx/stm32_dma.c | 453 ------------------- os/hal/ports/STM32/STM32F3xx/stm32_dma.h | 406 ----------------- os/hal/ports/STM32/STM32F3xx/stm32_registry.h | 220 ++++++++- 17 files changed, 487 insertions(+), 2853 deletions(-) delete mode 100644 os/hal/ports/STM32/STM32F1xx/stm32_dma.c delete mode 100644 os/hal/ports/STM32/STM32F1xx/stm32_dma.h delete mode 100644 os/hal/ports/STM32/STM32F37x/stm32_dma.c delete mode 100644 os/hal/ports/STM32/STM32F37x/stm32_dma.h delete mode 100644 os/hal/ports/STM32/STM32F3xx/stm32_dma.c delete mode 100644 os/hal/ports/STM32/STM32F3xx/stm32_dma.h (limited to 'os/hal/ports') diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c index 4f4daf04b..42b0001ce 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c @@ -70,6 +70,11 @@ #define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER #endif +#if defined(STM32_DMA2_CH45_NUMBER) +#define STM32_DMA2_CH4_NUMBER STM32_DMA2_CH45_NUMBER +#define STM32_DMA2_CH5_NUMBER STM32_DMA2_CH45_NUMBER +#endif + #if STM32_DMA_SUPPORTS_CSELR == TRUE #define ADDR_DMA1_CSELR &DMA1_CSELR->CSELR #define ADDR_DMA2_CSELR &DMA2_CSELR->CSELR @@ -103,8 +108,13 @@ #define DMA2_CH1_CMASK 0x00000080U #define DMA2_CH2_CMASK 0x00000100U #define DMA2_CH3_CMASK 0x00000200U +#if !defined(STM32_DMA2_CH45_NUMBER) #define DMA2_CH4_CMASK 0x00000400U #define DMA2_CH5_CMASK 0x00000800U +#else +#define DMA2_CH4_CMASK 0x00000C00U +#define DMA2_CH5_CMASK 0x00000C00U +#endif /*===========================================================================*/ /* Driver exported variables. */ @@ -254,7 +264,6 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) { } #endif /*!defined(STM32_DMA1_CH23_HANDLER) */ - /* Channels 4, 5, 6 and 7 are shared on some devices.*/ #if defined(STM32_DMA1_CH4567_HANDLER) /** @@ -438,6 +447,31 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) { OSAL_IRQ_EPILOGUE(); } +/* Channels 4 and 5 are shared on some devices.*/ +#if defined(STM32_DMA2_CH45_HANDLER) +/** + * @brief DMA2 streams 4 and 5 shared interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) { + uint32_t flags; + + OSAL_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA2->IFCR = flags << 12; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->IFCR = flags << 16; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + OSAL_IRQ_EPILOGUE(); +} +#else /* !defined(STM32_DMA2_CH45_HANDLER) */ /** * @brief DMA2 stream 4 shared interrupt handler. * @@ -473,6 +507,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) { OSAL_IRQ_EPILOGUE(); } +#endif /* defined(STM32_DMA2_CH45_HANDLER) */ #endif /* STM32_DMA2_NUM_CHANNELS > 0 */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk index 88eb3766e..2cbeab8cf 100644 --- a/os/hal/ports/STM32/STM32F0xx/platform.mk +++ b/os/hal/ports/STM32/STM32F0xx/platform.mk @@ -4,7 +4,6 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) @@ -17,7 +16,8 @@ ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c diff --git a/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c index ded663b36..61444218d 100644 --- a/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c +++ b/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c @@ -265,8 +265,7 @@ OSAL_IRQ_HANDLER(Vector138) { OSAL_IRQ_EPILOGUE(); } -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) +#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) #else /* Other STM32F1xx devices.*/ /** @@ -307,13 +306,12 @@ void ext_lld_exti_irq_enable(void) { nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(RTCAlarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); #if defined(STM32F10X_CL) /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) +#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) /* EXTI vectors specific to STM32F1xx Value Line.*/ #else /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ @@ -336,13 +334,12 @@ void ext_lld_exti_irq_disable(void) { nvicDisableVector(EXTI9_5_IRQn); nvicDisableVector(EXTI15_10_IRQn); nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTCAlarm_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); #if defined(STM32F10X_CL) /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ nvicDisableVector(OTG_FS_WKUP_IRQn); nvicDisableVector(ETH_WKUP_IRQn); -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) +#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) /* EXTI vectors specific to STM32F1xx Value Line.*/ #else /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.h b/os/hal/ports/STM32/STM32F1xx/hal_lld.h index 41ffdf862..34e83b366 100644 --- a/os/hal/ports/STM32/STM32F1xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.h @@ -24,14 +24,15 @@ * - STM32_HSE_BYPASS (optionally). * . * One of the following macros must also be defined: - * - STM32F10X_LD_VL for Value Line Low Density devices. - * - STM32F10X_MD_VL for Value Line Medium Density devices. - * - STM32F10X_HD_VL for Value Line High Density devices. - * - STM32F10X_LD for Performance Low Density devices. - * - STM32F10X_MD for Performance Medium Density devices. - * - STM32F10X_HD for Performance High Density devices. - * - STM32F10X_XL for Performance eXtra Density devices. - * - STM32F10X_CL for Connectivity Line devices. + * - STM32F100xB for Value Line Medium Density devices. + * - STM32F100xE for Value Line High Density devices. + * - STM32F101x6, STM32F102x6, STM32F103x6 for Performance + * Low Density devices. + * - STM32F101xB, STM32F102xB, STM32F103xB for Performance + * Medium Density devices. + * - STM32F101xE, STM32F103xE for Performance High Density devices. + * - STM32F101xG, STM32F103xG for Performance eXtra Density devices. + * - STM32F105xC, STM32F107xC for Connectivity Line devices. * . * * @addtogroup HAL @@ -54,9 +55,6 @@ #if defined(__DOXYGEN__) #define PLATFORM_NAME "STM32F1xx" -#elif defined(STM32F10X_LD_VL) -#define PLATFORM_NAME "STM32F100 Value Line Low Density" - #elif defined(STM32F10X_MD_VL) #define PLATFORM_NAME "STM32F100 Value Line Medium Density" @@ -179,8 +177,8 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) || defined(__DOXYGEN__) +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) || \ + defined(__DOXYGEN__) #include "hal_lld_f100.h" #elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ diff --git a/os/hal/ports/STM32/STM32F1xx/platform.mk b/os/hal/ports/STM32/STM32F1xx/platform.mk index eba585447..b5fc474db 100644 --- a/os/hal/ports/STM32/STM32F1xx/platform.mk +++ b/os/hal/ports/STM32/STM32F1xx/platform.mk @@ -3,8 +3,8 @@ ifeq ($(USE_SMART_BUILD),yes) HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/adc_lld.c @@ -54,12 +54,12 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/adc_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \ @@ -80,6 +80,7 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx \ $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1 \ diff --git a/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk b/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk index 446179a3a..ddf8a2156 100644 --- a/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk +++ b/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk @@ -3,8 +3,8 @@ ifeq ($(USE_SMART_BUILD),yes) HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/adc_lld.c @@ -57,12 +57,12 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/adc_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \ @@ -83,6 +83,7 @@ endif PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1 \ diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_dma.c b/os/hal/ports/STM32/STM32F1xx/stm32_dma.c deleted file mode 100644 index fe2413d92..000000000 --- a/os/hal/ports/STM32/STM32F1xx/stm32_dma.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/stm32_dma.c - * @brief DMA helper driver code. - * - * @addtogroup STM32F1xx_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * ISRs when allocating streams. - * @{ - */ - -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK 0x0000007F - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK 0x00000F80 - -/** - * @brief Post-reset value of the stream CCR register. - */ -#define STM32_DMA_CCR_RESET_VALUE 0x00000000 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, - {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, - {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, - {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, - {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, - {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, - {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) - {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, - {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, - {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, -#if defined(STM32F10X_CL) || defined(__DOXYGEN__) - {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, - {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, -#else /* !STM32F10X_CL */ - {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn}, - {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn}, -#endif /* !STM32F10X_CL */ -#endif /* STM32_HAS_DMA2 */ -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ - void *dma_param; /**< @brief DMA callback parameter. */ -} dma_isr_redir_t; - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/** - * @brief DMA IRQ redirectors. - */ -static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 stream 1 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector6C) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 0; - if (dma_isr_redir[0].dma_func) - dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 2 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector70) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 4; - if (dma_isr_redir[1].dma_func) - dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 3 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector74) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 8; - if (dma_isr_redir[2].dma_func) - dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 4 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector78) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 12; - if (dma_isr_redir[3].dma_func) - dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 5 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector7C) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 16; - if (dma_isr_redir[4].dma_func) - dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 6 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector80) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 20; - if (dma_isr_redir[5].dma_func) - dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 7 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector84) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 24; - if (dma_isr_redir[6].dma_func) - dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 1 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector120) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 0; - if (dma_isr_redir[7].dma_func) - dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 2 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector124) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 4; - if (dma_isr_redir[8].dma_func) - dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 3 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector128) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 8; - if (dma_isr_redir[9].dma_func) - dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -#if defined(STM32F10X_CL) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 4 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector12C) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 12; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 5 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector130) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 16; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} -#else /* !STM32F10X_CL */ -/** - * @brief DMA2 streams 4 and 5 shared interrupt handler. - * @note This IRQ is shared between DMA2 channels 4 and 5 so it is a - * bit less efficient because an extra check. - * - * @isr - */ -OSAL_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - /* Check on channel 4.*/ - flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA2->IFCR = flags << 12; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - } - - /* Check on channel 5.*/ - flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA2->IFCR = flags << 16; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - } - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !STM32F10X_CL */ -#endif /* STM32_HAS_DMA2 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dma_streams_mask = 0; - for (i = 0; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].channel->CCR = 0; - dma_isr_redir[i].dma_func = NULL; - } - DMA1->IFCR = 0xFFFFFFFF; -#if STM32_HAS_DMA2 - DMA2->IFCR = 0xFFFFFFFF; -#endif -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval FALSE no error, stream taken. - * @retval TRUE error, stream already taken. - * - * @special - */ -bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - osalDbgCheck(dmastp != NULL); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) - return TRUE; - - /* Marks the stream as allocated.*/ - dma_isr_redir[dmastp->selfindex].dma_func = func; - dma_isr_redir[dmastp->selfindex].dma_param = param; - dma_streams_mask |= (1 << dmastp->selfindex); - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) - rccEnableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) - rccEnableDMA2(FALSE); -#endif - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; - - /* Enables the associated IRQ vector if a callback is defined.*/ - if (func != NULL) - nvicEnableVector(dmastp->vector, priority); - - return FALSE; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - osalDbgCheck(dmastp != NULL); - - /* Check if the streams is not taken.*/ - osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "not allocated"); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1 << dmastp->selfindex); - - /* Disables the associated IRQ vector.*/ -#if !(STM32_HAS_DMA2 && !defined(STM32F10X_CL)) - nvicDisableVector(dmastp->vector); -#else - /* Check unless it is 10 or 11 stream. If yes, make additional check before - disabling IRQ.*/ - if (dmastp->selfindex < 10) - nvicDisableVector(dmastp->vector); - else { - if ((dma_streams_mask & (3 << 10)) == 0) - nvicDisableVector(dmastp->vector); - } -#endif /* STM32_HAS_DMA2 && !STM32F10X_CL */ - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) - rccDisableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) - rccDisableDMA2(FALSE); -#endif -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_dma.h b/os/hal/ports/STM32/STM32F1xx/stm32_dma.h deleted file mode 100644 index 028604da1..000000000 --- a/os/hal/ports/STM32/STM32F1xx/stm32_dma.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/stm32_dma.h - * @brief DMA helper driver header. - * @note This file requires definitions from the ST header file stm32f10x.h. - * @note This driver uses the new naming convention used for the STM32F2xx - * so the "DMA channels" are referred as "DMA streams". - * - * @addtogroup STM32F1xx_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Total number of DMA streams. - * @note This is the total number of streams among all the DMA units. - */ -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -#define STM32_DMA_STREAMS 12 -#else -#define STM32_DMA_STREAMS 7 -#endif - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x0F - -/** - * @brief Returns the channel associated to the specified stream. - * - * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) - * @param[in] c a stream/channel association word, one channel per - * nibble, not associated channels must be set to 0xF - * @return Always zero, in this platform there is no dynamic - * association between streams and channels. - */ -#define STM32_DMA_GETCHANNEL(n, c) 0 - -/** - * @brief Checks if a DMA priority is within the valid range. - * @param[in] prio DMA priority - * - * @retval The check result. - * @retval FALSE invalid DMA priority. - * @retval TRUE correct DMA priority. - */ -#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) - -/** - * @brief Returns an unique numeric identifier for a DMA stream. - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return An unique numeric stream identifier. - */ -#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) - -/** - * @brief Returns a DMA stream identifier mask. - * - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return A DMA stream identifier mask. - */ -#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ - (1 << STM32_DMA_STREAM_ID(dma, stream)) - -/** - * @brief Checks if a DMA stream unique identifier belongs to a mask. - * @param[in] id the stream numeric identifier - * @param[in] mask the stream numeric identifiers mask - * - * @retval The check result. - * @retval FALSE id does not belong to the mask. - * @retval TRUE id belongs to the mask. - */ -#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) - -/** - * @name DMA streams identifiers - * @{ - */ -/** - * @brief Returns a pointer to a stm32_dma_stream_t structure. - * - * @param[in] id the stream numeric identifier - * @return A pointer to the stm32_dma_stream_t constant structure - * associated to the DMA stream. - */ -#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) - -#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) -#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) -#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) -#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) -#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) -#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) -#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) -#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) -#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) -#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) -#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) -#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) -/** @} */ - -/** - * @name CR register constants common to all DMA types - * @{ - */ -#define STM32_DMA_CR_EN DMA_CCR1_EN -#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE -#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE -#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE -#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) -#define STM32_DMA_CR_DIR_P2M 0 -#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR -#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM -#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC -#define STM32_DMA_CR_PINC DMA_CCR1_PINC -#define STM32_DMA_CR_MINC DMA_CCR1_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0 -#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0 -#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 -#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ - STM32_DMA_CR_MSIZE_MASK) -#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL -#define STM32_DMA_CR_PL(n) ((n) << 12) -/** @} */ - -/** - * @name CR register constants only found in enhanced DMA - * @{ - */ -#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - * @{ - */ -#define STM32_DMA_ISR_FEIF 0 -#define STM32_DMA_ISR_DMEIF 0 -#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 -#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 -#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ - volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ - uint8_t ishift; /**< @brief Bits offset in xIFCR - register. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the ISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CPAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->channel->CPAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CMAR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->channel->CMAR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->channel->CNDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register - * - * @special - */ -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->channel->CCR = (uint32_t)(mode); \ -} - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmastp) { \ - (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @details The function disables the specified stream and then clears any - * pending interrupt. - * @note This function can be invoked in both ISR or thread context. - * @note Interrupts enabling flags are set to zero after this call, see - * bug 3607518. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ - dmaStreamClearInterrupt(dmastp); \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ -} - -/** - * @brief Starts a memory to memory operation using the specified stream. - * @note The default transfer data mode is "byte to byte" but it can be - * changed by specifying extra options in the @p mode parameter. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value - * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN - * . - * @param[in] src source address - * @param[in] dst destination address - * @param[in] n number of data units to copy - */ -#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamSetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ -} - -/** - * @brief Polled wait for DMA transfer end. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaWaitCompletion(dmastp) { \ - while ((dmastp)->channel->CNDTR > 0) \ - ; \ - dmaStreamDisable(dmastp); \ -} - -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h index 62a792e66..b8fbd815a 100644 --- a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h @@ -25,178 +25,34 @@ #ifndef _STM32_REGISTRY_H_ #define _STM32_REGISTRY_H_ -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ +#if defined(STM32F100xB) +#define STM32F10X_MD_VL -#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -/** - * @name STM32F100 LD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE +#elif defined(STM32F100xE) +#define STM32F10X_HD_VL -#define STM32_HAS_SDADC1 FALSE -#define STM32_HAS_SDADC2 FALSE -#define STM32_HAS_SDADC3 FALSE +#elif defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) +#define STM32F10X_LD -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 +#elif defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) +#define STM32F10X_MD -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#elif defined(STM32F101xE) || defined(STM32F103xE) +#define STM32F10X_HD -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) - -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE +#elif defined(STM32F101xG) || defined(STM32F103xG) +#define STM32F10X_XL -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 18 -#define STM32_EXTI_IMR_MASK 0x00000000U +#elif defined(STM32F105xC) || defined(STM32F107xC) +#define STM32F10X_CL -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) - -#define STM32_HAS_I2C2 FALSE -#define STM32_HAS_I2C3 FALSE -#define STM32_HAS_I2C4 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_IS_CALENDAR FALSE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) - -#define STM32_HAS_SPI2 FALSE -#define STM32_HAS_SPI3 FALSE -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 4 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 +#else +#error "unsupported or unrecognized STM32F1xx member" +#endif -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS FALSE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - -#define STM32_HAS_TIM15 TRUE -#define STM32_TIM15_IS_32BITS FALSE -#define STM32_TIM15_CHANNELS 2 - -#define STM32_HAS_TIM16 TRUE -#define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 - -#define STM32_HAS_TIM17 TRUE -#define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 - -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM20 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) - -#define STM32_HAS_USART2 TRUE -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) - -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_USART6 FALSE -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE FALSE -/** @} */ -#endif /* defined(STM32F10X_LD_VL) */ +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ #if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__) /** @@ -230,8 +86,25 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -407,8 +280,25 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -557,8 +447,25 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -726,8 +633,33 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH45_HANDLER Vector12C +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH45_NUMBER 59 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -931,8 +863,35 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -1136,8 +1095,35 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH TRUE diff --git a/os/hal/ports/STM32/STM32F37x/platform.mk b/os/hal/ports/STM32/STM32F37x/platform.mk index 8fc7c2854..c25aa2aff 100644 --- a/os/hal/ports/STM32/STM32F37x/platform.mk +++ b/os/hal/ports/STM32/STM32F37x/platform.mk @@ -3,8 +3,8 @@ ifeq ($(USE_SMART_BUILD),yes) HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/adc_lld.c @@ -51,12 +51,12 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/adc_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \ @@ -76,6 +76,7 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ $(CHIBIOS)/os/hal/ports/STM32/STM32F37x \ $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2 \ diff --git a/os/hal/ports/STM32/STM32F37x/stm32_dma.c b/os/hal/ports/STM32/STM32F37x/stm32_dma.c deleted file mode 100644 index dd273f599..000000000 --- a/os/hal/ports/STM32/STM32F37x/stm32_dma.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F37x/stm32_dma.c - * @brief DMA helper driver code. - * - * @addtogroup STM32F37x_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * ISRs when allocating streams. - * @{ - */ - -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK 0x0000007F - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK 0x00000F80 - -/** - * @brief Post-reset value of the stream CCR register. - */ -#define STM32_DMA_CCR_RESET_VALUE 0x00000000 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, - {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, - {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, - {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, - {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, - {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, - {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, - {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, - {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, - {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, - {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, - {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ - void *dma_param; /**< @brief DMA callback parameter. */ -} dma_isr_redir_t; - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/** - * @brief DMA IRQ redirectors. - */ -static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 stream 1 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector6C) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 0; - if (dma_isr_redir[0].dma_func) - dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 2 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector70) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 4; - if (dma_isr_redir[1].dma_func) - dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 3 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector74) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 8; - if (dma_isr_redir[2].dma_func) - dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 4 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector78) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 12; - if (dma_isr_redir[3].dma_func) - dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 5 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector7C) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 16; - if (dma_isr_redir[4].dma_func) - dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 6 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector80) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 20; - if (dma_isr_redir[5].dma_func) - dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 7 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector84) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 24; - if (dma_isr_redir[6].dma_func) - dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 1 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector120) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 0; - if (dma_isr_redir[7].dma_func) - dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 2 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector124) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 4; - if (dma_isr_redir[8].dma_func) - dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 3 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector128) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 8; - if (dma_isr_redir[9].dma_func) - dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 4 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector12C) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 12; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 5 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector130) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 16; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dma_streams_mask = 0; - for (i = 0; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].channel->CCR = 0; - dma_isr_redir[i].dma_func = NULL; - } - DMA1->IFCR = 0xFFFFFFFF; -#if STM32_HAS_DMA2 - DMA2->IFCR = 0xFFFFFFFF; -#endif -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval FALSE no error, stream taken. - * @retval TRUE error, stream already taken. - * - * @special - */ -bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - osalDbgCheck(dmastp != NULL); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) - return TRUE; - - /* Marks the stream as allocated.*/ - dma_isr_redir[dmastp->selfindex].dma_func = func; - dma_isr_redir[dmastp->selfindex].dma_param = param; - dma_streams_mask |= (1 << dmastp->selfindex); - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) - rccEnableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) - rccEnableDMA2(FALSE); -#endif - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; - - /* Enables the associated IRQ vector if a callback is defined.*/ - if (func != NULL) - nvicEnableVector(dmastp->vector, priority); - - return FALSE; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - osalDbgCheck(dmastp != NULL); - - /* Check if the streams is not taken.*/ - osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "not allocated"); - - /* Disables the associated IRQ vector.*/ - nvicDisableVector(dmastp->vector); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1 << dmastp->selfindex); - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) - rccDisableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) - rccDisableDMA2(FALSE); -#endif -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/stm32_dma.h b/os/hal/ports/STM32/STM32F37x/stm32_dma.h deleted file mode 100644 index d38938e74..000000000 --- a/os/hal/ports/STM32/STM32F37x/stm32_dma.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F37x/stm32_dma.h - * @brief DMA helper driver header. - * @note This file requires definitions from the ST header file stm32f30x.h. - * @note This driver uses the new naming convention used for the STM32F2xx - * so the "DMA channels" are referred as "DMA streams". - * - * @addtogroup STM32F37x_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Total number of DMA streams. - * @note This is the total number of streams among all the DMA units. - */ -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -#define STM32_DMA_STREAMS 12 -#else -#define STM32_DMA_STREAMS 7 -#endif - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x0F - -/** - * @brief Returns the channel associated to the specified stream. - * - * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) - * @param[in] c a stream/channel association word, one channel per - * nibble, not associated channels must be set to 0xF - * @return Always zero, in this platform there is no dynamic - * association between streams and channels. - */ -#define STM32_DMA_GETCHANNEL(n, c) 0 - -/** - * @brief Checks if a DMA priority is within the valid range. - * @param[in] prio DMA priority - * - * @retval The check result. - * @retval FALSE invalid DMA priority. - * @retval TRUE correct DMA priority. - */ -#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) - -/** - * @brief Returns an unique numeric identifier for a DMA stream. - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return An unique numeric stream identifier. - */ -#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) - -/** - * @brief Returns a DMA stream identifier mask. - * - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return A DMA stream identifier mask. - */ -#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ - (1 << STM32_DMA_STREAM_ID(dma, stream)) - -/** - * @brief Checks if a DMA stream unique identifier belongs to a mask. - * @param[in] id the stream numeric identifier - * @param[in] mask the stream numeric identifiers mask - * - * @retval The check result. - * @retval FALSE id does not belong to the mask. - * @retval TRUE id belongs to the mask. - */ -#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) - -/** - * @name DMA streams identifiers - * @{ - */ -/** - * @brief Returns a pointer to a stm32_dma_stream_t structure. - * - * @param[in] id the stream numeric identifier - * @return A pointer to the stm32_dma_stream_t constant structure - * associated to the DMA stream. - */ -#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) - -#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) -#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) -#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) -#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) -#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) -#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) -#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) -#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) -#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) -#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) -#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) -#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) -/** @} */ - -/** - * @name CR register constants common to all DMA types - * @{ - */ -#define STM32_DMA_CR_EN DMA_CCR_EN -#define STM32_DMA_CR_TEIE DMA_CCR_TEIE -#define STM32_DMA_CR_HTIE DMA_CCR_HTIE -#define STM32_DMA_CR_TCIE DMA_CCR_TCIE -#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM) -#define STM32_DMA_CR_DIR_P2M 0 -#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR -#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM -#define STM32_DMA_CR_CIRC DMA_CCR_CIRC -#define STM32_DMA_CR_PINC DMA_CCR_PINC -#define STM32_DMA_CR_MINC DMA_CCR_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0 -#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0 -#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1 -#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ - STM32_DMA_CR_MSIZE_MASK) -#define STM32_DMA_CR_PL_MASK DMA_CCR_PL -#define STM32_DMA_CR_PL(n) ((n) << 12) -/** @} */ - -/** - * @name CR register constants only found in enhanced DMA - * @{ - */ -#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - * @{ - */ -#define STM32_DMA_ISR_FEIF 0 -#define STM32_DMA_ISR_DMEIF 0 -#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 -#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 -#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ - volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ - uint8_t ishift; /**< @brief Bits offset in xIFCR - register. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the ISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CPAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->channel->CPAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CMAR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->channel->CMAR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->channel->CNDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register - * - * @special - */ -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->channel->CCR = (uint32_t)(mode); \ -} - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmastp) { \ - (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @details The function disables the specified stream and then clears any - * pending interrupt. - * @note This function can be invoked in both ISR or thread context. - * @note Interrupts enabling flags are set to zero after this call, see - * bug 3607518. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ - dmaStreamClearInterrupt(dmastp); \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ -} - -/** - * @brief Starts a memory to memory operation using the specified stream. - * @note The default transfer data mode is "byte to byte" but it can be - * changed by specifying extra options in the @p mode parameter. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value - * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN - * . - * @param[in] src source address - * @param[in] dst destination address - * @param[in] n number of data units to copy - */ -#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamSetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ -} - -/** - * @brief Polled wait for DMA transfer end. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaWaitCompletion(dmastp) { \ - while ((dmastp)->channel->CNDTR > 0) \ - ; \ - dmaStreamDisable(dmastp); \ -} - -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/stm32_registry.h b/os/hal/ports/STM32/STM32F37x/stm32_registry.h index be68d5497..1729f0909 100644 --- a/os/hal/ports/STM32/STM32F37x/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F37x/stm32_registry.h @@ -66,8 +66,35 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -276,8 +303,35 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk index 0f0837cab..78fbaaa4c 100644 --- a/os/hal/ports/STM32/STM32F3xx/platform.mk +++ b/os/hal/ports/STM32/STM32F3xx/platform.mk @@ -3,8 +3,8 @@ ifeq ($(USE_SMART_BUILD),yes) HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/adc_lld.c @@ -51,12 +51,12 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/adc_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \ @@ -76,6 +76,7 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx \ $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2 \ diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_dma.c b/os/hal/ports/STM32/STM32F3xx/stm32_dma.c deleted file mode 100644 index 26acf869f..000000000 --- a/os/hal/ports/STM32/STM32F3xx/stm32_dma.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F3xx/stm32_dma.c - * @brief DMA helper driver code. - * - * @addtogroup STM32F3xx_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * ISRs when allocating streams. - * @{ - */ - -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK 0x0000007F - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK 0x00000F80 - -/** - * @brief Post-reset value of the stream CCR register. - */ -#define STM32_DMA_CCR_RESET_VALUE 0x00000000 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, - {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, - {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, - {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, - {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, - {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, - {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, -#if STM32_HAS_DMA2 == TRUE - {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, - {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, - {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, - {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, - {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, -#endif -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ - void *dma_param; /**< @brief DMA callback parameter. */ -} dma_isr_redir_t; - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/** - * @brief DMA IRQ redirectors. - */ -static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 stream 1 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector6C) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 0; - if (dma_isr_redir[0].dma_func) - dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 2 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector70) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 4; - if (dma_isr_redir[1].dma_func) - dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 3 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector74) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 8; - if (dma_isr_redir[2].dma_func) - dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 4 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector78) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 12; - if (dma_isr_redir[3].dma_func) - dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 5 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector7C) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 16; - if (dma_isr_redir[4].dma_func) - dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 6 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector80) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 20; - if (dma_isr_redir[5].dma_func) - dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 7 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector84) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; - DMA1->IFCR = flags << 24; - if (dma_isr_redir[6].dma_func) - dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -#if (STM32_HAS_DMA2 == TRUE) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 1 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector120) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 0; - if (dma_isr_redir[7].dma_func) - dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 2 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector124) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 4; - if (dma_isr_redir[8].dma_func) - dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 3 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector128) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 8; - if (dma_isr_redir[9].dma_func) - dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 4 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector12C) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 12; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 5 shared interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector130) { - uint32_t flags; - - OSAL_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA2->IFCR = flags << 16; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_HAS_DMA2 == TRUE */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dma_streams_mask = 0; - for (i = 0; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].channel->CCR = 0; - dma_isr_redir[i].dma_func = NULL; - } - DMA1->IFCR = 0xFFFFFFFF; -#if STM32_HAS_DMA2 - DMA2->IFCR = 0xFFFFFFFF; -#endif -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval FALSE no error, stream taken. - * @retval TRUE error, stream already taken. - * - * @special - */ -bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - osalDbgCheck(dmastp != NULL); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) - return TRUE; - - /* Marks the stream as allocated.*/ - dma_isr_redir[dmastp->selfindex].dma_func = func; - dma_isr_redir[dmastp->selfindex].dma_param = param; - dma_streams_mask |= (1 << dmastp->selfindex); - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) - rccEnableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) - rccEnableDMA2(FALSE); -#endif - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; - - /* Enables the associated IRQ vector if a callback is defined.*/ - if (func != NULL) - nvicEnableVector(dmastp->vector, priority); - - return FALSE; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - osalDbgCheck(dmastp != NULL); - - /* Check if the streams is not taken.*/ - osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "not allocated"); - - /* Disables the associated IRQ vector.*/ - nvicDisableVector(dmastp->vector); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1 << dmastp->selfindex); - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) - rccDisableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) - rccDisableDMA2(FALSE); -#endif -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_dma.h b/os/hal/ports/STM32/STM32F3xx/stm32_dma.h deleted file mode 100644 index 3c50bcf92..000000000 --- a/os/hal/ports/STM32/STM32F3xx/stm32_dma.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F3xx/stm32_dma.h - * @brief DMA helper driver header. - * @note This file requires definitions from the ST header file stm32f30x.h. - * @note This driver uses the new naming convention used for the STM32F2xx - * so the "DMA channels" are referred as "DMA streams". - * - * @addtogroup STM32F3xx_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Total number of DMA streams. - * @note This is the total number of streams among all the DMA units. - */ -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -#define STM32_DMA_STREAMS 12 -#else -#define STM32_DMA_STREAMS 7 -#endif - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x0F - -/** - * @brief Returns the channel associated to the specified stream. - * - * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) - * @param[in] c a stream/channel association word, one channel per - * nibble, not associated channels must be set to 0xF - * @return Always zero, in this platform there is no dynamic - * association between streams and channels. - */ -#define STM32_DMA_GETCHANNEL(n, c) 0 - -/** - * @brief Checks if a DMA priority is within the valid range. - * @param[in] prio DMA priority - * - * @retval The check result. - * @retval FALSE invalid DMA priority. - * @retval TRUE correct DMA priority. - */ -#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3)) - -/** - * @brief Returns an unique numeric identifier for a DMA stream. - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return An unique numeric stream identifier. - */ -#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) - -/** - * @brief Returns a DMA stream identifier mask. - * - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return A DMA stream identifier mask. - */ -#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ - (1 << STM32_DMA_STREAM_ID(dma, stream)) - -/** - * @brief Checks if a DMA stream unique identifier belongs to a mask. - * @param[in] id the stream numeric identifier - * @param[in] mask the stream numeric identifiers mask - * - * @retval The check result. - * @retval FALSE id does not belong to the mask. - * @retval TRUE id belongs to the mask. - */ -#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) - -/** - * @name DMA streams identifiers - * @{ - */ -/** - * @brief Returns a pointer to a stm32_dma_stream_t structure. - * - * @param[in] id the stream numeric identifier - * @return A pointer to the stm32_dma_stream_t constant structure - * associated to the DMA stream. - */ -#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) - -#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) -#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) -#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) -#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) -#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) -#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) -#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) -#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) -#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) -#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) -#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) -#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) -/** @} */ - -/** - * @name CR register constants common to all DMA types - * @{ - */ -#define STM32_DMA_CR_EN DMA_CCR_EN -#define STM32_DMA_CR_TEIE DMA_CCR_TEIE -#define STM32_DMA_CR_HTIE DMA_CCR_HTIE -#define STM32_DMA_CR_TCIE DMA_CCR_TCIE -#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM) -#define STM32_DMA_CR_DIR_P2M 0 -#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR -#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM -#define STM32_DMA_CR_CIRC DMA_CCR_CIRC -#define STM32_DMA_CR_PINC DMA_CCR_PINC -#define STM32_DMA_CR_MINC DMA_CCR_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0 -#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0 -#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1 -#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ - STM32_DMA_CR_MSIZE_MASK) -#define STM32_DMA_CR_PL_MASK DMA_CCR_PL -#define STM32_DMA_CR_PL(n) ((n) << 12) -/** @} */ - -/** - * @name CR register constants only found in enhanced DMA - * @{ - */ -#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - * @{ - */ -#define STM32_DMA_ISR_FEIF 0 -#define STM32_DMA_ISR_DMEIF 0 -#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 -#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 -#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ - volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ - uint8_t ishift; /**< @brief Bits offset in xIFCR - register. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the ISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Macro Functions - * @{ - */ -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CPAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->channel->CPAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CMAR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->channel->CMAR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->channel->CNDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register - * - * @special - */ -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->channel->CCR = (uint32_t)(mode); \ -} - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmastp) { \ - (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @details The function disables the specified stream and then clears any - * pending interrupt. - * @note This function can be invoked in both ISR or thread context. - * @note Interrupts enabling flags are set to zero after this call, see - * bug 3607518. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ - dmaStreamClearInterrupt(dmastp); \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ -} - -/** - * @brief Starts a memory to memory operation using the specified stream. - * @note The default transfer data mode is "byte to byte" but it can be - * changed by specifying extra options in the @p mode parameter. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value - * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN - * . - * @param[in] src source address - * @param[in] dst destination address - * @param[in] n number of data units to copy - */ -#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamSetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ -} - -/** - * @brief Polled wait for DMA transfer end. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaWaitCompletion(dmastp) { \ - while ((dmastp)->channel->CNDTR > 0) \ - ; \ - dmaStreamDisable(dmastp); \ -} - -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h index 585a3728e..95906090f 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h @@ -69,11 +69,37 @@ #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE - /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -272,8 +298,25 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -449,8 +492,25 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -626,8 +686,25 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -806,8 +883,35 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -997,8 +1101,25 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -1177,8 +1298,25 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -1353,8 +1491,35 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -1548,8 +1713,25 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 0 /* ETH attributes.*/ #define STM32_HAS_ETH FALSE -- cgit v1.2.3