From 354bd66eb083691cab4c2c29b32a836805ac5edc Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 16 Nov 2010 18:39:47 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2371
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM8L/hal_lld.h | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

(limited to 'os/hal/platforms/STM8L/hal_lld.h')

diff --git a/os/hal/platforms/STM8L/hal_lld.h b/os/hal/platforms/STM8L/hal_lld.h
index 1df041782..2e21988e7 100644
--- a/os/hal/platforms/STM8L/hal_lld.h
+++ b/os/hal/platforms/STM8L/hal_lld.h
@@ -42,9 +42,7 @@
 
 #undef FALSE
 #undef TRUE
-
 #include "stm8l15x.h"
-
 #define FALSE 0
 #define TRUE (!FALSE)
 
@@ -217,7 +215,10 @@
 #error "requested LSE clock is not enabled"
 #endif
 
-#if STM8L_NO_CLOCK_INIT
+/**
+ * @brief   System clock.
+ */
+#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__)
 #define SYSCLK                      (HSICLK / 8)
 #elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI
 #define SYSCLK                      (HSICLK / (1 << STM8L_SYSCLK_DIVIDER))
@@ -231,7 +232,10 @@
 #error "specified invalid SYSCLK source"
 #endif
 
-#if STM8L_NO_CLOCK_INIT
+/**
+ * @brief   RTC clock.
+ */
+#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__)
 #define RTCCLK                      0
 #elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI
 #define RTCCLK                      (HSICLK / (1 << STM8L_RTCCLK_DIVIDER))
@@ -245,6 +249,12 @@
 #error "specified invalid RTCCLK source"
 #endif
 
+/**
+ * @brief   CPU clock.
+ * @details On the STM8L the CPU clock is always equal to the system clock.
+ */
+#define CPUCLK                      SYSCLK
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
-- 
cgit v1.2.3