From 792c06e58554c5ed4cb84e69fe4f6d9add173ec0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 12 Jun 2011 14:22:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3042 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.h | 499 +++++++++++++++++++++++++++++++++++ 1 file changed, 499 insertions(+) create mode 100644 os/hal/platforms/STM32L1xx/hal_lld.h (limited to 'os/hal/platforms/STM32L1xx/hal_lld.h') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h new file mode 100644 index 000000000..4559d7fb8 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -0,0 +1,499 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32L1xx/hal_lld.h + * @brief STM32L1xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_HSECLK. + * . + * One of the following macros must also be defined: + * - STM32L1XX_MD for Ultra Low Power Medium-density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/* Tricks required to make the TRUE/FALSE declaration inside the library + compatible.*/ +#undef FALSE +#undef TRUE +#include "stm32l1xx.h" +#define FALSE 0 +#define TRUE (!FALSE) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "STM32L Ultra Low Power Medium Density" + +#define STM32_HSICLK 16000000 /**< High speed internal clock. */ +#define STM32_LSICLK 38000 /**< Low speed internal clock. */ + +/* PWR_CR register bits definitions.*/ +#define STM32_VOS_1P2 (1 << 11) /**< Core voltage 1.2 Volts. */ +#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ +#define STM32_VOS_1P8 (3 << 11) /**< Core voltage 1.8 Volts. */ + +/* RCC_CFGR register bits definitions.*/ +#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */ +#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ + +#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCO_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCO_HSI (2 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCO_MSI (3 << 24) /**< MSI clock on MCO pin. */ +#define STM32_MCO_HSE (4 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCO_PLL (5 << 24) /**< PLL clock on MCO pin. */ +#define STM32_MCO_LSI (6 << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCO_LSE (7 << 24) /**< LSE clock on MCO pin. */ + +/* RCC_ICSCR register bits definitions.*/ +#define STM32_MSIRANGE_64K (0 << 13) /* 64KHz nominal. */ +#define STM32_MSIRANGE_128K (1 << 13) /* 128KHz nominal. */ +#define STM32_MSIRANGE_256K (2 << 13) /* 256KHz nominal. */ +#define STM32_MSIRANGE_512K (3 << 13) /* 512KHz nominal. */ +#define STM32_MSIRANGE_1M (4 << 13) /* 1MHz nominal. */ +#define STM32_MSIRANGE_2M (5 << 13) /* 2MHz nominal. */ +#define STM32_MSIRANGE_4M (6 << 13) /* 4MHz nominal. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Core voltage selection. + * @note This setting affects all the performance and clock related + * settings, the maximum performance is only obtainable selecting + * the maximum voltage. + */ +#if !defined(STM32_VOS) || defined(__DOXYGEN__) +#define STM32_VOS STM32_VOS_1P8 +#endif + +/** + * @brief MSI frequency setting. + */ +#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__) +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSI +#endif + +/** + * @brief PLL multiplier value. + * @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLMUL_VALUE 6 +#endif + +/** + * @brief PLL divider value. + * @note The allowed values are 2, 3, 4. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_DIVMUL_VALUE) || defined(__DOXYGEN__) +#define STM32_DIVMUL_VALUE 3 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#endif + +/** + * @brief MCO pin setting. + */ +#if !defined(STM32_MCO) || defined(__DOXYGEN__) +#define STM32_MCO STM32_MCO_NOCLOCK +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Voltage related limits.*/ +#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__) +/** + * @brief Maximum HSECLK at current voltage setting. + */ +#define STM32_HSECLK_MAX 32000000 + +/** + * @brief Maximum SYSCLK at current voltage setting. + */ +#define STM32_SYSCLK_MAX 32000000 + +/** + * @brief Maximum PLLCLKOUT at current voltage setting. + */ +#define STM32_PLLCLKOUT_MAX 96000000 + +/** + * @brief Maximum frequency not requiring a wait state for flash accesses. + */ +#define STM32_0WS_THRESHOLD 16000000 + +/** + * @brief HSI availability at current voltage settings. + */ +#define STM32_HSI_AVAILABLE TRUE + +#elif STM32_VOS == STM32_VOS_1P5 +#define STM32_HSECLK_MAX 16000000 +#define STM32_SYSCLK_MAX 16000000 +#define STM32_PLLCLKOUT_MAX 48000000 +#define STM32_0WS_THRESHOLD 8000000 +#define STM32_HSI_AVAILABLE TRUE +#elif STM32_VOS == STM32_VOS_1P2 +#define STM32_HSECLK_MAX 4000000 +#define STM32_SYSCLK_MAX 4000000 +#define STM32_PLLCLKOUT_MAX 24000000 +#define STM32_0WS_THRESHOLD 2000000 +#define STM32_HSI_AVAILABLE FALSE +#else +#error "invalid STM32_VOS value specified" +#endif + +#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)" +#endif + +#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000) +#error "STM32_LSECLK outside acceptable range (1...1000KHz)" +#endif + +/** + * @brief PLLMUL field. + */ +#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__) +#define STM32_PLLMUL (0 << 18) +#elif STM32_PLLMUL_VALUE == 4 +#define STM32_PLLMUL (1 << 18) +#elif STM32_PLLMUL_VALUE == 6 +#define STM32_PLLMUL (2 << 18) +#elif STM32_PLLMUL_VALUE == 8 +#define STM32_PLLMUL (3 << 18) +#elif STM32_PLLMUL_VALUE == 12 +#define STM32_PLLMUL (4 << 18) +#elif STM32_PLLMUL_VALUE == 16 +#define STM32_PLLMUL (5 << 18) +#elif STM32_PLLMUL_VALUE == 24 +#define STM32_PLLMUL (6 << 18) +#elif STM32_PLLMUL_VALUE == 32 +#define STM32_PLLMUL (7 << 18) +#elif STM32_PLLMUL_VALUE == 48 +#define STM32_PLLMUL (8 << 18) +#else +#error "invalid STM32_PLLMUL_VALUE value specified" +#endif + +/** + * @brief PLLDIV field. + */ +#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLDIV (1 << 22) +#elif STM32_PLLDIV_VALUE == 3 +#define STM32_PLLDIV (2 << 22) +#elif STM32_PLLDIV_VALUE == 4 +#define STM32_PLLDIV (3 << 22) +#else +#error "invalid STM32_PLLDIV_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN STM32_HSECLK +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +/* Verifies the HSI clock availability if the PLL used and requires HSI as + input.*/ +#if !STM32_HSI_AVAILABLE && (STM32_SW == STM32_SW_PLL) +#error "HSI clock not available in low voltage mode (1.2V)." +#endif +#define STM32_PLLCLKIN STM32_HSICLK +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000) +#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLVCO < 6000000) || (STM32_PLLVCO > 96000000) +#error "STM32_PLLVCO outside acceptable range (6...96MHz)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000) +#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)" +#endif + +/** + * @brief System clock source. + */ +#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_PLLCLKOUT +#elif (STM32_SW == STM32_SW_MSI) +#define STM32_SYSCLK STM32_MSICLK +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#else +#error "invalid STM32_SYSCLK_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK2 > STM32_SYSCLK_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_SYSCLK_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief ADC frequency. + */ +#define STM32_ADCCLK STM32_HSICLK + +/** + * @brief USB frequency. + */ +#define STM32_USBCLK (STM32_PLLVCO / 2) + +/** + * @brief Timers 2, 3, 4, 6, 7 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 9, 10, 11 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_FLASHBITS1 0x00000000 +#else +#define STM32_FLASHBITS1 0x00000004 +#define STM32_FLASHBITS2 0x00000003 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 DMA support code.*/ +#include "stm32_dma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ -- cgit v1.2.3 From d0dfc3715ad662443a73c83687396639e087ac05 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 14 Jun 2011 15:09:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3044 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.h | 300 +++++++++++++++++++++++++++++++---- 1 file changed, 271 insertions(+), 29 deletions(-) (limited to 'os/hal/platforms/STM32L1xx/hal_lld.h') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 4559d7fb8..e2e2fb925 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -58,10 +58,17 @@ #define STM32_LSICLK 38000 /**< Low speed internal clock. */ /* PWR_CR register bits definitions.*/ +#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */ #define STM32_VOS_1P2 (1 << 11) /**< Core voltage 1.2 Volts. */ #define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ #define STM32_VOS_1P8 (3 << 11) /**< Core voltage 1.8 Volts. */ +#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */ +#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */ +#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */ +#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */ +#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */ + /* RCC_CFGR register bits definitions.*/ #define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */ #define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */ @@ -93,28 +100,49 @@ #define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ #define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ -#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ -#define STM32_MCO_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */ -#define STM32_MCO_HSI (2 << 24) /**< HSI clock on MCO pin. */ -#define STM32_MCO_MSI (3 << 24) /**< MSI clock on MCO pin. */ -#define STM32_MCO_HSE (4 << 24) /**< HSE clock on MCO pin. */ -#define STM32_MCO_PLL (5 << 24) /**< PLL clock on MCO pin. */ -#define STM32_MCO_LSI (6 << 24) /**< LSI clock on MCO pin. */ -#define STM32_MCO_LSE (7 << 24) /**< LSE clock on MCO pin. */ +#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ +#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */ +#define STM32_MCOSEL_HSI (2 << 24) /**< HSI clock on MCO pin. */ +#define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */ +#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */ +#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */ +#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */ +#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */ + +#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 1. */ +#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 1. */ /* RCC_ICSCR register bits definitions.*/ -#define STM32_MSIRANGE_64K (0 << 13) /* 64KHz nominal. */ -#define STM32_MSIRANGE_128K (1 << 13) /* 128KHz nominal. */ -#define STM32_MSIRANGE_256K (2 << 13) /* 256KHz nominal. */ -#define STM32_MSIRANGE_512K (3 << 13) /* 512KHz nominal. */ -#define STM32_MSIRANGE_1M (4 << 13) /* 1MHz nominal. */ -#define STM32_MSIRANGE_2M (5 << 13) /* 2MHz nominal. */ -#define STM32_MSIRANGE_4M (6 << 13) /* 4MHz nominal. */ +#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */ +#define STM32_MSIRANGE_64K (0 << 13) /**< 64KHz nominal. */ +#define STM32_MSIRANGE_128K (1 << 13) /**< 128KHz nominal. */ +#define STM32_MSIRANGE_256K (2 << 13) /**< 256KHz nominal. */ +#define STM32_MSIRANGE_512K (3 << 13) /**< 512KHz nominal. */ +#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */ +#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */ +#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */ + +/* RCC_CSR register bits definitions.*/ +#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */ +#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */ +#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */ +#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + /** * @brief Core voltage selection. * @note This setting affects all the performance and clock related @@ -125,6 +153,48 @@ #define STM32_VOS STM32_VOS_1P8 #endif +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief ADC clock setting. + */ +#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_ADC_CLOCK_ENABLED TRUE +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_USB_CLOCK_ENABLED TRUE +#endif + /** * @brief MSI frequency setting. */ @@ -170,8 +240,8 @@ * @note The default value is calculated for a 32MHz system clock from * the internal 16MHz HSI clock. */ -#if !defined(STM32_DIVMUL_VALUE) || defined(__DOXYGEN__) -#define STM32_DIVMUL_VALUE 3 +#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLDIV_VALUE 3 #endif /** @@ -198,10 +268,31 @@ #endif /** - * @brief MCO pin setting. + * @brief MCO clock source. */ -#if !defined(STM32_MCO) || defined(__DOXYGEN__) -#define STM32_MCO STM32_MCO_NOCLOCK +#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__) +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#endif + +/** + * @brief MCO divider setting. + */ +#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__) +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#endif + +/** + * @brief Clock source for the RTC/LCD. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSE +#endif + +/** + * @brief HSE divider toward RTC setting. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCPRE STM32_RTCPRE_DIV2 #endif /*===========================================================================*/ @@ -251,13 +342,77 @@ #error "invalid STM32_VOS value specified" #endif +/* HSI related checks.*/ +#if STM32_HSI_ENABLED +#if !STM32_HSI_AVAILABLE + #error "impossible to activate HSI under the current voltage settings" +#endif +#else /* !STM32_HSI_ENABLED */ +#if STM32_ADC_CLOCK_ENABLED || \ + (STM32_SW == STM32_SW_HSI) || \ + ((STM32_SW == STM32_SW_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) || \ + (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "required HSI clock is not enabled" +#endif +#endif /* !STM32_HSI_ENABLED */ + +/* HSE related checks.*/ +#if STM32_HSE_ENABLED +#if STM32_HSECLK == 0 +#error "impossible to activate HSE" +#endif #if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX) #error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)" #endif +#else /* !#if STM32_HSE_ENABLED */ +#if (STM32_SW == STM32_SW_HSE) || \ + ((STM32_SW == STM32_SW_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM_RTC_SOURCE == STM32_RTCSEL_HSEDIV) +#error "required HSE clock is not enabled" +#endif +#endif /* !#if STM32_HSE_ENABLED */ + +/* LSI related checks.*/ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ +#if STM_RTCCLK == STM32_LSICLK +#error "required LSI clock is not enabled" +#endif +#endif /* !STM32_LSI_ENABLED */ +/* LSE related checks.*/ +#if STM32_LSE_ENABLED +#if (STM32_LSECLK == 0) +#error "impossible to activate LSE" +#endif #if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000) #error "STM32_LSECLK outside acceptable range (1...1000KHz)" #endif +#else /* !#if STM32_LSE_ENABLED */ +#if STM_RTCCLK == STM32_LSECLK +#error "required LSE clock is not enabled" +#endif +#endif /* !#if STM32_LSE_ENABLED */ + +/* PLL related checks.*/ +#if STM32_USB_CLOCK_ENABLED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif /** * @brief PLLMUL field. @@ -303,11 +458,6 @@ #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) #define STM32_PLLCLKIN STM32_HSECLK #elif STM32_PLLSRC == STM32_PLLSRC_HSI -/* Verifies the HSI clock availability if the PLL used and requires HSI as - input.*/ -#if !STM32_HSI_AVAILABLE && (STM32_SW == STM32_SW_PLL) -#error "HSI clock not available in low voltage mode (1.2V)." -#endif #define STM32_PLLCLKIN STM32_HSICLK #else #error "invalid STM32_PLLSRC value specified" @@ -338,19 +488,43 @@ #error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)" #endif +/** + * @brief MSI frequency. + * @note Values are taken from the STM8Lxx datasheet. + */ +#if STM32_MSIRANGE == STM32_MSIRANGE_64K +#define STM32_MSICLK 65500 +#elif STM32_MSIRANGE == STM32_MSIRANGE_128K +#define STM32_MSICLK 131000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_256K +#define STM32_MSICLK 262000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_512K +#define STM32_MSICLK 524000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_1M +#define STM32_MSICLK 1050000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_2M +#define STM32_MSICLK 2100000 +#elif STM32_MSIRANGE == STM32_MSIRANGE_4M +#define STM32_MSICLK 4200000 +#else +#error "invalid STM32_MSIRANGE value specified" +#endif + /** * @brief System clock source. */ -#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) -#define STM32_SYSCLK STM32_PLLCLKOUT +#if STM32_NO_INIT || defined(__DOXYGEN__) +#define STM32_SYSCLK 2100000 #elif (STM32_SW == STM32_SW_MSI) #define STM32_SYSCLK STM32_MSICLK #elif (STM32_SW == STM32_SW_HSI) #define STM32_SYSCLK STM32_HSICLK #elif (STM32_SW == STM32_SW_HSE) #define STM32_SYSCLK STM32_HSECLK +#elif (STM32_SW == STM32_SW_PLL) +#define STM32_SYSCLK STM32_PLLCLKOUT #else -#error "invalid STM32_SYSCLK_SW value specified" +#error "invalid STM32_SW value specified" #endif /* Check on the system clock.*/ @@ -432,6 +606,74 @@ #error "STM32_PCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)" #endif +/** + * @brief MCO divider clock. + */ +#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM_MCODIVCLK 0 +#elif STM32_MCOSEL == STM32_MCOSEL_HSI +#define STM_MCODIVCLK STM32_HSICLK +#elif STM32_MCOSEL == STM32_MCOSEL_MSI +#define STM_MCODIVCLK STM32_MSICLK +#elif STM32_MCOSEL == STM32_MCOSEL_HSE +#define STM_MCODIVCLK STM32_HSECLK +#elif STM32_MCOSEL == STM32_MCOSEL_PLL +#define STM_MCODIVCLK STM32_PLLCLKOUT +#elif STM32_MCOSEL == STM32_MCOSEL_LSI +#define STM_MCODIVCLK STM32_LSICLK +#elif STM32_MCOSEL == STM32_MCOSEL_LSE +#define STM_MCODIVCLK STM32_LSECLK +#else +#error "invalid STM32_MCOSEL value specified" +#endif + +/** + * @brief MCO output pin clock. + */ +#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__) +#define STM_MCOCLK STM_MCODIVCLK +#elif STM32_MCOPRE == STM32_MCOPRE_DIV2 +#define STM_MCOCLK (STM_MCODIVCLK / 2) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV4 +#define STM_MCOCLK (STM_MCODIVCLK / 4) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV8 +#define STM_MCOCLK (STM_MCODIVCLK / 8) +#elif STM32_MCOPRE == STM32_MCOPRE_DIV16 +#define STM_MCOCLK (STM_MCODIVCLK / 16) +#else +#error "invalid STM32_MCOPRE value specified" +#endif + +/** + * @brief HSE divider toward RTC clock. + */ +#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (HSECLK / 2) +#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (HSECLK / 4) +#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (HSECLK / 8) +#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (HSECLK / 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief RTC/LCD clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM_RTCCLK 0 +#elif STM32_RTCSEL == STM32_RTCSEL_LSE +#define STM_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM_RTCCLK STM32_HSEDIVCLK +#else +#error "invalid STM32_RTCSEL value specified" +#endif + /** * @brief ADC frequency. */ @@ -467,7 +709,7 @@ #define STM32_FLASHBITS1 0x00000000 #else #define STM32_FLASHBITS1 0x00000004 -#define STM32_FLASHBITS2 0x00000003 +#define STM32_FLASHBITS2 0x00000007 #endif /*===========================================================================*/ -- cgit v1.2.3 From ec3ca5b4e615639dd3b4650eaa8d5739b78a1cbc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Jun 2011 10:45:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3061 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.h | 1 + 1 file changed, 1 insertion(+) (limited to 'os/hal/platforms/STM32L1xx/hal_lld.h') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index e2e2fb925..5e451409d 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -63,6 +63,7 @@ #define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ #define STM32_VOS_1P8 (3 << 11) /**< Core voltage 1.8 Volts. */ +/* RCC_CR register bits definitions.*/ #define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */ #define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */ #define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */ -- cgit v1.2.3 From 45765c3f7671d99cccab31ceea52e300b07d2ecd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Jun 2011 11:35:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3062 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'os/hal/platforms/STM32L1xx/hal_lld.h') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 5e451409d..37dff216e 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -59,9 +59,9 @@ /* PWR_CR register bits definitions.*/ #define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */ -#define STM32_VOS_1P2 (1 << 11) /**< Core voltage 1.2 Volts. */ +#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */ #define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ -#define STM32_VOS_1P8 (3 << 11) /**< Core voltage 1.8 Volts. */ +#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */ /* RCC_CR register bits definitions.*/ #define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */ -- cgit v1.2.3 From c4c18450fffdfcc1e39a753d373d65e43c708117 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Jun 2011 14:41:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3063 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.h | 62 ++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'os/hal/platforms/STM32L1xx/hal_lld.h') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 37dff216e..ca69ac784 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -133,6 +133,68 @@ #define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */ #define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */ +/* STM32L1xx capabilities.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE + +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE + +#define STM32_HAS_DAC TRUE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +#define STM32_HAS_ETH FALSE + +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH TRUE + +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE + +#define STM32_HAS_RTC TRUE + +#define STM32_HAS_SDIO FALSE + +#define STM32_HAS_SPI1 TRUE +#define STM32_HAS_SPI2 TRUE +#define STM32_HAS_SPI3 FALSE + +#define STM32_HAS_TIM1 FALSE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART3 FALSE +#define STM32_HAS_UART4 FALSE + +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ -- cgit v1.2.3