From 792c06e58554c5ed4cb84e69fe4f6d9add173ec0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 12 Jun 2011 14:22:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3042 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.c | 97 ++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 os/hal/platforms/STM32L1xx/hal_lld.c (limited to 'os/hal/platforms/STM32L1xx/hal_lld.c') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c new file mode 100644 index 000000000..956ad9fcc --- /dev/null +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -0,0 +1,97 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32L1xx/hal_lld.c + * @brief STM32L1xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#define AIRCR_VECTKEY 0x05FA0000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ + RCC->APB1RSTR = 0xFFFFFFFF; + RCC->APB2RSTR = 0xFFFFFFFF; + RCC->APB1RSTR = 0; + RCC->APB2RSTR = 0; + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif +} + +/** + * @brief STM32L1xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function must be invoked only after the system reset. + * + * @special + */ +#if defined(STM32L1XX_MD) || defined(__DOXYGEN__) +/* + * Clocks initialization for the LD, MD and HD sub-families. + */ +void stm32_clock_init(void) { + +} +#else +void stm32_clock_init(void) {} +#endif + +/** @} */ -- cgit v1.2.3 From d0dfc3715ad662443a73c83687396639e087ac05 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 14 Jun 2011 15:09:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3044 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.c | 83 ++++++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 4 deletions(-) (limited to 'os/hal/platforms/STM32L1xx/hal_lld.c') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c index 956ad9fcc..8f6027865 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.c +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -77,18 +77,93 @@ void hal_lld_init(void) { } /** - * @brief STM32L1xx clocks and PLL initialization. + * @brief STM32L1xx voltage, clocks and PLL initialization. * @note All the involved constants come from the file @p board.h. - * @note This function must be invoked only after the system reset. + * @note This function should be invoked just after the system reset. * * @special */ #if defined(STM32L1XX_MD) || defined(__DOXYGEN__) -/* - * Clocks initialization for the LD, MD and HD sub-families. +/** + * @brief Clocks and internal voltage initialization. */ void stm32_clock_init(void) { +#if !STM32_NO_INIT + /* Core voltage setup.*/ + while ((PWR->CSR & PWR_CSR_VOSF) != 0) + ; /* Waits until regulator is stable. */ + PWR->CR = STM32_VOS; + while ((PWR->CSR & PWR_CSR_VOSF) != 0) + ; /* Waits until regulator is stable. */ + + /* Initial clocks setup and wait for MSI stabilization, the MSI clock is + always enabled because it is the fallback clock when PLL the fails. + Trim fields are not altered from reset values.*/ + RCC->CFGR = 0; + RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE; + RCC->CSR = RCC_CSR_RMVF; + RCC->CR = RCC_CR_MSION; + while ((RCC->CR & RCC_CR_MSIRDY) == 0) + ; /* Waits until MSI is stable. */ + +#if STM32_HSI_ENABLED + /* HSI activation.*/ + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0) + ; /* Waits until HSI is stable. */ +#endif + +#if STM32_HSE_ENABLED + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while ((RCC->CR & RCC_CR_HSERDY) == 0) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_LSE_ENABLED + /* LSE activation.*/ + RCC->CSR |= RCC_CSR_LSEON; + while ((RCC->CSR & RCC_CSR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + + /* Other clock-related settings (dividers, MCO etc).*/ + RCC->CR |= STM32_RTCPRE; + RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL | + STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + RCC->CSR |= STM32_RTCSEL; + + /* Flash setup and final clock selection. */ +#if defined(STM32_FLASHBITS1) + FLASH->ACR = STM32_FLASHBITS1; +#endif +#if defined(STM32_FLASHBITS2) + FLASH->ACR = STM32_FLASHBITS2; +#endif + + /* Switching to the configured clock source if it is different from MSI.*/ +#if (STM32_SW != STM32_SW_MSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* STM32_NO_INIT */ } #else void stm32_clock_init(void) {} -- cgit v1.2.3 From ec3ca5b4e615639dd3b4650eaa8d5739b78a1cbc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Jun 2011 10:45:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3061 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'os/hal/platforms/STM32L1xx/hal_lld.c') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c index 8f6027865..c9d8a3914 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.c +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -59,10 +59,10 @@ void hal_lld_init(void) { /* Reset of all peripherals.*/ - RCC->APB1RSTR = 0xFFFFFFFF; - RCC->APB2RSTR = 0xFFFFFFFF; - RCC->APB1RSTR = 0; - RCC->APB2RSTR = 0; +// RCC->APB1RSTR = 0xFFFFFFFF; +// RCC->APB2RSTR = 0xFFFFFFFF; +// RCC->APB1RSTR = 0; +// RCC->APB2RSTR = 0; /* SysTick initialization using the system clock.*/ SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; @@ -129,8 +129,12 @@ void stm32_clock_init(void) { #endif #if STM32_LSE_ENABLED - /* LSE activation.*/ - RCC->CSR |= RCC_CSR_LSEON; + /* LSE activation, have to unlock the register.*/ + if ((RCC->CSR & RCC_CSR_LSEON) == 0) { + PWR->CR |= PWR_CR_DBP; + RCC->CSR |= RCC_CSR_LSEON; + PWR->CR &= ~PWR_CR_DBP; + } while ((RCC->CSR & RCC_CSR_LSERDY) == 0) ; /* Waits until LSE is stable. */ #endif -- cgit v1.2.3 From 45765c3f7671d99cccab31ceea52e300b07d2ecd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Jun 2011 11:35:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3062 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'os/hal/platforms/STM32L1xx/hal_lld.c') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c index c9d8a3914..9a8265365 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.c +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -90,6 +90,9 @@ void hal_lld_init(void) { void stm32_clock_init(void) { #if !STM32_NO_INIT + /* PWR clock enable.*/ + RCC->APB1ENR = RCC_APB1ENR_PWREN; + /* Core voltage setup.*/ while ((PWR->CSR & PWR_CSR_VOSF) != 0) ; /* Waits until regulator is stable. */ -- cgit v1.2.3