From c4a3d44d53f667cc73abf655542b2974a9b0bb93 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 17 May 2012 18:44:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4205 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 91 ---------------------------------- os/hal/platforms/STM32F0xx/hal_lld.h | 21 ++++---- os/hal/platforms/STM32F0xx/platform.mk | 5 ++ os/hal/platforms/STM32F0xx/stm32f0xx.h | 3 +- 4 files changed, 18 insertions(+), 102 deletions(-) create mode 100644 os/hal/platforms/STM32F0xx/platform.mk (limited to 'os/hal/platforms/STM32F0xx') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 806ec3ea3..24dc11f5c 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -132,13 +132,6 @@ void hal_lld_init(void) { * * @special */ -#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) || \ - defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ - defined(__DOXYGEN__) -/* - * Clocks initialization for all sub-families except CL. - */ void stm32_clock_init(void) { #if !STM32_NO_INIT @@ -198,88 +191,4 @@ void stm32_clock_init(void) { #endif /* !STM32_NO_INIT */ } -#elif defined(STM32F10X_CL) -/* - * Clocks initialization for the CL sub-family. - */ -void stm32_clock_init(void) { - -#if !STM32_NO_INIT - /* HSI setup.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - RCC->CFGR = 0; - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Wait until HSI is the source.*/ - -#if STM32_HSE_ENABLED -#if defined(STM32_HSE_BYPASS) - /* HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEBYP; -#endif - /* HSE activation.*/ - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR & RCC_CR_HSERDY)) - ; /* Waits until HSE is stable. */ -#endif - -#if STM32_LSI_ENABLED - /* LSI activation.*/ - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) - ; /* Waits until LSI is stable. */ -#endif - - /* Settings of various dividers and multipliers in CFGR2.*/ - RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 | - STM32_PREDIV1 | STM32_PREDIV1SRC; - - /* PLL2 setup, if activated.*/ -#if STM32_ACTIVATE_PLL2 - RCC->CR |= RCC_CR_PLL2ON; - while (!(RCC->CR & RCC_CR_PLL2RDY)) - ; /* Waits until PLL2 is stable. */ -#endif - - /* PLL3 setup, if activated.*/ -#if STM32_ACTIVATE_PLL3 - RCC->CR |= RCC_CR_PLL3ON; - while (!(RCC->CR & RCC_CR_PLL3RDY)) - ; /* Waits until PLL3 is stable. */ -#endif - - /* PLL1 setup, if activated.*/ -#if STM32_ACTIVATE_PLL1 - RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC; - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; /* Waits until PLL1 is stable. */ -#endif - - /* Clock settings.*/ -#if STM32_HAS_OTG1 - RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; -#else - RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; -#endif - - /* Flash setup and final clock selection. */ - FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ - - /* Switching to the configured clock source if it is different from HSI.*/ -#if (STM32_SW != STM32_SW_HSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; -#endif -#endif /* !STM32_NO_INIT */ -} -#else -void stm32_clock_init(void) {} -#endif - /** @} */ diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h index 74df91f54..3b66910fc 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.h +++ b/os/hal/platforms/STM32F0xx/hal_lld.h @@ -38,7 +38,7 @@ #ifndef _HAL_LLD_H_ #define _HAL_LLD_H_ -#include "stm32.h" +#include "stm32f0xx.h" /*===========================================================================*/ /* Driver constants. */ @@ -471,7 +471,7 @@ * @brief Main clock source selection. * @note If the selected clock source is not the PLL then the PLL is not * initialized and started. - * @note The default value is calculated for a 72MHz system clock from + * @note The default value is calculated for a 48MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_SW) || defined(__DOXYGEN__) @@ -482,7 +482,7 @@ * @brief Clock source for the PLL. * @note This setting has only effect if the PLL is selected as the * system clock source. - * @note The default value is calculated for a 72MHz system clock from + * @note The default value is calculated for a 48MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) @@ -493,7 +493,7 @@ * @brief Crystal PLL pre-divider. * @note This setting has only effect if the PLL is selected as the * system clock source. - * @note The default value is calculated for a 72MHz system clock from + * @note The default value is calculated for a 48MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) @@ -503,16 +503,16 @@ /** * @brief PLL multiplier value. * @note The allowed range is 2...16. - * @note The default value is calculated for a 72MHz system clock from + * @note The default value is calculated for a 48MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLMUL_VALUE 9 +#define STM32_PLLMUL_VALUE 6 #endif /** * @brief AHB prescaler value. - * @note The default value is calculated for a 72MHz system clock from + * @note The default value is calculated for a 48MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_HPRE) || defined(__DOXYGEN__) @@ -523,7 +523,7 @@ * @brief APB1 prescaler value. */ #if !defined(STM32_PPRE) || defined(__DOXYGEN__) -#define STM32_PPRE STM32_PPRE_DIV2 +#define STM32_PPRE STM32_PPRE_DIV1 #endif /** @@ -531,6 +531,7 @@ */ #if !defined(STM32_ADCSW) || defined(__DOXYGEN__) #define STM32_ADCSW STM32_ADCSW_HSI14 +#endif /** * @brief ADC prescaler value. @@ -860,8 +861,8 @@ /*===========================================================================*/ /* STM32 DMA and RCC helpers.*/ -#include "stm32_dma.h" -#include "stm32_rcc.h" +/*#include "stm32_dma.h" +#include "stm32_rcc.h"*/ #ifdef __cplusplus extern "C" { diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk new file mode 100644 index 000000000..c22930f58 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/platform.mk @@ -0,0 +1,5 @@ +# List of all the STM32F1xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \ No newline at end of file diff --git a/os/hal/platforms/STM32F0xx/stm32f0xx.h b/os/hal/platforms/STM32F0xx/stm32f0xx.h index 07c252c11..23ee738ec 100644 --- a/os/hal/platforms/STM32F0xx/stm32f0xx.h +++ b/os/hal/platforms/STM32F0xx/stm32f0xx.h @@ -213,7 +213,8 @@ typedef enum IRQn */ #include "core_cm0.h" -#include "system_stm32f0xx.h" +/* CHIBIOS FIX */ +/*#include "system_stm32f0xx.h"*/ #include /** @addtogroup Exported_types -- cgit v1.2.3