From b0c0f93b8f60d3cf5225987d04c4ef84f8f72cee Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 16 May 2012 17:04:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4201 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 285 +++++++++++++++++++++++++++++++++++ 1 file changed, 285 insertions(+) create mode 100644 os/hal/platforms/STM32F0xx/hal_lld.c (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c new file mode 100644 index 000000000..806ec3ea3 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -0,0 +1,285 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F0xx/hal_lld.c + * @brief STM32F0xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR |= PWR_CR_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ + rccResetAPB1(0xFFFFFFFF); + rccResetAPB2(0xFFFFFFFF); + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* DWT cycle counter enable.*/ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + DWT_CTRL |= DWT_CTRL_CYCCNTENA; + + /* PWR and BD clocks enabled.*/ + rccEnablePWRInterface(FALSE); + rccEnableBKPInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) || \ + defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(__DOXYGEN__) +/* + * Clocks initialization for all sub-families except CL. + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* HSI setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + RCC->CFGR = 0; /* CFGR reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Waits until HSI is selected. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while (!(RCC->CR & RCC_CR_HSERDY)) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + + /* Clock settings.*/ +#if STM32_HAS_USB + RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | + STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | + STM32_HPRE; +#else + RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | + STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | + STM32_HPRE; +#endif + + /* Flash setup and final clock selection. */ + FLASH->ACR = STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + /* Switches clock source.*/ + RCC->CFGR |= STM32_SW; + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; /* Waits selection complete. */ +#endif +#endif /* !STM32_NO_INIT */ +} + +#elif defined(STM32F10X_CL) +/* + * Clocks initialization for the CL sub-family. + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* HSI setup.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + RCC->CFGR = 0; + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Wait until HSI is the source.*/ + +#if STM32_HSE_ENABLED +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEBYP; +#endif + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while (!(RCC->CR & RCC_CR_HSERDY)) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + + /* Settings of various dividers and multipliers in CFGR2.*/ + RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 | + STM32_PREDIV1 | STM32_PREDIV1SRC; + + /* PLL2 setup, if activated.*/ +#if STM32_ACTIVATE_PLL2 + RCC->CR |= RCC_CR_PLL2ON; + while (!(RCC->CR & RCC_CR_PLL2RDY)) + ; /* Waits until PLL2 is stable. */ +#endif + + /* PLL3 setup, if activated.*/ +#if STM32_ACTIVATE_PLL3 + RCC->CR |= RCC_CR_PLL3ON; + while (!(RCC->CR & RCC_CR_PLL3RDY)) + ; /* Waits until PLL3 is stable. */ +#endif + + /* PLL1 setup, if activated.*/ +#if STM32_ACTIVATE_PLL1 + RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL1 is stable. */ +#endif + + /* Clock settings.*/ +#if STM32_HAS_OTG1 + RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#else + RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#endif + + /* Flash setup and final clock selection. */ + FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* !STM32_NO_INIT */ +} +#else +void stm32_clock_init(void) {} +#endif + +/** @} */ -- cgit v1.2.3 From c4a3d44d53f667cc73abf655542b2974a9b0bb93 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 17 May 2012 18:44:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4205 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 91 ------------------------------------ 1 file changed, 91 deletions(-) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 806ec3ea3..24dc11f5c 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -132,13 +132,6 @@ void hal_lld_init(void) { * * @special */ -#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) || \ - defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ - defined(__DOXYGEN__) -/* - * Clocks initialization for all sub-families except CL. - */ void stm32_clock_init(void) { #if !STM32_NO_INIT @@ -198,88 +191,4 @@ void stm32_clock_init(void) { #endif /* !STM32_NO_INIT */ } -#elif defined(STM32F10X_CL) -/* - * Clocks initialization for the CL sub-family. - */ -void stm32_clock_init(void) { - -#if !STM32_NO_INIT - /* HSI setup.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - RCC->CFGR = 0; - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Wait until HSI is the source.*/ - -#if STM32_HSE_ENABLED -#if defined(STM32_HSE_BYPASS) - /* HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEBYP; -#endif - /* HSE activation.*/ - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR & RCC_CR_HSERDY)) - ; /* Waits until HSE is stable. */ -#endif - -#if STM32_LSI_ENABLED - /* LSI activation.*/ - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) - ; /* Waits until LSI is stable. */ -#endif - - /* Settings of various dividers and multipliers in CFGR2.*/ - RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 | - STM32_PREDIV1 | STM32_PREDIV1SRC; - - /* PLL2 setup, if activated.*/ -#if STM32_ACTIVATE_PLL2 - RCC->CR |= RCC_CR_PLL2ON; - while (!(RCC->CR & RCC_CR_PLL2RDY)) - ; /* Waits until PLL2 is stable. */ -#endif - - /* PLL3 setup, if activated.*/ -#if STM32_ACTIVATE_PLL3 - RCC->CR |= RCC_CR_PLL3ON; - while (!(RCC->CR & RCC_CR_PLL3RDY)) - ; /* Waits until PLL3 is stable. */ -#endif - - /* PLL1 setup, if activated.*/ -#if STM32_ACTIVATE_PLL1 - RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC; - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; /* Waits until PLL1 is stable. */ -#endif - - /* Clock settings.*/ -#if STM32_HAS_OTG1 - RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; -#else - RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; -#endif - - /* Flash setup and final clock selection. */ - FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ - - /* Switching to the configured clock source if it is different from HSI.*/ -#if (STM32_SW != STM32_SW_HSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; -#endif -#endif /* !STM32_NO_INIT */ -} -#else -void stm32_clock_init(void) {} -#endif - /** @} */ -- cgit v1.2.3 From 01a811d27f05c73904200aaeaf618ed657b65283 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 May 2012 15:29:20 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4206 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 24dc11f5c..401afe7e3 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -95,7 +95,7 @@ void hal_lld_init(void) { /* Reset of all peripherals.*/ rccResetAPB1(0xFFFFFFFF); - rccResetAPB2(0xFFFFFFFF); + rccResetAPB2(!RCC_APB2RSTR_DBGMCURST); /* SysTick initialization using the system clock.*/ SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; @@ -104,13 +104,8 @@ void hal_lld_init(void) { SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk; - /* DWT cycle counter enable.*/ - SCS_DEMCR |= SCS_DEMCR_TRCENA; - DWT_CTRL |= DWT_CTRL_CYCCNTENA; - /* PWR and BD clocks enabled.*/ rccEnablePWRInterface(FALSE); - rccEnableBKPInterface(FALSE); /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); @@ -152,6 +147,13 @@ void stm32_clock_init(void) { ; /* Waits until HSE is stable. */ #endif +#if STM32_HSE14_ENABLED + /* HSI14 activation.*/ + RCC->CR2 |= RCC_CR2_HSI14ON; + while (!(RCC->CR2 & RCC_CR2_HSI14RDY)) + ; /* Waits until HSI14 is stable. */ +#endif + #if STM32_LSI_ENABLED /* LSI activation.*/ RCC->CSR |= RCC_CSR_LSION; @@ -168,15 +170,9 @@ void stm32_clock_init(void) { #endif /* Clock settings.*/ -#if STM32_HAS_USB - RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE | - STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | - STM32_HPRE; -#else - RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | - STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | - STM32_HPRE; -#endif + RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | + STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE | STM32_HPRE; + RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW; /* Flash setup and final clock selection. */ FLASH->ACR = STM32_FLASHBITS; @@ -188,6 +184,10 @@ void stm32_clock_init(void) { while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) ; /* Waits selection complete. */ #endif + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); #endif /* !STM32_NO_INIT */ } -- cgit v1.2.3 From 7112dfa32e35f35998bf4ab05888317ef5aed59a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 23 Oct 2012 20:51:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4777 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 401afe7e3..1e7a83e36 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -29,6 +29,10 @@ #include "ch.h" #include "hal.h" +/* TODO: LSEBYP like in F3.*/ +/* TODO: LSEDRV like in F3.*/ +/* TODO: PREDIV like in F3.*/ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -142,7 +146,13 @@ void stm32_clock_init(void) { #if STM32_HSE_ENABLED /* HSE activation.*/ +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; +#else + /* No HSE Bypass.*/ RCC->CR |= RCC_CR_HSEON; +#endif while (!(RCC->CR & RCC_CR_HSERDY)) ; /* Waits until HSE is stable. */ #endif -- cgit v1.2.3 From ca0b2a235d6b537896efeb11f263d7e103a92d82 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 24 Oct 2012 09:46:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4778 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 1e7a83e36..10b6db940 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -171,19 +171,20 @@ void stm32_clock_init(void) { ; /* Waits until LSI is stable. */ #endif + /* Clock settings.*/ + RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | + STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE | + STM32_HPRE; + RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | + STM32_USART1SW; + #if STM32_ACTIVATE_PLL /* PLL activation.*/ - RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC; RCC->CR |= RCC_CR_PLLON; while (!(RCC->CR & RCC_CR_PLLRDY)) ; /* Waits until PLL is stable. */ #endif - /* Clock settings.*/ - RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | - STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE | STM32_HPRE; - RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW; - /* Flash setup and final clock selection. */ FLASH->ACR = STM32_FLASHBITS; -- cgit v1.2.3 From 633098ebcd87d2a654deede6feff0d93fdabaebc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 6 Dec 2012 10:53:16 +0000 Subject: STM32F3 SPI working, STM32F0 support update. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4879 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 10b6db940..57b548ce3 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -29,10 +29,6 @@ #include "ch.h" #include "hal.h" -/* TODO: LSEBYP like in F3.*/ -/* TODO: LSEDRV like in F3.*/ -/* TODO: PREDIV like in F3.*/ - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -64,7 +60,13 @@ static void hal_lld_backup_domain_init(void) { /* If enabled then the LSE is started.*/ #if STM32_LSE_ENABLED - RCC->BDCR |= RCC_BDCR_LSEON; +#if defined(STM32_LSE_BYPASS) + /* LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; +#else + /* No LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; +#endif while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) ; /* Waits until LSE is stable. */ #endif @@ -172,10 +174,10 @@ void stm32_clock_init(void) { #endif /* Clock settings.*/ - RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | - STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE | - STM32_HPRE; - RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | + RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE | STM32_HPRE; + RCC->CFGR2 = STM32_PREDIV; + RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW; #if STM32_ACTIVATE_PLL -- cgit v1.2.3 From b999931853091a3683a9f9fa5a1eb2c1c5c856a2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 25 Dec 2012 08:20:13 +0000 Subject: Code templates-related fixes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4971 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 57b548ce3..7c76cb272 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -29,6 +29,10 @@ #include "ch.h" #include "hal.h" +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ -- cgit v1.2.3 From c4dcbb3e9881654b9c4d96837a994ce305ab4d35 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 30 Dec 2012 17:41:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4999 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 7c76cb272..a8b73fd88 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -114,7 +114,7 @@ void hal_lld_init(void) { SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk; - /* PWR and BD clocks enabled.*/ + /* PWR clock enabled.*/ rccEnablePWRInterface(FALSE); /* Initializes the backup domain.*/ -- cgit v1.2.3 From 184a71345c6a36a9a8664eda8fbcc3ea728267a8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Feb 2013 10:58:09 +0000 Subject: Updated license years. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5102 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index a8b73fd88..bde03e23f 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -1,6 +1,6 @@ /* ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. + 2011,2012,2013 Giovanni Di Sirio. This file is part of ChibiOS/RT. -- cgit v1.2.3 From 01f971ba1d63d8568789adf51cde22fb35f69e73 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 28 Feb 2013 16:23:19 +0000 Subject: Adjusted C file templates. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5339 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index bde03e23f..bf1f26e39 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -38,7 +38,7 @@ /*===========================================================================*/ /*===========================================================================*/ -/* Driver local variables. */ +/* Driver local variables and types. */ /*===========================================================================*/ /*===========================================================================*/ -- cgit v1.2.3 From 853216256ad4cdacf5f94edb7d6b738c6be165a1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 30 Mar 2013 10:32:37 +0000 Subject: Relicensing parts of the tree under the Apache 2.0 license. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5521 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index bf1f26e39..7c5bdce8e 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -1,21 +1,17 @@ /* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - This file is part of ChibiOS/RT. + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. + http://www.apache.org/licenses/LICENSE-2.0 - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. */ /** -- cgit v1.2.3 From eff9b74c9c3714a8aec6a61f86e84f38edfd213a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 11 May 2013 07:05:28 +0000 Subject: Fixed bug #409. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5703 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/hal_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c') diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 7c5bdce8e..debc51ea3 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -101,7 +101,7 @@ void hal_lld_init(void) { /* Reset of all peripherals.*/ rccResetAPB1(0xFFFFFFFF); - rccResetAPB2(!RCC_APB2RSTR_DBGMCURST); + rccResetAPB2(~RCC_APB2RSTR_DBGMCURST); /* SysTick initialization using the system clock.*/ SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; -- cgit v1.2.3