From 16178e1c45a76544d34ce63db37932838353637c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 28 Nov 2009 12:25:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1333 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/MSP430/pal_lld.c | 115 ++++++++++++++ os/hal/platforms/MSP430/pal_lld.h | 293 +++++++++++++++++++++++++++++++++++ os/hal/platforms/MSP430/platform.dox | 60 +++++++ os/hal/platforms/MSP430/serial_lld.c | 292 ++++++++++++++++++++++++++++++++++ os/hal/platforms/MSP430/serial_lld.h | 159 +++++++++++++++++++ 5 files changed, 919 insertions(+) create mode 100644 os/hal/platforms/MSP430/pal_lld.c create mode 100644 os/hal/platforms/MSP430/pal_lld.h create mode 100644 os/hal/platforms/MSP430/platform.dox create mode 100644 os/hal/platforms/MSP430/serial_lld.c create mode 100644 os/hal/platforms/MSP430/serial_lld.h (limited to 'os/hal/platforms/MSP430') diff --git a/os/hal/platforms/MSP430/pal_lld.c b/os/hal/platforms/MSP430/pal_lld.c new file mode 100644 index 000000000..227853a12 --- /dev/null +++ b/os/hal/platforms/MSP430/pal_lld.c @@ -0,0 +1,115 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file MSP430/pal_lld.c + * @brief MSP430 Digital I/O low level driver code + * @addtogroup MSP430_PAL + * @{ + */ + +#include +#include + +/** + * @brief MSP430 I/O ports configuration. + * + * @param[in] config the MSP430 ports configuration + * + * @note The @p PxIFG, @p PxIE and @p PxSEL registers are cleared. @p PxOUT + * and @p PxDIR are configured as specified. + */ +void _pal_lld_init(const MSP430DIOConfig *config) { + +#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__) + IOPORT1->iop_full.ie.reg_p = 0; + IOPORT1->iop_full.ifg.reg_p = 0; + IOPORT1->iop_full.sel.reg_p = 0; + IOPORT1->iop_common.out = config->P1Data.out; + IOPORT1->iop_common.dir = config->P1Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__) + IOPORT2->iop_full.ie.reg_p = 0; + IOPORT2->iop_full.ifg.reg_p = 0; + IOPORT2->iop_full.sel.reg_p = 0; + IOPORT2->iop_common.out = config->P2Data.out; + IOPORT2->iop_common.dir = config->P2Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__) + IOPORT3->iop_simple.sel.reg_p = 0; + IOPORT3->iop_common.out = config->P3Data.out; + IOPORT3->iop_common.dir = config->P3Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__) + IOPORT4->iop_simple.sel.reg_p = 0; + IOPORT4->iop_common.out = config->P4Data.out; + IOPORT4->iop_common.dir = config->P4Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__) + IOPORT5->iop_simple.sel.reg_p = 0; + IOPORT5->iop_common.out = config->P5Data.out; + IOPORT5->iop_common.dir = config->P5Data.dir; +#endif + +#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__) + IOPORT6->iop_simple.sel.reg_p = 0; + IOPORT6->iop_common.out = config->P6Data.out; + IOPORT6->iop_common.dir = config->P6Data.dir; +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @note This function is not meant to be invoked directly by the application + * code. + * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by + * the MSP430x1xx Family User's Guide. Unconnected pads are set to + * high logic state by default. + * @note This function does not alter the @p PxSEL registers. Alternate + * functions setup must be handled by device-specific code. + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + uint_fast8_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->iop_common.dir.reg_p &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + port->iop_common.out.reg_p |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->iop_common.dir.reg_p |= mask; + break; + } +} + +/** @} */ diff --git a/os/hal/platforms/MSP430/pal_lld.h b/os/hal/platforms/MSP430/pal_lld.h new file mode 100644 index 000000000..4fbde7a40 --- /dev/null +++ b/os/hal/platforms/MSP430/pal_lld.h @@ -0,0 +1,293 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file MSP430/pal_lld.h + * @brief MSP430 Digital I/O low level driver header + * @addtogroup MSP430_PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#include + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Simplified MSP430 I/O port representation. + * @details This structure represents the common part of all the MSP430 I/O + * ports. + */ +struct port_common_t { + ioregister_t in; + ioregister_t out; + ioregister_t dir; +}; + +/** + * @brief Generic MSP430 I/O port. + */ +union __ioport { + struct port_common_t iop_common; + struct port_simple_t iop_simple; + struct port_full_t iop_full; +}; + +/** + * @brief Setup registers common to all the MSP430 ports. + */ +typedef struct { + ioregister_t out; + ioregister_t dir; +} msp430_dio_setup_t; + +/** + * @brief MSP430 I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if defined(__MSP430_HAS_PORT1__) || \ + defined(__MSP430_HAS_PORT1_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 1 setup data.*/ + msp430_dio_setup_t P1Data; +#endif +#if defined(__MSP430_HAS_PORT2__) || \ + defined(__MSP430_HAS_PORT2_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 2 setup data.*/ + msp430_dio_setup_t P2Data; +#endif +#if defined(__MSP430_HAS_PORT3__) || \ + defined(__MSP430_HAS_PORT3_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 3 setup data.*/ + msp430_dio_setup_t P3Data; +#endif +#if defined(__MSP430_HAS_PORT4__) || \ + defined(__MSP430_HAS_PORT4_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 4 setup data.*/ + msp430_dio_setup_t P4Data; +#endif +#if defined(__MSP430_HAS_PORT5__) || \ + defined(__MSP430_HAS_PORT5_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 5 setup data.*/ + msp430_dio_setup_t P5Data; +#endif +#if defined(__MSP430_HAS_PORT6__) || \ + defined(__MSP430_HAS_PORT6_R__) || \ + defined(__DOXYGEN__) + /** @brief Port 6 setup data.*/ + msp430_dio_setup_t P6Data; +#endif +} MSP430DIOConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef union __ioport * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief I/O port A identifier. + * @details This port identifier is mapped on the MSP430 port 1 (P1). + */ +#if defined(__MSP430_HAS_PORT1__) || \ + defined(__MSP430_HAS_PORT1_R__) || \ + defined(__DOXYGEN__) +#define IOPORT1 ((ioportid_t)0x0020) +#endif + +/** + * @brief I/O port B identifier. + * @details This port identifier is mapped on the MSP430 port 2 (P2). + */ +#if defined(__MSP430_HAS_PORT2__) || \ + defined(__MSP430_HAS_PORT2_R__) || \ + defined(__DOXYGEN__) +#define IOPORT2 ((ioportid_t)0x0028) +#endif + +/** + * @brief I/O port C identifier. + * @details This port identifier is mapped on the MSP430 port 3 (P3). + */ +#if defined(__MSP430_HAS_PORT3__) || \ + defined(__MSP430_HAS_PORT3_R__) || \ + defined(__DOXYGEN__) +#define IOPORT3 ((ioportid_t)0x0018) +#endif + +/** + * @brief I/O port D identifier. + * @details This port identifier is mapped on the MSP430 port 4 (P4). + */ +#if defined(__MSP430_HAS_PORT4__) || \ + defined(__MSP430_HAS_PORT4_R__) || \ + defined(__DOXYGEN__) +#define IOPORT4 ((ioportid_t)0x001c) +#endif + +/** + * @brief I/O port E identifier. + * @details This port identifier is mapped on the MSP430 port 5 (P5). + */ +#if defined(__MSP430_HAS_PORT5__) || \ + defined(__MSP430_HAS_PORT5_R__) || \ + defined(__DOXYGEN__) +#define IOPORT5 ((ioportid_t)0x0030) +#endif + +/** + * @brief I/O port F identifier. + * @details This port identifier is mapped on the MSP430 port 6 (P6). + */ +#if defined(__MSP430_HAS_PORT6__) || \ + defined(__MSP430_HAS_PORT6_R__) || \ + defined(__DOXYGEN__) +#define IOPORT6 ((ioportid_t)0x0034) +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in a file named pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * @details In MSP430 programs all the ports as input. + * + * @param[in] config the MSP430 ports configuration + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * @details This function is implemented by reading the PxIN register, the + * implementation has no side effects. + * + * @param[in] port the port identifier + * @return The port bits. + * + * @note This function is not meant to be invoked directly by the application + * code. + */ +#define pal_lld_readport(port) ((port)->iop_common.in.reg_p) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the PxOUT register, the + * implementation has no side effects. + * + * @param[in] port the port identifier + * @return The latched logical states. + * + * @note This function is not meant to be invoked directly by the application + * code. + */ +#define pal_lld_readlatch(port) ((port)->iop_common.out.reg_p) + +/** + * @brief Writes a bits mask on a I/O port. + * @details This function is implemented by writing the PxOUT register, the + * implementation has no side effects. + * + * @param[in] port the port identifier + * @param[in] bits the bits to be written on the specified port + * + * @note This function is not meant to be invoked directly by the application + * code. + */ +#define pal_lld_writeport(port, bits) { \ + (port)->iop_common.out.reg_p = (bits); \ +} + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @note This function is not meant to be invoked directly by the application + * code. + * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by + * the MSP430x1xx Family User's Guide. + * @note This function does not alter the @p PxSEL registers. Alternate + * functions setup must be handled by device-specific code. + */ +#define pal_lld_setgroupmode(port, mask, mode) \ + _pal_lld_setgroupmode(port, mask, mode) + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const MSP430DIOConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + uint_fast8_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/MSP430/platform.dox b/os/hal/platforms/MSP430/platform.dox new file mode 100644 index 000000000..22f404ddb --- /dev/null +++ b/os/hal/platforms/MSP430/platform.dox @@ -0,0 +1,60 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup MSP430_DRIVERS MSP430 Drivers + * @brief Device drivers included in the MSP430 support. + * + * @ingroup MSP430 + */ + +/** + * @defgroup MSP430_PAL MSP430 I/O Ports Support + * @brief I/O Ports peripherals support. + * @details This module supports the MSP430 Digital I/O controller. The + * controller supports the following features (see @ref PAL): + * - 8 bits wide ports. + * - Atomic set/reset/toggle functions because special MSP430 instruction set. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + *

Supported Setup Modes

+ * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + *

Suboptimal Behavior

+ * Some MSP430 I/O ports features are less than optimal: + * - Bus/group writing is not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup MSP430_DRIVERS + */ + +/** + * @defgroup MSP430_SERIAL MSP430 USART Support + * @brief USART support. + * @details The serial driver supports both the MSP430 USARTs in asynchronous + * mode. + * + * @ingroup MSP430_DRIVERS + */ diff --git a/os/hal/platforms/MSP430/serial_lld.c b/os/hal/platforms/MSP430/serial_lld.c new file mode 100644 index 000000000..4130432cd --- /dev/null +++ b/os/hal/platforms/MSP430/serial_lld.c @@ -0,0 +1,292 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file MSP430/serial_lld.c + * @brief MSP430 low level serial driver code + * @addtogroup MSP430_SERIAL + * @{ + */ + +#include +#include + +#include + +#include "board.h" + +#if USE_MSP430_USART0 || defined(__DOXYGEN__) +/** @brief USART0 serial driver identifier.*/ +SerialDriver SD1; +#endif +#if USE_MSP430_USART1 || defined(__DOXYGEN__) +/** @brief USART1 serial driver identifier.*/ +SerialDriver SD2; +#endif + +/** @brief Driver default configuration.*/ +static const SerialDriverConfig default_config = { + UBR(DEFAULT_USART_BITRATE), + 0, + CHAR +}; + +/*===========================================================================*/ +/* Low Level Driver local functions. */ +/*===========================================================================*/ + +static void set_error(uint8_t urctl, SerialDriver *sdp) { + sdflags_t sts = 0; + + if (urctl & OE) + sts |= SD_OVERRUN_ERROR; + if (urctl & PE) + sts |= SD_PARITY_ERROR; + if (urctl & FE) + sts |= SD_FRAMING_ERROR; + if (urctl & BRK) + sts |= SD_BREAK_DETECTED; + chSysLockFromIsr(); + sdAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if USE_MSP430_USART0 || defined(__DOXYGEN__) +static void notify1(void) { + + if (!(U0IE & UTXIE0)) { + chSysLockFromIsr(); + U0TXBUF = (uint8_t)sdRequestDataI(&SD1); + chSysUnlockFromIsr(); + U0IE |= UTXIE0; + } +} + +/** + * @brief USART0 initialization. + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart0_init(const SerialDriverConfig *config) { + + U0CTL = SWRST; /* Resets the USART, it should already be.*/ + /* USART init */ + U0TCTL = SSEL0 | SSEL1; /* SMCLK as clock source.*/ + U0MCTL = config->mod; /* Modulator.*/ + U0BR1 = (uint8_t)(config->div >> 8); /* Divider high.*/ + U0BR0 = (uint8_t)(config->div >> 0); /* Divider low.*/ + /* Clear USART status.*/ + (void)U0RXBUF; + U0RCTL = 0; + /* USART enable.*/ + U0ME |= UTXE0 + URXE0; /* Enables the USART.*/ + U0CTL = config->ctl & ~SWRST; /* Various settings, clears reset state.*/ + U0IE |= URXIE0; /* Enables RX interrupt.*/ +} + +/** + * @brief USART0 de-initialization. + */ +static void usart0_deinit(void) { + + U0IE &= ~URXIE0; + U0CTL = SWRST; +} +#endif /* USE_MSP430_USART0 */ + +#if USE_MSP430_USART1 || defined(__DOXYGEN__) +static void notify2(void) { + + if (!(U1IE & UTXIE1)) { + U1TXBUF = (uint8_t)sdRequestDataI(&SD2); + U1IE |= UTXIE1; + } +} + +/** + * @brief USART1 initialization. + * @param[in] config the architecture-dependent serial driver configuration + */ +static void usart1_init(const SerialDriverConfig *config) { + + U1CTL = SWRST; /* Resets the USART, it should already be.*/ + /* USART init.*/ + U1TCTL = SSEL0 | SSEL1; /* SMCLK as clock source.*/ + U1MCTL = config->mod; /* Modulator.*/ + U1BR1 = (uint8_t)(config->div >> 8); /* Divider high.*/ + U1BR0 = (uint8_t)(config->div >> 0); /* Divider low.*/ + /* Clear USART status.*/ + (void)U0RXBUF; + U1RCTL = 0; + /* USART enable.*/ + U1ME |= UTXE0 + URXE0; /* Enables the USART.*/ + U1CTL = config->ctl & ~SWRST; /* Various settings, clears reset state.*/ + U1IE |= URXIE0; /* Enables RX interrupt.*/ +} + +/** + * @brief USART1 de-initialization. + */ +static void usart1_deinit(void) { + + U1IE &= ~URXIE0; + U1CTL = SWRST; +} +#endif /* USE_MSP430_USART1 */ + +/*===========================================================================*/ +/* Low Level Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_MSP430_USART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(USART0TX_VECTOR) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD1); + chSysUnlockFromIsr(); + if (b < Q_OK) + U0IE &= ~UTXIE0; + else + U0TXBUF = b; + + CH_IRQ_EPILOGUE(); +} + +CH_IRQ_HANDLER(USART0RX_VECTOR) { + uint8_t urctl; + + CH_IRQ_PROLOGUE(); + + if ((urctl = U0RCTL) & RXERR) + set_error(urctl, &SD1); + chSysLockFromIsr(); + sdIncomingDataI(&SD1, U0RXBUF); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_MSP430_USART0 */ + +#if USE_MSP430_USART1 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(USART1TX_VECTOR) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD2); + chSysUnlockFromIsr(); + if (b < Q_OK) + U1IE &= ~UTXIE1; + else + U1TXBUF = b; + + CH_IRQ_EPILOGUE(); +} + +CH_IRQ_HANDLER(USART1RX_VECTOR) { + uint8_t urctl; + + CH_IRQ_PROLOGUE(); + + if ((urctl = U1RCTL) & RXERR) + set_error(urctl, &SD2); + chSysLockFromIsr(); + sdIncomingDataI(&SD2, U1RXBUF); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* USE_MSP430_USART1 */ + +/*===========================================================================*/ +/* Low Level Driver exported functions. */ +/*===========================================================================*/ + +/** + * Low level serial driver initialization. + */ +void sd_lld_init(void) { + +#if USE_MSP430_USART0 + sdObjectInit(&SD1, NULL, notify1); + /* I/O pins for USART0.*/ + P3SEL |= BV(4) + BV(5); +#endif + +#if USE_MSP430_USART1 + sdObjectInit(&SD2, NULL, notify2); + /* I/O pins for USART1.*/ + P3SEL |= BV(6) + BV(7); +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + */ +void sd_lld_start(SerialDriver *sdp, const SerialDriverConfig *config) { + + if (config == NULL) + config = &default_config; + +#if USE_MSP430_USART0 + if (&SD1 == sdp) { + usart0_init(config); + return; + } +#endif +#if USE_MSP430_USART1 + if (&SD2 == sdp) { + usart1_init(config); + return; + } +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +void sd_lld_stop(SerialDriver *sdp) { + +#if USE_MSP430_USART0 + if (&SD1 == sdp) { + usart0_deinit(); + return; + } +#endif +#if USE_MSP430_USART1 + if (&SD2 == sdp) { + usart1_deinit(); + return; + } +#endif +} + +/** @} */ diff --git a/os/hal/platforms/MSP430/serial_lld.h b/os/hal/platforms/MSP430/serial_lld.h new file mode 100644 index 000000000..63d94046e --- /dev/null +++ b/os/hal/platforms/MSP430/serial_lld.h @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file MSP430/serial_lld.h + * @brief MSP430 low level serial driver header + * @addtogroup MSP430_SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 32 bytes for both the transmission and receive buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 32 +#endif + +/** + * @brief Default bit rate. + * @details Configuration parameter, at startup the UARTs are configured at + * this speed. + */ +#if !defined(DEFAULT_USART_BITRATE) || defined(__DOXYGEN__) +#define DEFAULT_USART_BITRATE 38400 +#endif + +/** + * @brief USART0 driver enable switch. + * @details If set to @p TRUE the support for USART0 is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_MSP430_USART0) || defined(__DOXYGEN__) +#define USE_MSP430_USART0 TRUE +#endif + +/** + * @brief USART1 driver enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(USE_MSP430_USART1) || defined(__DOXYGEN__) +#define USE_MSP430_USART1 FALSE +#endif + +/*===========================================================================*/ +/* Unsupported event flags and custom events. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * Serial Driver condition flags type. + */ +typedef uint8_t sdflags_t; + +/** + * @brief @p SerialDriver specific data. + */ +struct _serial_driver_data { + /** + * Input queue, incoming data can be read from this input queue by + * using the queues APIs. + */ + InputQueue iqueue; + /** + * Output queue, outgoing data can be written to this output queue by + * using the queues APIs. + */ + OutputQueue oqueue; + /** + * Status Change @p EventSource. This event is generated when one or more + * condition flags change. + */ + EventSource sevent; + /** + * I/O driver status flags. + */ + sdflags_t flags; + /** + * Input circular buffer. + */ + uint8_t ib[SERIAL_BUFFERS_SIZE]; + /** + * Output circular buffer. + */ + uint8_t ob[SERIAL_BUFFERS_SIZE]; +}; + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define UBR(b) (SMCLK / (b)) + +/** + * @brief MSP430 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + uint16_t div; + uint8_t mod; + uint8_t ctl; +} SerialDriverConfig; + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/** @cond never*/ +#if USE_MSP430_USART0 +extern SerialDriver SD1; +#endif +#if USE_MSP430_USART1 +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialDriverConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif +/** @endcond*/ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ -- cgit v1.2.3