From ef6632705780c60540f4ee837085fdc9290ed846 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 31 Oct 2018 17:28:46 +0000 Subject: Improved flash drive, layers reorganized for better portability and abstraction. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12399 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- .../devices/micron_n25q/hal_flash_device.c | 62 +++--- .../devices/micron_n25q/hal_flash_device.h | 130 +++++++++++- .../devices/micron_n25q/hal_flash_device.mk | 8 +- os/hal/lib/complex/serial_nor/hal_serial_nor.c | 218 ++++----------------- os/hal/lib/complex/serial_nor/hal_serial_nor.h | 23 +-- 5 files changed, 211 insertions(+), 230 deletions(-) (limited to 'os/hal/lib/complex') diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.c b/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.c index e82af004d..6242a91ba 100644 --- a/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.c +++ b/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.c @@ -60,7 +60,7 @@ flash_descriptor_t snor_descriptor = { .address = 0U }; -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) || defined(__DOXYGEN__) +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) #if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__) /** * @brief Fast read command for memory mapped mode. @@ -70,11 +70,11 @@ const wspi_command_t snor_memmap_read = { .addr = 0, .dummy = N25Q_READ_DUMMY_CYCLES - 2, .cfg = WSPI_CFG_ADDR_SIZE_24 | -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L +#if N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI1L WSPI_CFG_CMD_MODE_ONE_LINE | WSPI_CFG_ADDR_MODE_ONE_LINE | WSPI_CFG_DATA_MODE_ONE_LINE | -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI2L WSPI_CFG_CMD_MODE_TWO_LINES | WSPI_CFG_ADDR_MODE_TWO_LINES | WSPI_CFG_DATA_MODE_TWO_LINES | @@ -94,7 +94,7 @@ const wspi_command_t snor_memmap_read = { /* Driver local variables and types. */ /*===========================================================================*/ -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI /* Initial N25Q_CMD_READ_ID command.*/ static const wspi_command_t n25q_cmd_read_id = { .cmd = N25Q_CMD_READ_ID, @@ -103,13 +103,13 @@ static const wspi_command_t n25q_cmd_read_id = { WSPI_CFG_CMD_MODE_ONE_LINE | WSPI_CFG_DATA_MODE_ONE_LINE, #else -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L +#if N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI1L WSPI_CFG_CMD_MODE_ONE_LINE | WSPI_CFG_DATA_MODE_ONE_LINE, -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI2L WSPI_CFG_CMD_MODE_TWO_LINES | WSPI_CFG_DATA_MODE_TWO_LINES, -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI4L WSPI_CFG_CMD_MODE_FOUR_LINES | WSPI_CFG_DATA_MODE_FOUR_LINES, #else @@ -130,13 +130,13 @@ static const wspi_command_t n25q_cmd_write_evconf = { WSPI_CFG_CMD_MODE_ONE_LINE | WSPI_CFG_DATA_MODE_ONE_LINE, #else -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L +#if N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI1L WSPI_CFG_CMD_MODE_ONE_LINE | WSPI_CFG_DATA_MODE_ONE_LINE, -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI2L WSPI_CFG_CMD_MODE_TWO_LINES | WSPI_CFG_DATA_MODE_TWO_LINES, -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI4L WSPI_CFG_CMD_MODE_FOUR_LINES | WSPI_CFG_DATA_MODE_FOUR_LINES, #else @@ -156,11 +156,11 @@ static const wspi_command_t n25q_cmd_write_enable = { #if N25Q_SWITCH_WIDTH == TRUE WSPI_CFG_CMD_MODE_ONE_LINE, #else -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L +#if N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI1L WSPI_CFG_CMD_MODE_ONE_LINE, -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI2L WSPI_CFG_CMD_MODE_TWO_LINES, -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI4L WSPI_CFG_CMD_MODE_FOUR_LINES, #else WSPI_CFG_CMD_MODE_EIGHT_LINES, @@ -172,14 +172,14 @@ static const wspi_command_t n25q_cmd_write_enable = { }; /* Bus width initialization.*/ -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L +#if N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI1L static const uint8_t n25q_evconf_value[1] = {0xCF}; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI2L static const uint8_t n25q_evconf_value[1] = {0x8F}; #else static const uint8_t n25q_evconf_value[1] = {0x4F}; #endif -#endif /* SNOR_BUS_MODE != SNOR_BUS_MODE_SPI */ +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ /*===========================================================================*/ /* Driver local functions. */ @@ -220,7 +220,7 @@ static flash_error_t n25q_poll_status(SNORDriver *devp) { return FLASH_NO_ERROR; } -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) || defined(__DOXYGEN__) +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) static void n25q_reset_memory(SNORDriver *devp) { /* 1x N25Q_CMD_RESET_ENABLE command.*/ @@ -245,7 +245,7 @@ static void n25q_reset_memory(SNORDriver *devp) { rejected because shorter than 8 bits. If the device is in multiple bits mode then the commands are accepted and the device is reset to one bit mode.*/ -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L +#if N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI4L /* 4x N25Q_CMD_RESET_ENABLE command.*/ static const wspi_command_t cmd_reset_enable_4 = { .cmd = N25Q_CMD_RESET_ENABLE, @@ -294,7 +294,7 @@ static void n25q_reset_memory(SNORDriver *devp) { wspiCommand(devp->config->busp, &cmd_reset_enable_1); wspiCommand(devp->config->busp, &cmd_reset_memory_1); } -#endif /* #if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI */ +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ static const uint8_t n25q_manufacturer_ids[] = N25Q_SUPPORTED_MANUFACTURE_IDS; static const uint8_t n25q_memory_type_ids[] = N25Q_SUPPORTED_MEMORY_TYPE_IDS; @@ -305,12 +305,12 @@ static const uint8_t n25q_memory_type_ids[] = N25Q_SUPPORTED_MEMORY_TYPE_IDS; void snor_device_init(SNORDriver *devp) { -#if SNOR_BUS_MODE == SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_SPI /* Reading device ID.*/ bus_cmd_receive(devp->config->busp, N25Q_CMD_READ_ID, sizeof devp->device_id, devp->device_id); -#else /* SNOR_BUS_MODE != SNOR_BUS_MODE_SPI */ +#else /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ /* Attempting a reset of the XIP mode, it could be in an unexpected state because a CPU reset does not reset the memory too.*/ snor_reset_xip(devp); @@ -322,7 +322,7 @@ void snor_device_init(SNORDriver *devp) { /* Reading device ID and unique ID.*/ wspiReceive(devp->config->busp, &n25q_cmd_read_id, sizeof devp->device_id, devp->device_id); -#endif /* SNOR_BUS_MODE != SNOR_BUS_MODE_SPI */ +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ /* Checking if the device is white listed.*/ osalDbgAssert(n25q_find_id(n25q_manufacturer_ids, @@ -334,7 +334,7 @@ void snor_device_init(SNORDriver *devp) { devp->device_id[1]), "invalid memory type id"); -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) && (N25Q_SWITCH_WIDTH == TRUE) +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && (N25Q_SWITCH_WIDTH == TRUE) /* Setting up final bus width.*/ wspiCommand(devp->config->busp, &n25q_cmd_write_enable); wspiSend(devp->config->busp, &n25q_cmd_write_evconf, 1, n25q_evconf_value); @@ -355,7 +355,7 @@ void snor_device_init(SNORDriver *devp) { snor_descriptor.sectors_count = (1U << (size_t)devp->device_id[2]) / SECTOR_SIZE; -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI { static const uint8_t flash_conf[1] = { (N25Q_READ_DUMMY_CYCLES << 4U) | 0x0FU @@ -382,7 +382,7 @@ const flash_descriptor_t *snor_get_descriptor(void *instance) { flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset, size_t n, uint8_t *rp) { -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI /* Fast read command in WSPI mode.*/ bus_cmd_addr_dummy_receive(devp->config->busp, N25Q_CMD_FAST_READ, offset, N25Q_READ_DUMMY_CYCLES, n, rp); @@ -467,7 +467,7 @@ flash_error_t snor_device_verify_erase(SNORDriver *devp, while (n > 0U) { uint8_t *p; -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI bus_cmd_addr_dummy_receive(devp->config->busp, N25Q_CMD_FAST_READ, offset, N25Q_READ_DUMMY_CYCLES, sizeof cmpbuf, cmpbuf); @@ -539,7 +539,7 @@ flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset, return FLASH_NO_ERROR; } -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) || defined(__DOXYGEN__) +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) void snor_activate_xip(SNORDriver *devp) { static const uint8_t flash_status_xip[1] = { (N25Q_READ_DUMMY_CYCLES << 4U) | 0x07U @@ -564,13 +564,13 @@ void snor_reset_xip(SNORDriver *devp) { cmd.dummy = N25Q_READ_DUMMY_CYCLES - 2; cmd.cfg = WSPI_CFG_CMD_MODE_NONE | WSPI_CFG_ADDR_SIZE_24 | -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L +#if N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI1L WSPI_CFG_ADDR_MODE_ONE_LINE | WSPI_CFG_DATA_MODE_ONE_LINE | -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI2L WSPI_CFG_ADDR_MODE_TWO_LINES | WSPI_CFG_DATA_MODE_TWO_LINES | -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI4L WSPI_CFG_ADDR_MODE_FOUR_LINES | WSPI_CFG_DATA_MODE_FOUR_LINES | #else @@ -588,6 +588,6 @@ void snor_reset_xip(SNORDriver *devp) { bus_cmd_send(devp->config->busp, N25Q_CMD_WRITE_V_CONF_REGISTER, 1, flash_conf); } -#endif /* SNOR_BUS_MODE != SNOR_BUS_MODE_SPI */ +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ /** @} */ diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.h b/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.h index 1f13f0c82..1cb77f932 100644 --- a/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.h +++ b/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.h @@ -91,6 +91,15 @@ N25Q_FLAGS_PROTECTION_ERROR) /** @} */ +/** + * @name Bus interface modes. + * @{ + */ +#define N25Q_BUS_MODE_WSPI1L 1U +#define N25Q_BUS_MODE_WSPI2L 2U +#define N25Q_BUS_MODE_WSPI4L 4U +/** @} */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -101,12 +110,24 @@ * Enhanced Volatile Configuration Register. If the flash * device is configured using the Non Volatile Configuration * Register then this option is not required. - * @note This option is only valid in QSPI bus modes. + * @note This option is only valid in WSPI bus mode. */ #if !defined(N25Q_SWITCH_WIDTH) || defined(__DOXYGEN__) #define N25Q_SWITCH_WIDTH TRUE #endif +/** + * @brief Device bus mode to be used. + * #note if @p N25Q_SWITCH_WIDTH is @p FALSE then this is the bus mode + * that the device is expected to be using. + * #note if @p N25Q_SWITCH_WIDTH is @p TRUE then this is the bus mode + * that the device will be switched in. + * @note This option is only valid in WSPI bus mode. + */ +#if !defined(N25Q_BUS_MODE) || defined(__DOXYGEN__) +#define N25Q_BUS_MODE N25Q_BUS_MODE_WSPI4L +#endif + /** * @brief Delays insertions. * @details If enabled this options inserts delays into the flash waiting @@ -156,6 +177,109 @@ #error "invalid N25Q_READ_DUMMY_CYCLES value (1..15)" #endif +#if (N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI4L) || defined(__DOXYGEN__) +/** + * @brief WSPI settings for command only. + */ +#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +/** + * @brief WSPI settings for command and address. + */ +#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_FOUR_LINES| \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +/** + * @brief WSPI settings for command and data. + */ +#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_FOUR_LINES| \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +/** + * @brief WSPI settings for command, address and data. + */ +#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_FOUR_LINES | \ + WSPI_CFG_ADDR_MODE_FOUR_LINES| \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_FOUR_LINES| \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI2L +#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_TWO_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_TWO_LINES | \ + WSPI_CFG_ADDR_MODE_TWO_LINES | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_TWO_LINES | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_TWO_LINES | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_ONE_LINE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_ONE_LINE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +#elif N25Q_BUS_MODE == N25Q_BUS_MODE_WSPI1L +#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_ONE_LINE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_NONE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_NONE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_ONE_LINE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \ + WSPI_CFG_ADDR_MODE_ONE_LINE | \ + WSPI_CFG_ALT_MODE_NONE | \ + WSPI_CFG_DATA_MODE_ONE_LINE | \ + WSPI_CFG_CMD_SIZE_8 | \ + WSPI_CFG_ADDR_SIZE_24) + +#else +#error "invalid N25Q_BUS_MODE setting" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -172,7 +296,7 @@ extern flash_descriptor_t snor_descriptor; #endif -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) && (WSPI_SUPPORTS_MEMMAP == TRUE) +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && (WSPI_SUPPORTS_MEMMAP == TRUE) extern const wspi_command_t snor_memmap_read; #endif @@ -193,7 +317,7 @@ extern "C" { flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec); flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset, size_t n, uint8_t *rp); -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI void snor_activate_xip(SNORDriver *devp); void snor_reset_xip(SNORDriver *devp); #endif diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.mk b/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.mk index c333513dd..39b0eb146 100644 --- a/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.mk +++ b/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.mk @@ -1,13 +1,13 @@ # List of all the Micron N25Q device files. -N25QSRC := $(CHIBIOS)/os/hal/lib/peripherals/flash/hal_flash.c \ +SNORSRC := $(CHIBIOS)/os/hal/lib/peripherals/flash/hal_flash.c \ $(CHIBIOS)/os/hal/lib/complex/serial_nor/hal_serial_nor.c \ $(CHIBIOS)/os/hal/lib/complex/serial_nor/devices/micron_n25q/hal_flash_device.c # Required include directories -N25QINC := $(CHIBIOS)/os/hal/lib/peripherals/flash \ +SNORINC := $(CHIBIOS)/os/hal/lib/peripherals/flash \ $(CHIBIOS)/os/hal/lib/complex/serial_nor \ $(CHIBIOS)/os/hal/lib/complex/serial_nor/devices/micron_n25q # Shared variables -ALLCSRC += $(N25QSRC) -ALLINC += $(N25QINC) +ALLCSRC += $(SNORSRC) +ALLINC += $(SNORINC) diff --git a/os/hal/lib/complex/serial_nor/hal_serial_nor.c b/os/hal/lib/complex/serial_nor/hal_serial_nor.c index 95d4ac267..417b52614 100644 --- a/os/hal/lib/complex/serial_nor/hal_serial_nor.c +++ b/os/hal/lib/complex/serial_nor/hal_serial_nor.c @@ -66,7 +66,7 @@ static const struct SNORDriverVMT snor_vmt = { /* Driver local functions. */ /*===========================================================================*/ -#if ((SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) && \ +#if ((SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && \ (SNOR_SHARED_BUS == TRUE)) || defined(__DOXYGEN__) /** * @brief Bus acquisition and lock. @@ -97,7 +97,8 @@ static void bus_release(BUSDriver *busp) { wspiReleaseBus(busp); } -#elif (SNOR_BUS_MODE == SNOR_BUS_MODE_SPI) && \ + +#elif (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_SPI) && \ (SNOR_SHARED_BUS == TRUE) void bus_acquire(BUSDriver *busp, const BUSConfig *config) { @@ -111,7 +112,9 @@ void bus_release(BUSDriver *busp) { spiReleaseBus(busp); } + #else +/* No bus sharing, empty macros.*/ #define bus_acquire(busp) #define bus_release(busp) #endif @@ -348,10 +351,10 @@ static flash_error_t snor_read_sfdp(void *instance, flash_offset_t offset, */ void bus_stop(BUSDriver *busp) { -#if SNOR_BUS_MODE == SNOR_BUS_MODE_SPI - spiStop(busp); -#else +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI wspiStop(busp); +#else + spiStop(busp); #endif } @@ -364,23 +367,14 @@ void bus_stop(BUSDriver *busp) { * @notapi */ void bus_cmd(BUSDriver *busp, uint32_t cmd) { -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI wspi_command_t mode; mode.cmd = cmd; + mode.cfg = SNOR_WSPI_CFG_CMD; + mode.addr = 0U; + mode.alt = 0U; mode.dummy = 0U; - mode.cfg = 0U | -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L - WSPI_CFG_CMD_MODE_ONE_LINE; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L - WSPI_CFG_CMD_MODE_TWO_LINES; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L - WSPI_CFG_CMD_MODE_FOUR_LINES; -#else - WSPI_CFG_CMD_MODE_EIGHT_LINES; -#endif - mode.addr = 0U; - mode.alt = 0U; wspiCommand(busp, &mode); #else uint8_t buf[1]; @@ -403,27 +397,14 @@ void bus_cmd(BUSDriver *busp, uint32_t cmd) { * @notapi */ void bus_cmd_send(BUSDriver *busp, uint32_t cmd, size_t n, const uint8_t *p) { -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI wspi_command_t mode; mode.cmd = cmd; + mode.cfg = SNOR_WSPI_CFG_CMD_DATA; + mode.addr = 0U; + mode.alt = 0U; mode.dummy = 0U; - mode.cfg = 0U | -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L - WSPI_CFG_CMD_MODE_ONE_LINE | - WSPI_CFG_DATA_MODE_ONE_LINE; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L - WSPI_CFG_CMD_MODE_TWO_LINES | - WSPI_CFG_DATA_MODE_TWO_LINES; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L - WSPI_CFG_CMD_MODE_FOUR_LINES | - WSPI_CFG_DATA_MODE_FOUR_LINES; -#else - WSPI_CFG_CMD_MODE_EIGHT_LINES | - WSPI_CFG_DATA_MODE_EIGHT_LINES; -#endif - mode.addr = 0U; - mode.alt = 0U; wspiSend(busp, &mode, n, p); #else uint8_t buf[1]; @@ -450,27 +431,14 @@ void bus_cmd_receive(BUSDriver *busp, uint32_t cmd, size_t n, uint8_t *p) { -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI wspi_command_t mode; mode.cmd = cmd; + mode.cfg = SNOR_WSPI_CFG_CMD_DATA; + mode.addr = 0U; + mode.alt = 0U; mode.dummy = 0U; - mode.cfg = 0U | -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L - WSPI_CFG_CMD_MODE_ONE_LINE | - WSPI_CFG_DATA_MODE_ONE_LINE; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L - WSPI_CFG_CMD_MODE_TWO_LINES | - WSPI_CFG_DATA_MODE_TWO_LINES; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L - WSPI_CFG_CMD_MODE_FOUR_LINES | - WSPI_CFG_DATA_MODE_FOUR_LINES; -#else - WSPI_CFG_CMD_MODE_EIGHT_LINES | - WSPI_CFG_DATA_MODE_EIGHT_LINES; -#endif - mode.addr = 0U; - mode.alt = 0U; wspiReceive(busp, &mode, n, p); #else uint8_t buf[1]; @@ -493,41 +461,14 @@ void bus_cmd_receive(BUSDriver *busp, * @notapi */ void bus_cmd_addr(BUSDriver *busp, uint32_t cmd, flash_offset_t offset) { -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI wspi_command_t mode; mode.cmd = cmd; + mode.cfg = SNOR_WSPI_CFG_CMD_ADDR; + mode.addr = offset; + mode.alt = 0U; mode.dummy = 0U; - mode.cfg = 0U | -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L - WSPI_CFG_CMD_MODE_ONE_LINE | - WSPI_CFG_ADDR_MODE_ONE_LINE | - WSPI_CFG_ADDR_SIZE_24; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L - WSPI_CFG_CMD_MODE_TWO_LINES | - WSPI_CFG_ADDR_MODE_TWO_LINES | - WSPI_CFG_ADDR_SIZE_24; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L - WSPI_CFG_CMD_MODE_FOUR_LINES | - WSPI_CFG_ADDR_MODE_FOUR_LINES | - WSPI_CFG_ADDR_SIZE_24; -#else - WSPI_CFG_CMD_MODE_EIGHT_LINES | - WSPI_CFG_ADDR_MODE_EIGHT_LINES | - WSPI_CFG_ADDR_SIZE_24; -#endif - - /* Handling 32 bits addressing. - TODO: Address size should come from upper levels.*/ - if ((cmd & SNOR_BUS_CMD_EXTENDED_ADDRESSING) == 0) { - mode.cfg |= WSPI_CFG_ADDR_SIZE_24; - } - else { - mode.cfg |= WSPI_CFG_ADDR_SIZE_32; - } - - mode.addr = offset; - mode.alt = 0U; wspiCommand(busp, &mode); #else uint8_t buf[4]; @@ -559,41 +500,14 @@ void bus_cmd_addr_send(BUSDriver *busp, flash_offset_t offset, size_t n, const uint8_t *p) { -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI wspi_command_t mode; mode.cmd = cmd; + mode.cfg = SNOR_WSPI_CFG_CMD_ADDR_DATA; + mode.addr = offset; + mode.alt = 0U; mode.dummy = 0U; - mode.cfg = 0U | -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L - WSPI_CFG_CMD_MODE_ONE_LINE | - WSPI_CFG_ADDR_MODE_ONE_LINE | - WSPI_CFG_DATA_MODE_ONE_LINE; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L - WSPI_CFG_CMD_MODE_TWO_LINES | - WSPI_CFG_ADDR_MODE_TWO_LINES | - WSPI_CFG_DATA_MODE_TWO_LINES; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L - WSPI_CFG_CMD_MODE_FOUR_LINES | - WSPI_CFG_ADDR_MODE_FOUR_LINES | - WSPI_CFG_DATA_MODE_FOUR_LINES; -#else - WSPI_CFG_CMD_MODE_EIGHT_LINES | - WSPI_CFG_ADDR_MODE_EIGHT_LINES | - WSPI_CFG_DATA_MODE_EIGHT_LINES; -#endif - - /* Handling 32 bits addressing. - TODO: Address size should come from upper levels.*/ - if ((cmd & SNOR_BUS_CMD_EXTENDED_ADDRESSING) == 0) { - mode.cfg |= WSPI_CFG_ADDR_SIZE_24; - } - else { - mode.cfg |= WSPI_CFG_ADDR_SIZE_32; - } - - mode.addr = offset; - mode.alt = 0U; wspiSend(busp, &mode, n, p); #else uint8_t buf[4]; @@ -626,41 +540,14 @@ void bus_cmd_addr_receive(BUSDriver *busp, flash_offset_t offset, size_t n, uint8_t *p) { -#if SNOR_BUS_MODE != SNOR_BUS_MODE_SPI +#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI wspi_command_t mode; mode.cmd = cmd; + mode.cfg = SNOR_WSPI_CFG_CMD_ADDR_DATA; + mode.addr = offset; + mode.alt = 0U; mode.dummy = 0U; - mode.cfg = 0U | -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L - WSPI_CFG_CMD_MODE_ONE_LINE | - WSPI_CFG_ADDR_MODE_ONE_LINE | - WSPI_CFG_DATA_MODE_ONE_LINE; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L - WSPI_CFG_CMD_MODE_TWO_LINES | - WSPI_CFG_ADDR_MODE_TWO_LINES | - WSPI_CFG_DATA_MODE_TWO_LINES; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L - WSPI_CFG_CMD_MODE_TWO_LINES | - WSPI_CFG_ADDR_MODE_TWO_LINES | - WSPI_CFG_DATA_MODE_TWO_LINES; -#else - WSPI_CFG_CMD_MODE_EIGHT_LINES | - WSPI_CFG_ADDR_MODE_EIGHT_LINES | - WSPI_CFG_DATA_MODE_EIGHT_LINES; -#endif - - /* Handling 32 bits addressing. - TODO: Address size should come from upper levels.*/ - if ((cmd & SNOR_BUS_CMD_EXTENDED_ADDRESSING) == 0) { - mode .cfg |= WSPI_CFG_ADDR_SIZE_24; - } - else { - mode .cfg |= WSPI_CFG_ADDR_SIZE_32; - } - - mode.addr = offset; - mode.alt = 0U; wspiReceive(busp, &mode, n, p); #else uint8_t buf[4]; @@ -676,7 +563,7 @@ void bus_cmd_addr_receive(BUSDriver *busp, #endif } -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) || defined(__DOXYGEN__) +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) /** * @brief Sends a command followed by a flash address, dummy cycles and a * data receive phase. @@ -699,40 +586,13 @@ void bus_cmd_addr_dummy_receive(BUSDriver *busp, wspi_command_t mode; mode.cmd = cmd; + mode.cfg = SNOR_WSPI_CFG_CMD_ADDR_DATA; + mode.addr = offset; + mode.alt = 0U; mode.dummy = dummy; - mode.cfg = 0U | -#if SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI1L - WSPI_CFG_CMD_MODE_ONE_LINE | - WSPI_CFG_ADDR_MODE_ONE_LINE | - WSPI_CFG_DATA_MODE_ONE_LINE; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI2L - WSPI_CFG_CMD_MODE_TWO_LINES | - WSPI_CFG_ADDR_MODE_TWO_LINES | - WSPI_CFG_DATA_MODE_TWO_LINES; -#elif SNOR_BUS_MODE == SNOR_BUS_MODE_WSPI4L - WSPI_CFG_CMD_MODE_FOUR_LINES | - WSPI_CFG_ADDR_MODE_FOUR_LINES | - WSPI_CFG_DATA_MODE_FOUR_LINES; -#else - WSPI_CFG_CMD_MODE_EIGHT_LINES | - WSPI_CFG_ADDR_MODE_EIGHT_LINES | - WSPI_CFG_DATA_MODE_EIGHT_LINES; -#endif - - /* Handling 32 bits addressing. - TODO: Address size should come from upper levels.*/ - if ((cmd & SNOR_BUS_CMD_EXTENDED_ADDRESSING) == 0) { - mode .cfg |= WSPI_CFG_ADDR_SIZE_24; - } - else { - mode .cfg |= WSPI_CFG_ADDR_SIZE_32; - } - - mode.addr = offset; - mode.alt = 0U; wspiReceive(busp, &mode, n, p); } -#endif /* SNOR_BUS_MODE != SNOR_BUS_MODE_SPI */ +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ /** * @brief Initializes an instance. @@ -812,7 +672,7 @@ void snorStop(SNORDriver *devp) { } } -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) || defined(__DOXYGEN__) +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) #if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__) /** * @brief Enters the memory Mapping mode. @@ -862,6 +722,6 @@ void snorMemoryUnmap(SNORDriver *devp) { bus_release(devp->config->busp); } #endif /* WSPI_SUPPORTS_MEMMAP == TRUE */ -#endif /* SNOR_BUS_MODE != SNOR_BUS_MODE_SPI */ +#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */ /** @} */ diff --git a/os/hal/lib/complex/serial_nor/hal_serial_nor.h b/os/hal/lib/complex/serial_nor/hal_serial_nor.h index 6be8e8e0c..cb2451a6b 100644 --- a/os/hal/lib/complex/serial_nor/hal_serial_nor.h +++ b/os/hal/lib/complex/serial_nor/hal_serial_nor.h @@ -36,15 +36,10 @@ * @name Bus interface modes. * @{ */ -#define SNOR_BUS_MODE_SPI 0U -#define SNOR_BUS_MODE_WSPI1L 1U -#define SNOR_BUS_MODE_WSPI2L 2U -#define SNOR_BUS_MODE_WSPI4L 4U -#define SNOR_BUS_MODE_WSPI8L 8U +#define SNOR_BUS_DRIVER_SPI 0U +#define SNOR_BUS_DRIVER_WSPI 1U /** @} */ -#define SNOR_BUS_CMD_EXTENDED_ADDRESSING 0x80000000U - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -56,8 +51,8 @@ /** * @brief Physical transport interface. */ -#if !defined(SNOR_BUS_MODE) || defined(__DOXYGEN__) -#define SNOR_BUS_MODE SNOR_BUS_MODE_WSPI4L +#if !defined(SNOR_BUS_DRIVER) || defined(__DOXYGEN__) +#define SNOR_BUS_DRIVER SNOR_BUS_DRIVER_WSPI #endif /** @@ -77,12 +72,14 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) || defined(__DOXYGEN__) +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_SPI) || defined(__DOXYGEN__) +#define BUSConfig SPIConfig +#define BUSDriver SPIDriver +#elif SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI #define BUSConfig WSPIConfig #define BUSDriver WSPIDriver #else -#define BUSConfig SPIConfig -#define BUSDriver SPIDriver +#error "invalid SNOR_BUS_DRIVER setting" #endif /*===========================================================================*/ @@ -181,7 +178,7 @@ extern "C" { void snorObjectInit(SNORDriver *devp); void snorStart(SNORDriver *devp, const SNORConfig *config); void snorStop(SNORDriver *devp); -#if (SNOR_BUS_MODE != SNOR_BUS_MODE_SPI) || defined(__DOXYGEN__) +#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) || defined(__DOXYGEN__) #if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__) void snorMemoryMap(SNORDriver *devp, uint8_t ** addrp); void snorMemoryUnmap(SNORDriver *devp); -- cgit v1.2.3