From 211dcdd26d5b6355ac217832746b2c2b27a48522 Mon Sep 17 00:00:00 2001 From: isiora Date: Sun, 22 Oct 2017 21:51:29 +0000 Subject: Reintegrate sama5d2_dev branch git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10878 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h | 135 +++++++++++++++++++++ os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h | 32 +++-- os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h | 8 +- .../ext/ARM/CMSIS/Core_A/Include/system_ARMCA5.h | 65 ++++++++++ .../ARM/compilers/GCC/mk/startup_sama5d2.mk | 3 +- os/common/startup/ARM/devices/SAMA5D2/armparams.h | 31 +++++ os/common/startup/ARM/devices/SAMA5D2/boot.S | 55 ++++++--- os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h | 63 ++++++++-- 8 files changed, 355 insertions(+), 37 deletions(-) create mode 100644 os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h create mode 100644 os/common/ext/ARM/CMSIS/Core_A/Include/system_ARMCA5.h (limited to 'os/common') diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h b/os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h new file mode 100644 index 000000000..02d80d2b9 --- /dev/null +++ b/os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file ARMCA5.h + * @brief CMSIS Cortex-A5 Core Peripheral Access Layer Header File + * @version V1.00 + * @data 16 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARMCA5_H__ +#define __ARMCA5_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/****** SGI Interrupts Numbers ****************************************/ + SGI0_IRQn = 0, + SGI1_IRQn = 1, + SGI2_IRQn = 2, + SGI3_IRQn = 3, + SGI4_IRQn = 4, + SGI5_IRQn = 5, + SGI6_IRQn = 6, + SGI7_IRQn = 7, + SGI8_IRQn = 8, + SGI9_IRQn = 9, + SGI10_IRQn = 10, + SGI11_IRQn = 11, + SGI12_IRQn = 12, + SGI13_IRQn = 13, + SGI14_IRQn = 14, + SGI15_IRQn = 15, + +/****** Cortex-A5 Processor Exceptions Numbers ****************************************/ + GlobalTimer_IRQn = 27, /*!< Global Timer Interrupt */ + PrivTimer_IRQn = 29, /*!< Private Timer Interrupt */ + PrivWatchdog_IRQn = 30, /*!< Private Watchdog Interrupt */ + +/****** Platform Exceptions Numbers ***************************************************/ + Watchdog_IRQn = 32, /*!< SP805 Interrupt */ + Timer0_IRQn = 34, /*!< SP804 Interrupt */ + Timer1_IRQn = 35, /*!< SP804 Interrupt */ + RTClock_IRQn = 36, /*!< PL031 Interrupt */ + UART0_IRQn = 37, /*!< PL011 Interrupt */ + UART1_IRQn = 38, /*!< PL011 Interrupt */ + UART2_IRQn = 39, /*!< PL011 Interrupt */ + UART3_IRQn = 40, /*!< PL011 Interrupt */ + MCI0_IRQn = 41, /*!< PL180 Interrupt (1st) */ + MCI1_IRQn = 42, /*!< PL180 Interrupt (2nd) */ + AACI_IRQn = 43, /*!< PL041 Interrupt */ + Keyboard_IRQn = 44, /*!< PL050 Interrupt */ + Mouse_IRQn = 45, /*!< PL050 Interrupt */ + CLCD_IRQn = 46, /*!< PL111 Interrupt */ + Ethernet_IRQn = 47, /*!< SMSC_91C111 Interrupt */ + VFS2_IRQn = 73, /*!< VFS2 Interrupt */ +} IRQn_Type; + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +/* Peripheral and RAM base address */ +#define VE_A5_MP_FLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ +#define VE_A5_MP_FLASH_BASE1 (0x08000000UL) /*!< (FLASH1 ) Base Address */ +#define VE_A5_MP_PERIPH_BASE (0x18000000UL) /*!< (Peripheral) Base Address */ +#define VE_A5_MP_SRAM_BASE (0x2E000000UL) /*!< (SRAM ) Base Address */ +#define VE_A5_MP_DRAM_BASE (0x80000000UL) /*!< (DRAM ) Base Address */ +#define VE_A5_MP_VRAM_BASE (0x18000000UL) /*!< (VRAM ) Base Address */ +#define VE_A5_MP_ETHERNET_BASE (0x02000000UL + VE_A5_MP_PERIPH_BASE) /*!< (ETHERNET ) Base Address */ +#define VE_A5_MP_USB_BASE (0x03000000UL + VE_A5_MP_PERIPH_BASE) /*!< (USB ) Base Address */ +#define VE_A5_MP_DAP_BASE (0x1C000000UL) /*!< (DAP ) Base Address */ +#define VE_A5_MP_SYSTEM_REG_BASE (0x00010000UL + 0x1C000000UL) /*!< (SYSTEM REG) Base Address */ +#define VE_A5_MP_SERIAL_BASE (0x00030000UL + 0x1C000000UL) /*!< (SERIAL ) Base Address */ +#define VE_A5_MP_AACI_BASE (0x00040000UL + 0x1C000000UL) /*!< (AACI ) Base Address */ +#define VE_A5_MP_MMCI_BASE (0x00050000UL + 0x1C000000UL) /*!< (MMCI ) Base Address */ +#define VE_A5_MP_KMI0_BASE (0x00060000UL + 0x1C000000UL) /*!< (KMI0 ) Base Address */ +#define VE_A5_MP_UART_BASE (0x00090000UL + 0x1C000000UL) /*!< (UART ) Base Address */ +#define VE_A5_MP_WDT_BASE (0x000F0000UL + 0x1C000000UL) /*!< (WDT ) Base Address */ +#define VE_A5_MP_TIMER_BASE (0x00110000UL + 0x1C000000UL) /*!< (TIMER ) Base Address */ +#define VE_A5_MP_DVI_BASE (0x00160000UL + 0x1C000000UL) /*!< (DVI ) Base Address */ +#define VE_A5_MP_RTC_BASE (0x00170000UL + 0x1C000000UL) /*!< (RTC ) Base Address */ +#define VE_A5_MP_UART4_BASE (0x001B0000UL + 0x1C000000UL) /*!< (UART4 ) Base Address */ +#define VE_A5_MP_CLCD_BASE (0x001F0000UL + 0x1C000000UL) /*!< (CLCD ) Base Address */ +#define VE_A5_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + 0x2C000000UL) /*!< (GIC DIST ) Base Address */ +#define VE_A5_MP_GIC_INTERFACE_BASE (0x00000100UL + 0x2C000000UL) /*!< (GIC CPU IF) Base Address */ +#define VE_A5_MP_PRIVATE_TIMER (0x00000600UL + 0x2C000000UL) /*!< (PTIM ) Base Address */ +#define GIC_DISTRIBUTOR_BASE VE_A5_MP_GIC_DISTRIBUTOR_BASE +#define GIC_INTERFACE_BASE VE_A5_MP_GIC_INTERFACE_BASE +#define TIMER_BASE VE_A5_MP_PRIVATE_TIMER + +//The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache. +//Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort. +#define VE_A5_MP_PL310_BASE (0x2C0F0000UL) /*!< (L2C-310 ) Base Address */ +#define L2C_310_BASE VE_A5_MP_PL310_BASE + +/* -------- Configuration of the Cortex-A5 Processor and Core Peripherals ------- */ +#define __CA_REV 0x0000U /* Core revision r0p0 */ +#define __CORTEX_A 5U /* Cortex-A5 Core */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 1U /* TIM present */ +#define __L2C_PRESENT 0U /* L2C present */ + +#include "core_ca.h" +#include + +#ifdef __cplusplus +} +#endif + +#endif // __ARMCA5_H__ diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h index 4e95b82fb..634558987 100644 --- a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h +++ b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h @@ -558,7 +558,9 @@ __STATIC_INLINE void __set_CPACR(uint32_t cpacr) /** \brief Get CBAR \return Configuration Base Address register value */ -__STATIC_INLINE uint32_t __get_CBAR() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t __get_CBAR() { +__STATIC_INLINE uint32_t __get_CBAR(void) { uint32_t result; __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result)); return result; @@ -570,7 +572,9 @@ __STATIC_INLINE uint32_t __get_CBAR() { \return Translation Table Base Register 0 value */ -__STATIC_INLINE uint32_t __get_TTBR0() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t __get_TTBR0() { +__STATIC_INLINE uint32_t __get_TTBR0(void) { uint32_t result; __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result)); return result; @@ -592,7 +596,9 @@ __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { \return Domain Access Control Register value */ -__STATIC_INLINE uint32_t __get_DACR() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t __get_DACR() { +__STATIC_INLINE uint32_t __get_DACR(void) { uint32_t result; __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result)); return result; @@ -622,7 +628,9 @@ __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) /** \brief Get SCTLR \return System Control Register value */ -__STATIC_INLINE uint32_t __get_SCTLR() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t __get_SCTLR() { +__STATIC_INLINE uint32_t __get_SCTLR(void) { uint32_t result; __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result)); return result; @@ -709,7 +717,9 @@ __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) { \return CNTP_TVAL Register value */ -__STATIC_INLINE uint32_t __get_CNTP_TVAL() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t __get_CNTP_TVAL() { +__STATIC_INLINE uint32_t __get_CNTP_TVAL(void) { uint32_t result; __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result)); return result; @@ -728,7 +738,9 @@ __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) { /** \brief Get CNTP_CTL register \return CNTP_CTL Register value */ -__STATIC_INLINE uint32_t __get_CNTP_CTL() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t __get_CNTP_CTL() { +__STATIC_INLINE uint32_t __get_CNTP_CTL(void) { uint32_t result; __ASM volatile("MRC p15, 0, %0, c14, c2, 1" : "=r"(result)); return result; @@ -792,7 +804,9 @@ __STATIC_INLINE void __set_CCSIDR(uint32_t value) { /** \brief Get CCSIDR \return CCSIDR Register value */ -__STATIC_INLINE uint32_t __get_CCSIDR() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t __get_CCSIDR() { +__STATIC_INLINE uint32_t __get_CCSIDR(void) { uint32_t result; __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result)); return result; @@ -801,7 +815,9 @@ __STATIC_INLINE uint32_t __get_CCSIDR() { /** \brief Get CLIDR \return CLIDR Register value */ -__STATIC_INLINE uint32_t __get_CLIDR() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t __get_CLIDR() { +__STATIC_INLINE uint32_t __get_CLIDR(void) { uint32_t result; __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result)); return result; diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h b/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h index a80150298..1ef78b584 100644 --- a/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h +++ b/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h @@ -1495,7 +1495,9 @@ __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) { /** \brief Get the load value from timers LOAD register. * \return Timer_Type::LOAD */ -__STATIC_INLINE uint32_t PTIM_GetLoadValue() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t PTIM_GetLoadValue() { +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) { return(PTIM->LOAD); } @@ -1508,7 +1510,9 @@ __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) { /** \brief Get current counter value from timers COUNTER register. * \result Timer_Type::COUNTER */ -__STATIC_INLINE uint32_t PTIM_GetCurrentValue() { +/* CHIBIOS FIX */ +//__STATIC_INLINE uint32_t PTIM_GetCurrentValue() { +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) { return(PTIM->COUNTER); } diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/system_ARMCA5.h b/os/common/ext/ARM/CMSIS/Core_A/Include/system_ARMCA5.h new file mode 100644 index 000000000..7d48ceb91 --- /dev/null +++ b/os/common/ext/ARM/CMSIS/Core_A/Include/system_ARMCA5.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * @file system_ARMCA5.h + * @brief CMSIS Device System Header File for ARM Cortex-A Device Series + * @version V1.00 + * @date 16 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_ARMCA5_H +#define __SYSTEM_ARMCA5_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_ARMCA5_H */ diff --git a/os/common/startup/ARM/compilers/GCC/mk/startup_sama5d2.mk b/os/common/startup/ARM/compilers/GCC/mk/startup_sama5d2.mk index a646ca5fd..8ffb23281 100755 --- a/os/common/startup/ARM/compilers/GCC/mk/startup_sama5d2.mk +++ b/os/common/startup/ARM/compilers/GCC/mk/startup_sama5d2.mk @@ -5,6 +5,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARM/devices/SAMA5D2/boot.S \ $(CHIBIOS)/os/common/startup/ARM/compilers/GCC/vectors.S \ $(CHIBIOS)/os/common/startup/ARM/compilers/GCC/crt0.S -STARTUPINC = ${CHIBIOS}/os/common/startup/ARM/devices/SAMA5D2 +STARTUPINC = ${CHIBIOS}/os/common/startup/ARM/devices/SAMA5D2 \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core_A/Include STARTUPLD = ${CHIBIOS}/os/common/startup/ARM/compilers/GCC/ld diff --git a/os/common/startup/ARM/devices/SAMA5D2/armparams.h b/os/common/startup/ARM/devices/SAMA5D2/armparams.h index 9e0ba1210..29e6613fe 100755 --- a/os/common/startup/ARM/devices/SAMA5D2/armparams.h +++ b/os/common/startup/ARM/devices/SAMA5D2/armparams.h @@ -33,6 +33,11 @@ */ #define ARM_CORE ARM_CORE_CORTEX_A5 +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 5 + /** * @brief Thumb-capable. */ @@ -43,18 +48,44 @@ */ #define ARM_SUPPORTS_THUMB2 1 +/** + * @brief VFPv4-D16 FPU. + */ +#define TARGET_FEATURE_EXTENSION_REGISTER_COUNT 16 + /** * @brief Implementation of the wait-for-interrupt state enter. */ #define ARM_WFI_IMPL asm volatile ("wfi") #if !defined(_FROM_ASM_) || defined(__DOXYGEN__) +/* If the device type is not externally defined, for example from the Makefile, + then a file named board.h is included. This file must contain a device + definition compatible with the vendor include file.*/ +#if !defined (SAMA5D21) && !defined (SAMA5D22) && !defined (SAMA5D23) && \ + !defined (SAMA5D24) && !defined (SAMA5D25) && !defined (SAMA5D26) && \ + !defined (SAMA5D27) && !defined (SAMA5D28) +#include "board.h" +#endif + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "sama5d2x.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_A +#error "CMSIS __CORTEX_A mismatch" +#endif + /** * @brief Address of the IRQ vector register in the interrupt controller. */ #define ARM_IRQ_VECTOR_REG 0xF803C010U #else #define ARM_IRQ_VECTOR_REG 0xF803C010 + #endif #endif /* ARMPARAMS_H */ diff --git a/os/common/startup/ARM/devices/SAMA5D2/boot.S b/os/common/startup/ARM/devices/SAMA5D2/boot.S index d507ea8b4..2de5be0f2 100644 --- a/os/common/startup/ARM/devices/SAMA5D2/boot.S +++ b/os/common/startup/ARM/devices/SAMA5D2/boot.S @@ -23,9 +23,11 @@ */ #if !defined(__DOXYGEN__) - .set AIC_REDIR_KEY, 0x5B6C0E26 << 1 - .set SFR_SN1, 0xF8030050 - .set SFR_AICREDIR, 0xF8030054 + .set AIC_REDIR_KEY, 0x5B6C0E26 << 1 + .set SFR_SN1, 0xF8030050 + .set SFR_AICREDIR, 0xF8030054 + .set SFR_L2CC_HRAMC, 0xF8030058 + .set L2CC_CR, 0x00A00100 .section .boot .code 32 @@ -35,22 +37,45 @@ */ .global Boot_Handler Boot_Handler: - /* - * Set VBAR to system vectors table - */ - ldr r0, =_start - mcr p15, 0, r0, c12, c0, 0 + /* + * Set VBAR to system vectors table + */ + ldr r0, =_start + mcr p15, 0, r0, c12, c0, 0 /* * Do not redirect secure interrupts to AIC */ - ldr r0, =AIC_REDIR_KEY + ldr r0, =AIC_REDIR_KEY ldr r1, =SFR_SN1 - ldr r1, [r1] - eor r0, r0, r1 - bic r0, r0, #0x1 - ldr r1, =SFR_AICREDIR - str r0, [r1] - b Reset_Handler + ldr r1, [r1] + eor r0, r0, r1 + bic r0, r0, #0x1 + ldr r1, =SFR_AICREDIR + str r0, [r1] + /* + * Reset SCTLR Settings + */ + mrc p15, 0, r0, c1, c0, 0 // Read CP15 System Control register + bic r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 // Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) // Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 // Write value back to CP15 System Control register + isb + /* + * Turn off L2Cache + */ + bic r0, r0, #0x1 + ldr r1, =L2CC_CR + str r0, [r1] + /* + * Configure the L2 cache to be used as an internal SRAM + */ + bic r0, r0, #0x1 + ldr r1, =SFR_L2CC_HRAMC + str r0, [r1] + b Reset_Handler #endif /* !defined(__DOXYGEN__) */ /** @} */ diff --git a/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h b/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h index c00f6b8fd..86123a031 100644 --- a/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h +++ b/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h @@ -32,16 +32,7 @@ #include #include #include - -#ifdef __cplusplus -#define __I volatile /**< Defines 'read-only' permissions */ -#else -#define __I volatile const /**< Defines 'read-only' permissions */ -#endif - -#define __O volatile /**< Defines 'write-only' permissions */ -#define __IO volatile /**< Defines 'read/write' permissions */ - +#include "ARMCA5.h" /** * @brief SAMA5D2 Family */ @@ -70,6 +61,7 @@ #else #error "Please select first the target SAMA5D2x device used in your application (in sama5d2x.h file)" #endif + /**@} */ /** @@ -317,7 +309,56 @@ #define ID_RXLP_MSK (1 << (ID_RXLP & 0x1F)) #define ID_CHIPID_MSK (1 << (ID_CHIPID & 0x1F)) -/**@} */ +/* MASTER MATRIX ID DEFINITION FOR SAMA5D2x */ + +#define H64MX_MASTER_BRIDGE_FROM_AXI 0 +#define H64MX_MASTER_XDMAC0_0 1 +#define H64MX_MASTER_XDMAC0_1 2 +#define H64MX_MASTER_XDMAC1_0 3 +#define H64MX_MASTER_XDMAC1_1 4 +#define H64MX_MASTER_LCDC_DMA_0 5 +#define H64MX_MASTER_LCDC_DMA_1 6 +#define H64MX_MASTER_SDMMC0 7 +#define H64MX_MASTER_SDMMC1 8 +#define H64MX_MASTER_ISC_DMA 9 +#define H64MX_MASTER_AESB 10 +#define H64MX_MASTER_BRIDGE_H64MX 11 + +#define H32MX_MASTER_BRIDGE_H32MX 0 +#define H32MX_MASTER_ICM 1 +#define H32MX_MASTER_UHPHS_EHCI_DMA 2 +#define H32MX_MASTER_UHPHS_OHCI_DMA 3 +#define H32MX_MASTER_UDPHS_DMA 4 +#define H32MX_MASTER_GMAC_DMA 5 +#define H32MX_MASTER_CAN0_DMA 6 +#define H32MX_MASTER_CAN1_DMA 7 + + /* SLAVE MATRIX ID DEFINITIONS FOR SAMA5D2x */ + + #define H64MX_SLAVE_BRIDGE_H32MX 0 + #define H64MX_SLAVE_APB 1 + #define H64MX_SLAVE_SDMMC 1 + #define H64MX_SLAVE_DDR_PORT0 2 + #define H64MX_SLAVE_DDR_PORT1 3 + #define H64MX_SLAVE_DDR_PORT2 4 + #define H64MX_SLAVE_DDR_PORT3 5 + #define H64MX_SLAVE_DDR_PORT4 6 + #define H64MX_SLAVE_DDR_PORT5 7 + #define H64MX_SLAVE_DDR_PORT6 8 + #define H64MX_SLAVE_DDR_PORT7 9 + #define H64MX_SLAVE_SRAM 10 + #define H64MX_SLAVE_L2C_SRAM 11 + #define H64MX_SLAVE_QSPI0 12 + #define H64MX_SLAVE_QSPI1 13 + #define H64MX_SLAVE_AESB 14 + + #define H32MX_SLAVE_BRIDGE_H64MX 0 + #define H32MX_SLAVE_APB0 1 + #define H32MX_SLAVE_APB1 2 + #define H32MX_SLAVE_EBI 3 + #define H32MX_SLAVE_NFC_CMD 3 + #define H32MX_SLAVE_NFC_SRAM 4 + #define H32MX_SLAVE_USB 5 #ifdef __cplusplus } -- cgit v1.2.3