From 13e854961f71c2d06d67b66ee2ab8a5c8dde9b61 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Tue, 10 Jul 2018 12:02:55 +0000 Subject: Missing files. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12156 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- .../ARMCMx/compilers/LLVM/ld/STM32F401xE.ld | 465 +++++++++++++++++++++ .../ARMCMx/compilers/LLVM/mk/startup_stm32f4xx.mk | 18 + 2 files changed, 483 insertions(+) create mode 100644 os/common/startup/ARMCMx/compilers/LLVM/ld/STM32F401xE.ld create mode 100644 os/common/startup/ARMCMx/compilers/LLVM/mk/startup_stm32f4xx.mk (limited to 'os/common/startup/ARMCMx/compilers') diff --git a/os/common/startup/ARMCMx/compilers/LLVM/ld/STM32F401xE.ld b/os/common/startup/ARMCMx/compilers/LLVM/ld/STM32F401xE.ld new file mode 100644 index 000000000..b1ac10141 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/LLVM/ld/STM32F401xE.ld @@ -0,0 +1,465 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F401xE memory setup. + */ +MEMORY +{ + flash0 : org = 0x08000000, len = 512k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 96k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +__ram0_start__ = ORIGIN(ram0); +__ram0_size__ = LENGTH(ram0); +__ram0_end__ = __ram0_start__ + __ram0_size__; +__ram1_start__ = ORIGIN(ram1); +__ram1_size__ = LENGTH(ram1); +__ram1_end__ = __ram1_start__ + __ram1_size__; +__ram2_start__ = ORIGIN(ram2); +__ram2_size__ = LENGTH(ram2); +__ram2_end__ = __ram2_start__ + __ram2_size__; +__ram3_start__ = ORIGIN(ram3); +__ram3_size__ = LENGTH(ram3); +__ram3_end__ = __ram3_start__ + __ram3_size__; +__ram4_start__ = ORIGIN(ram4); +__ram4_size__ = LENGTH(ram4); +__ram4_end__ = __ram4_start__ + __ram4_size__; +__ram5_start__ = ORIGIN(ram5); +__ram5_size__ = LENGTH(ram5); +__ram5_end__ = __ram5_start__ + __ram5_size__; +__ram6_start__ = ORIGIN(ram6); +__ram6_size__ = LENGTH(ram6); +__ram6_end__ = __ram6_start__ + __ram6_size__; +__ram7_start__ = ORIGIN(ram7); +__ram7_size__ = LENGTH(ram7); +__ram7_end__ = __ram7_start__ + __ram7_size__; + +__flash0_start__ = ORIGIN(flash0); +__flash0_size__ = LENGTH(flash0); +__flash0_end__ = __flash0_start__ + __flash0_size__; +__flash1_start__ = ORIGIN(flash1); +__flash1_size__ = LENGTH(flash1); +__flash1_end__ = __flash1_start__ + __flash1_size__; +__flash2_start__ = ORIGIN(flash2); +__flash2_size__ = LENGTH(flash2); +__flash2_end__ = __flash2_start__ + __flash2_size__; +__flash3_start__ = ORIGIN(flash3); +__flash3_size__ = LENGTH(flash3); +__flash3_end__ = __flash3_start__ + __flash3_size__; +__flash4_start__ = ORIGIN(flash4); +__flash4_size__ = LENGTH(flash4); +__flash4_end__ = __flash4_start__ + __flash4_size__; +__flash5_start__ = ORIGIN(flash5); +__flash5_size__ = LENGTH(flash5); +__flash5_end__ = __flash5_start__ + __flash5_size__; +__flash6_start__ = ORIGIN(flash6); +__flash6_size__ = LENGTH(flash6); +__flash6_end__ = __flash6_start__ + __flash6_size__; +__flash7_start__ = ORIGIN(flash7); +__flash7_size__ = LENGTH(flash7); +__flash7_end__ = __flash7_start__ + __flash7_size__; + +ENTRY(Reset_Handler) + +SECTIONS +{ + /* Special section for exceptions stack.*/ + .mstack (NOLOAD) : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + } > ram0 + + /* Special section for process stack.*/ + .pstack (NOLOAD) : + { + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram0 + + .vectors : ALIGN(16) + { + KEEP(*(.vectors)) + } > flash0 + + .xtors : ALIGN(4) + { + __init_array_start = .; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = .; + __fini_array_start = .; + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + __fini_array_end = .; + } > flash0 + + .text : ALIGN(16) + { + __text_base = .; + *(.text) + *(.text.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + __text_end = .; + } > flash0 + + .rodata : ALIGN(4) + { + __rodata_base__ = .; + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + __rodata_end__ = .; + } > flash0 + + .data : ALIGN(4) + { + . = ALIGN(4); + PROVIDE(_textdata = LOADADDR(.data)); + PROVIDE(_data = .); + _textdata_start = LOADADDR(.data); + _data_start = .; + *(.data) + *(.data.*) + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + _data_end = .; + } > ram0 AT > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > flash0 + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash0 + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash0 + + .bss (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + _bss_start = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + _bss_end = .; + PROVIDE(end = .); + } > ram0 + + .ram0_init : ALIGN(4) + { + . = ALIGN(4); + __ram0_init_text__ = LOADADDR(.ram0_init); + __ram0_init__ = .; + KEEP(*(.ram0_init)) + KEEP(*(.ram0_init.*)) + . = ALIGN(4); + } > ram0 AT > flash0 + + .ram0 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram0_clear__ = .; + *(.ram0_clear) + *(.ram0_clear.*) + . = ALIGN(4); + __ram0_noinit__ = .; + *(.ram0) + *(.ram0.*) + . = ALIGN(4); + __ram0_free__ = .; + } > ram0 + + .ram1_init : ALIGN(4) + { + . = ALIGN(4); + __ram1_init_text__ = LOADADDR(.ram1_init); + __ram1_init__ = .; + KEEP(*(.ram1_init)) + KEEP(*(.ram1_init.*)) + . = ALIGN(4); + } > ram1 AT > flash0 + + .ram1 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram1_clear__ = .; + *(.ram1_clear) + *(.ram1_clear.*) + . = ALIGN(4); + __ram1_noinit__ = .; + *(.ram1) + *(.ram1.*) + . = ALIGN(4); + __ram1_free__ = .; + } > ram1 + + .ram2_init : ALIGN(4) + { + . = ALIGN(4); + __ram2_init_text__ = LOADADDR(.ram2_init); + __ram2_init__ = .; + KEEP(*(.ram2_init)) + KEEP(*(.ram2_init.*)) + . = ALIGN(4); + } > ram2 AT > flash0 + + .ram2 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram2_clear__ = .; + *(.ram2_clear) + *(.ram2_clear.*) + . = ALIGN(4); + __ram2_noinit__ = .; + *(.ram2) + *(.ram2.*) + . = ALIGN(4); + __ram2_free__ = .; + } > ram2 + + .ram3_init : ALIGN(4) + { + . = ALIGN(4); + __ram3_init_text__ = LOADADDR(.ram3_init); + __ram3_init__ = .; + KEEP(*(.ram3_init)) + KEEP(*(.ram3_init.*)) + . = ALIGN(4); + } > ram3 AT > flash0 + + .ram3 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram3_clear__ = .; + *(.ram3_clear) + *(.ram3_clear.*) + . = ALIGN(4); + __ram3_noinit__ = .; + *(.ram3) + *(.ram3.*) + . = ALIGN(4); + __ram3_free__ = .; + } > ram3 + + .ram4_init : ALIGN(4) + { + . = ALIGN(4); + __ram4_init_text__ = LOADADDR(.ram4_init); + __ram4_init__ = .; + KEEP(*(.ram4_init)) + KEEP(*(.ram4_init.*)) + . = ALIGN(4); + } > ram4 AT > flash0 + + .ram4 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram4_clear__ = .; + *(.ram4_clear) + *(.ram4_clear.*) + . = ALIGN(4); + __ram4_noinit__ = .; + *(.ram4) + *(.ram4.*) + . = ALIGN(4); + __ram4_free__ = .; + } > ram4 + + .ram5_init : ALIGN(4) + { + . = ALIGN(4); + __ram5_init_text__ = LOADADDR(.ram5_init); + __ram5_init__ = .; + KEEP(*(.ram5_init)) + KEEP(*(.ram5_init.*)) + . = ALIGN(4); + } > ram5 AT > flash0 + + .ram5 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram5_clear__ = .; + *(.ram5_clear) + *(.ram5_clear.*) + . = ALIGN(4); + __ram5_noinit__ = .; + *(.ram5) + *(.ram5.*) + . = ALIGN(4); + __ram5_free__ = .; + } > ram5 + + .ram6_init : ALIGN(4) + { + . = ALIGN(4); + __ram6_init_text__ = LOADADDR(.ram6_init); + __ram6_init__ = .; + KEEP(*(.ram6_init)) + KEEP(*(.ram6_init.*)) + . = ALIGN(4); + } > ram6 AT > flash0 + + .ram6 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram6_clear__ = .; + *(.ram6_clear) + *(.ram6_clear.*) + . = ALIGN(4); + __ram6_noinit__ = .; + *(.ram6) + *(.ram6.*) + . = ALIGN(4); + __ram6_free__ = .; + } > ram6 + + .ram7_init : ALIGN(4) + { + . = ALIGN(4); + __ram7_init_text__ = LOADADDR(.ram7_init); + __ram7_init__ = .; + KEEP(*(.ram7_init)) + KEEP(*(.ram7_init.*)) + . = ALIGN(4); + } > ram7 AT > flash0 + + .ram7 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram7_clear__ = .; + *(.ram7_clear) + *(.ram7_clear.*) + . = ALIGN(4); + __ram7_noinit__ = .; + *(.ram7) + *(.ram7.*) + . = ALIGN(4); + __ram7_free__ = .; + } > ram7 + + .flash0 : ALIGN(4) + { + __flash0_init__ = .; + KEEP(*(.flash0_init)) + KEEP(*(.flash0_init.*)) + __flash0_free__ = .; + } > flash0 + + .flash1 : ALIGN(4) + { + __flash1_init__ = .; + KEEP(*(.flash1_init)) + KEEP(*(.flash1_init.*)) + __flash1_free__ = .; + } > flash1 + + .flash2 : ALIGN(4) + { + __flash2_init__ = .; + KEEP(*(.flash2_init)) + KEEP(*(.flash2_init.*)) + __flash2_free__ = .; + } > flash2 + + .flash3 : ALIGN(4) + { + __flash3_init__ = .; + KEEP(*(.flash3_init)) + KEEP(*(.flash3_init.*)) + __flash3_free__ = .; + } > flash3 + + .flash4 : ALIGN(4) + { + __flash4_init__ = .; + KEEP(*(.flash4_init)) + KEEP(*(.flash4_init.*)) + __flash4_free__ = .; + } > flash4 + + .flash5 : ALIGN(4) + { + __flash5_init__ = .; + KEEP(*(.flash5_init)) + KEEP(*(.flash5_init.*)) + __flash5_free__ = .; + } > flash5 + + .flash6 : ALIGN(4) + { + __flash6_init__ = .; + KEEP(*(.flash6_init)) + KEEP(*(.flash6_init.*)) + __flash6_free__ = .; + } > flash6 + + .flash7 : ALIGN(4) + { + __flash7_init__ = .; + KEEP(*(.flash7_init)) + KEEP(*(.flash7_init.*)) + __flash7_free__ = .; + } > flash7 + + /* The default heap uses the (statically) unused part of a RAM section.*/ + .heap (NOLOAD) : + { + . = ALIGN(8); + __heap_base__ = .; + . = ORIGIN(ram0) + LENGTH(ram0); + __heap_end__ = .; + } > ram0 +} diff --git a/os/common/startup/ARMCMx/compilers/LLVM/mk/startup_stm32f4xx.mk b/os/common/startup/ARMCMx/compilers/LLVM/mk/startup_stm32f4xx.mk new file mode 100644 index 000000000..c20ba0938 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/LLVM/mk/startup_stm32f4xx.mk @@ -0,0 +1,18 @@ +# List of the ChibiOS generic STM32F4xx startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/LLVM \ + $(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32F4xx \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS)/os/common/ext/ST/STM32F4xx + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/LLVM/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) -- cgit v1.2.3