From 7dc3e6a0f0d660aa2695f46ef4e6ccac4f6553de Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 4 Jun 2013 12:11:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5812 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/PPC-SPC564A-GCC/mcuconf.h | 63 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/PPC-SPC564A-GCC/mcuconf.h b/demos/PPC-SPC564A-GCC/mcuconf.h index 9414d1f41..0683912f9 100644 --- a/demos/PPC-SPC564A-GCC/mcuconf.h +++ b/demos/PPC-SPC564A-GCC/mcuconf.h @@ -53,7 +53,27 @@ #define SPC5_ADC_USE_ADC1_Q3 FALSE #define SPC5_ADC_USE_ADC1_Q4 FALSE #define SPC5_ADC_USE_ADC1_Q5 FALSE -#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5) +#define SPC5_ADC_FIFO0_DMA_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_PRIO 12 +#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12 +#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12 +#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(10) +#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE, \ + ADC_PUDCR_NONE} /* * SERIAL driver system settings. @@ -64,3 +84,44 @@ #define SPC5_ESCIA_PRIORITY 8 #define SPC5_ESCIB_PRIORITY 8 #define SPC5_ESCIC_PRIORITY 8 + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI1 TRUE +#define SPC5_SPI_USE_DSPI2 TRUE +#define SPC5_SPI_USE_DSPI3 TRUE +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_DMA_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() -- cgit v1.2.3