From 646d8a2376e3d476a3d00edb665770596fb252f6 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 5 Dec 2009 14:59:37 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1376
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 demos/ARMCM3-STM32F103-FATFS-GCC/board.h | 44 +-------------------------------
 demos/ARMCM3-STM32F103-GCC/board.h       | 44 +-------------------------------
 2 files changed, 2 insertions(+), 86 deletions(-)

(limited to 'demos')

diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h
index bf04625c5..588ea3c5d 100644
--- a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h
+++ b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h
@@ -21,53 +21,11 @@
 #define _BOARD_H_
 
 /*
- * Uncomment this if you want a 48MHz system clock, else it will be 72MHz.
- */
-//#define SYSCLK_48
-
-/*
- * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
+ * Board frequencies.
  */
 #define LSECLK          32768
 #define HSECLK          8000000
 #define HSICLK          8000000
-#define PLLPRE          1
-#ifdef SYSCLK_48
-  #define PLLMUL        6
-#else
-  #define PLLMUL        9
-#endif
-#define PLLCLK          ((HSECLK / PLLPRE) * PLLMUL)
-#define SYSCLK          PLLCLK
-#define APB1CLK         (SYSCLK / 2)
-#define APB2CLK         (SYSCLK / 2)
-#define AHB1CLK         (SYSCLK / 1)
-
-/*
- * Values derived from the clock settings.
- */
-#define PLLPREBITS      ((PLLPRE - 1) << 17)
-#define PLLMULBITS      ((PLLMUL - 2) << 18)
-#ifdef SYSCLK_48
-  #define USBPREBITS    RCC_CFGR_USBPRE_DIV1_BITS
-  #define FLASHBITS     0x00000011
-#else
-  #define USBPREBITS    RCC_CFGR_USBPRE_DIV1P5_BITS
-  #define FLASHBITS     0x00000012
-#endif
-
-/*
- * Extra definitions for RCC_CR register (missing from the ST header file).
- */
-#define RCC_CR_HSITRIM_RESET_BITS       (0x10 << 3)
-
-/*
- * Extra definitions for RCC_CFGR register (missing from the ST header file).
- */
-#define RCC_CFGR_PLLSRC_HSI_BITS        (0 << 16)
-#define RCC_CFGR_PLLSRC_HSE_BITS        (1 << 16)
-#define RCC_CFGR_USBPRE_DIV1P5_BITS     (0 << 22)
-#define RCC_CFGR_USBPRE_DIV1_BITS       (1 << 22)
 
 /*
  * IO pins assignments.
diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h
index bf04625c5..588ea3c5d 100644
--- a/demos/ARMCM3-STM32F103-GCC/board.h
+++ b/demos/ARMCM3-STM32F103-GCC/board.h
@@ -21,53 +21,11 @@
 #define _BOARD_H_
 
 /*
- * Uncomment this if you want a 48MHz system clock, else it will be 72MHz.
- */
-//#define SYSCLK_48
-
-/*
- * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
+ * Board frequencies.
  */
 #define LSECLK          32768
 #define HSECLK          8000000
 #define HSICLK          8000000
-#define PLLPRE          1
-#ifdef SYSCLK_48
-  #define PLLMUL        6
-#else
-  #define PLLMUL        9
-#endif
-#define PLLCLK          ((HSECLK / PLLPRE) * PLLMUL)
-#define SYSCLK          PLLCLK
-#define APB1CLK         (SYSCLK / 2)
-#define APB2CLK         (SYSCLK / 2)
-#define AHB1CLK         (SYSCLK / 1)
-
-/*
- * Values derived from the clock settings.
- */
-#define PLLPREBITS      ((PLLPRE - 1) << 17)
-#define PLLMULBITS      ((PLLMUL - 2) << 18)
-#ifdef SYSCLK_48
-  #define USBPREBITS    RCC_CFGR_USBPRE_DIV1_BITS
-  #define FLASHBITS     0x00000011
-#else
-  #define USBPREBITS    RCC_CFGR_USBPRE_DIV1P5_BITS
-  #define FLASHBITS     0x00000012
-#endif
-
-/*
- * Extra definitions for RCC_CR register (missing from the ST header file).
- */
-#define RCC_CR_HSITRIM_RESET_BITS       (0x10 << 3)
-
-/*
- * Extra definitions for RCC_CFGR register (missing from the ST header file).
- */
-#define RCC_CFGR_PLLSRC_HSI_BITS        (0 << 16)
-#define RCC_CFGR_PLLSRC_HSE_BITS        (1 << 16)
-#define RCC_CFGR_USBPRE_DIV1P5_BITS     (0 << 22)
-#define RCC_CFGR_USBPRE_DIV1_BITS       (1 << 22)
 
 /*
  * IO pins assignments.
-- 
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