From f7809b2ec0ba18425462345d36c715b7a6250b9c Mon Sep 17 00:00:00 2001 From: Uladzimir Pylinski Date: Mon, 31 Oct 2016 13:38:19 +0000 Subject: STM32F7x. Linker scripts renamed according to ordering information scheme from datasheet. Flash size corrected too. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9892 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM32/RT-STM32F767ZI-NUCLEO144/Makefile | 2 +- demos/STM32/RT-STM32F769I-DISCOVERY/Makefile | 2 +- .../startup/ARMCMx/compilers/GCC/ld/STM32F767Zx.ld | 132 --------------------- .../startup/ARMCMx/compilers/GCC/ld/STM32F769Ix.ld | 132 --------------------- .../startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld | 132 +++++++++++++++++++++ .../startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld | 132 +++++++++++++++++++++ 6 files changed, 266 insertions(+), 266 deletions(-) delete mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/STM32F767Zx.ld delete mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/STM32F769Ix.ld create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld diff --git a/demos/STM32/RT-STM32F767ZI-NUCLEO144/Makefile b/demos/STM32/RT-STM32F767ZI-NUCLEO144/Makefile index 39be534d4..9c93479c1 100644 --- a/demos/STM32/RT-STM32F767ZI-NUCLEO144/Makefile +++ b/demos/STM32/RT-STM32F767ZI-NUCLEO144/Makefile @@ -106,7 +106,7 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F767Zx.ld +LDSCRIPT= $(STARTUPLD)/STM32F76xxI.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/Makefile b/demos/STM32/RT-STM32F769I-DISCOVERY/Makefile index b9f274a5c..4659fbbfc 100644 --- a/demos/STM32/RT-STM32F769I-DISCOVERY/Makefile +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/Makefile @@ -106,7 +106,7 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32F769Ix.ld +LDSCRIPT= $(STARTUPLD)/STM32F76xxI.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F767Zx.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F767Zx.ld deleted file mode 100644 index 5a365ea41..000000000 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F767Zx.ld +++ /dev/null @@ -1,132 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F767Zx generic setup. - * - * RAM0 - Data, Heap. - * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. - * - * Notes: - * BSS is placed in DTCM RAM in order to simplify DMA buffers management. - */ -MEMORY -{ - flash0 : org = 0x08000000, len = 2M /* Flash as AXIM (writable) */ - flash1 : org = 0x00200000, len = 2M /* Flash as ITCM */ - flash2 : org = 0x00000000, len = 0 - flash3 : org = 0x00000000, len = 0 - flash4 : org = 0x00000000, len = 0 - flash5 : org = 0x00000000, len = 0 - flash6 : org = 0x00000000, len = 0 - flash7 : org = 0x00000000, len = 0 - ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20020000, len = 368k /* SRAM1 */ - ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ - ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ - ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* For each data/text section two region are defined, a virtual region - and a load region (_LMA suffix).*/ - -/* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash1); -REGION_ALIAS("VECTORS_FLASH_LMA", flash0); - -/* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash1); -REGION_ALIAS("XTORS_FLASH_LMA", flash0); - -/* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash1); -REGION_ALIAS("TEXT_FLASH_LMA", flash0); - -/* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash0); -REGION_ALIAS("RODATA_FLASH_LMA", flash0); - -/* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash1); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); - -/* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts.*/ -REGION_ALIAS("MAIN_STACK_RAM", ram3); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram3); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram3); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* Stack rules inclusion.*/ -INCLUDE rules_stacks.ld - -/*===========================================================================*/ -/* Custom sections for STM32F7xx. */ -/*===========================================================================*/ - -/* RAM region to be used for nocache segment.*/ -REGION_ALIAS("NOCACHE_RAM", ram3); - -/* RAM region to be used for eth segment.*/ -REGION_ALIAS("ETH_RAM", ram3); - -SECTIONS -{ - /* Special section for non cache-able areas.*/ - .nocache (NOLOAD) : ALIGN(4) - { - __nocache_base__ = .; - *(.nocache) - *(.nocache.*) - *(.bss.__nocache_*) - . = ALIGN(4); - __nocache_end__ = .; - } > NOCACHE_RAM - - /* Special section for Ethernet DMA non cache-able areas.*/ - .eth (NOLOAD) : ALIGN(4) - { - __eth_base__ = .; - *(.eth) - *(.eth.*) - *(.bss.__eth_*) - . = ALIGN(4); - __eth_end__ = .; - } > ETH_RAM -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* Data rules inclusion.*/ -INCLUDE rules_data.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F769Ix.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F769Ix.ld deleted file mode 100644 index 990a8adfa..000000000 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F769Ix.ld +++ /dev/null @@ -1,132 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F769Ix generic setup. - * - * RAM0 - Data, Heap. - * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. - * - * Notes: - * BSS is placed in DTCM RAM in order to simplify DMA buffers management. - */ -MEMORY -{ - flash0 : org = 0x08000000, len = 2M /* Flash as AXIM (writable) */ - flash1 : org = 0x00200000, len = 2M /* Flash as ITCM */ - flash2 : org = 0x00000000, len = 0 - flash3 : org = 0x00000000, len = 0 - flash4 : org = 0x00000000, len = 0 - flash5 : org = 0x00000000, len = 0 - flash6 : org = 0x00000000, len = 0 - flash7 : org = 0x00000000, len = 0 - ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20020000, len = 368k /* SRAM1 */ - ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ - ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ - ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* For each data/text section two region are defined, a virtual region - and a load region (_LMA suffix).*/ - -/* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash1); -REGION_ALIAS("VECTORS_FLASH_LMA", flash0); - -/* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash1); -REGION_ALIAS("XTORS_FLASH_LMA", flash0); - -/* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash1); -REGION_ALIAS("TEXT_FLASH_LMA", flash0); - -/* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash0); -REGION_ALIAS("RODATA_FLASH_LMA", flash0); - -/* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash1); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); - -/* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts.*/ -REGION_ALIAS("MAIN_STACK_RAM", ram3); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram3); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram3); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* Stack rules inclusion.*/ -INCLUDE rules_stacks.ld - -/*===========================================================================*/ -/* Custom sections for STM32F7xx. */ -/*===========================================================================*/ - -/* RAM region to be used for nocache segment.*/ -REGION_ALIAS("NOCACHE_RAM", ram3); - -/* RAM region to be used for eth segment.*/ -REGION_ALIAS("ETH_RAM", ram3); - -SECTIONS -{ - /* Special section for non cache-able areas.*/ - .nocache (NOLOAD) : ALIGN(4) - { - __nocache_base__ = .; - *(.nocache) - *(.nocache.*) - *(.bss.__nocache_*) - . = ALIGN(4); - __nocache_end__ = .; - } > NOCACHE_RAM - - /* Special section for Ethernet DMA non cache-able areas.*/ - .eth (NOLOAD) : ALIGN(4) - { - __eth_base__ = .; - *(.eth) - *(.eth.*) - *(.bss.__eth_*) - . = ALIGN(4); - __eth_end__ = .; - } > ETH_RAM -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* Data rules inclusion.*/ -INCLUDE rules_data.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld new file mode 100644 index 000000000..92aa1042c --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxG.ld @@ -0,0 +1,132 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F76xxG generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */ + flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */ + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stack rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld new file mode 100644 index 000000000..a7a25eb84 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F76xxI.ld @@ -0,0 +1,132 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F76xxI generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash0 : org = 0x08000000, len = 2M /* Flash as AXIM (writable) */ + flash1 : org = 0x00200000, len = 2M /* Flash as ITCM */ + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash1); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash1); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash1); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash1); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stack rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld -- cgit v1.2.3