From d2228809d1e2232362f6f951bc1667057a5d0b00 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 16 Mar 2019 16:17:22 +0000
Subject: Fixed bug #1021.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_19.1.x@12699 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 os/hal/ports/STM32/STM32H7xx/hal_lld.h | 48 +++++++++++++++++-----------------
 readme.txt                             |  1 +
 2 files changed, 25 insertions(+), 24 deletions(-)

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
index 2c6e75b6b..11af45327 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
@@ -2432,58 +2432,58 @@
 /**
  * @brief   USART4 clock.
  */
-#define STM32_USART4CLK             STM32_PCLK1
+#define STM32_UART4CLK              STM32_PCLK1
 
 /**
  * @brief   USART5 clock.
  */
-#define STM32_USART5CLK             STM32_PCLK1
+#define STM32_UART5CLK              STM32_PCLK1
 
 /**
  * @brief   USART7 clock.
  */
-#define STM32_USART7CLK             STM32_PCLK1
+#define STM32_UART7CLK              STM32_PCLK1
 
 /**
  * @brief   USART8 clock.
  */
-#define STM32_USART8CLK             STM32_PCLK2
+#define STM32_UART8CLK              STM32_PCLK1
 
 #elif STM32_USART234578SEL == STM32_USART234578SEL_PLL2_Q_CK
 #define STM32_USART2CLK             STM32_PLL2_Q_CK
 #define STM32_USART3CLK             STM32_PLL2_Q_CK
-#define STM32_USART4CLK             STM32_PLL2_Q_CK
-#define STM32_USART5CLK             STM32_PLL2_Q_CK
-#define STM32_USART7CLK             STM32_PLL2_Q_CK
-#define STM32_USART8CLK             STM32_PLL2_Q_CK
+#define STM32_UART4CLK              STM32_PLL2_Q_CK
+#define STM32_UART5CLK              STM32_PLL2_Q_CK
+#define STM32_UART7CLK              STM32_PLL2_Q_CK
+#define STM32_UART8CLK              STM32_PLL2_Q_CK
 #elif STM32_USART234578SEL == STM32_USART234578SEL_PLL3_Q_CK
 #define STM32_USART2CLK             STM32_PLL3_Q_CK
 #define STM32_USART3CLK             STM32_PLL3_Q_CK
-#define STM32_USART4CLK             STM32_PLL3_Q_CK
-#define STM32_USART5CLK             STM32_PLL3_Q_CK
-#define STM32_USART7CLK             STM32_PLL3_Q_CK
-#define STM32_USART8CLK             STM32_PLL3_Q_CK
+#define STM32_UART4CLK              STM32_PLL3_Q_CK
+#define STM32_UART5CLK              STM32_PLL3_Q_CK
+#define STM32_UART7CLK              STM32_PLL3_Q_CK
+#define STM32_UART8CLK              STM32_PLL3_Q_CK
 #elif STM32_USART234578SEL == STM32_USART234578SEL_HSI_KER_CK
 #define STM32_USART2CLK             STM32_HSI_CK
 #define STM32_USART3CLK             STM32_HSI_CK
-#define STM32_USART4CLK             STM32_HSI_CK
-#define STM32_USART5CLK             STM32_HSI_CK
-#define STM32_USART7CLK             STM32_HSI_CK
-#define STM32_USART8CLK             STM32_HSI_CK
+#define STM32_UART4CLK              STM32_HSI_CK
+#define STM32_UART5CLK              STM32_HSI_CK
+#define STM32_UART7CLK              STM32_HSI_CK
+#define STM32_UART8CLK              STM32_HSI_CK
 #elif STM32_USART234578SEL == STM32_USART234578SEL_CSI_KER_CK
 #define STM32_USART2CLK             STM32_CSI_CK
 #define STM32_USART3CLK             STM32_CSI_CK
-#define STM32_USART4CLK             STM32_CSI_CK
-#define STM32_USART5CLK             STM32_CSI_CK
-#define STM32_USART7CLK             STM32_CSI_CK
-#define STM32_USART8CLK             STM32_CSI_CK
+#define STM32_UART4CLK              STM32_CSI_CK
+#define STM32_UART5CLK              STM32_CSI_CK
+#define STM32_UART7CLK              STM32_CSI_CK
+#define STM32_UART8CLK              STM32_CSI_CK
 #elif STM32_USART234578SEL == STM32_USART234578SEL_LSE_CK
 #define STM32_USART2CLK             STM32_LSE_CK
 #define STM32_USART3CLK             STM32_LSE_CK
-#define STM32_USART4CLK             STM32_LSE_CK
-#define STM32_USART6CLK             STM32_LSE_CK
-#define STM32_USART7CLK             STM32_LSE_CK
-#define STM32_USART8CLK             STM32_LSE_CK
+#define STM32_UART4CLK              STM32_LSE_CK
+#define STM32_UART6CLK              STM32_LSE_CK
+#define STM32_UART7CLK              STM32_LSE_CK
+#define STM32_UART8CLK              STM32_LSE_CK
 #else
 #error "invalid source selected for STM32_USART234578SEL clock"
 #endif
diff --git a/readme.txt b/readme.txt
index 15b8a025f..49a540ab7 100644
--- a/readme.txt
+++ b/readme.txt
@@ -77,6 +77,7 @@
 - LIB: Re-introduced missing chGuardedPoolGetCounterI() function to guarded
        pools allocator.
 - NEW: Extra timer checks in STM32 ST driver.
+- FIX: Fixed various UART clock naming errors in STM32H7 HAL (bug #1021).
 - FIX: Fixed missing STM32L4+ check in GPIOv3 driver (bug #1020).
 - FIX: Fixed call to obsolete dmaStreamRelease() in STM32 I2Cv3 driver
        (bug #1019).
-- 
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