From c953aa5ac86e4f913c41333a773a0903e0860d35 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 17 Jan 2018 14:55:12 +0000 Subject: Defaulted all STM32 drivers to enable peripheral clocks during stop/sleep modes. Now RCC macros are able to set or clear the LP bit of a peripheral. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11300 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c | 4 ++-- os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c | 6 +++--- os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c | 24 +++++++++++----------- os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c | 8 ++++---- os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c | 2 +- os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c | 10 ++++----- os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c | 8 ++++---- os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 4 ++-- os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c | 4 ++-- os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c | 4 ++-- os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c | 2 +- os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c | 6 +++--- os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c | 8 ++++---- os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c | 8 ++++---- os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c | 4 ++-- os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c | 4 ++-- os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld_alt.c | 4 ++-- os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c | 2 +- os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c | 2 +- os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c | 4 ++-- os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c | 6 +++--- os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c | 12 +++++------ os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c | 6 +++--- os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c | 12 +++++------ os/hal/ports/STM32/LLD/SPIv3/hal_i2s_lld.c | 6 +++--- os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c | 12 +++++------ os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c | 24 +++++++++++----------- os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c | 14 ++++++------- os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c | 14 ++++++------- os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c | 12 +++++------ os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c | 16 +++++++-------- os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c | 12 +++++------ os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c | 18 ++++++++--------- os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c | 16 +++++++-------- os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c | 2 +- os/hal/ports/STM32/STM32F0xx/hal_lld.c | 4 ++-- os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c | 4 ++-- os/hal/ports/STM32/STM32F1xx/hal_lld.c | 4 ++-- os/hal/ports/STM32/STM32F37x/hal_adc_lld.c | 8 ++++---- os/hal/ports/STM32/STM32F37x/hal_lld.c | 4 ++-- os/hal/ports/STM32/STM32F3xx/hal_lld.c | 4 ++-- os/hal/ports/STM32/STM32F4xx/hal_lld.c | 6 +++--- os/hal/ports/STM32/STM32F4xx/stm32_rcc.h | 21 ++++++++++++------- os/hal/ports/STM32/STM32F7xx/hal_lld.c | 4 ++-- os/hal/ports/STM32/STM32F7xx/stm32_rcc.h | 15 +++++++++----- os/hal/ports/STM32/STM32H7xx/hal_lld.c | 2 +- os/hal/ports/STM32/STM32H7xx/stm32_rcc.h | 27 ++++++++++++++++--------- os/hal/ports/STM32/STM32L0xx/hal_lld.c | 6 +++--- os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | 12 +++++++---- os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c | 2 +- os/hal/ports/STM32/STM32L1xx/hal_lld.c | 4 ++-- os/hal/ports/STM32/STM32L1xx/stm32_rcc.h | 9 ++++++--- os/hal/ports/STM32/STM32L4xx/hal_lld.c | 4 ++-- os/hal/ports/STM32/STM32L4xx/stm32_rcc.h | 24 ++++++++++++++++++++++ 54 files changed, 258 insertions(+), 206 deletions(-) diff --git a/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c index a7a6c63ee..97412d680 100644 --- a/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c @@ -153,7 +153,7 @@ void adc_lld_init(void) { #endif /* Calibration procedure.*/ - rccEnableADC1(false); + rccEnableADC1(true); /* CCR setup.*/ #if STM32_ADC_SUPPORTS_PRESCALER @@ -190,7 +190,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(false); + rccEnableADC1(true); /* Clock settings.*/ adcp->adc->CFGR2 = STM32_ADC_ADC1_CKMODE; diff --git a/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c index 93534b2e3..4845374ef 100644 --- a/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c @@ -243,7 +243,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(false); + rccEnableADC1(true); } #endif /* STM32_ADC_USE_ADC1 */ @@ -256,7 +256,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR); - rccEnableADC2(false); + rccEnableADC2(true); } #endif /* STM32_ADC_USE_ADC2 */ @@ -269,7 +269,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR); - rccEnableADC3(false); + rccEnableADC3(true); } #endif /* STM32_ADC_USE_ADC3 */ diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c index f6a2748b3..d16659ddb 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c @@ -535,21 +535,21 @@ void adc_lld_init(void) { #if defined(STM32F3XX) #if STM32_HAS_ADC1 && STM32_HAS_ADC2 #if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 - rccEnableADC12(false); + rccEnableADC12(true); rccResetADC12(); ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; rccDisableADC12(); #endif #else #if STM32_ADC_USE_ADC1 - rccEnableADC12(false); + rccEnableADC12(true); rccResetADC12(); ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; rccDisableADC12(); #endif #endif #if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4 - rccEnableADC34(false); + rccEnableADC34(true); rccResetADC34(); ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA; rccDisableADC34(); @@ -557,7 +557,7 @@ void adc_lld_init(void) { #endif #if defined(STM32L4XX) - rccEnableADC123(false); + rccEnableADC123(true); rccResetADC123(); #if defined(ADC1_2_COMMON) @@ -599,10 +599,10 @@ void adc_lld_start(ADCDriver *adcp) { clkmask |= (1 << 0); #if defined(STM32F3XX) - rccEnableADC12(false); + rccEnableADC12(true); #endif #if defined(STM32L4XX) - rccEnableADC123(false); + rccEnableADC123(true); #endif } #endif /* STM32_ADC_USE_ADC1 */ @@ -618,10 +618,10 @@ void adc_lld_start(ADCDriver *adcp) { clkmask |= (1 << 1); #if defined(STM32F3XX) - rccEnableADC12(false); + rccEnableADC12(true); #endif #if defined(STM32L4XX) - rccEnableADC123(false); + rccEnableADC123(true); #endif } #endif /* STM32_ADC_USE_ADC2 */ @@ -637,10 +637,10 @@ void adc_lld_start(ADCDriver *adcp) { clkmask |= (1 << 2); #if defined(STM32F3XX) - rccEnableADC34(false); + rccEnableADC34(true); #endif #if defined(STM32L4XX) - rccEnableADC123(false); + rccEnableADC123(true); #endif } #endif /* STM32_ADC_USE_ADC3 */ @@ -656,10 +656,10 @@ void adc_lld_start(ADCDriver *adcp) { clkmask |= (1 << 3); #if defined(STM32F3XX) - rccEnableADC34(false); + rccEnableADC34(true); #endif #if defined(STM32L4XX) - rccEnableADC123(false); + rccEnableADC123(true); #endif } #endif /* STM32_ADC_USE_ADC4 */ diff --git a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c index 5e98cfbd8..aa0436e15 100644 --- a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c @@ -360,13 +360,13 @@ void adc_lld_init(void) { /* ADC units pre-initializations.*/ #if (STM32_HAS_ADC1 == TRUE) && (STM32_HAS_ADC2 == TRUE) #if STM32_ADC_USE_ADC12 == TRUE - rccEnableADC12(false); + rccEnableADC12(true); rccResetADC12(); ADC12_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_DAMDF; rccDisableADC12(); #endif #if STM32_ADC_USE_ADC3 == TRUE - rccEnableADC3(false); + rccEnableADC3(true); rccResetADC3(); ADC3_COMMON->CCR = STM32_ADC_ADC3_CLOCK_MODE | ADC_DMA_DAMDF; rccDisableADC3(); @@ -398,7 +398,7 @@ void adc_lld_start(ADCDriver *adcp) { (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp); osalDbgAssert(!b, "stream already allocated"); - rccEnableADC12(false); + rccEnableADC12(true); } #endif /* STM32_ADC_USE_ADC12 == TRUE */ @@ -410,7 +410,7 @@ void adc_lld_start(ADCDriver *adcp) { (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp); osalDbgAssert(!b, "stream already allocated"); - rccEnableADC3(false); + rccEnableADC3(true); } #endif /* STM32_ADC_USE_ADC3 == TRUE */ diff --git a/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c b/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c index f8dbb0760..db1d4cc61 100644 --- a/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c +++ b/os/hal/ports/STM32/LLD/BDMAv1/stm32_bdma.c @@ -307,7 +307,7 @@ bool bdmaStreamAllocate(const stm32_bdma_stream_t *stp, /* Enabling BDMA clocks required by the current streams set.*/ if ((bdma.streams_mask & STM32_BDMA_STREAMS_MASK) == 0U) { - rccEnableBDMA1(false); + rccEnableBDMA1(true); } /* Putting the stream in a safe state.*/ diff --git a/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c b/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c index 31c1bf480..c9130327a 100644 --- a/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c +++ b/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c @@ -92,7 +92,7 @@ static void can_lld_set_filters(CANDriver* canp, /* Temporarily enabling CAN clock.*/ #if STM32_CAN_USE_CAN1 if(canp == &CAND1) { - rccEnableCAN1(false); + rccEnableCAN1(true); /* Filters initialization.*/ canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT; canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | (can2sb << 8) | CAN_FMR_FINIT; @@ -101,7 +101,7 @@ static void can_lld_set_filters(CANDriver* canp, #if STM32_CAN_USE_CAN3 if(canp == &CAND3) { - rccEnableCAN3(false); + rccEnableCAN3(true); /* Filters initialization.*/ canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT; } @@ -682,7 +682,7 @@ void can_lld_start(CANDriver *canp) { /* Clock activation.*/ #if STM32_CAN_USE_CAN1 if (&CAND1 == canp) { - rccEnableCAN1(false); + rccEnableCAN1(true); } #endif @@ -691,13 +691,13 @@ void can_lld_start(CANDriver *canp) { osalDbgAssert(CAND1.state != CAN_STOP, "CAN1 must be started"); - rccEnableCAN2(false); + rccEnableCAN2(true); } #endif #if STM32_CAN_USE_CAN3 if (&CAND3 == canp) { - rccEnableCAN3(false); + rccEnableCAN3(true); } #endif diff --git a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c index de2f6104b..1997f89c4 100644 --- a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c +++ b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c @@ -226,26 +226,26 @@ void dac_lld_start(DACDriver *dacp) { /* Enabling the clock source.*/ #if STM32_DAC_USE_DAC1_CH1 if (&DACD1 == dacp) { - rccEnableDAC1(false); + rccEnableDAC1(true); } #endif #if STM32_DAC_USE_DAC1_CH2 if (&DACD2 == dacp) { - rccEnableDAC1(false); + rccEnableDAC1(true); channel = 1; } #endif #if STM32_DAC_USE_DAC2_CH1 if (&DACD3 == dacp) { - rccEnableDAC2(false); + rccEnableDAC2(true); } #endif #if STM32_DAC_USE_DAC2_CH2 if (&DACD4 == dacp) { - rccEnableDAC2(false); + rccEnableDAC2(true); channel = 1; } #endif diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c index bd11353fc..fa8b07a3e 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c @@ -493,11 +493,11 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, /* Enabling DMA clocks required by the current streams set.*/ if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) { - rccEnableDMA1(false); + rccEnableDMA1(true); } #if STM32_DMA2_NUM_CHANNELS > 0 if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) { - rccEnableDMA2(false); + rccEnableDMA2(true); } #endif diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c index ac1d71964..fe0d7cb8e 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c @@ -462,10 +462,10 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, /* Enabling DMA clocks required by the current streams set.*/ if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) { - rccEnableDMA1(false); + rccEnableDMA1(true); } if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) { - rccEnableDMA2(false); + rccEnableDMA2(true); } /* Putting the stream in a safe state.*/ diff --git a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c index 180dd4b7b..10cc8ca8b 100644 --- a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c @@ -467,10 +467,10 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *stp, /* Enabling DMA clocks required by the current streams set.*/ if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) { - rccEnableDMA1(false); + rccEnableDMA1(true); } if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) { - rccEnableDMA2(false); + rccEnableDMA2(true); } /* Putting the stream in a safe state.*/ diff --git a/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c index 3e73ad3a6..83c4f6e9f 100644 --- a/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c +++ b/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c @@ -91,7 +91,7 @@ void _pal_lld_init(const PALConfig *config) { /* * Enables the GPIO related clocks. */ - rccEnableAPB2(APB2_EN_MASK, false); + rccEnableAPB2(APB2_EN_MASK, true); /* * Initial GPIO setup. diff --git a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c index 6b1b05919..c2a558d59 100644 --- a/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c +++ b/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c @@ -564,7 +564,7 @@ void i2c_lld_start(I2CDriver *i2cp) { (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); - rccEnableI2C1(false); + rccEnableI2C1(true); nvicEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); nvicEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); @@ -590,7 +590,7 @@ void i2c_lld_start(I2CDriver *i2cp) { (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); - rccEnableI2C2(false); + rccEnableI2C2(true); nvicEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); nvicEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); @@ -616,7 +616,7 @@ void i2c_lld_start(I2CDriver *i2cp) { (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); osalDbgAssert(!b, "stream already allocated"); - rccEnableI2C3(false); + rccEnableI2C3(true); nvicEnableVector(I2C3_EV_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY); nvicEnableVector(I2C3_ER_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY); diff --git a/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c index f2f0d8043..19fa223eb 100644 --- a/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c +++ b/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c @@ -688,7 +688,7 @@ void i2c_lld_start(I2CDriver *i2cp) { if (&I2CD1 == i2cp) { rccResetI2C1(); - rccEnableI2C1(false); + rccEnableI2C1(true); #if STM32_I2C_USE_DMA == TRUE { bool b; @@ -726,7 +726,7 @@ void i2c_lld_start(I2CDriver *i2cp) { if (&I2CD2 == i2cp) { rccResetI2C2(); - rccEnableI2C2(false); + rccEnableI2C2(true); #if STM32_I2C_USE_DMA == TRUE { bool b; @@ -764,7 +764,7 @@ void i2c_lld_start(I2CDriver *i2cp) { if (&I2CD3 == i2cp) { rccResetI2C3(); - rccEnableI2C3(false); + rccEnableI2C3(true); #if STM32_I2C_USE_DMA == TRUE { bool b; @@ -802,7 +802,7 @@ void i2c_lld_start(I2CDriver *i2cp) { if (&I2CD4 == i2cp) { rccResetI2C4(); - rccEnableI2C4(false); + rccEnableI2C4(true); #if STM32_I2C_USE_DMA == TRUE { bool b; diff --git a/os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c b/os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c index eda526e15..cc390df4a 100644 --- a/os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c +++ b/os/hal/ports/STM32/LLD/I2Cv3/hal_i2c_lld.c @@ -820,7 +820,7 @@ void i2c_lld_start(I2CDriver *i2cp) { if (&I2CD1 == i2cp) { rccResetI2C1(); - rccEnableI2C1(false); + rccEnableI2C1(true); #if STM32_I2C_USE_DMA == TRUE { bool b; @@ -849,7 +849,7 @@ void i2c_lld_start(I2CDriver *i2cp) { if (&I2CD2 == i2cp) { rccResetI2C2(); - rccEnableI2C2(false); + rccEnableI2C2(true); #if STM32_I2C_USE_DMA == TRUE { bool b; @@ -878,7 +878,7 @@ void i2c_lld_start(I2CDriver *i2cp) { if (&I2CD3 == i2cp) { rccResetI2C3(); - rccEnableI2C3(false); + rccEnableI2C3(true); #if STM32_I2C_USE_DMA == TRUE { bool b; @@ -907,7 +907,7 @@ void i2c_lld_start(I2CDriver *i2cp) { if (&I2CD4 == i2cp) { rccResetI2C4(); - rccEnableI2C4(false); + rccEnableI2C4(true); #if STM32_I2C_USE_DMA == TRUE { bool b; diff --git a/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c b/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c index d305af56e..d19123998 100644 --- a/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c +++ b/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c @@ -267,7 +267,7 @@ void mac_lld_init(void) { rccResetETH(); /* MAC clocks temporary activation.*/ - rccEnableETH(false); + rccEnableETH(true); /* PHY address setup.*/ #if defined(BOARD_PHY_ADDRESS) @@ -317,7 +317,7 @@ void mac_lld_start(MACDriver *macp) { macp->txptr = (stm32_eth_tx_descriptor_t *)__eth_td; /* MAC clocks activation and commanded reset procedure.*/ - rccEnableETH(false); + rccEnableETH(true); #if defined(STM32_MAC_DMABMR_SR) ETH->DMABMR |= ETH_DMABMR_SR; while(ETH->DMABMR & ETH_DMABMR_SR) diff --git a/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c b/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c index 98b7fd74e..d1f31d058 100644 --- a/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c +++ b/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c @@ -814,7 +814,7 @@ void usb_lld_start(USBDriver *usbp) { #if STM32_USB_USE_OTG1 if (&USBD1 == usbp) { /* OTG FS clock enable and reset.*/ - rccEnableOTG_FS(false); + rccEnableOTG_FS(true); rccResetOTG_FS(); /* Enables IRQ vector.*/ @@ -834,7 +834,7 @@ void usb_lld_start(USBDriver *usbp) { #if STM32_USB_USE_OTG2 if (&USBD2 == usbp) { /* OTG HS clock enable and reset.*/ - rccEnableOTG_HS(false); + rccEnableOTG_HS(true); rccResetOTG_HS(); /* ULPI clock is managed depending on the presence of an external diff --git a/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld_alt.c b/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld_alt.c index 4fb1ff111..43c9b0bdd 100644 --- a/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld_alt.c +++ b/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld_alt.c @@ -812,7 +812,7 @@ void usb_lld_start(USBDriver *usbp) { #if STM32_USB_USE_OTG1 if (&USBD1 == usbp) { /* OTG FS clock enable and reset.*/ - rccEnableOTG_FS(false); + rccEnableOTG_FS(true); rccResetOTG_FS(); /* Enables IRQ vector.*/ @@ -832,7 +832,7 @@ void usb_lld_start(USBDriver *usbp) { #if STM32_USB_USE_OTG2 if (&USBD2 == usbp) { /* OTG HS clock enable and reset.*/ - rccEnableOTG_HS(false); + rccEnableOTG_HS(true); rccResetOTG_HS(); /* ULPI clock is managed depending on the presence of an external diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c index 529bb9b95..c94d54ac1 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c @@ -157,7 +157,7 @@ void qspi_lld_start(QSPIDriver *qspip) { (stm32_dmaisr_t)qspi_lld_serve_dma_interrupt, (void *)qspip); osalDbgAssert(!b, "stream already allocated"); - rccEnableQUADSPI1(false); + rccEnableQUADSPI1(true); } #endif diff --git a/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c b/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c index f3ef0b753..676610675 100644 --- a/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c +++ b/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c @@ -386,7 +386,7 @@ void sdc_lld_start(SDCDriver *sdcp) { dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); #endif nvicEnableVector(STM32_SDIO_NUMBER, STM32_SDC_SDIO_IRQ_PRIORITY); - rccEnableSDIO(false); + rccEnableSDIO(true); } /* Configuration, card clock is initially stopped.*/ diff --git a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c index 0fe6fe032..fda4db30a 100644 --- a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c +++ b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c @@ -450,7 +450,7 @@ void sdc_lld_start(SDCDriver *sdcp) { dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); #endif - rccEnableSDMMC1(false); + rccEnableSDMMC1(true); } #endif /* STM32_SDC_USE_SDMMC1 */ @@ -466,7 +466,7 @@ void sdc_lld_start(SDCDriver *sdcp) { dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL); #endif - rccEnableSDMMC2(false); + rccEnableSDMMC2(true); } #endif /* STM32_SDC_USE_SDMMC2 */ } diff --git a/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c b/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c index 9d1dd219d..a3f21b9cb 100644 --- a/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c @@ -360,7 +360,7 @@ void i2s_lld_start(I2SDriver *i2sp) { bool b; /* Enabling I2S unit clock.*/ - rccEnableSPI1(false); + rccEnableSPI1(true); #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) b = dmaStreamAllocate(i2sp->dmarx, @@ -394,7 +394,7 @@ void i2s_lld_start(I2SDriver *i2sp) { bool b; /* Enabling I2S unit clock.*/ - rccEnableSPI2(false); + rccEnableSPI2(true); #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) b = dmaStreamAllocate(i2sp->dmarx, @@ -428,7 +428,7 @@ void i2s_lld_start(I2SDriver *i2sp) { bool b; /* Enabling I2S unit clock.*/ - rccEnableSPI3(false); + rccEnableSPI3(true); #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) b = dmaStreamAllocate(i2sp->dmarx, diff --git a/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c b/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c index ed64010ec..f55cbb4b6 100644 --- a/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c @@ -329,7 +329,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI1(false); + rccEnableSPI1(true); } #endif #if STM32_SPI_USE_SPI2 @@ -345,7 +345,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI2(false); + rccEnableSPI2(true); } #endif #if STM32_SPI_USE_SPI3 @@ -361,7 +361,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI3(false); + rccEnableSPI3(true); } #endif #if STM32_SPI_USE_SPI4 @@ -377,7 +377,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI4(false); + rccEnableSPI4(true); } #endif #if STM32_SPI_USE_SPI5 @@ -393,7 +393,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI5(false); + rccEnableSPI5(true); } #endif #if STM32_SPI_USE_SPI6 @@ -409,7 +409,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI6(false); + rccEnableSPI6(true); } #endif diff --git a/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c b/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c index 54f6dd984..9ac3ec7f8 100644 --- a/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c @@ -360,7 +360,7 @@ void i2s_lld_start(I2SDriver *i2sp) { bool b; /* Enabling I2S unit clock.*/ - rccEnableSPI1(false); + rccEnableSPI1(true); #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) b = dmaStreamAllocate(i2sp->dmarx, @@ -394,7 +394,7 @@ void i2s_lld_start(I2SDriver *i2sp) { bool b; /* Enabling I2S unit clock.*/ - rccEnableSPI2(false); + rccEnableSPI2(true); #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) b = dmaStreamAllocate(i2sp->dmarx, @@ -428,7 +428,7 @@ void i2s_lld_start(I2SDriver *i2sp) { bool b; /* Enabling I2S unit clock.*/ - rccEnableSPI3(false); + rccEnableSPI3(true); #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) b = dmaStreamAllocate(i2sp->dmarx, diff --git a/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c b/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c index 3d91bac46..439b8e3f6 100644 --- a/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c @@ -330,7 +330,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI1(false); + rccEnableSPI1(true); } #endif #if STM32_SPI_USE_SPI2 @@ -346,7 +346,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI2(false); + rccEnableSPI2(true); } #endif #if STM32_SPI_USE_SPI3 @@ -362,7 +362,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI3(false); + rccEnableSPI3(true); } #endif #if STM32_SPI_USE_SPI4 @@ -378,7 +378,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI4(false); + rccEnableSPI4(true); } #endif #if STM32_SPI_USE_SPI5 @@ -394,7 +394,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI5(false); + rccEnableSPI5(true); } #endif #if STM32_SPI_USE_SPI6 @@ -410,7 +410,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI6(false); + rccEnableSPI6(true); } #endif diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_i2s_lld.c b/os/hal/ports/STM32/LLD/SPIv3/hal_i2s_lld.c index 54f6dd984..9ac3ec7f8 100644 --- a/os/hal/ports/STM32/LLD/SPIv3/hal_i2s_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv3/hal_i2s_lld.c @@ -360,7 +360,7 @@ void i2s_lld_start(I2SDriver *i2sp) { bool b; /* Enabling I2S unit clock.*/ - rccEnableSPI1(false); + rccEnableSPI1(true); #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) b = dmaStreamAllocate(i2sp->dmarx, @@ -394,7 +394,7 @@ void i2s_lld_start(I2SDriver *i2sp) { bool b; /* Enabling I2S unit clock.*/ - rccEnableSPI2(false); + rccEnableSPI2(true); #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) b = dmaStreamAllocate(i2sp->dmarx, @@ -428,7 +428,7 @@ void i2s_lld_start(I2SDriver *i2sp) { bool b; /* Enabling I2S unit clock.*/ - rccEnableSPI3(false); + rccEnableSPI3(true); #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) b = dmaStreamAllocate(i2sp->dmarx, diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c index df4c5685c..94ce5cf9a 100644 --- a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c @@ -514,7 +514,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI1(false); + rccEnableSPI1(true); dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI1_RX); dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI1_TX); } @@ -532,7 +532,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI2(false); + rccEnableSPI2(true); dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI2_RX); dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI2_TX); } @@ -550,7 +550,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI3(false); + rccEnableSPI3(true); dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI3_RX); dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI3_TX); } @@ -568,7 +568,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI4(false); + rccEnableSPI4(true); dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI4_RX); dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI4_TX); } @@ -586,7 +586,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_dma_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI5(false); + rccEnableSPI5(true); dmaSetRequestSource(spip->rx.dma, STM32_DMAMUX1_SPI5_RX); dmaSetRequestSource(spip->tx.dma, STM32_DMAMUX1_SPI5_TX); } @@ -604,7 +604,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_bdmaisr_t)spi_lld_serve_bdma_tx_interrupt, (void *)spip); osalDbgAssert(!b, "stream already allocated"); - rccEnableSPI6(false); + rccEnableSPI6(true); bdmaSetRequestSource(spip->rx.bdma, STM32_DMAMUX2_SPI6_RX); bdmaSetRequestSource(spip->tx.bdma, STM32_DMAMUX2_SPI6_TX); } diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c index ce36ce224..79b126ec0 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c @@ -492,7 +492,7 @@ void gpt_lld_start(GPTDriver *gptp) { /* Clock activation.*/ #if STM32_GPT_USE_TIM1 if (&GPTD1 == gptp) { - rccEnableTIM1(false); + rccEnableTIM1(true); rccResetTIM1(); #if !defined(STM32_TIM1_SUPPRESS_ISR) nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY); @@ -507,7 +507,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM2 if (&GPTD2 == gptp) { - rccEnableTIM2(false); + rccEnableTIM2(true); rccResetTIM2(); #if !defined(STM32_TIM2_SUPPRESS_ISR) nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY); @@ -522,7 +522,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM3 if (&GPTD3 == gptp) { - rccEnableTIM3(false); + rccEnableTIM3(true); rccResetTIM3(); #if !defined(STM32_TIM3_SUPPRESS_ISR) nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY); @@ -537,7 +537,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM4 if (&GPTD4 == gptp) { - rccEnableTIM4(false); + rccEnableTIM4(true); rccResetTIM4(); #if !defined(STM32_TIM4_SUPPRESS_ISR) nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY); @@ -552,7 +552,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM5 if (&GPTD5 == gptp) { - rccEnableTIM5(false); + rccEnableTIM5(true); rccResetTIM5(); #if !defined(STM32_TIM5_SUPPRESS_ISR) nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY); @@ -567,7 +567,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM6 if (&GPTD6 == gptp) { - rccEnableTIM6(false); + rccEnableTIM6(true); rccResetTIM6(); #if !defined(STM32_TIM6_SUPPRESS_ISR) nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY); @@ -582,7 +582,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM7 if (&GPTD7 == gptp) { - rccEnableTIM7(false); + rccEnableTIM7(true); rccResetTIM7(); #if !defined(STM32_TIM7_SUPPRESS_ISR) nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY); @@ -597,7 +597,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM8 if (&GPTD8 == gptp) { - rccEnableTIM8(false); + rccEnableTIM8(true); rccResetTIM8(); #if !defined(STM32_TIM8_SUPPRESS_ISR) nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY); @@ -612,7 +612,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM9 if (&GPTD9 == gptp) { - rccEnableTIM9(false); + rccEnableTIM9(true); rccResetTIM9(); #if !defined(STM32_TIM9_SUPPRESS_ISR) nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY); @@ -627,7 +627,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM11 if (&GPTD11 == gptp) { - rccEnableTIM11(false); + rccEnableTIM11(true); rccResetTIM11(); #if !defined(STM32_TIM11_SUPPRESS_ISR) nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY); @@ -642,7 +642,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM12 if (&GPTD12 == gptp) { - rccEnableTIM12(false); + rccEnableTIM12(true); rccResetTIM12(); #if !defined(STM32_TIM12_SUPPRESS_ISR) nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY); @@ -657,7 +657,7 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM14 if (&GPTD14 == gptp) { - rccEnableTIM14(false); + rccEnableTIM14(true); rccResetTIM14(); #if !defined(STM32_TIM14_SUPPRESS_ISR) nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY); diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c index 861c07247..98a02fabb 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c @@ -395,7 +395,7 @@ void icu_lld_start(ICUDriver *icup) { /* Clock activation and timer reset.*/ #if STM32_ICU_USE_TIM1 if (&ICUD1 == icup) { - rccEnableTIM1(false); + rccEnableTIM1(true); rccResetTIM1(); #if !defined(STM32_TIM1_SUPPRESS_ISR) nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY); @@ -411,7 +411,7 @@ void icu_lld_start(ICUDriver *icup) { #if STM32_ICU_USE_TIM2 if (&ICUD2 == icup) { - rccEnableTIM2(false); + rccEnableTIM2(true); rccResetTIM2(); #if !defined(STM32_TIM2_SUPPRESS_ISR) nvicEnableVector(STM32_TIM2_NUMBER, STM32_ICU_TIM2_IRQ_PRIORITY); @@ -426,7 +426,7 @@ void icu_lld_start(ICUDriver *icup) { #if STM32_ICU_USE_TIM3 if (&ICUD3 == icup) { - rccEnableTIM3(false); + rccEnableTIM3(true); rccResetTIM3(); #if !defined(STM32_TIM3_SUPPRESS_ISR) nvicEnableVector(STM32_TIM3_NUMBER, STM32_ICU_TIM3_IRQ_PRIORITY); @@ -441,7 +441,7 @@ void icu_lld_start(ICUDriver *icup) { #if STM32_ICU_USE_TIM4 if (&ICUD4 == icup) { - rccEnableTIM4(false); + rccEnableTIM4(true); rccResetTIM4(); #if !defined(STM32_TIM4_SUPPRESS_ISR) nvicEnableVector(STM32_TIM4_NUMBER, STM32_ICU_TIM4_IRQ_PRIORITY); @@ -456,7 +456,7 @@ void icu_lld_start(ICUDriver *icup) { #if STM32_ICU_USE_TIM5 if (&ICUD5 == icup) { - rccEnableTIM5(false); + rccEnableTIM5(true); rccResetTIM5(); #if !defined(STM32_TIM5_SUPPRESS_ISR) nvicEnableVector(STM32_TIM5_NUMBER, STM32_ICU_TIM5_IRQ_PRIORITY); @@ -471,7 +471,7 @@ void icu_lld_start(ICUDriver *icup) { #if STM32_ICU_USE_TIM8 if (&ICUD8 == icup) { - rccEnableTIM8(false); + rccEnableTIM8(true); rccResetTIM8(); #if !defined(STM32_TIM8_SUPPRESS_ISR) nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY); @@ -487,7 +487,7 @@ void icu_lld_start(ICUDriver *icup) { #if STM32_ICU_USE_TIM9 if (&ICUD9 == icup) { - rccEnableTIM9(false); + rccEnableTIM9(true); rccResetTIM9(); #if !defined(STM32_TIM9_SUPPRESS_ISR) nvicEnableVector(STM32_TIM9_NUMBER, STM32_ICU_TIM9_IRQ_PRIORITY); diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c index c32b9e4a0..629096665 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c @@ -373,7 +373,7 @@ void pwm_lld_start(PWMDriver *pwmp) { /* Clock activation and timer reset.*/ #if STM32_PWM_USE_TIM1 if (&PWMD1 == pwmp) { - rccEnableTIM1(false); + rccEnableTIM1(true); rccResetTIM1(); #if !defined(STM32_TIM1_SUPPRESS_ISR) nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY); @@ -389,7 +389,7 @@ void pwm_lld_start(PWMDriver *pwmp) { #if STM32_PWM_USE_TIM2 if (&PWMD2 == pwmp) { - rccEnableTIM2(false); + rccEnableTIM2(true); rccResetTIM2(); #if !defined(STM32_TIM2_SUPPRESS_ISR) nvicEnableVector(STM32_TIM2_NUMBER, STM32_PWM_TIM2_IRQ_PRIORITY); @@ -404,7 +404,7 @@ void pwm_lld_start(PWMDriver *pwmp) { #if STM32_PWM_USE_TIM3 if (&PWMD3 == pwmp) { - rccEnableTIM3(false); + rccEnableTIM3(true); rccResetTIM3(); #if !defined(STM32_TIM3_SUPPRESS_ISR) nvicEnableVector(STM32_TIM3_NUMBER, STM32_PWM_TIM3_IRQ_PRIORITY); @@ -419,7 +419,7 @@ void pwm_lld_start(PWMDriver *pwmp) { #if STM32_PWM_USE_TIM4 if (&PWMD4 == pwmp) { - rccEnableTIM4(false); + rccEnableTIM4(true); rccResetTIM4(); #if !defined(STM32_TIM4_SUPPRESS_ISR) nvicEnableVector(STM32_TIM4_NUMBER, STM32_PWM_TIM4_IRQ_PRIORITY); @@ -434,7 +434,7 @@ void pwm_lld_start(PWMDriver *pwmp) { #if STM32_PWM_USE_TIM5 if (&PWMD5 == pwmp) { - rccEnableTIM5(false); + rccEnableTIM5(true); rccResetTIM5(); #if !defined(STM32_TIM5_SUPPRESS_ISR) nvicEnableVector(STM32_TIM5_NUMBER, STM32_PWM_TIM5_IRQ_PRIORITY); @@ -449,7 +449,7 @@ void pwm_lld_start(PWMDriver *pwmp) { #if STM32_PWM_USE_TIM8 if (&PWMD8 == pwmp) { - rccEnableTIM8(false); + rccEnableTIM8(true); rccResetTIM8(); #if !defined(STM32_TIM8_SUPPRESS_ISR) nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY); @@ -465,7 +465,7 @@ void pwm_lld_start(PWMDriver *pwmp) { #if STM32_PWM_USE_TIM9 if (&PWMD9 == pwmp) { - rccEnableTIM9(false); + rccEnableTIM9(true); rccResetTIM9(); #if !defined(STM32_TIM9_SUPPRESS_ISR) nvicEnableVector(STM32_TIM9_NUMBER, STM32_PWM_TIM9_IRQ_PRIORITY); diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c index 9625ad28c..dd9c9f35c 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c @@ -52,7 +52,7 @@ #define ST_HANDLER STM32_TIM2_HANDLER #define ST_NUMBER STM32_TIM2_NUMBER #define ST_CLOCK_SRC STM32_TIMCLK1 -#define ST_ENABLE_CLOCK() rccEnableTIM2(false) +#define ST_ENABLE_CLOCK() rccEnableTIM2(true) #if defined(STM32F1XX) #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP #elif defined(STM32L4XX) @@ -77,7 +77,7 @@ #define ST_HANDLER STM32_TIM3_HANDLER #define ST_NUMBER STM32_TIM3_NUMBER #define ST_CLOCK_SRC STM32_TIMCLK1 -#define ST_ENABLE_CLOCK() rccEnableTIM3(false) +#define ST_ENABLE_CLOCK() rccEnableTIM3(true) #if defined(STM32F1XX) #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP #elif defined(STM32L4XX) @@ -102,7 +102,7 @@ #define ST_HANDLER STM32_TIM4_HANDLER #define ST_NUMBER STM32_TIM4_NUMBER #define ST_CLOCK_SRC STM32_TIMCLK1 -#define ST_ENABLE_CLOCK() rccEnableTIM4(false) +#define ST_ENABLE_CLOCK() rccEnableTIM4(true) #if defined(STM32F1XX) #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP #elif defined(STM32L4XX) @@ -127,7 +127,7 @@ #define ST_HANDLER STM32_TIM5_HANDLER #define ST_NUMBER STM32_TIM5_NUMBER #define ST_CLOCK_SRC STM32_TIMCLK1 -#define ST_ENABLE_CLOCK() rccEnableTIM5(false) +#define ST_ENABLE_CLOCK() rccEnableTIM5(true) #if defined(STM32F1XX) #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM5_STOP #elif defined(STM32L4XX) @@ -152,7 +152,7 @@ #define ST_HANDLER STM32_TIM21_HANDLER #define ST_NUMBER STM32_TIM21_NUMBER #define ST_CLOCK_SRC STM32_TIMCLK2 -#define ST_ENABLE_CLOCK() rccEnableTIM21(false) +#define ST_ENABLE_CLOCK() rccEnableTIM21(true) #define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP #elif STM32_ST_USE_TIMER == 22 @@ -169,7 +169,7 @@ #define ST_HANDLER STM32_TIM22_HANDLER #define ST_NUMBER STM32_TIM22_NUMBER #define ST_CLOCK_SRC STM32_TIMCLK2 -#define ST_ENABLE_CLOCK() rccEnableTIM22(false) +#define ST_ENABLE_CLOCK() rccEnableTIM22(true) #define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP #else diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c b/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c index bed91861e..6a0994dfa 100644 --- a/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c @@ -513,49 +513,49 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { if (sdp->state == SD_STOP) { #if STM32_SERIAL_USE_USART1 if (&SD1 == sdp) { - rccEnableUSART1(false); + rccEnableUSART1(true); nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY); } #endif #if STM32_SERIAL_USE_USART2 if (&SD2 == sdp) { - rccEnableUSART2(false); + rccEnableUSART2(true); nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY); } #endif #if STM32_SERIAL_USE_USART3 if (&SD3 == sdp) { - rccEnableUSART3(false); + rccEnableUSART3(true); nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY); } #endif #if STM32_SERIAL_USE_UART4 if (&SD4 == sdp) { - rccEnableUART4(false); + rccEnableUART4(true); nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY); } #endif #if STM32_SERIAL_USE_UART5 if (&SD5 == sdp) { - rccEnableUART5(false); + rccEnableUART5(true); nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY); } #endif #if STM32_SERIAL_USE_USART6 if (&SD6 == sdp) { - rccEnableUSART6(false); + rccEnableUSART6(true); nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY); } #endif #if STM32_SERIAL_USE_UART7 if (&SD7 == sdp) { - rccEnableUART7(false); + rccEnableUART7(true); nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY); } #endif #if STM32_SERIAL_USE_UART8 if (&SD8 == sdp) { - rccEnableUART8(false); + rccEnableUART8(true); nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY); } #endif diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c index 31a8f179b..570133669 100644 --- a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c @@ -514,7 +514,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART1(false); + rccEnableUSART1(true); nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); @@ -534,7 +534,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART2(false); + rccEnableUSART2(true); nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); @@ -554,7 +554,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART3(false); + rccEnableUSART3(true); nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); @@ -580,7 +580,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUART4(false); + rccEnableUART4(true); nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); @@ -606,7 +606,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUART5(false); + rccEnableUART5(true); nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); @@ -626,7 +626,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART6(false); + rccEnableUSART6(true); nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c index 7e4ee6f60..620a7b9b8 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c @@ -767,47 +767,47 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { if (sdp->state == SD_STOP) { #if STM32_SERIAL_USE_USART1 if (&SD1 == sdp) { - rccEnableUSART1(false); + rccEnableUSART1(true); } #endif #if STM32_SERIAL_USE_USART2 if (&SD2 == sdp) { - rccEnableUSART2(false); + rccEnableUSART2(true); } #endif #if STM32_SERIAL_USE_USART3 if (&SD3 == sdp) { - rccEnableUSART3(false); + rccEnableUSART3(true); } #endif #if STM32_SERIAL_USE_UART4 if (&SD4 == sdp) { - rccEnableUART4(false); + rccEnableUART4(true); } #endif #if STM32_SERIAL_USE_UART5 if (&SD5 == sdp) { - rccEnableUART5(false); + rccEnableUART5(true); } #endif #if STM32_SERIAL_USE_USART6 if (&SD6 == sdp) { - rccEnableUSART6(false); + rccEnableUSART6(true); } #endif #if STM32_SERIAL_USE_UART7 if (&SD7 == sdp) { - rccEnableUART7(false); + rccEnableUART7(true); } #endif #if STM32_SERIAL_USE_UART8 if (&SD8 == sdp) { - rccEnableUART8(false); + rccEnableUART8(true); } #endif #if STM32_SERIAL_USE_LPUART1 if (&LPSD1 == sdp) { - rccEnableLPUART1(false); + rccEnableLPUART1(true); } #endif } diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c index ede3fa8fb..f406d86a3 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c @@ -709,7 +709,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART1(false); + rccEnableUSART1(true); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); } @@ -728,7 +728,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART2(false); + rccEnableUSART2(true); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); } @@ -747,7 +747,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART3(false); + rccEnableUSART3(true); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); } @@ -766,7 +766,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUART4(false); + rccEnableUART4(true); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); } @@ -785,7 +785,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUART5(false); + rccEnableUART5(true); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); } @@ -804,7 +804,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUSART6(false); + rccEnableUSART6(true); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); } @@ -823,7 +823,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUART7(false); + rccEnableUART7(true); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); } @@ -842,7 +842,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); - rccEnableUART8(false); + rccEnableUART8(true); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); } diff --git a/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c index 9f8bde707..4f2322a57 100644 --- a/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c +++ b/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c @@ -478,7 +478,7 @@ void usb_lld_start(USBDriver *usbp) { #if STM32_USB_USE_USB1 if (&USBD1 == usbp) { /* USB clock enabled.*/ - rccEnableUSB(false); + rccEnableUSB(true); /* Powers up the transceiver while holding the USB in reset state.*/ STM32_USB->CNTR = CNTR_FRES; /* Enabling the USB IRQ vectors, this also gives enough time to allow diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c index 73ca9552a..a53b8a230 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c @@ -234,7 +234,7 @@ void hal_lld_init(void) { rccResetAPB2(~RCC_APB2RSTR_DBGMCURST); /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); + rccEnablePWRInterface(true); /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); @@ -347,7 +347,7 @@ void stm32_clock_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); #endif /* !STM32_NO_INIT */ } diff --git a/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c index 8bd671d58..92e79b9a5 100644 --- a/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c +++ b/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c @@ -99,7 +99,7 @@ void adc_lld_init(void) { STM32_DMA_CR_TEIE; /* Temporary activation.*/ - rccEnableADC1(false); + rccEnableADC1(true); ADC1->CR1 = 0; ADC1->CR2 = ADC_CR2_ADON; @@ -139,7 +139,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(false); + rccEnableADC1(true); } #endif diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_lld.c index 711335004..80fac7bbb 100644 --- a/os/hal/ports/STM32/STM32F1xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.c @@ -136,8 +136,8 @@ void hal_lld_init(void) { rccResetAPB2(0xFFFFFFFF); /* PWR and BD clocks enabled.*/ - rccEnablePWRInterface(FALSE); - rccEnableBKPInterface(FALSE); + rccEnablePWRInterface(true); + rccEnableBKPInterface(true); /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); diff --git a/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c b/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c index 2a36f9827..03f14cc32 100644 --- a/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c +++ b/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c @@ -398,7 +398,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(false); + rccEnableADC1(true); } #endif /* STM32_ADC_USE_ADC1 */ @@ -410,7 +410,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR); - rccEnableSDADC1(false); + rccEnableSDADC1(true); PWR->CR |= PWR_CR_SDADC1EN; adcp->sdadc->CR2 = 0; adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & @@ -427,7 +427,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR); - rccEnableSDADC2(false); + rccEnableSDADC2(true); PWR->CR |= PWR_CR_SDADC2EN; adcp->sdadc->CR2 = 0; adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & @@ -444,7 +444,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR); - rccEnableSDADC3(false); + rccEnableSDADC3(true); PWR->CR |= PWR_CR_SDADC3EN; adcp->sdadc->CR2 = 0; adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.c b/os/hal/ports/STM32/STM32F37x/hal_lld.c index bc5d27e96..76a7ab954 100644 --- a/os/hal/ports/STM32/STM32F37x/hal_lld.c +++ b/os/hal/ports/STM32/STM32F37x/hal_lld.c @@ -112,7 +112,7 @@ void hal_lld_init(void) { rccResetAPB2(0xFFFFFFFF); /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); + rccEnablePWRInterface(true); /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); @@ -132,7 +132,7 @@ void hal_lld_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); } /** diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c index 33424ae05..a409285e6 100644 --- a/os/hal/ports/STM32/STM32F3xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.c @@ -112,7 +112,7 @@ void hal_lld_init(void) { rccResetAPB2(0xFFFFFFFF); /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); + rccEnablePWRInterface(true); /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); @@ -132,7 +132,7 @@ void hal_lld_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); #if STM32_HAS_USB /* USB IRQ relocated to not conflict with CAN.*/ diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c index f71160961..1918c0638 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c @@ -88,7 +88,7 @@ static void hal_lld_backup_domain_init(void) { #endif /* HAL_USE_RTC */ #if STM32_BKPRAM_ENABLE - rccEnableBKPSRAM(false); + rccEnableBKPSRAM(true); PWR->CSR |= PWR_CSR_BRE; while ((PWR->CSR & PWR_CSR_BRR) == 0) @@ -125,7 +125,7 @@ void hal_lld_init(void) { rccResetAPB2(~0); /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); + rccEnablePWRInterface(true); /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); @@ -321,7 +321,7 @@ void stm32_clock_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); } /** @} */ diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h index 0d0435c4d..caa4db8bd 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h @@ -62,6 +62,8 @@ RCC->APB1ENR |= (mask); \ if (lp) \ RCC->APB1LPENR |= (mask); \ + else \ + RCC->APB1LPENR &= ~(mask); \ } /** @@ -73,7 +75,6 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ - RCC->APB1LPENR &= ~(mask); \ } /** @@ -97,7 +98,10 @@ */ #define rccEnableAPB2(mask, lp) { \ RCC->APB2ENR |= (mask); \ - RCC->APB2LPENR |= (mask); \ + if (lp) \ + RCC->APB2LPENR |= (mask); \ + else \ + RCC->APB2LPENR &= ~(mask); \ } /** @@ -109,7 +113,6 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ - RCC->APB2LPENR &= ~(mask); \ } /** @@ -134,7 +137,10 @@ */ #define rccEnableAHB1(mask, lp) { \ RCC->AHB1ENR |= (mask); \ - RCC->AHB1LPENR |= (mask); \ + if (lp) \ + RCC->AHB1LPENR |= (mask); \ + else \ + RCC->AHB1LPENR &= ~(mask); \ } /** @@ -146,7 +152,6 @@ */ #define rccDisableAHB1(mask) { \ RCC->AHB1ENR &= ~(mask); \ - RCC->AHB1LPENR &= ~(mask); \ } /** @@ -173,6 +178,8 @@ RCC->AHB2ENR |= (mask); \ if (lp) \ RCC->AHB2LPENR |= (mask); \ + else \ + RCC->AHB2LPENR &= ~(mask); \ } /** @@ -184,7 +191,6 @@ */ #define rccDisableAHB2(mask) { \ RCC->AHB2ENR &= ~(mask); \ - RCC->AHB2LPENR &= ~(mask); \ } /** @@ -211,6 +217,8 @@ RCC->AHB3ENR |= (mask); \ if (lp) \ RCC->AHB3LPENR |= (mask); \ + else \ + RCC->AHB3LPENR &= ~(mask); \ } /** @@ -222,7 +230,6 @@ */ #define rccDisableAHB3(mask) { \ RCC->AHB3ENR &= ~(mask); \ - RCC->AHB3LPENR &= ~(mask); \ } /** diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c index 87698308f..20af00675 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c @@ -88,7 +88,7 @@ static void hal_lld_backup_domain_init(void) { #endif /* HAL_USE_RTC */ #if STM32_BKPRAM_ENABLE - rccEnableBKPSRAM(false); + rccEnableBKPSRAM(true); PWR->CSR1 |= PWR_CSR1_BRE; while ((PWR->CSR1 & PWR_CSR1_BRR) == 0) @@ -299,7 +299,7 @@ void stm32_clock_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); } /** @} */ diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index 094d6900f..a34ced725 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -62,6 +62,8 @@ RCC->APB1ENR |= (mask); \ if (lp) \ RCC->APB1LPENR |= (mask); \ + else \ + RCC->APB1LPENR &= ~(mask); \ } /** @@ -73,7 +75,6 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ - RCC->APB1LPENR &= ~(mask); \ } /** @@ -100,6 +101,8 @@ RCC->APB2ENR |= (mask); \ if (lp) \ RCC->APB2LPENR |= (mask); \ + else \ + RCC->APB2LPENR &= ~(mask); \ } /** @@ -111,7 +114,6 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ - RCC->APB2LPENR &= ~(mask); \ } /** @@ -138,6 +140,8 @@ RCC->AHB1ENR |= (mask); \ if (lp) \ RCC->AHB1LPENR |= (mask); \ + else \ + RCC->AHB1LPENR &= ~(mask); \ } /** @@ -149,7 +153,6 @@ */ #define rccDisableAHB1(mask) { \ RCC->AHB1ENR &= ~(mask); \ - RCC->AHB1LPENR &= ~(mask); \ } /** @@ -176,6 +179,8 @@ RCC->AHB2ENR |= (mask); \ if (lp) \ RCC->AHB2LPENR |= (mask); \ + else \ + RCC->AHB2LPENR &= ~(mask); \ } /** @@ -187,7 +192,6 @@ */ #define rccDisableAHB2(mask) { \ RCC->AHB2ENR &= ~(mask); \ - RCC->AHB2LPENR &= ~(mask); \ } /** @@ -214,6 +218,8 @@ RCC->AHB3ENR |= (mask); \ if (lp) \ RCC->AHB3LPENR |= (mask); \ + else \ + RCC->AHB3LPENR &= ~(mask); \ } /** @@ -225,7 +231,6 @@ */ #define rccDisableAHB3(mask) { \ RCC->AHB3ENR &= ~(mask); \ - RCC->AHB3LPENR &= ~(mask); \ } /** diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c index 7e7b0c3b1..48004d3a5 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c @@ -107,7 +107,7 @@ static inline void init_pwr(void) { #if STM32_PWR_CR2 & PWR_CR2_BREN // while ((PWR->CR2 & PWR_CR2_BRRDY) == 0) // ; -// rccEnableBKPRAM(false); +// rccEnableBKPRAM(true); #endif } diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h index d8a2de894..b258f79b1 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h @@ -62,6 +62,8 @@ RCC->APB1LENR |= (mask); \ if (lp) \ RCC->APB1LLPENR |= (mask); \ + else \ + RCC->APB1LLPENR &= ~(mask); \ } /** @@ -76,6 +78,8 @@ RCC->APB1HENR |= (mask); \ if (lp) \ RCC->APB1HLPENR |= (mask); \ + else \ + RCC->APB1HLPENR &= ~(mask); \ } /** @@ -87,7 +91,6 @@ */ #define rccDisableAPB1L(mask) { \ RCC->APB1LENR &= ~(mask); \ - RCC->APB1LLPENR &= ~(mask); \ } /** @@ -99,7 +102,6 @@ */ #define rccDisableAPB1H(mask) { \ RCC->APB1HENR &= ~(mask); \ - RCC->APB1HLPENR &= ~(mask); \ } /** @@ -138,6 +140,8 @@ RCC->APB2ENR |= (mask); \ if (lp) \ RCC->APB2LPENR |= (mask); \ + else \ + RCC->APB2LPENR &= ~(mask); \ } /** @@ -149,7 +153,6 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ - RCC->APB2LPENR &= ~(mask); \ } /** @@ -176,6 +179,8 @@ RCC->APB3ENR |= (mask); \ if (lp) \ RCC->APB3LPENR |= (mask); \ + else \ + RCC->APB3LPENR &= ~(mask); \ } /** @@ -187,7 +192,6 @@ */ #define rccDisableAPB3(mask) { \ RCC->APB3ENR &= ~(mask); \ - RCC->APB3LPENR &= ~(mask); \ } /** @@ -214,6 +218,8 @@ RCC->APB4ENR |= (mask); \ if (lp) \ RCC->APB4LPENR |= (mask); \ + else \ + RCC->APB4LPENR &= ~(mask); \ } /** @@ -225,7 +231,6 @@ */ #define rccDisableAPB4(mask) { \ RCC->APB4ENR &= ~(mask); \ - RCC->APB4LPENR &= ~(mask); \ } /** @@ -252,6 +257,8 @@ RCC->AHB1ENR |= (mask); \ if (lp) \ RCC->AHB1LPENR |= (mask); \ + else \ + RCC->AHB1LPENR &= ~(mask); \ } /** @@ -263,7 +270,6 @@ */ #define rccDisableAHB1(mask) { \ RCC->AHB1ENR &= ~(mask); \ - RCC->AHB1LPENR &= ~(mask); \ } /** @@ -290,6 +296,8 @@ RCC->AHB2ENR |= (mask); \ if (lp) \ RCC->AHB2LPENR |= (mask); \ + else \ + RCC->AHB2LPENR &= ~(mask); \ } /** @@ -301,7 +309,6 @@ */ #define rccDisableAHB2(mask) { \ RCC->AHB2ENR &= ~(mask); \ - RCC->AHB2LPENR &= ~(mask); \ } /** @@ -328,6 +335,8 @@ RCC->AHB3ENR |= (mask); \ if (lp) \ RCC->AHB3LPENR |= (mask); \ + else \ + RCC->AHB3LPENR &= ~(mask); \ } /** @@ -339,7 +348,6 @@ */ #define rccDisableAHB3(mask) { \ RCC->AHB3ENR &= ~(mask); \ - RCC->AHB3LPENR &= ~(mask); \ } /** @@ -366,6 +374,8 @@ RCC->AHB4ENR |= (mask); \ if (lp) \ RCC->AHB4LPENR |= (mask); \ + else \ + RCC->AHB4LPENR &= ~(mask); \ } /** @@ -377,7 +387,6 @@ */ #define rccDisableAHB4(mask) { \ RCC->AHB4ENR &= ~(mask); \ - RCC->AHB4LPENR &= ~(mask); \ } /** diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.c b/os/hal/ports/STM32/STM32L0xx/hal_lld.c index 6ef788d7a..9779fc476 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.c @@ -156,7 +156,7 @@ void hal_lld_init(void) { rccResetAPB2(~0); /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); + rccEnablePWRInterface(true); /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); @@ -266,7 +266,7 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_HSI48 /* Enabling SYSCFG clock. */ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, FALSE); + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); /* Configuring SYSCFG to enable VREFINT and HSI48 VREFINT buffer. */ SYSCFG->CFGR3 = STM32_VREFINT_EN | SYSCFG_CFGR3_ENREF_HSI48; @@ -305,7 +305,7 @@ void stm32_clock_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); #endif /* STM32_NO_INIT */ } diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h index 01283be58..e53e6db67 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h @@ -63,6 +63,8 @@ RCC->APB1ENR |= (mask); \ if (lp) \ RCC->APB1SMENR |= (mask); \ + else \ + RCC->APB1SMENR &= ~(mask); \ } /** @@ -74,7 +76,6 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ - RCC->APB1SMENR &= ~(mask); \ } /** @@ -101,6 +102,8 @@ RCC->APB2ENR |= (mask); \ if (lp) \ RCC->APB2SMENR |= (mask); \ + else \ + RCC->APB2SMENR &= ~(mask); \ } /** @@ -112,7 +115,6 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ - RCC->APB2SMENR &= ~(mask); \ } /** @@ -139,6 +141,8 @@ RCC->AHBENR |= (mask); \ if (lp) \ RCC->AHBSMENR |= (mask); \ + else \ + RCC->AHBSMENR &= ~(mask); \ } /** @@ -150,7 +154,6 @@ */ #define rccDisableAHB(mask) { \ RCC->AHBENR &= ~(mask); \ - RCC->AHBSMENR &= ~(mask); \ } /** @@ -177,6 +180,8 @@ RCC->IOPENR |= (mask); \ if (lp) \ RCC->IOPSMENR |= (mask); \ + else \ + RCC->IOPSMENR &= ~(mask); \ } /** @@ -188,7 +193,6 @@ */ #define rccDisableIOP(mask) { \ RCC->IOPENR &= ~(mask); \ - RCC->IOPSMENR &= ~(mask); \ } /** diff --git a/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c b/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c index 7b6c61a3a..072b196e1 100644 --- a/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c +++ b/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c @@ -155,7 +155,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(!b, "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(false); + rccEnableADC1(true); } #endif /* STM32_ADC_USE_ADC1 */ diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.c b/os/hal/ports/STM32/STM32L1xx/hal_lld.c index 3f4c04329..cdbdf3992 100644 --- a/os/hal/ports/STM32/STM32L1xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.c @@ -106,7 +106,7 @@ void hal_lld_init(void) { rccResetAPB2(~0); /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); + rccEnablePWRInterface(true); /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); @@ -225,7 +225,7 @@ void stm32_clock_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); } /** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h index 989735afd..8593aca9d 100644 --- a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h @@ -63,6 +63,8 @@ RCC->APB1ENR |= (mask); \ if (lp) \ RCC->APB1LPENR |= (mask); \ + else \ + RCC->APB1LPENR &= ~(mask); \ } /** @@ -74,7 +76,6 @@ */ #define rccDisableAPB1(mask) { \ RCC->APB1ENR &= ~(mask); \ - RCC->APB1LPENR &= ~(mask); \ } /** @@ -101,6 +102,8 @@ RCC->APB2ENR |= (mask); \ if (lp) \ RCC->APB2LPENR |= (mask); \ + else \ + RCC->APB2LPENR &= ~(mask); \ } /** @@ -112,7 +115,6 @@ */ #define rccDisableAPB2(mask) { \ RCC->APB2ENR &= ~(mask); \ - RCC->APB2LPENR &= ~(mask); \ } /** @@ -139,6 +141,8 @@ RCC->AHBENR |= (mask); \ if (lp) \ RCC->AHBLPENR |= (mask); \ + else \ + RCC->AHBLPENR &= ~(mask); \ } /** @@ -150,7 +154,6 @@ */ #define rccDisableAHB(mask) { \ RCC->AHBENR &= ~(mask); \ - RCC->AHBLPENR &= ~(mask); \ } /** diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index 06dc36d58..4ea836e69 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -120,7 +120,7 @@ void hal_lld_init(void) { rccResetAPB2(~0); /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); + rccEnablePWRInterface(true); /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); @@ -367,7 +367,7 @@ void stm32_clock_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); } /** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h index df7e93c83..3d1711da4 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h @@ -60,6 +60,10 @@ */ #define rccEnableAPB1R1(mask, lp) { \ RCC->APB1ENR1 |= (mask); \ + if (lp) \ + RCC->APB1SMENR1 |= (mask); \ + else \ + RCC->APB1SMENR1 &= ~(mask); \ } /** @@ -95,6 +99,10 @@ */ #define rccEnableAPB1R2(mask, lp) { \ RCC->APB1ENR2 |= (mask); \ + if (lp) \ + RCC->APB1SMENR2 |= (mask); \ + else \ + RCC->APB1SMENR2 &= ~(mask); \ } /** @@ -130,6 +138,10 @@ */ #define rccEnableAPB2(mask, lp) { \ RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2SMENR |= (mask); \ + else \ + RCC->APB2SMENR &= ~(mask); \ } /** @@ -165,6 +177,10 @@ */ #define rccEnableAHB1(mask, lp) { \ RCC->AHB1ENR |= (mask); \ + if (lp) \ + RCC->AHB1SMENR |= (mask); \ + else \ + RCC->AHB1SMENR &= ~(mask); \ } /** @@ -200,6 +216,10 @@ */ #define rccEnableAHB2(mask, lp) { \ RCC->AHB2ENR |= (mask); \ + if (lp) \ + RCC->AHB2SMENR |= (mask); \ + else \ + RCC->AHB2SMENR &= ~(mask); \ } /** @@ -235,6 +255,10 @@ */ #define rccEnableAHB3(mask, lp) { \ RCC->AHB3ENR |= (mask); \ + if (lp) \ + RCC->AHB3SMENR |= (mask); \ + else \ + RCC->AHB3SMENR &= ~(mask); \ } /** -- cgit v1.2.3