From c6bc9ad95152f851fd4527f40dd5f2695cd286ec Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 28 Mar 2010 10:27:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1798 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/LPC11xx/hal_lld.c | 50 +++++++++++++++++++++++++++++++++--- os/hal/platforms/LPC11xx/hal_lld.h | 52 ++++++++++++++++++++++++++++++++------ os/hal/platforms/STM32/hal_lld.c | 2 +- readme.txt | 2 +- 4 files changed, 93 insertions(+), 13 deletions(-) diff --git a/os/hal/platforms/LPC11xx/hal_lld.c b/os/hal/platforms/LPC11xx/hal_lld.c index d513a6156..f0b2fdc95 100644 --- a/os/hal/platforms/LPC11xx/hal_lld.c +++ b/os/hal/platforms/LPC11xx/hal_lld.c @@ -28,6 +28,11 @@ #include "ch.h" #include "hal.h" +/** + * @brief Register missing in NXP header file. + */ +#define FLASHCFG (*((volatile uint32_t *)0x4003C010)) + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -59,10 +64,12 @@ void hal_lld_init(void) { NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); NVICSetSystemHandlerPriority(HANDLER_PENDSV, CORTEX_PRIORITY_PENDSV); - /* Systick initialization.*/ - SysTick->LOAD = LPC11xx_SYSCLK / (8000000 / CH_FREQUENCY) - 1; + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1; SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; } /** @@ -70,6 +77,43 @@ void hal_lld_init(void) { * @note All the involved constants come from the file @p board.h. */ void lpc111x_clock_init(void) { + unsigned i; + + /* Flash wait states setting, the code takes care to not touch TBD bits.*/ + FLASHCFG = (FLASHCFG & ~3) | LPC11xx_FLASHCFG_FLASHTIM; + + /* System oscillator initialization if required.*/ +#if LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC + LPC_SYSCON->SYSOSCCTRL = LPC11xx_SYSOSCCTRL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ + for (i = 0; i < 200; i++) + __NOP(); /* Stabilization delay. */ + + /* PLL initialization if required.*/ +#if LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT + LPC_SYSCON->SYSPLLCTRL = LPC11xx_SYSPLLCTRL_MSEL | LPC11xx_SYSPLLCTRL_PSEL; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ + while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ + ; +#endif /* LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ +#endif /* LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ + + /* Main clock source selection.*/ + LPC_SYSCON->MAINCLKSEL = LPC11xx_MAINCLK_SOURCE; + LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = 1; + while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ + ; + + /* ABH divider initialization, peripheral clocks are initially disabled, + the various device drivers will handle their own setup except GPIO and + IOCON that are left enabled.*/ + LPC_SYSCON->SYSAHBCLKDIV = LPC11xx_SYSABHCLK_DIV; + LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; + + /* Memory remapping, vectors always in ROM.*/ + LPC_SYSCON->SYSMEMREMAP = 2; } /** @} */ diff --git a/os/hal/platforms/LPC11xx/hal_lld.h b/os/hal/platforms/LPC11xx/hal_lld.h index 98f4034ce..72c0776f7 100644 --- a/os/hal/platforms/LPC11xx/hal_lld.h +++ b/os/hal/platforms/LPC11xx/hal_lld.h @@ -41,7 +41,7 @@ #define PLATFORM_NAME "LPC11xx" #define IRCOSCCLK 12000000 /**< High speed internal clock. */ -#define WDGOSCCLK 12000000 /**< Watchdog internal clock. */ +#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ #define SYSPLLCLKSEL_IRCOCS 0 /**< Internal RC oscillator clock source. */ @@ -93,13 +93,22 @@ * @note The value must be chosen between (1...255). */ #if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__) -#define LPC11xx_SYSCLK_DIV 1 +#define LPC11xx_SYSABHCLK_DIV 1 #endif /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ +/** + * @brief Calculated SYSOSCCTRL setting. + */ +#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#define LPC11xx_SYSOSCCTRL 0 +#else +#define LPC11xx_SYSOSCCTRL 1 +#endif + /** * @brief PLL input clock frequency. */ @@ -111,12 +120,28 @@ #error "invalid LPC11xx_PLLCLK_SOURCE clock source specified" #endif -#if (LPC11xx_SYSPLL_MUL < 1) || (LPC11xx_SYSPLL_MUL > 32) +/** + * @brief MSEL mask in SYSPLLCTRL register. + */ +#if (LPC11xx_SYSPLL_MUL >= 1) && (LPC11xx_SYSPLL_MUL <= 32) || \ + defined(__DOXYGEN__) +#define LPC11xx_SYSPLLCTRL_MSEL (LPC11xx_SYSPLL_MUL - 1) +#else #error "LPC11xx_SYSPLL_MUL out of range (1...32)" #endif -#if (LPC11xx_SYSPLL_DIV != 2) && (LPC11xx_SYSPLL_DIV != 4) && \ - (LPC11xx_SYSPLL_DIV != 8) && (LPC11xx_SYSPLL_DIV != 16) +/** + * @brief PSEL mask in SYSPLLCTRL register. + */ +#if (LPC11xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__) +#define LPC11xx_SYSPLLCTRL_PSEL (0 << 5) +#elif LPC11xx_SYSPLL_DIV == 4 +#define LPC11xx_SYSPLLCTRL_PSEL (1 << 5) +#elif LPC11xx_SYSPLL_DIV == 8 +#define LPC11xx_SYSPLLCTRL_PSEL (2 << 5) +#elif LPC11xx_SYSPLL_DIV == 16 +#define LPC11xx_SYSPLLCTRL_PSEL (3 << 5) +#else #error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)" #endif @@ -149,12 +174,23 @@ /** * @brief AHB clock. */ -#define LPC11xx_SYSCLK (LPC11xx_MAINCLK / LPC11xx_SYSCLK_DIV) - -#if LPC11xx_SYSCLK > 50000000 +#if (LPC11xx_SYSCLK <= 50000000) || defined(__DOXYGEN__) +#define LPC11xx_SYSCLK (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV) +#else #error "AHB clock frequency out of the acceptable range (50MHz max)" #endif +/** + * @brief Flash wait states. + */ +#if (LPC11xx_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define LPC11xx_FLASHCFG_FLASHTIM 0 +#elif LPC11xx_SYSCLK <= 40000000 +#define LPC11xx_FLASHCFG_FLASHTIM 1 +#else +#define LPC11xx_FLASHCFG_FLASHTIM 2 +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index c98de5104..b28795ad9 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -80,7 +80,7 @@ void hal_lld_init(void) { NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); NVICSetSystemHandlerPriority(HANDLER_PENDSV, CORTEX_PRIORITY_PENDSV); - /* Systick initialization using the system clock.*/ + /* SysTick initialization using the system clock.*/ SysTick->LOAD = SYSCLK / CH_FREQUENCY - 1; SysTick->VAL = 0; SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | diff --git a/readme.txt b/readme.txt index ecd525c43..68c243339 100644 --- a/readme.txt +++ b/readme.txt @@ -96,7 +96,7 @@ - CHANGE: The module documentation has been moved from the kernel.dox file to the various source code files in order to make it easier to maintain and double as source comments. -- CHANGE: Updated CMSIS files to version 1.3 and fixed the warnings in there +- CHANGE: Updated CMSIS files to version 1.3 and fixed the warnings in there, again... *** 1.5.3 *** -- cgit v1.2.3