From a3653f3b16f71bfb8ddb2a51599d30e93f13380b Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 5 Jan 2019 15:18:32 +0000
Subject: Bypass option for SDIOv1 driver.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12527 110e8d01-0319-4d1e-a829-52ad28d1bb01
---
 os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c  | 3 ++-
 os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.h  | 8 ++++++++
 os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c | 3 ++-
 readme.txt                                   | 2 ++
 4 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c b/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
index d0abcf0ed..f929a42bf 100644
--- a/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
+++ b/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
@@ -451,7 +451,8 @@ void sdc_lld_start_clk(SDCDriver *sdcp) {
  * @notapi
  */
 void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
-#if 0
+
+#if STM32_SDC_SDIO_50MHZ
   if (SDC_CLK_50MHz == clk) {
     sdcp->sdio->CLKCR = (sdcp->sdio->CLKCR & 0xFFFFFF00U) | STM32_SDIO_DIV_HS
                                                           | SDIO_CLKCR_BYPASS;
diff --git a/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.h b/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.h
index 71329aae4..7c05836be 100644
--- a/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.h
+++ b/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.h
@@ -91,6 +91,14 @@
 #define STM32_SDC_SDIO_IRQ_PRIORITY         9
 #endif
 
+/**
+ * @brief   Enable clock bypass.
+ * @note    Allow clock speed up to 50 Mhz.
+ */
+#if !defined(STM32_SDC_SDIO_50MHZ) || defined(__DOXYGEN__)
+#define STM32_SDC_SDIO_50MHZ                FALSE
+#endif
+
 /**
  * @brief   Write timeout in milliseconds.
  */
diff --git a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
index 7af68b255..0015258d9 100644
--- a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
+++ b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
@@ -548,7 +548,8 @@ void sdc_lld_start_clk(SDCDriver *sdcp) {
  * @notapi
  */
 void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
-#if STM32_SDC_SDMMC_50MHZ && defined(STM32F7XX)
+
+#if STM32_SDC_SDMMC_50MHZ
   if (SDC_CLK_50MHz == clk) {
     sdcp->sdmmc->CLKCR = (sdcp->sdmmc->CLKCR & 0xFFFFFF00U) |
 #if STM32_SDC_SDMMC_PWRSAV
diff --git a/readme.txt b/readme.txt
index df4ca4b7c..d3d01b545 100644
--- a/readme.txt
+++ b/readme.txt
@@ -75,6 +75,8 @@
 *****************************************************************************
 
 *** Next ***
+- NEW: Added option to enable bypass on SDIOv1 driver allowing to use a
+       50MHz clock.
 - NEW: Added TIM15, TIM16 and TIM17 support on GPT, ICU and PWM drivers,
        limited to STM32F3, L4 and L4+ platforms.
 - NEW: STM32H7xx and STM32L4+ ports reworked to support dynamic DMA
-- 
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