From 646d8a2376e3d476a3d00edb665770596fb252f6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Dec 2009 14:59:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1376 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/board.h | 44 +------------------------------- demos/ARMCM3-STM32F103-GCC/board.h | 44 +------------------------------- docs/reports/STM32F103-72.txt | 4 +-- os/hal/platforms/MSP430/hal_lld.h | 4 +++ os/hal/platforms/STM32/hal_lld.c | 4 +-- os/hal/platforms/STM32/hal_lld.h | 44 +++++++++++++++++++++++++++++++- os/hal/templates/hal_lld.h | 4 +++ 7 files changed, 57 insertions(+), 91 deletions(-) diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h index bf04625c5..588ea3c5d 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h @@ -21,53 +21,11 @@ #define _BOARD_H_ /* - * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. - */ -//#define SYSCLK_48 - -/* - * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. + * Board frequencies. */ #define LSECLK 32768 #define HSECLK 8000000 #define HSICLK 8000000 -#define PLLPRE 1 -#ifdef SYSCLK_48 - #define PLLMUL 6 -#else - #define PLLMUL 9 -#endif -#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL) -#define SYSCLK PLLCLK -#define APB1CLK (SYSCLK / 2) -#define APB2CLK (SYSCLK / 2) -#define AHB1CLK (SYSCLK / 1) - -/* - * Values derived from the clock settings. - */ -#define PLLPREBITS ((PLLPRE - 1) << 17) -#define PLLMULBITS ((PLLMUL - 2) << 18) -#ifdef SYSCLK_48 - #define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS - #define FLASHBITS 0x00000011 -#else - #define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS - #define FLASHBITS 0x00000012 -#endif - -/* - * Extra definitions for RCC_CR register (missing from the ST header file). - */ -#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3) - -/* - * Extra definitions for RCC_CFGR register (missing from the ST header file). - */ -#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16) -#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16) -#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22) -#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22) /* * IO pins assignments. diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index bf04625c5..588ea3c5d 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -21,53 +21,11 @@ #define _BOARD_H_ /* - * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. - */ -//#define SYSCLK_48 - -/* - * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. + * Board frequencies. */ #define LSECLK 32768 #define HSECLK 8000000 #define HSICLK 8000000 -#define PLLPRE 1 -#ifdef SYSCLK_48 - #define PLLMUL 6 -#else - #define PLLMUL 9 -#endif -#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL) -#define SYSCLK PLLCLK -#define APB1CLK (SYSCLK / 2) -#define APB2CLK (SYSCLK / 2) -#define AHB1CLK (SYSCLK / 1) - -/* - * Values derived from the clock settings. - */ -#define PLLPREBITS ((PLLPRE - 1) << 17) -#define PLLMULBITS ((PLLMUL - 2) << 18) -#ifdef SYSCLK_48 - #define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS - #define FLASHBITS 0x00000011 -#else - #define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS - #define FLASHBITS 0x00000012 -#endif - -/* - * Extra definitions for RCC_CR register (missing from the ST header file). - */ -#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3) - -/* - * Extra definitions for RCC_CFGR register (missing from the ST header file). - */ -#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16) -#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16) -#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22) -#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22) /* * IO pins assignments. diff --git a/docs/reports/STM32F103-72.txt b/docs/reports/STM32F103-72.txt index 06e35a4a8..7f8556c86 100644 --- a/docs/reports/STM32F103-72.txt +++ b/docs/reports/STM32F103-72.txt @@ -5,9 +5,9 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) *** ChibiOS/RT test suite *** -*** Kernel: 1.3.3unstable +*** Kernel: 1.3.5unstable *** Architecture: ARM Cortex-M3 -*** GCC Version: 4.4.1 +*** GCC Version: 4.4.2 ---------------------------------------------------------------------------- --- Test Case 1.1 (Threads, enqueuing test #1) diff --git a/os/hal/platforms/MSP430/hal_lld.h b/os/hal/platforms/MSP430/hal_lld.h index 07c5863eb..2795a7edc 100644 --- a/os/hal/platforms/MSP430/hal_lld.h +++ b/os/hal/platforms/MSP430/hal_lld.h @@ -51,6 +51,10 @@ #define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK #endif +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + /* * Calculating the derived clock constants. */ diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index d25b0f026..b69bbbd9b 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -95,7 +95,7 @@ void hal_lld_init(void) { void stm32_clock_init(void) { /* HSI setup.*/ - RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION; + RCC->CR = 0x00000083; /* Reset value, HSI ON. */ while (!(RCC->CR & RCC_CR_HSIRDY)) ; /* Waits until HSI stable. */ /* HSE setup.*/ @@ -103,7 +103,7 @@ void stm32_clock_init(void) { while (!(RCC->CR & RCC_CR_HSERDY)) ; /* Waits until HSE stable. */ /* PLL setup.*/ - RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS; + RCC->CFGR = RCC_CFGR_PLLSRC | PLLPREBITS | PLLMULBITS; RCC->CR |= RCC_CR_PLLON; while (!(RCC->CR & RCC_CR_PLLRDY)) ; /* Waits until PLL stable. */ diff --git a/os/hal/platforms/STM32/hal_lld.h b/os/hal/platforms/STM32/hal_lld.h index a6fdc9661..45f74aff0 100644 --- a/os/hal/platforms/STM32/hal_lld.h +++ b/os/hal/platforms/STM32/hal_lld.h @@ -40,14 +40,56 @@ #include "nvic.h" #include "stm32_dma.h" +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @brief System clock setting. + * @note Only 48MHz and 72MHz are currently supported. + */ +#if !defined(STM32_SYSCLK) || defined(__DOXYGEN__) +#define STM32_SYSCLK 72 +#endif + /*===========================================================================*/ -/* Driver constants. */ +/* Derived constants and error checks. */ /*===========================================================================*/ +/* + * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. + */ +#define PLLPRE 1 +#if STM32_SYSCLK == 48 + #define PLLMUL 6 +#elif STM32_SYSCLK == 72 + #define PLLMUL 9 +#else +#error "unsupported STM32_SYSCLK setting" +#endif +#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL) +#define SYSCLK PLLCLK +#define APB1CLK (SYSCLK / 2) +#define APB2CLK (SYSCLK / 2) +#define AHB1CLK (SYSCLK / 1) + +/* + * Values derived from the clock settings. + */ +#define PLLPREBITS ((PLLPRE - 1) << 17) +#define PLLMULBITS ((PLLMUL - 2) << 18) +#if STM32_SYSCLK == 48 + #define USBPREBITS RCC_CFGR_USBPRE + #define FLASHBITS 0x00000011 +#elif STM32_SYSCLK == 72 + #define USBPREBITS 0 + #define FLASHBITS 0x00000012 +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/templates/hal_lld.h b/os/hal/templates/hal_lld.h index b401e4217..2f5af5b17 100644 --- a/os/hal/templates/hal_lld.h +++ b/os/hal/templates/hal_lld.h @@ -35,6 +35,10 @@ /* Driver constants. */ /*===========================================================================*/ +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ -- cgit v1.2.3