From 4d1c817475411bea3a3b08426011ecd8faf0f44d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 24 Feb 2014 11:09:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6722 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/rt/RT-SPC56EC-EVB/.cproject | 57 +++ demos/rt/RT-SPC56EC-EVB/.project | 43 ++ demos/rt/RT-SPC56EC-EVB/Makefile | 169 +++++++ demos/rt/RT-SPC56EC-EVB/UDE/debug.wsx | 273 +++++++++++ ...56ec74a256s_spc56ec74_minimodule_debug_jtag.cfg | 290 ++++++++++++ demos/rt/RT-SPC56EC-EVB/chconf.h | 498 +++++++++++++++++++++ demos/rt/RT-SPC56EC-EVB/halconf.h | 312 +++++++++++++ demos/rt/RT-SPC56EC-EVB/main.c | 203 +++++++++ demos/rt/RT-SPC56EC-EVB/mcuconf.h | 288 ++++++++++++ os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld | 31 ++ os/common/ports/e200/devices/SPC56ECxx/boot.h | 252 +++++++++++ os/common/ports/e200/devices/SPC56ECxx/boot.s | 407 +++++++++++++++++ os/common/ports/e200/devices/SPC56ECxx/ppcparams.h | 77 ++++ os/common/ports/e200/devices/SPC56ELxx/boot.h | 252 +++++++++++ os/common/ports/e200/devices/SPC56ELxx/boot.s | 225 ++-------- os/hal/boards/ST_EVB_SPC56EC/board.c | 73 +++ os/hal/boards/ST_EVB_SPC56EC/board.h | 71 +++ os/hal/boards/ST_EVB_SPC56EC/board.mk | 5 + os/hal/boards/ST_EVB_SPC56EL/board.c | 35 +- os/hal/boards/ST_EVB_SPC56EL/board.h | 28 +- .../ports/e200/compilers/GCC/mk/port_spc56ecxx.mk | 14 + 21 files changed, 3384 insertions(+), 219 deletions(-) create mode 100644 demos/rt/RT-SPC56EC-EVB/.cproject create mode 100644 demos/rt/RT-SPC56EC-EVB/.project create mode 100644 demos/rt/RT-SPC56EC-EVB/Makefile create mode 100644 demos/rt/RT-SPC56EC-EVB/UDE/debug.wsx create mode 100644 demos/rt/RT-SPC56EC-EVB/UDE/stm_spc56ec74a256s_spc56ec74_minimodule_debug_jtag.cfg create mode 100644 demos/rt/RT-SPC56EC-EVB/chconf.h create mode 100644 demos/rt/RT-SPC56EC-EVB/halconf.h create mode 100644 demos/rt/RT-SPC56EC-EVB/main.c create mode 100644 demos/rt/RT-SPC56EC-EVB/mcuconf.h create mode 100644 os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld create mode 100644 os/common/ports/e200/devices/SPC56ECxx/boot.h create mode 100644 os/common/ports/e200/devices/SPC56ECxx/boot.s create mode 100644 os/common/ports/e200/devices/SPC56ECxx/ppcparams.h create mode 100644 os/common/ports/e200/devices/SPC56ELxx/boot.h create mode 100644 os/hal/boards/ST_EVB_SPC56EC/board.c create mode 100644 os/hal/boards/ST_EVB_SPC56EC/board.h create mode 100644 os/hal/boards/ST_EVB_SPC56EC/board.mk create mode 100644 os/rt/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk diff --git a/demos/rt/RT-SPC56EC-EVB/.cproject b/demos/rt/RT-SPC56EC-EVB/.cproject new file mode 100644 index 000000000..88dcf471d --- /dev/null +++ b/demos/rt/RT-SPC56EC-EVB/.cproject @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/rt/RT-SPC56EC-EVB/.project b/demos/rt/RT-SPC56EC-EVB/.project new file mode 100644 index 000000000..4eee5e231 --- /dev/null +++ b/demos/rt/RT-SPC56EC-EVB/.project @@ -0,0 +1,43 @@ + + + RT-SPC56EC-EVB + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/os/hal/boards/ST_EVB_SPC56EC + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/rt/RT-SPC56EC-EVB/Makefile b/demos/rt/RT-SPC56EC-EVB/Makefile new file mode 100644 index 000000000..4d0b90e38 --- /dev/null +++ b/demos/rt/RT-SPC56EC-EVB/Makefile @@ -0,0 +1,169 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the optional exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/boards/ST_EVB_SPC56EC/board.mk +include $(CHIBIOS)/os/hal/ports/SPC5/SPC56ECxx/platform.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk +include $(CHIBIOS)/test/rt/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC56EC74.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(OSALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/chprintf.c \ + $(CHIBIOS)/os/various/shell.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +MOT = $(CP) -O srec +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/ports/e200/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/demos/rt/RT-SPC56EC-EVB/UDE/debug.wsx b/demos/rt/RT-SPC56EC-EVB/UDE/debug.wsx new file mode 100644 index 000000000..c5cf4bb90 --- /dev/null +++ b/demos/rt/RT-SPC56EC-EVB/UDE/debug.wsx @@ -0,0 +1,273 @@ + + + debug.wsx001vQTv/gAAAQAXAAIA6AkIAAAABAAAAAAAPwAAAAAAAAAEAAAAAgAAAAAAAAAAAAAAAAAAAA==4.028.08.2013 14:58:49:999000000WorkspaceManagerWorkspaceManager01Core01Target0.Controller0.Core0Target0.Controller0.Core010Core11Target0.Controller0.Core1Target0.Controller0.Core11033007632112968181280780NormalfalseTop1272falseBottom0000falsefalse00DockPaneltrue457falseLeft0000falsefalse00DockPanelfalse457falseLeft0000falsefalse10DockPanelfalse0falseTop0000falsefalse0-1TabbedDocumenttrue457falseLeft0000falsefalse30DockPaneltrue457falseLeft0000falsefalse20DockPanelfalse457falseLeft0000falsefalse40DockPanelfalsetrue632false200false200true200true100truetrue0012807400128024Platform Main Menufalsetrue32427625Macro ToolbarfalsetrueUDE_0x3B_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueRun MacroImagetrueUDE_0x40_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueDebug MacroImagetrueUDE_0x3_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueBreak MacroImagetrueUDE_0x3C_{F5FC9736-9EE3-460B-BB80-67C14C9581BF}trueReload MacroImagetrueUDE_Ctrl_{4D5190CD-077D-4F92-B890-4545242BF32A}_UDEWorkspacetrueImageAndTextfalse2792414125Config ToolbarfalsetrueUDE_0x3_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueTarget ConfigurationImagetrueUDE_0xFE_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueConnect TargetImagetrueUDE_0x100_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueDisconnect TargetImagetrueUDE_0x6_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}trueSetup Target InterfaceImagetrueUDE_0x12_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueMCU Run ControlImagetrue4202425925Tools ToolbarfalsetrueUDE_Ctrl_{377CE046-823C-4A05-8828-13C25D345D77}_Core0trueImageAndTextfalseUDE_0xE1_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueExecution Time SetupImagetrueUDE_Ctrl_{377CE046-823C-4A05-8828-13C25D345D77}_Core1trueImageAndTextfalse679249525Edit ToolbarfalsetrueUDE_Workspace_0x1779trueCutImagetrueUDE_Workspace_0x177AtrueCopyImagetrueUDE_Workspace_0x177BtruePasteImagetrue774244925File ToolbarfalsetrueUDE_Workspace_0x1770trueNew WorkspaceImagetrueUDE_Workspace_0x1771falseOpen workspaceImagetrueUDE_Workspace_0x1772falseSave workspace asImagetrueUDE_Workspace_0x1773falseSave workspaceImagetrueUDE_Workspace_0x1774falseClose workspaceImagetrueUDE_Workspace_0x177FfalseExport view contentImagetrueUDE_Workspace_0x1778falsePrintImagetrueUDE_0x1_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}falseLoad ProgramImagetrue8232444025Views ToolbarfalsetrueUDE_0x4_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueTarget BrowserImagetrueUDE_0x15_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueDiagnostic Message ViewerImagetrueUDE_0xF_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueConsoleImagetrueUDE_0x0_{DED51A60-E0B7-11D4-9112-0001034962B6}trueCPU WindowImagetrueUDE_0x1E_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueExplore SymbolsImagetrueUDE_0xA_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueProgramImagetrueUDE_0x5C_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueSingle Program WindowImagetrueUDE_0x5A_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueDisassembly WindowImagetrueUDE_0x2D_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueShow Special Function RegisterImagetrueUDE_0x3C_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueLocalsImagetrueUDE_0x46_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueWatchImagetrueUDE_0xA_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueSimulated I/OImagetrueUDE_0x14_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueUDE HTMLImagetrueUDE_0x19_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueArray ChartImagetrueUDE_0x1B_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueTime Traced Signal ChartImagetrueUDE_0x50_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueIP Trace ProfilingImagetrueUDE_0x28_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueMemoryImagetrueUDE_0x46_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueCall StackImagetrue34949225Debug ToolbarfalsetrueUDE_0x18_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueShow IPImagetrueUDE_0x5E_{27B09B6B-1CF9-4B8E-8F03-63D41538E5D2}trueShow program codeImagetrueUDE_0x7_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStart ProgramImagetrueUDE_0x9_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStep OverImagetrueUDE_0xA_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStep IntoImagetrueUDE_0xB_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueStep OutImagetrueUDE_0x8_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueRun CursorImagetrueUDE_0x321_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueBreak ProgramImagetrueUDE_0xD_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueResetImagetrueUDE_0xC_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueRestart ProgramImagetrueUDE_0x3_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueBreakpointsImagetrueUDE_0x6_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueToggle BreakImagetrueUDE_Ctrl_{FB7BC773-88A4-4ECE-B9B6-7189610B0735}_Core0trueImageAndTextfalseUDE_0x3_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}falseTrigger setupImagetrueUDE_Ctrl_{FB7BC773-88A4-4ECE-B9B6-7189610B0735}_Core1falseImageAndTextfalse01002625Show Toolbarfalsefalse02002625Window Toolbarfalsefalse02252625Workspace Toolbarfalsefalse02752625Help Toolbarfalsefalse075712802300128023Platform Status Barfalsetrue0740683128074068328.08.2013 15:00:07:1451007782411WorkspaceManager11028.08.2013 15:00:07:129MgAAAA==AQAAAA==ZAAAAA==AQAAAA==lgAAAA==AQAAAA==6AMAAA==AQAAAA==9011201WorkspaceManager11000\\napnt002.nap.st.com\NAPPRT0001..\..\..\..\..\..\Program Files (x86)\pls\UDE 4.0\StdLibrary.mso416,1097,367,613620,965,340,66200{866f82d3-fac5-43cd-8a82-0af01e46e2c5}..\..\..\..\..\..\Users\disiriog\Documents\pls\UDE 4.0The script contains a collection of macros to save memory content into different file formats +and fill target memory rangesV:\UDE\AddOns\Macro\MacroLibrary\StdMacros1.dsm' +' $Header: /Ude/AddOns/Macro/MacroLibrary/StdMacros.dsm 3 30.04.04 9:34 Weisses $ +'_______________________________________________________ +' +' universal debug engine +' +' Standard command line macros - part 1 +' +' pls Development Tools 1999-2004 +' +' 28.04.04 SW correction for UDE 1.10 +' 03.06.03 SW initial version +'_______________________________________________________ + +'_______________________________________________________ +' +' UnAss command line function +' +' generates disassembly file +' +' command line UnAss output-file range1 [range2] [range3] ..... +' range description: +' C:<startaddress>,<length> or - code +' DB:<startaddress>,<length> or - data byte +' DW:<startaddress>,<length> or - data word +' DD:<startaddress>,<length> or - data dword +'_______________________________________________________ + +Sub UnAss(File,ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + If IsNumeric(File) Then + MsgBox "File parameter wrong - " & File + Exit Sub + End If + DisASMObj.OutputPath = CStr(File) + bRetVal = DisASMObj.CreateStream(True,"UDE Disassembler output of current Program",False) + If bRetVal = True Then + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + For Range = 0 To RangeCnt -1 + KindOfRange = CStr(ParameterObj.Parameter(ParamIndex)) + KindOfRange = UCase(KindOfRange) + Address = CLng(ParameterObj.Parameter(ParamIndex +1)) + Length = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + If IsNumeric(KindOfRange) Then + If KindOfRange = 12 Then + DisASMObj.AddRange Address,Length,1 + ElseIf KindOfRange = 219 Then + DisASMObj.AddRange Address,Length,2 + ElseIf KindOfRange = 221 Then + DisASMObj.AddRange Address,Length,4 + Else + MsgBox "Invalid range type " & KindOfRange & "of range " & Range +1 + Exit Sub + End If + Else + If KindOfRange = "C" Then + DisASMObj.AddRange Address,Length,1 + ElseIf KindOfRange = "DB" Then + DisASMObj.AddRange Address,Length,2 + ElseIf KindOfRange = "DW" Then + DisASMObj.AddRange Address,Length,3 + ElseIf KindOfRange = "DD" Then + DisASMObj.AddRange Address,Length,4 + Else + MsgBox "Invalid range type " & KindOfRange & "of range " & Range +1 + Exit Sub + End If + End If + Next + DisASMObj.HexFileModeFlag = False + DisASMObj.ListModeFlag = False + DisASMObj.WriteAllRanges(False) + End If + +End Sub + +'_______________________________________________________ +' +' SaveHEX command line function +' +' generates intel-HEX file +' +' command line SaveHex output-file range1 [range2] [range3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub SaveHEX(File,ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + If IsNumeric(File) Then + MsgBox "File parameter wrong - " & File + Exit Sub + End If + DisASMObj.OutputPath = CStr(File) + bRetVal = DisASMObj.CreateStream(True,"UDE generated intel-Hex file of current Program",False) + If bRetVal = True Then + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 2 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/2 + ParamIndex = 0 + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)) + ParamIndex = ParamIndex +2 + DisASMObj.AddRange Address,Length,0 + Next + DisASMObj.HexFileModeFlag = True + DisASMObj.WriteAllRanges(False) + End If + +End Sub + +'_______________________________________________________ +' +' FillByte command line function +' +' fills memory range with byte pattern +' +' command line FillByte range1,pattern1 [range2,pattern2] [range3,pattern3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub FillByte(ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + set udearrayobj = debugger.ByteArrayObj(1) + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)) + Pattern = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + udearrayobj.Resize(Length) + udearrayobj.Fill(Pattern) + debugger.Write Address,udearrayobj + Next + +End Sub + +'_______________________________________________________ +' +' FillWord command line function +' +' fills memory range with word pattern +' +' command line FillWord range1,pattern1 [range2,pattern2] [range3,pattern3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub FillWord(ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + set udearrayobj = debugger.WordArrayObj(1) + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)/2) + Pattern = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + udearrayobj.Resize(Length) + udearrayobj.Fill(Pattern) + debugger.Write Address,udearrayobj + Next + +End Sub + +'_______________________________________________________ +' +' FillDWord command line function +' +' fills memory range with dword pattern +' +' command line FillDWord range1,pattern1 [range2,pattern2] [range3,pattern3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub FillDWord(ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + set udearrayobj = debugger.DWordArrayObj(1) + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)/4) + Pattern = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + udearrayobj.Resize(Length) + udearrayobj.Fill(Pattern) + debugger.Write Address,udearrayobj + Next + +End Sub63VBScript24.11.2006 14:43:20:0001WS_CORE_DUOMacro_24_09_13_12_19_33_010Execute UnAss ..Macro UnAssExecute macro UnAss0210Execute SaveHEX ..Macro SaveHEXExecute macro SaveHEX0210Execute FillByte ..Macro FillByteExecute macro FillByte0110Execute FillWord ..Macro FillWordExecute macro FillWord0110Execute FillDWord ..Macro FillDWordExecute macro FillDWord0150128.08.2013 15:32:24:4787782650Target0.Controller0.Core01028.08.2013 15:00:07:1767782740Target0.Controller0.Core0110128.08.2013 15:30:43:451..\main.c17372830Target0.Controller0.Core01024.09.2013 12:18:42:066..\..\..\SPC56ECxx\SPC5-HAL_SPC56ECxx_HAL_Drivers_Component\component\lib\src\spc5_edma.c27372880Target0.Controller0.Core011128.08.2013 15:31:19:129AwAAAA==AQAAAA==fQAAAA==UwAAAA==QwAAAA==QwAAAA==QwAAAA==QwAAAA==QwAAAA==SAAAAA==AAAAAA==AAAAAA==AAAAAA==AAAAAA==7782520Target0.Controller0.Core010028.08.2013 15:32:08:193144096008601642949672950Target0.Controller0.Core010000000001..\build\out.elfSoftware;enabled;0;disabled;'main {C:\ChibiStudio\workspace\SPC5\demos\SPC56ECxx OS-Less Test Application\main.c} .25';main.c;1;0;;$disabled; ;disabled; ;Software;enabled;0;disabled;'vector10 {C:\ChibiStudio\workspace\SPC5\SPC56ECxx\SPC5-HAL_SPC56ECxx_HAL_Drivers_Component\component\lib\src\spc5_edma.c} .78';spc5_edma.c;1;10;;$disabled; ;disabled; ;2..\build\out.elf3,0000000000x140x141011100000verify.txt0000003..\..\..\SPC56ECxx\SPC5-HAL_SPC56ECxx_HAL_Drivers_Component\component\lib\src\spc5_edma.ccode <0x2BC0-0x2FBF>..\main.c028.08.2013 15:00:07:3797782860Target0.Controller0.Core111024.09.2013 12:15:58:262code <0xFFFFFC00-0xFFFFFFFF>87372870Target0.Controller0.Core110028.08.2013 15:30:43:4997372842949672950Target0.Controller0.Core1100000000002101..\build\out.elf01100001code <0xFFFFFC00-0xFFFFFFFF>stm_spc56ec74a256s_spc56ec74_minimodule_debug_jtag.cfg24.09.2013 12:19:33:000 diff --git a/demos/rt/RT-SPC56EC-EVB/UDE/stm_spc56ec74a256s_spc56ec74_minimodule_debug_jtag.cfg b/demos/rt/RT-SPC56EC-EVB/UDE/stm_spc56ec74a256s_spc56ec74_minimodule_debug_jtag.cfg new file mode 100644 index 000000000..efb0181f4 --- /dev/null +++ b/demos/rt/RT-SPC56EC-EVB/UDE/stm_spc56ec74a256s_spc56ec74_minimodule_debug_jtag.cfg @@ -0,0 +1,290 @@ +[Main] +Signature=UDE_TARGINFO_2.0 +Description=STM SPC56EC74A256S Mini Module with Dual Core SPC56EC74 (Jtag) +Description1=MMU preinitialized, memory mapping 1:1, VLE enabled for SRAM and Flash +Description2=PLL set for 120MHz +Description3=FLASH programming prepared but not enabled +Description4=Write Filter for BAM Module +MCUs=Controller0 +Architecture=PowerPC +Vendor=STM +Board=SPC56EC74A256S Mini Module + +[Controller0] +Family=PowerPC +Type=SPC56EC74 +Enabled=1 +IntClock=120000 +MemDevs=BAMWriteFilter +ExtClock=40000 + +[Controller0.Core0] +Protocol=PPCJTAG +Enabled=1 + +[Controller0.Core1] +Protocol=PPCJTAG +Enabled=1 + +[Controller0.BAMWriteFilter] +Description=BAM WriteAccess Filter +Range0Start=0xFFFFC000 +Range0Size=0x4000 +Enabled=1 +Handler=AccessFilter +Mode=ReadOnly + +[Controller0.PFLASH] +Enabled=1 +EnableMemtoolByDefault=1 + +[Controller0.PFLASH1] +Enabled=1 +EnableMemtoolByDefault=1 + +[Controller0.DFLASH] +Enabled=1 +EnableMemtoolByDefault=1 + +[Controller0.SHADOWFLASH] +Enabled=1 +EnableMemtoolByDefault=0 + +[Controller0.Core0.LoadedAddOn] +UDEMemtool=1 + +[Controller0.Core0.PpcJtagTargIntf] +PortType=FTDI +ResetWaitTime=500 +MaxJtagClk=5000 +DoSramInit=1 +UseNexus=1 +AdaptiveJtagPhaseShift=1 +ConnOption=Default +ChangeJtagClk=-1 +HaltAfterReset=1 +SimioAddr=g_JtagSimioAccess +FreezeTimers=1 +InvalidTlbOnReset=1 +InvalidateCache=1 +ForceCacheFlush=1 +IgnoreLockedLines=0 +ExecInitCmds=1 +JtagTapNumber=0 +JtagNumOfTaps=1 +JtagNumIrBefore=0 +JtagNumIrAfter=0 +SimioAddr=g_JtagSimioAccess +FlushCache=0 +AllowMmuSetup=1 +UseExtReset=1 +HandleWdtBug=0 +ForceEndOfReset=0 +JtagViaPod=0 +AllowResetOnCheck=0 +ChangeMsr=0 +ChangeMsrValue=0x0 +ExecOnStartCmds=0 +ExecOnHaltCmds=0 +EnableProgramTimeMeasurement=0 +UseHwResetMode=0 +TargetPort=Default +HandleNexusAccessBug=0 +DoNotEnableTrapSwBrp=0 +BootPasswd0=0xFEEDFACE +BootPasswd1=0xCAFEBEEF +BootPasswd2=0xFFFFFFFF +BootPasswd3=0xFFFFFFFF +BootPasswd4=0xFFFFFFFF +BootPasswd5=0xFFFFFFFF +BootPasswd6=0xFFFFFFFF +BootPasswd7=0xFFFFFFFF +CommDevSel=PortType=USB,Type=FTDI +JtagIoType=Jtag +ExecOnHaltCmdsWhileHalted=0 +TimerForPTM=Default +AllowBreakOnUpdateBreakpoints=0 +ClearDebugStatusOnHalt=1 +HwResetMode=Simulate +UseMasterNexusIfResetState=1 +UseLocalAddressTranslation=1 +Use64BitNexus=0 +InitSramOnlyWhenNotInitialized=0 +AllowHarrForUpdateDebugRegs=0 +DisableE2EECC=0 +UseCore0ForNexusMemoryAccessWhileRunning=0 + +[Controller0.Core0.PpcJtagTargIntf.InitScript] + +// select TLB 1 +SETSPR 0x274 0x10000108 0xFFFFFFFF + +// programm internal Flash, no cache because of flash +// TLB 1, entry 0 +SETSPR 0x270 0x10000000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=16MB +SETSPR 0x271 0xC0000700 0xFFFFFFFF +// effective page number 00000000 +SETSPR 0x272 0x28 0xFFFFFFFF +// real page 00000000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0x3F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm internal SRAM +// TLB 1, entry 1 +SETSPR 0x270 0x10010000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=16MB +SETSPR 0x271 0xC0000700 0xFFFFFFFF +// effective page number 40000000, I +SETSPR 0x272 0x40000028 0xFFFFFFFF +// real page 0x40000000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0x4000003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm peripheral A modules +// TLB 1, entry 2 +SETSPR 0x270 0x10020000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=1MB +SETSPR 0x271 0xC0000500 0xFFFFFFFF +// effective page number C3F00000, I +SETSPR 0x272 0xC3F0000A 0xFFFFFFFF +// real page C3F00000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0xC3F0003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm off plattfrom modules +// TLB 1, entry 3 +SETSPR 0x270 0x10030000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=1MB +SETSPR 0x271 0xC0000500 0xFFFFFFFF +// effective page number FFE00000, I,G +SETSPR 0x272 0xFFE0000A 0xFFFFFFFF +// real page FFE00000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0xFFE0003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm on plattfrom modules +// TLB 1, entry 4 +SETSPR 0x270 0x10040000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=1MB +SETSPR 0x271 0xC0000500 0xFFFFFFFF +// effective page number FFF00000, I,G +SETSPR 0x272 0xFFF0000A 0xFFFFFFFF +// real page FFF00000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0xFFF0003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// setup IVOPR +// points to internal memory at 0x40000000 +SETSPR 0x3F 0x40000000 0xFFFFFFFF + +// disable watchdog +SET SWT_SR 0x0000C520 +SET SWT_SR 0x0000D928 +SET SWT_CR 0xFF00000A + +// setup pll and clocks +// Oscillator select +SET 0xC3FE0374 0x1000000 +SET 0xC3FE0370 0x1 +// enable all modes +SET 0xC3FDC008 0x5FF +// run mode +SET 0xC3FDC02C 0x1F0032 +// enable peripherals in run and low power modes +SET 0xC3FDC080 0xFE +SET 0xC3FDC0A0 0x500 +// Z0 clock dividers -> 0.5 system clock +//SET8 0xC3FE00C0 0x01 +// system clock dividers +SET8 0xC3FE037C 0x80 +SET8 0xC3FE037D 0x80 +SET8 0xC3FE037E 0x80 +// enable auxiliary clocks +SET16 0xC3FE0380 0x100 +SET16 0xC3FE0388 0x0 +SET8 0xC3FE038C 0x80 +// setup clock monitor +SET 0xC3FE0100 0x6 +// Make DRUN configuration active +SET 0xC3FDC004 0x30005AF0 +SET 0xC3FDC004 0x3000A50F +WAIT 5 +// setup pll to 120MHz 40Mz external +SET 0xC3FE00A0 0x0D300041 +// run mode +SET 0xC3FDC02C 0x1F00F4 +// Make DRUN configuration active +SET 0xC3FDC004 0x30005AF0 +SET 0xC3FDC004 0x3000A50F +WAIT 5 +// setup SSCM erro cfg for debug +SET 0xC3FD8006 0x3 0x3 + +[Controller0.Core0.PpcJtagTargIntf.OnStartScript] + +[Controller0.Core0.PpcJtagTargIntf.OnHaltScript] + +[Controller0.Core1.PpcJtagTargIntf] +PortType=Default +ResetWaitTime=500 +MaxJtagClk=5000 +DoSramInit=1 +UseNexus=1 +AdaptiveJtagPhaseShift=1 +ConnOption=Break +ChangeJtagClk=-1 +HaltAfterReset=0 +SimioAddr=g_JtagSimioAccess +FreezeTimers=1 +InvalidTlbOnReset=0 +InvalidateCache=0 +ForceCacheFlush=0 +IgnoreLockedLines=0 +ExecInitCmds=0 +JtagTapNumber=0 +JtagNumOfTaps=1 +JtagNumIrBefore=0 +JtagNumIrAfter=0 +SimioAddr=g_JtagSimioAccess +FlushCache=0 +AllowMmuSetup=0 +UseExtReset=0 +HandleWdtBug=0 +ForceEndOfReset=0 +JtagViaPod=0 +AllowResetOnCheck=0 +TargetPort=Default +ChangeMsr=0 +ChangeMsrValue=0x0 +ExecOnStartCmds=0 +ExecOnHaltCmds=0 +EnableProgramTimeMeasurement=0 +UseHwResetMode=0 +HandleNexusAccessBug=0 +DoNotEnableTrapSwBrp=0 +BootPasswd0=0xFEEDFACE +BootPasswd1=0xCAFEBEEF +BootPasswd2=0xFFFFFFFF +BootPasswd3=0xFFFFFFFF +BootPasswd4=0xFFFFFFFF +BootPasswd5=0xFFFFFFFF +BootPasswd6=0xFFFFFFFF +BootPasswd7=0xFFFFFFFF +CommDevSel= + +[Controller0.Core1.PpcJtagTargIntf.InitScript] + +[Controller0.Core1.PpcJtagTargIntf.OnStartScript] + +[Controller0.Core1.PpcJtagTargIntf.OnHaltScript] + +[Controller0.Core0.DebugServer.DbgFramework] +FRAMEWORK_COLOR=14804223 +[Controller0.Core1.DebugServer.DbgFramework] +FRAMEWORK_COLOR=16777152 diff --git a/demos/rt/RT-SPC56EC-EVB/chconf.h b/demos/rt/RT-SPC56EC-EVB/chconf.h new file mode 100644 index 000000000..d65051ce3 --- /dev/null +++ b/demos/rt/RT-SPC56EC-EVB/chconf.h @@ -0,0 +1,498 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 0 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_TRACE FALSE + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/rt/RT-SPC56EC-EVB/halconf.h b/demos/rt/RT-SPC56EC-EVB/halconf.h new file mode 100644 index 000000000..3858828e6 --- /dev/null +++ b/demos/rt/RT-SPC56EC-EVB/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/rt/RT-SPC56EC-EVB/main.c b/demos/rt/RT-SPC56EC-EVB/main.c new file mode 100644 index 000000000..bb670c8d1 --- /dev/null +++ b/demos/rt/RT-SPC56EC-EVB/main.c @@ -0,0 +1,203 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "chprintf.h" + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(1024) +#define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256) + +static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t n, size; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: mem\r\n"); + return; + } + n = chHeapStatus(NULL, &size); + chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus()); + chprintf(chp, "heap fragments : %u\r\n", n); + chprintf(chp, "heap free total : %u bytes\r\n", size); +} + +static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *states[] = {CH_STATE_NAMES}; + thread_t *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: threads\r\n"); + return; + } + chprintf(chp, " addr stack prio refs state time\r\n"); + tp = chRegFirstThread(); + do { + chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s\r\n", + (uint32_t)tp, (uint32_t)tp->p_ctx.sp, + (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1), + states[tp->p_state]); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) { + thread_t *tp; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: test\r\n"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriorityX(), + TestThread, chp); + if (tp == NULL) { + chprintf(chp, "out of memory\r\n"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SD1, + commands +}; + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + + while (TRUE) { + unsigned i; + + for (i = 0; i < 4; i++) { + palClearPad(PORT_E, PE_LED1); + chThdSleepMilliseconds(100); + palClearPad(PORT_E, PE_LED2); + chThdSleepMilliseconds(100); + palClearPad(PORT_E, PE_LED3); + chThdSleepMilliseconds(100); + palClearPad(PORT_E, PE_LED4); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED1); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED2); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED3); + chThdSleepMilliseconds(100); + palSetPad(PORT_E, PE_LED4); + chThdSleepMilliseconds(300); + } + + for (i = 0; i < 4; i++) { + palTogglePort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED2) | + PAL_PORT_BIT(PE_LED3) | PAL_PORT_BIT(PE_LED4)); + chThdSleepMilliseconds(500); + palTogglePort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED2) | + PAL_PORT_BIT(PE_LED3) | PAL_PORT_BIT(PE_LED4)); + chThdSleepMilliseconds(500); + } + + for (i = 0; i < 4; i++) { + palTogglePad(PORT_E, PE_LED1); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED1); + palTogglePad(PORT_E, PE_LED2); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED2); + palTogglePad(PORT_E, PE_LED3); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED3); + palTogglePad(PORT_E, PE_LED4); + chThdSleepMilliseconds(250); + palTogglePad(PORT_E, PE_LED4); + } + + for (i = 0; i < 4; i++) { + palClearPort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED3)); + palSetPort(PORT_E, PAL_PORT_BIT(PE_LED2) | PAL_PORT_BIT(PE_LED4)); + chThdSleepMilliseconds(500); + palClearPort(PORT_E, PAL_PORT_BIT(PE_LED2) | PAL_PORT_BIT(PE_LED4)); + palSetPort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED3)); + chThdSleepMilliseconds(500); + } + + palSetPort(PORT_E, PAL_PORT_BIT(PE_LED1) | PAL_PORT_BIT(PE_LED2) | + PAL_PORT_BIT(PE_LED3) | PAL_PORT_BIT(PE_LED4)); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + thread_t *shelltp = NULL; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminatedX(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chThdSleepMilliseconds(1000); + } + return 0; +} diff --git a/demos/rt/RT-SPC56EC-EVB/mcuconf.h b/demos/rt/RT-SPC56EC-EVB/mcuconf.h new file mode 100644 index 000000000..06e494cbf --- /dev/null +++ b/demos/rt/RT-SPC56EC-EVB/mcuconf.h @@ -0,0 +1,288 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC56ECxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC56ECxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 60 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_XOSCDIV_VALUE 1 +#define SPC5_IRCDIV_VALUE 1 +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 4 +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#define SPC5_Z0_CLK_DIV_VALUE 2 +#define SPC5_FEC_CLK_DIV_VALUE 2 +#define SPC5_FLASH_CLK_DIV_VALUE 2 +#define SPC5_CLOCK_FAILURE_HOOK() osalSysHalt("clock failure") + +#define SPC5_EMIOS0_GPRE_VALUE 20 +#define SPC5_EMIOS1_GPRE_VALUE 20 + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_EMLM | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 12 +#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure") + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 FALSE +#define SPC5_SERIAL_USE_LINFLEX2 FALSE +#define SPC5_SERIAL_USE_LINFLEX3 FALSE +#define SPC5_SERIAL_USE_LINFLEX4 FALSE +#define SPC5_SERIAL_USE_LINFLEX5 FALSE +#define SPC5_SERIAL_USE_LINFLEX6 FALSE +#define SPC5_SERIAL_USE_LINFLEX7 FALSE +#define SPC5_SERIAL_USE_LINFLEX8 FALSE +#define SPC5_SERIAL_USE_LINFLEX9 FALSE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX2_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX3_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX4_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX5_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX6_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX7_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX8_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX9_PRIORITY 8 + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 FALSE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_USE_DSPI3 FALSE +#define SPC5_SPI_USE_DSPI4 FALSE +#define SPC5_SPI_USE_DSPI5 FALSE +#define SPC5_SPI_USE_DSPI6 FALSE +#define SPC5_SPI_USE_DSPI7 FALSE +#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_RX_ONLY +#define SPC5_SPI_DSPI0_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1 | SPC5_MCR_PCSIS2 | SPC5_MCR_PCSIS3 | SPC5_MCR_PCSIS4 | SPC5_MCR_PCSIS5) +#define SPC5_SPI_DSPI1_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1 | SPC5_MCR_PCSIS2 | SPC5_MCR_PCSIS3 | SPC5_MCR_PCSIS4) +#define SPC5_SPI_DSPI2_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1 | SPC5_MCR_PCSIS2 | SPC5_MCR_PCSIS3) +#define SPC5_SPI_DSPI3_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1) +#define SPC5_SPI_DSPI4_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1) +#define SPC5_SPI_DSPI5_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1 | SPC5_MCR_PCSIS2) +#define SPC5_SPI_DSPI6_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1 | SPC5_MCR_PCSIS2 | SPC5_MCR_PCSIS3) +#define SPC5_SPI_DSPI7_MCR (0 | SPC5_MCR_PCSIS0 | SPC5_MCR_PCSIS1 | SPC5_MCR_PCSIS2 | SPC5_MCR_PCSIS3) +#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4 +#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5 +#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6 +#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7 +#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8 +#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9 +#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10 +#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11 +#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12 +#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 13 +#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 14 +#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 15 +#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID 16 +#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID 17 +#define SPC5_SPI_DSPI4_RX_DMA_CH_ID 18 +#define SPC5_SPI_DSPI5_TX1_DMA_CH_ID 19 +#define SPC5_SPI_DSPI5_TX2_DMA_CH_ID 20 +#define SPC5_SPI_DSPI5_RX_DMA_CH_ID 21 +#define SPC5_SPI_DSPI6_TX1_DMA_CH_ID 22 +#define SPC5_SPI_DSPI6_TX2_DMA_CH_ID 23 +#define SPC5_SPI_DSPI6_RX_DMA_CH_ID 24 +#define SPC5_SPI_DSPI7_TX1_DMA_CH_ID 25 +#define SPC5_SPI_DSPI7_TX2_DMA_CH_ID 26 +#define SPC5_SPI_DSPI7_RX_DMA_CH_ID 27 +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI5_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI6_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI7_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DSPI3_IRQ_PRIO 10 +#define SPC5_SPI_DSPI4_IRQ_PRIO 10 +#define SPC5_SPI_DSPI5_IRQ_PRIO 10 +#define SPC5_SPI_DSPI6_IRQ_PRIO 10 +#define SPC5_SPI_DSPI7_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DSPI DMA failure") + +/* + * ICU-PWM driver system settings. + */ +#define SPC5_ICU_USE_EMIOS0_CH0 FALSE +#define SPC5_ICU_USE_EMIOS0_CH1 FALSE +#define SPC5_ICU_USE_EMIOS0_CH2 FALSE +#define SPC5_ICU_USE_EMIOS0_CH3 FALSE +#define SPC5_ICU_USE_EMIOS0_CH4 FALSE +#define SPC5_ICU_USE_EMIOS0_CH5 FALSE +#define SPC5_ICU_USE_EMIOS0_CH6 FALSE +#define SPC5_ICU_USE_EMIOS0_CH7 FALSE +#define SPC5_ICU_USE_EMIOS0_CH24 FALSE + +#define SPC5_PWM_USE_EMIOS0_GROUP0 FALSE +#define SPC5_PWM_USE_EMIOS0_GROUP1 FALSE + +#define SPC5_EMIOS0_GFR_F0F1_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F2F3_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F4F5_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F6F7_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 8 +#define SPC5_EMIOS0_GFR_F24F25_PRIORITY 8 + +#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ICU_USE_EMIOS1_CH24 FALSE + +#define SPC5_PWM_USE_EMIOS1_GROUP0 FALSE +#define SPC5_PWM_USE_EMIOS1_GROUP1 FALSE +#define SPC5_PWM_USE_EMIOS1_GROUP2 FALSE + +#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 8 +#define SPC5_EMIOS1_GFR_F24F25_PRIORITY 8 + +#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * CAN driver system settings. + */ +#define SPC5_CAN_USE_FILTERS FALSE + +#define SPC5_CAN_USE_FLEXCAN0 FALSE +#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK FALSE +#define SPC5_CAN_FLEXCAN0_PRIORITY 11 +#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN1 FALSE +#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK FALSE +#define SPC5_CAN_FLEXCAN1_PRIORITY 11 +#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN2 FALSE +#define SPC5_CAN_FLEXCAN2_USE_EXT_CLK FALSE +#define SPC5_CAN_FLEXCAN2_PRIORITY 11 +#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN3 FALSE +#define SPC5_CAN_FLEXCAN3_USE_EXT_CLK FALSE +#define SPC5_CAN_FLEXCAN3_PRIORITY 11 +#define SPC5_CAN_FLEXCAN3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN4 FALSE +#define SPC5_CAN_FLEXCAN4_USE_EXT_CLK FALSE +#define SPC5_CAN_FLEXCAN4_PRIORITY 11 +#define SPC5_CAN_FLEXCAN4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_CAN_USE_FLEXCAN5 FALSE +#define SPC5_CAN_FLEXCAN5_USE_EXT_CLK FALSE +#define SPC5_CAN_FLEXCAN5_PRIORITY 11 +#define SPC5_CAN_FLEXCAN5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_CAN_FLEXCAN5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* +* ADC driver system settings. +*/ +#define SPC5_ADC_USE_ADC0 FALSE +#define SPC5_ADC_ADC0_CLK_FREQUENCY HALF_PERIPHERAL_SET_CLOCK_FREQUENCY +#define SPC5_ADC_ADC0_AUTO_CLOCK_OFF FALSE +#define SPC5_ADC_ADC0_WD_PRIORITY 12 +#define SPC5_ADC_ADC0_DMA_CH_ID 1 +#define SPC5_ADC_ADC0_DMA_IRQ_PRIO 12 +#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +#define SPC5_ADC_USE_ADC1 FALSE +#define SPC5_ADC_ADC1_CLK_FREQUENCY HALF_PERIPHERAL_SET_CLOCK_FREQUENCY +#define SPC5_ADC_ADC1_AUTO_CLOCK_OFF FALSE +#define SPC5_ADC_ADC1_WD_PRIORITY 12 +#define SPC5_ADC_ADC1_DMA_CH_ID 2 +#define SPC5_ADC_ADC1_DMA_IRQ_PRIO 12 +#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld b/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld new file mode 100644 index 000000000..d37b357c9 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC56EC74 memory setup. + */ +MEMORY +{ + flash : org = 0x00000000, len = 3M + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 256k +} + +INCLUDE rules_z4.ld diff --git a/os/common/ports/e200/devices/SPC56ECxx/boot.h b/os/common/ports/e200/devices/SPC56ECxx/boot.h new file mode 100644 index 000000000..74d0cfe90 --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ECxx/boot.h @@ -0,0 +1,252 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file boot.h + * @brief Boot parameters for the SPC56ECxx. + * @{ + */ + +#ifndef _BOOT_H_ +#define _BOOT_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name MASx registers definitions + * @{ + */ +#define MAS0_TBLMAS_TBL 0x10000000 +#define MAS0_ESEL_MASK 0x000F0000 +#define MAS0_ESEL(n) ((n) << 16) + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID_MASK 0x00FF0000 +#define MAS1_TS 0x00001000 +#define MAS1_TSISE_MASK 0x00000F80 +#define MAS1_TSISE_1K 0x00000000 +#define MAS1_TSISE_2K 0x00000080 +#define MAS1_TSISE_4K 0x00000100 +#define MAS1_TSISE_8K 0x00000180 +#define MAS1_TSISE_16K 0x00000200 +#define MAS1_TSISE_32K 0x00000280 +#define MAS1_TSISE_64K 0x00000300 +#define MAS1_TSISE_128K 0x00000380 +#define MAS1_TSISE_256K 0x00000400 +#define MAS1_TSISE_512K 0x00000480 +#define MAS1_TSISE_1M 0x00000500 +#define MAS1_TSISE_2M 0x00000580 +#define MAS1_TSISE_4M 0x00000600 +#define MAS1_TSISE_8M 0x00000680 +#define MAS1_TSISE_16M 0x00000700 +#define MAS1_TSISE_32M 0x00000780 +#define MAS1_TSISE_64M 0x00000800 +#define MAS1_TSISE_128M 0x00000880 +#define MAS1_TSISE_256M 0x00000900 +#define MAS1_TSISE_512M 0x00000980 +#define MAS1_TSISE_1G 0x00000A00 +#define MAS1_TSISE_2G 0x00000A80 +#define MAS1_TSISE_4G 0x00000B00 + +#define MAS2_EPN_MASK 0xFFFFFC00 +#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) +#define MAS2_EBOOK 0x00000000 +#define MAS2_VLE 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 + +#define MAS3_RPN_MASK 0xFFFFFC00 +#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 +/** @} */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BPRED_MASK 0x00000006 +#define BUCSR_BPRED_0 0x00000000 +#define BUCSR_BPRED_1 0x00000002 +#define BUCSR_BPRED_2 0x00000004 +#define BUCSR_BPRED_3 0x00000006 +#define BUCSR_BALLOC_MASK 0x00000030 +#define BUCSR_BALLOC_0 0x00000000 +#define BUCSR_BALLOC_1 0x00000010 +#define BUCSR_BALLOC_2 0x00000020 +#define BUCSR_BALLOC_3 0x00000030 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name LICSR1 registers definitions + * @{ + */ +#define LICSR1_ICE 0x00000001 +#define LICSR1_ICINV 0x00000002 +#define LICSR1_ICORG 0x00000010 +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_UCLE 0x04000000 +#define MSR_SPE 0x02000000 +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_FP 0x00002000 +#define MSR_ME 0x00001000 +#define MSR_FE0 0x00000800 +#define MSR_DE 0x00000200 +#define MSR_FE1 0x00000100 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/* + * TLB default settings. + */ +#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) +#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M) +#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) +#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) +#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) +#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) +#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) +#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) +#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) +#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) +#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) +#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I) +#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5)) +#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) +#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +/* + * BUCSR default settings. + */ +#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ + BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) +#endif + +/* + * LICSR1 default settings. + */ +#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) +#endif + +/* + * MSR default settings. + */ +#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) +#endif + +/* + * Boot default settings. + */ +#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) +#define BOOT_PERFORM_CORE_INIT 1 +#endif + +/* + * VLE mode default settings. + */ +#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) +#define BOOT_USE_VLE 1 +#endif + +/* + * RAM relocation flag. + */ +#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) +#define BOOT_RELOCATE_IN_RAM 0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* _BOOT_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC56ECxx/boot.s b/os/common/ports/e200/devices/SPC56ECxx/boot.s new file mode 100644 index 000000000..10319e6e2 --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ECxx/boot.s @@ -0,0 +1,407 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC56ECxx/boot.s + * @brief SPC56ECxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + +#if BOOT_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_ramcode: + tlbwe + isync + blr + + .align 2 +_coreinit: + /* + * Invalidating all TLBs except TLB0. + */ + lis %r3, 0 + mtspr 625, %r3 /* MAS1 */ + mtspr 626, %r3 /* MAS2 */ + mtspr 627, %r3 /* MAS3 */ + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + + /* + * TLB1 allocated to internal RAM. + */ + lis %r3, TLB1_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB1_MAS1@h + ori %r3, %r3, TLB1_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB1_MAS2@h + ori %r3, %r3, TLB1_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB1_MAS3@h + ori %r3, %r3, TLB1_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB2 allocated to internal Peripherals Bridge A. + */ + lis %r3, TLB2_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB2_MAS1@h + ori %r3, %r3, TLB2_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB2_MAS2@h + ori %r3, %r3, TLB2_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB2_MAS3@h + ori %r3, %r3, TLB2_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB3 allocated to internal Peripherals Bridge B. + */ + lis %r3, TLB3_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB3_MAS1@h + ori %r3, %r3, TLB3_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB3_MAS2@h + ori %r3, %r3, TLB3_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB3_MAS3@h + ori %r3, %r3, TLB3_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB4 allocated to on-platform peripherals. + */ + lis %r3, TLB4_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB4_MAS1@h + ori %r3, %r3, TLB4_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB4_MAS2@h + ori %r3, %r3, TLB4_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB4_MAS3@h + ori %r3, %r3, TLB4_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB5 allocated to on-platform peripherals. + */ + lis %r3, TLB5_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB5_MAS1@h + ori %r3, %r3, TLB5_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB5_MAS2@h + ori %r3, %r3, TLB5_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB5_MAS3@h + ori %r3, %r3, TLB5_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Special function registers clearing, required in order to avoid + * possible problems with lockstep mode. + */ + mtcrf 0xFF, %r31 + mtspr 9, %r31 /* CTR */ + mtspr 22, %r31 /* DEC */ + mtspr 26, %r31 /* SRR0-1 */ + mtspr 27, %r31 + mtspr 54, %r31 /* DECAR */ + mtspr 58, %r31 /* CSRR0-1 */ + mtspr 59, %r31 + mtspr 61, %r31 /* DEAR */ + mtspr 256, %r31 /* USPRG0 */ + mtspr 272, %r31 /* SPRG1-7 */ + mtspr 273, %r31 + mtspr 274, %r31 + mtspr 275, %r31 + mtspr 276, %r31 + mtspr 277, %r31 + mtspr 278, %r31 + mtspr 279, %r31 + mtspr 285, %r31 /* TBU */ + mtspr 284, %r31 /* TBL */ +#if 0 + mtspr 318, %r31 /* DVC1-2 */ + mtspr 319, %r31 +#endif + mtspr 562, %r31 /* DBCNT */ + mtspr 570, %r31 /* MCSRR0 */ + mtspr 571, %r31 /* MCSRR1 */ + mtspr 604, %r31 /* SPRG8-9 */ + mtspr 605, %r31 + + /* + * *Finally* the TLB0 is re-allocated to flash, note, the final phase + * is executed from RAM. + */ + lis %r3, TLB0_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB0_MAS1@h + ori %r3, %r3, TLB0_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB0_MAS2@h + ori %r3, %r3, TLB0_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB0_MAS3@h + ori %r3, %r3, TLB0_MAS3@l + mtspr 627, %r3 /* MAS3 */ + mflr %r4 + lis %r6, _ramcode@h + ori %r6, %r6, _ramcode@l + lis %r7, 0x40010000@h + mtctr %r7 + lwz %r3, 0(%r6) + stw %r3, 0(%r7) + lwz %r3, 4(%r6) + stw %r3, 4(%r7) + lwz %r3, 8(%r6) + stw %r3, 8(%r7) + bctrl + mtlr %r4 + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + /* + * Cache invalidated and then enabled. + */ + li %r3, LICSR1_ICINV + mtspr 1011, %r3 /* LICSR1 */ +.inv: mfspr %r3, 1011 /* LICSR1 */ + andi. %r3, %r3, LICSR1_ICINV + bne .inv + lis %r3, BOOT_LICSR1_DEFAULT@h + ori %r3, %r3, BOOT_LICSR1_DEFAULT@l + mtspr 1011, %r3 /* LICSR1 */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h b/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h new file mode 100644 index 000000000..d46216e73 --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC56ECxx/ppcparams.h + * @brief PowerPC parameters for the SPC56ECxx. + * + * @defgroup PPC_SPC56ECxx SPC56ECxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC56ECxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z4 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 16 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS TRUE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE TRUE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER TRUE + +/** + * @brief Number of interrupt sources. + */ +#define PPC_NUM_VECTORS 279 + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC56ELxx/boot.h b/os/common/ports/e200/devices/SPC56ELxx/boot.h new file mode 100644 index 000000000..9bc54e695 --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ELxx/boot.h @@ -0,0 +1,252 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file boot.h + * @brief Boot parameters for the SPC56ELxx. + * @{ + */ + +#ifndef _BOOT_H_ +#define _BOOT_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name MASx registers definitions + * @{ + */ +#define MAS0_TBLMAS_TBL 0x10000000 +#define MAS0_ESEL_MASK 0x000F0000 +#define MAS0_ESEL(n) ((n) << 16) + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID_MASK 0x00FF0000 +#define MAS1_TS 0x00001000 +#define MAS1_TSISE_MASK 0x00000F80 +#define MAS1_TSISE_1K 0x00000000 +#define MAS1_TSISE_2K 0x00000080 +#define MAS1_TSISE_4K 0x00000100 +#define MAS1_TSISE_8K 0x00000180 +#define MAS1_TSISE_16K 0x00000200 +#define MAS1_TSISE_32K 0x00000280 +#define MAS1_TSISE_64K 0x00000300 +#define MAS1_TSISE_128K 0x00000380 +#define MAS1_TSISE_256K 0x00000400 +#define MAS1_TSISE_512K 0x00000480 +#define MAS1_TSISE_1M 0x00000500 +#define MAS1_TSISE_2M 0x00000580 +#define MAS1_TSISE_4M 0x00000600 +#define MAS1_TSISE_8M 0x00000680 +#define MAS1_TSISE_16M 0x00000700 +#define MAS1_TSISE_32M 0x00000780 +#define MAS1_TSISE_64M 0x00000800 +#define MAS1_TSISE_128M 0x00000880 +#define MAS1_TSISE_256M 0x00000900 +#define MAS1_TSISE_512M 0x00000980 +#define MAS1_TSISE_1G 0x00000A00 +#define MAS1_TSISE_2G 0x00000A80 +#define MAS1_TSISE_4G 0x00000B00 + +#define MAS2_EPN_MASK 0xFFFFFC00 +#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) +#define MAS2_EBOOK 0x00000000 +#define MAS2_VLE 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 + +#define MAS3_RPN_MASK 0xFFFFFC00 +#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 +/** @} */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BPRED_MASK 0x00000006 +#define BUCSR_BPRED_0 0x00000000 +#define BUCSR_BPRED_1 0x00000002 +#define BUCSR_BPRED_2 0x00000004 +#define BUCSR_BPRED_3 0x00000006 +#define BUCSR_BALLOC_MASK 0x00000030 +#define BUCSR_BALLOC_0 0x00000000 +#define BUCSR_BALLOC_1 0x00000010 +#define BUCSR_BALLOC_2 0x00000020 +#define BUCSR_BALLOC_3 0x00000030 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name LICSR1 registers definitions + * @{ + */ +#define LICSR1_ICE 0x00000001 +#define LICSR1_ICINV 0x00000002 +#define LICSR1_ICORG 0x00000010 +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_UCLE 0x04000000 +#define MSR_SPE 0x02000000 +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_FP 0x00002000 +#define MSR_ME 0x00001000 +#define MSR_FE0 0x00000800 +#define MSR_DE 0x00000200 +#define MSR_FE1 0x00000100 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/* + * TLB default settings. + */ +#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) +#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M) +#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) +#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) +#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) +#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) +#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) +#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) +#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) +#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) +#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) +#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I) +#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5)) +#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) +#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +/* + * BUCSR default settings. + */ +#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ + BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) +#endif + +/* + * LICSR1 default settings. + */ +#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) +#endif + +/* + * MSR default settings. + */ +#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) +#endif + +/* + * Boot default settings. + */ +#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) +#define BOOT_PERFORM_CORE_INIT 1 +#endif + +/* + * VLE mode default settings. + */ +#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) +#define BOOT_USE_VLE 1 +#endif + +/* + * RAM relocation flag. + */ +#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) +#define BOOT_RELOCATE_IN_RAM 0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* _BOOT_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC56ELxx/boot.s b/os/common/ports/e200/devices/SPC56ELxx/boot.s index 86e35b4ee..2a6c57f2c 100644 --- a/os/common/ports/e200/devices/SPC56ELxx/boot.s +++ b/os/common/ports/e200/devices/SPC56ELxx/boot.s @@ -26,192 +26,14 @@ * @{ */ - -/** - * @name MASx registers definitions - * @{ - */ -#define MAS0_TBLMAS_TBL 0x10000000 -#define MAS0_ESEL_MASK 0x000F0000 -#define MAS0_ESEL(n) ((n) << 16) - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID_MASK 0x00FF0000 -#define MAS1_TS 0x00001000 -#define MAS1_TSISE_MASK 0x00000F80 -#define MAS1_TSISE_1K 0x00000000 -#define MAS1_TSISE_2K 0x00000080 -#define MAS1_TSISE_4K 0x00000100 -#define MAS1_TSISE_8K 0x00000180 -#define MAS1_TSISE_16K 0x00000200 -#define MAS1_TSISE_32K 0x00000280 -#define MAS1_TSISE_64K 0x00000300 -#define MAS1_TSISE_128K 0x00000380 -#define MAS1_TSISE_256K 0x00000400 -#define MAS1_TSISE_512K 0x00000480 -#define MAS1_TSISE_1M 0x00000500 -#define MAS1_TSISE_2M 0x00000580 -#define MAS1_TSISE_4M 0x00000600 -#define MAS1_TSISE_8M 0x00000680 -#define MAS1_TSISE_16M 0x00000700 -#define MAS1_TSISE_32M 0x00000780 -#define MAS1_TSISE_64M 0x00000800 -#define MAS1_TSISE_128M 0x00000880 -#define MAS1_TSISE_256M 0x00000900 -#define MAS1_TSISE_512M 0x00000980 -#define MAS1_TSISE_1G 0x00000A00 -#define MAS1_TSISE_2G 0x00000A80 -#define MAS1_TSISE_4G 0x00000B00 - -#define MAS2_EPN_MASK 0xFFFFFC00 -#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) -#define MAS2_EBOOK 0x00000000 -#define MAS2_VLE 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 - -#define MAS3_RPN_MASK 0xFFFFFC00 -#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 -/** @} */ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BPRED_MASK 0x00000006 -#define BUCSR_BPRED_0 0x00000000 -#define BUCSR_BPRED_1 0x00000002 -#define BUCSR_BPRED_2 0x00000004 -#define BUCSR_BPRED_3 0x00000006 -#define BUCSR_BALLOC_MASK 0x00000030 -#define BUCSR_BALLOC_0 0x00000000 -#define BUCSR_BALLOC_1 0x00000010 -#define BUCSR_BALLOC_2 0x00000020 -#define BUCSR_BALLOC_3 0x00000030 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name LICSR1 registers definitions - * @{ - */ -#define LICSR1_ICE 0x00000001 -#define LICSR1_ICINV 0x00000002 -#define LICSR1_ICORG 0x00000010 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_UCLE 0x04000000 -#define MSR_SPE 0x02000000 -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_FP 0x00002000 -#define MSR_ME 0x00001000 -#define MSR_FE0 0x00000800 -#define MSR_DE 0x00000200 -#define MSR_FE1 0x00000100 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/* - * TLB default settings. - */ -#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) -#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M) -#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) -#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \ - MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ - MAS3_UR | MAS3_SR) - -#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) -#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) -#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) -#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \ - MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ - MAS3_UR | MAS3_SR) - -#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) -#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) -#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) -#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) -#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) -#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I) -#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5)) -#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) -#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) -#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \ - MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) - -/* - * BUCSR default settings. - */ -#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ - BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) - -/* - * LICSR1 default settings. - */ -#define LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) - -/* - * MSR default settings. - */ -#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) - -/* - * Boot default settings. - */ -#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) -#define BOOT_PERFORM_CORE_INIT 1 -#endif - -/* - * VLE mode default settings. - */ -#if !defined(PPC_USE_VLE) || defined(__DOXYGEN__) -#define PPC_USE_VLE 1 -#endif +#include "boot.h" #if !defined(__DOXYGEN__) /* BAM record.*/ .section .boot, "ax" -#if PPC_USE_VLE +#if BOOT_USE_VLE .long 0x015A0000 #else .long 0x005A0000 @@ -222,12 +44,35 @@ .globl _reset_address .type _reset_address, @function _reset_address: -#if BOOT_PERFORM_CORE_INIT bl _coreinit -#endif bl _ivinit +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else b _boot_address +#endif #if BOOT_PERFORM_CORE_INIT .align 2 @@ -235,9 +80,11 @@ _ramcode: tlbwe isync blr +#endif /* BOOT_PERFORM_CORE_INIT */ .align 2 _coreinit: +#if BOOT_PERFORM_CORE_INIT /* * Invalidating all TLBs except TLB0. */ @@ -419,6 +266,7 @@ _coreinit: addi %r4, %r4, 64 b .cleareccloop .cleareccend: +#endif /* BOOT_PERFORM_CORE_INIT */ /* * Special function registers clearing, required in order to avoid @@ -454,6 +302,7 @@ _coreinit: mtspr 604, %r31 /* SPRG8-9 */ mtspr 605, %r31 +#if BOOT_PERFORM_CORE_INIT /* * *Finally* the TLB0 is re-allocated to flash, note, the final phase * is executed from RAM. @@ -482,11 +331,12 @@ _coreinit: stw %r3, 8(%r7) bctrl mtlr %r4 +#endif /* BOOT_PERFORM_CORE_INIT */ /* * Branch prediction enabled. */ - li %r3, BUCSR_DEFAULT + li %r3, BOOT_BUCSR_DEFAULT mtspr 1013, %r3 /* BUCSR */ /* @@ -497,12 +347,11 @@ _coreinit: .inv: mfspr %r3, 1011 /* LICSR1 */ andi. %r3, %r3, LICSR1_ICINV bne .inv - lis %r3, LICSR1_DEFAULT@h - ori %r3, %r3, LICSR1_DEFAULT@l + lis %r3, BOOT_LICSR1_DEFAULT@h + ori %r3, %r3, BOOT_LICSR1_DEFAULT@l mtspr 1011, %r3 /* LICSR1 */ blr -#endif /* BOOT_PERFORM_CORE_INIT */ /* * Exception vectors initialization. @@ -510,8 +359,8 @@ _coreinit: .align 2 _ivinit: /* MSR initialization.*/ - lis %r3, MSR_DEFAULT@h - ori %r3, %r3, MSR_DEFAULT@l + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l mtMSR %r3 /* IVPR initialization.*/ diff --git a/os/hal/boards/ST_EVB_SPC56EC/board.c b/os/hal/boards/ST_EVB_SPC56EC/board.c new file mode 100644 index 000000000..a2dafb994 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC56EC/board.c @@ -0,0 +1,73 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/ +static const spc_siu_init_t spc_siu_init[] = { + {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_BUTTON4), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_E, PE_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_E, PE_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_E, PE_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_E, PE_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {-1, 0, 0} +}; + +/* Initialization array for the PSMI registers.*/ +static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, +}; + +/** + * @brief PAL setup. + */ +const PALConfig pal_default_config = +{ + PAL_MODE_UNCONNECTED, + spc_siu_init, + spc_padsels_init +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + spc_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/os/hal/boards/ST_EVB_SPC56EC/board.h b/os/hal/boards/ST_EVB_SPC56EC/board.h new file mode 100644 index 000000000..aef240066 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC56EC/board.h @@ -0,0 +1,71 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for a generic SPC56ECxx board. + */ + +/* + * Board identifiers. + */ +#define BOARD_SPC56ECXX_EVB +#define BOARD_NAME "EVB with SPC56ECxx Mini Module" + +/* + * Device identifier. + */ +#define _SPC56EC74L8_ + +/* + * Board frequencies. + */ +#if !defined(SPC5_XOSC_CLK) +#define SPC5_XOSC_CLK 40000000 +#endif + +/* + * I/O definitions. + */ +#define PB_LIN0_TDX 2 +#define PB_LIN0_RDX 3 +#define PE_BUTTON1 0 +#define PE_BUTTON2 1 +#define PE_BUTTON3 2 +#define PE_BUTTON4 3 +#define PE_LED1 4 +#define PE_LED2 5 +#define PE_LED3 6 +#define PE_LED4 7 + +/* + * Support macros. + */ +#define PCR(port, pin) (((port) * 16) + (pin)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/ST_EVB_SPC56EC/board.mk b/os/hal/boards/ST_EVB_SPC56EC/board.mk new file mode 100644 index 000000000..c0d1627a1 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC56EC/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC56EC/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/os/hal/boards/ST_EVB_SPC56EC diff --git a/os/hal/boards/ST_EVB_SPC56EL/board.c b/os/hal/boards/ST_EVB_SPC56EL/board.c index 721f452e3..a6595d7d4 100644 --- a/os/hal/boards/ST_EVB_SPC56EL/board.c +++ b/os/hal/boards/ST_EVB_SPC56EL/board.c @@ -19,31 +19,35 @@ #if HAL_USE_PAL || defined(__DOXYGEN__) /* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/ static const spc_siu_init_t spc_siu_init[] = { - {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, - {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT}, - {PCR(PORT_D, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, - {PCR(PORT_D, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, - {PCR(PORT_D, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, - {PCR(PORT_D, PD_BUTTON4), PAL_LOW, PAL_MODE_INPUT}, - {PCR(PORT_D, PD_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, - {PCR(PORT_D, PD_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, - {PCR(PORT_D, PD_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, - {PCR(PORT_D, PD_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)}, + {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_BUTTON4), PAL_LOW, PAL_MODE_INPUT}, + {PCR(PORT_D, PD_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_D, PD_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_D, PD_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, + {PCR(PORT_D, PD_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL}, {-1, 0, 0} }; /* Initialization array for the PSMI registers.*/ static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, }; /** * @brief PAL setup. */ -const PALConfig pal_default_config = { - PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */ +const PALConfig pal_default_config = +{ + PAL_MODE_UNCONNECTED, spc_siu_init, spc_padsels_init }; @@ -63,5 +67,4 @@ void __early_init(void) { * Board-specific initialization code. */ void boardInit(void) { - } diff --git a/os/hal/boards/ST_EVB_SPC56EL/board.h b/os/hal/boards/ST_EVB_SPC56EL/board.h index d6bc39115..23815b747 100644 --- a/os/hal/boards/ST_EVB_SPC56EL/board.h +++ b/os/hal/boards/ST_EVB_SPC56EL/board.h @@ -18,14 +18,14 @@ #define _BOARD_H_ /* - * Setup for a generic SPC56ELxx proto board. + * Setup for a generic SPC56ELxx board. */ /* * Board identifiers. */ -#define BOARD_GENERIC_SPC56EL -#define BOARD_NAME "Generic SPC56ELxx" +#define BOARD_SPC56ELXX_EVB +#define BOARD_NAME "EVB with SPC56ELxx Mini Module" /* * Board frequencies. @@ -37,18 +37,16 @@ /* * I/O definitions. */ -#define PB_LIN0_TDX 2 -#define PB_LIN0_RDX 3 - -#define PD_BUTTON1 0 -#define PD_BUTTON2 1 -#define PD_BUTTON3 2 -#define PD_BUTTON4 3 - -#define PD_LED1 4 -#define PD_LED2 5 -#define PD_LED3 6 -#define PD_LED4 7 +#define PB_LIN0_TDX 2 +#define PB_LIN0_RDX 3 +#define PD_BUTTON1 0 +#define PD_BUTTON2 1 +#define PD_BUTTON3 2 +#define PD_BUTTON4 3 +#define PD_LED1 4 +#define PD_LED2 5 +#define PD_LED3 6 +#define PD_LED4 7 /* * Support macros. diff --git a/os/rt/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk b/os/rt/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk new file mode 100644 index 000000000..4a951d1c2 --- /dev/null +++ b/os/rt/ports/e200/compilers/GCC/mk/port_spc56ecxx.mk @@ -0,0 +1,14 @@ +# List of the ChibiOS/RT e200z4 SPC56ECxx port files. +PORTSRC = ${CHIBIOS}/os/rt/ports/e200/chcore.c + +PORTASM = $(CHIBIOS)/os/common/ports/e200/devices/SPC56ECxx/boot.s \ + $(CHIBIOS)/os/common/ports/e200/compilers/GCC/vectors.s \ + $(CHIBIOS)/os/common/ports/e200/compilers/GCC/crt0.s \ + $(CHIBIOS)/os/rt/ports/e200/compilers/GCC/ivor.s + +PORTINC = ${CHIBIOS}/os/common/ports/e200/compilers/GCC \ + ${CHIBIOS}/os/common/ports/e200/devices/SPC56ECxx \ + ${CHIBIOS}/os/rt/ports/e200 \ + ${CHIBIOS}/os/rt/ports/e200/compilers/GCC + +PORTLD = ${CHIBIOS}/os/common/ports/e200/compilers/GCC/ld -- cgit v1.2.3