From 84fcd0571ea085d691ca0f8d6d099aa870c384a3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 28 Aug 2011 17:44:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3267 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- todo.txt | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/todo.txt b/todo.txt index 6cf27e77e..5f38eb2a1 100644 --- a/todo.txt +++ b/todo.txt @@ -14,27 +14,35 @@ Current Pipeline (2.3.x): * Eclipse plugin. * FatFs 0.8x integration. * Kernel-only demo for users not interested in HAL (Cortex-Mx only). -X STM32L support. -X STM32L-Discovery demo and article. -X File System infrastructure. -X STM32F2xx support. - USB and USB_SERIAL APIs reclassification (if needed), incorporate the USB bus attach/detach handling in usbStart()/usbStop(). +- USB double buffering support for STM32 implementation. +X STM32L1xx support (verify and test existing STM32F1xx drivers). + - Specific ADC driver for STM32L1xx. + X STM32L-Discovery demo and article. +X STM32F2xx support (adapt and re-verify all drivers). + * New STM32 DMA helper driver abstracting differences between STM32F2xx and + other sub-families. + ? Specific ADC driver for STM32F2xx. - MMC_SPI driver revision and speedup. -- Test suite overhaul, the API should be more generic in order to be used - with different subsystems and not just the kernel. -- STM32 USB support for double buffering. -- LPC17xx support. X Implement the "transmission end" serial driver event on those platforms supporting the feature, so far only done in STM32 driver. X I2C device driver class support and at least one implementation. -- Reduce number of demos globally, add demos to a repository or on web site. - Required in order to reduce support effort. +X Evaluate a modified I2C API where the synchronous mode is default and the + callback mode optional. This would allow a portable I2C driver based on + a GPT instance. + - Software I2C implementation. - Add a CH_THREAD macro for threads declaration in order to hide compiler-specific optimizations for thread functions. All demos will have to be updated. +- LPC17xx support. Within 2.x.x +X File System infrastructure. +- Test suite overhaul, the API should be more generic in order to be used + with different subsystems and not just the kernel. +- Reduce number of demos globally, add demos to a repository or on web site. + Required in order to reduce support effort. - Improved Makefile system. - MAC driver for STM32F107. - FatFs wrapper. -- cgit v1.2.3 -- cgit v1.2.3 From 22d2162db773e677c900b8b397889b7087470248 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 30 Aug 2011 22:52:11 +0000 Subject: RTC. Initial commit. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3269 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/hal.mk | 3 +- os/hal/include/hal.h | 1 + os/hal/include/rtc.h | 77 +++++++++++ os/hal/platforms/STM32/rtc_lld.c | 236 +++++++++++++++++++++++++++++++++ os/hal/platforms/STM32/rtc_lld.h | 100 ++++++++++++++ os/hal/platforms/STM32F1xx/platform.mk | 3 +- os/hal/src/hal.c | 3 + os/hal/src/rtc.c | 108 +++++++++++++++ 8 files changed, 529 insertions(+), 2 deletions(-) create mode 100644 os/hal/include/rtc.h create mode 100644 os/hal/platforms/STM32/rtc_lld.c create mode 100644 os/hal/platforms/STM32/rtc_lld.h create mode 100644 os/hal/src/rtc.c diff --git a/os/hal/hal.mk b/os/hal/hal.mk index 762bda57f..87a3c6dc3 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -15,7 +15,8 @@ HALSRC = ${CHIBIOS}/os/hal/src/hal.c \ ${CHIBIOS}/os/hal/src/uart.c \ ${CHIBIOS}/os/hal/src/usb.c \ ${CHIBIOS}/os/hal/src/mmc_spi.c \ - ${CHIBIOS}/os/hal/src/serial_usb.c + ${CHIBIOS}/os/hal/src/serial_usb.c \ + ${CHIBIOS}/os/hal/src/rtc.c # Required include directories HALINC = ${CHIBIOS}/os/hal/include diff --git a/os/hal/include/hal.h b/os/hal/include/hal.h index 1ed893aab..b92789b02 100644 --- a/os/hal/include/hal.h +++ b/os/hal/include/hal.h @@ -49,6 +49,7 @@ #include "usb.h" #include "mmc_spi.h" #include "serial_usb.h" +#include "rtc.h" /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h new file mode 100644 index 000000000..4a36f4317 --- /dev/null +++ b/os/hal/include/rtc.h @@ -0,0 +1,77 @@ +/** + * @file rtc.h + * @brief RTC Driver macros and structures. + * + * @addtogroup RTC + * @{ + */ + + +#ifndef _RTC_H_ +#define _RTC_H_ + + + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +/* TODO: move this to hal_lld_f103.h & mcuconf.h */ +#define STM32_LSECLK 32768 /**< Low speed external clock. */ + + +/* RCC_CFGR register bits definitions.*/ +#define STM32_RTC_NONE (0 << 8) /**< */ +#define STM32_RTC_LSE (1 << 8) /**< LSE oscillator clock used as RTC clock */ +#define STM32_RTC_LSI (2 << 8) /**< LSI oscillator clock used as RTC clock */ +#define STM32_RTC_HSE (3 << 8) /**< HSE oscillator clock divided by 128 used as RTC clock */ + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +typedef struct RTCDriver RTCDriver; + +typedef void (*rtccb_t)(RTCDriver *rtcp); + +#include "rtc_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void rtcInit(void); +#if RTC_SUPPORTS_CALLBACKS + void rtcStart(RTCDriver *rtcp, RTCConfig *rtccfgp); + void rtcStop(void); +#endif /* RTC_SUPPORTS_CALLBACKS */ + void rtcSetTime(uint32_t tv_sec); + uint32_t rtcGetSec(void); + uint16_t rtcGetMsec(void); + void rtcSetAlarm(uint32_t tv_alarm); + uint32_t rtcGetAlarm(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ +#endif /* _RTC_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c new file mode 100644 index 000000000..4af863005 --- /dev/null +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -0,0 +1,236 @@ +/** + * @file STM32/rtc_lld.c + * @brief STM32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#include "ch.h" +#include "hal.h" + + + + + + +// TODO: defines look in 4492 stm32f10x.h + + + + + +/** The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected +by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). +This selection +CANNOT +be modified without resetting the Backup domain. + +The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. +Consequently: +* If LSE is selected as RTC clock: +– The RTC continues to work even if the VDD supply is switched off, provided the +VBAT supply is maintained. +* If LSI is selected as Auto-Wakeup unit (AWU) clock: +– The AWU state is not guaranteed if the VDD supply is powered off. Refer to +Section 6.2.5: LSI clock on page 87 for more details on LSI calibration. +* If the HSE clock divided by 128 is used as the RTC clock: +– The RTC state is not guaranteed if the VDD supply is powered off or if the internal +voltage regulator is powered off (removing power from the 1.8 V domain). +– The DPB bit (Disable backup domain write protection) in the Power controller +register must be set to 1 (refer to Section 4.4.1: Power control register +(PWR_CR)). +*/ + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +RTCDriver RTCD; + + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] rtcp pointer to a @p RTCDriver object + */ +#if RTC_SUPPORTS_CALLBACKS + +static void rtc_lld_serve_interrupt(RTCDriver *rtcp){ + chSysLockFromIsr(); +//TODO: do not forget to reset flags manually + if (RTC->CRL & RTC_CRL_SECF){ + rtcp->config->second_cb(rtcp); + RTC->CRL &= ~RTC_CRL_SECF; + } + if (RTC->CRL & RTC_CRL_ALRF){ + rtcp->config->alarm_cb(rtcp); + RTC->CRL &= ~RTC_CRL_ALRF; + } + if (RTC->CRL & RTC_CRL_OWF){ + rtcp->config->overflow_cb(rtcp); + RTC->CRL &= ~RTC_CRL_OWF; + } + chSysUnlockFromIsr(); +} +#endif /* RTC_SUPPORTS_CALLBACKS */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief RTC interrupt handler. + * @isr + */ +#if RTC_SUPPORTS_CALLBACKS + +CH_IRQ_HANDLER(RTC_IRQHandler) { + CH_IRQ_PROLOGUE(); + rtc_lld_serve_interrupt(&RTCD); + CH_IRQ_EPILOGUE(); +} + +#endif /* RTC_SUPPORTS_CALLBACKS */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enable access to registers and initialize RTC if BKP domain + * was previously reseted. + */ +void rtc_lld_init(void){ + RCC->APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); /* enable clocking */ + PWR->CR |= PWR_CR_DBP; /* enable access */ + + if (!(RCC->BDCR & (RCC_BDCR_RTCEN | RCC_BDCR_LSEON))){ /* BKP domain was reseted */ + RCC->BDCR |= STM32_RTC_LSE; /* select clocking from LSE */ + RCC->BDCR |= RCC_BDCR_LSEON; /* switch LSE on */ + while(!(RCC->BDCR & RCC_BDCR_LSEON)) /* wait for stabilization */ + ; + RCC->BDCR |= RCC_BDCR_RTCEN; /* run clock */ + } + + /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling + * clocking on APB1, because these values only update when APB1 functioning.*/ + RTC->CRL &= ~(RTC_CRL_RSF); + while (!(RTC->CRL & RTC_CRL_RSF)) + ; +} + +/** + * @brief Configure and start interrupt servicing routines. + * + * @param[in] rtcp pointer to a @p RTCDriver object + * @param[in] rtccfgp pointer to a @p RTCDriver config object + */ +#if RTC_SUPPORTS_CALLBACKS +void rtc_lld_start(RTCDriver *rtcp, RTCConfig *rtccfgp){ + uint16_t flags = 0; + + NVICEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); + + rtcp->config = rtccfgp; + if (rtcp->config->overflow_cb != NULL){ + flags |= RTC_CRH_OWIE; + } + if (rtcp->config->alarm_cb != NULL){ + flags |= RTC_CRH_ALRIE; + } + if (rtcp->config->second_cb != NULL){ + flags |= RTC_CRH_SECIE; + } + + RTC->CRH |= flags; +} + +/** + * @brief Disable interrupt servicing routines. + */ +void rtc_lld_stop(void){ + NVICDisableVector(RTC_IRQn); + RTC->CRH = 0; +} +#endif /* RTC_SUPPORTS_CALLBACKS */ + + + +/** + * @brief Set current time. + * + * @param[in] tv_sec time value in UNIX notation. + */ +void rtc_lld_set_time(uint32_t tv_sec){ + uint32_t preload = STM32_LSECLK - 1UL; + + while(!(RTC->CRL & RTC_CRL_RTOFF)) + ; + + RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ + RTC->PRLH = (uint16_t)((preload >> 16) & 0b1111); /* write preloader */ + RTC->PRLL = (uint16_t)(preload & 0xFFFF); + RTC->CNTH = (uint16_t)((tv_sec >> 16) & 0xFFFF); /* write time */ + RTC->CNTL = (uint16_t)(tv_sec & 0xFFFF); + RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ + ; +} + +/** + * @brief Return current time in UNIX notation. + */ +uint32_t rtc_lld_get_sec(void){ + return ((RTC->CNTH << 16) + RTC->CNTL); +} + +/** + * @brief Return fractional part of current time (milliseconds). + */ +uint16_t rtc_lld_get_msec(void){ + uint32_t time_frac = 0; + time_frac = (((uint32_t)RTC->DIVH) << 16) + (RTC->DIVL); + return(((STM32_LSECLK - time_frac) * 1000) / STM32_LSECLK); +} + +/** + * @brief Set alarm date in UNIX notation. + */ +void rtc_lld_set_alarm(uint32_t tv_alarm){ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) + ; + + RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ + RTC->ALRH = (uint16_t)((tv_alarm >> 16) & 0xFFFF); /* write time */ + RTC->ALRL = (uint16_t)(tv_alarm & 0xFFFF); + RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ + ; +} + +/** + * @brief Get current alarm date in UNIX notation. + * @note Default value after reset is 0xFFFFFFFF + */ +uint32_t rtc_lld_get_alarm(void){ + return ((RTC->ALRH << 16) + RTC->ALRL); +} + + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h new file mode 100644 index 000000000..cf18b664c --- /dev/null +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -0,0 +1,100 @@ + +/** + * @file STM32/rtc_lld.h + * @brief STM32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef _RTC_LLD_H_ +#define _RTC_LLD_H_ + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @brief Switch to TRUE if you need callbacks from RTC. Switch to FALSE + * if you need only time keeping. + * @note Default is true. + */ +#if !defined(RTC_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) +#define RTC_SUPPORTS_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !STM32_HAS_RTC +#error "RTC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Structure representing an RTC driver config. + */ +typedef struct { + /** + * @brief Overflow callback. Set it to NULL if not used. + */ + rtccb_t overflow_cb; + + /** + * @brief Every second callback. Set it to NULL if not used. + */ + rtccb_t second_cb; + + /** + * @brief Alarm callback. Set it to NULL if not used. + */ + rtccb_t alarm_cb; +}RTCConfig; + + +/** + * @brief Structure representing an RTC driver. + */ +struct RTCDriver{ + /** + * @brief Pointer to RCT config. + */ + const RTCConfig *config; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_init(void); +#if RTC_SUPPORTS_CALLBACKS + void rtc_lld_start(RTCDriver *rtcp, RTCConfig *rtccfgp); + void rtc_lld_stop(void); +#endif /* RTC_SUPPORTS_CALLBACKS */ + void rtc_lld_set_time(uint32_t tv_sec); + uint32_t rtc_lld_get_sec(void); + uint16_t rtc_lld_get_msec(void); +#ifdef __cplusplus +} +#endif + + +#endif /* HAL_USE_RTC */ +#endif /* _RTC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk index 010a3f96d..26f13cd81 100644 --- a/os/hal/platforms/STM32F1xx/platform.mk +++ b/os/hal/platforms/STM32F1xx/platform.mk @@ -12,7 +12,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/uart_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/stm32_dma.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c + ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/rtc_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \ diff --git a/os/hal/src/hal.c b/os/hal/src/hal.c index ef7d7af8b..3c8fb2fe6 100644 --- a/os/hal/src/hal.c +++ b/os/hal/src/hal.c @@ -106,6 +106,9 @@ void halInit(void) { #endif #if HAL_USE_SERIAL_USB || defined(__DOXYGEN__) sduInit(); +#endif +#if HAL_USE_RTC || defined(__DOXYGEN__) + rtcInit(); #endif /* Board specific initialization.*/ boardInit(); diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c new file mode 100644 index 000000000..bb0dc11f0 --- /dev/null +++ b/os/hal/src/rtc.c @@ -0,0 +1,108 @@ +/** + * @file rtc.c + * @brief Real Time Clock Abstraction Layer code. + * + * @addtogroup RTC + * @{ + */ + +#include "ch.h" +#include "hal.h" + + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/** + * @brief Enable access to registers and initialize RTC if BKP doamin + * was previously reseted. + */ +void rtcInit(void){ + rtc_lld_init(); +} + +#if RTC_SUPPORTS_CALLBACKS +/** + * @brief Configure and start interrupt servicing routines. + * @param[in] rtcp - pointer to RTC driver structure. + * @param[in] rtccfgp - pointer to RTC config structure. + */ +void rtcStart(RTCDriver *rtcp, RTCConfig *rtccfgp){ + chDbgCheck(((rtcp != NULL) && (rtccfgp != NULL)), "rtcStart"); + rtc_lld_start(rtcp, rtccfgp); +} + +/** + * @brief Stop interrupt servicing routines. + */ +void rtcStop(void){ + rtc_lld_stop(); +} +#endif /* RTC_SUPPORTS_CALLBACKS */ + +/** + * @brief Set current time. + * @param[in] tv_sec - time value in UNIX notation. + */ +void rtcSetTime(uint32_t tv_sec){ + rtc_lld_set_time(tv_sec); +} + +/** + * @brief Return current time in UNIX notation. + */ +uint32_t rtcGetSec(void){ + return rtc_lld_get_sec(); +} + +/** + * @brief Return fractional part of current time (milliseconds). + */ +uint16_t rtcGetMsec(void){ + return rtc_lld_get_msec(); +} + +/** + * @brief Set alarm date in UNIX notation. + */ +void rtcSetAlarm(uint32_t tv_alarm){ + rtc_lld_set_alarm(tv_alarm); +} + +/** + * @brief Get current alarm date in UNIX notation. + */ +uint32_t rtcGetAlarm(void){ + return rtc_lld_get_alarm(); +} + + + + + + +#endif /* HAL_USE_RTC */ + + + +/** @} */ + + -- cgit v1.2.3 From 2991a477339a28ec275647930df45443a9f8a253 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 31 Aug 2011 09:34:42 +0000 Subject: RTC. nop git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3270 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/rtc.h | 2 +- os/hal/platforms/STM32/rtc_lld.c | 28 +++++++++++++++++++--------- os/hal/platforms/STM32/rtc_lld.h | 7 ++++++- os/hal/src/rtc.c | 3 ++- 4 files changed, 28 insertions(+), 12 deletions(-) diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h index 4a36f4317..474862910 100644 --- a/os/hal/include/rtc.h +++ b/os/hal/include/rtc.h @@ -59,7 +59,7 @@ extern "C" { #endif void rtcInit(void); #if RTC_SUPPORTS_CALLBACKS - void rtcStart(RTCDriver *rtcp, RTCConfig *rtccfgp); + void rtcStart(RTCDriver *rtcp, const RTCConfig *rtccfgp); void rtcStop(void); #endif /* RTC_SUPPORTS_CALLBACKS */ void rtcSetTime(uint32_t tv_sec); diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 4af863005..80f0185ba 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -48,6 +48,7 @@ register must be set to 1 (refer to Section 4.4.1: Power control register /* Driver exported variables. */ /*===========================================================================*/ +/** @brief RTC driver identifier.*/ RTCDriver RTCD; @@ -69,15 +70,21 @@ RTCDriver RTCD; static void rtc_lld_serve_interrupt(RTCDriver *rtcp){ chSysLockFromIsr(); //TODO: do not forget to reset flags manually - if (RTC->CRL & RTC_CRL_SECF){ + if ((RTC->CRH & RTC_CRH_SECIE) && \ + (RTC->CRL & RTC_CRL_SECF) && \ + (rtcp->config->second_cb != NULL)){ rtcp->config->second_cb(rtcp); RTC->CRL &= ~RTC_CRL_SECF; } - if (RTC->CRL & RTC_CRL_ALRF){ + if ((RTC->CRH & RTC_CRH_ALRIE) && \ + (RTC->CRL & RTC_CRL_ALRF) && \ + (rtcp->config->alarm_cb != NULL)){ rtcp->config->alarm_cb(rtcp); RTC->CRL &= ~RTC_CRL_ALRF; } - if (RTC->CRL & RTC_CRL_OWF){ + if ((RTC->CRH & RTC_CRH_OWIE) && \ + (RTC->CRL & RTC_CRL_OWF) && \ + (rtcp->config->overflow_cb != NULL)){ rtcp->config->overflow_cb(rtcp); RTC->CRL &= ~RTC_CRL_OWF; } @@ -128,6 +135,8 @@ void rtc_lld_init(void){ RTC->CRL &= ~(RTC_CRL_RSF); while (!(RTC->CRL & RTC_CRL_RSF)) ; + + RTCD.config = NULL; } /** @@ -137,23 +146,24 @@ void rtc_lld_init(void){ * @param[in] rtccfgp pointer to a @p RTCDriver config object */ #if RTC_SUPPORTS_CALLBACKS -void rtc_lld_start(RTCDriver *rtcp, RTCConfig *rtccfgp){ - uint16_t flags = 0; +void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp){ + uint16_t isr_flags = 0; NVICEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); rtcp->config = rtccfgp; if (rtcp->config->overflow_cb != NULL){ - flags |= RTC_CRH_OWIE; + isr_flags |= RTC_CRH_OWIE; } if (rtcp->config->alarm_cb != NULL){ - flags |= RTC_CRH_ALRIE; + isr_flags |= RTC_CRH_ALRIE; } if (rtcp->config->second_cb != NULL){ - flags |= RTC_CRH_SECIE; + isr_flags |= RTC_CRH_SECIE; } - RTC->CRH |= flags; + RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); /* clear all even flags*/ + RTC->CRH |= isr_flags; } /** diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h index cf18b664c..f26315784 100644 --- a/os/hal/platforms/STM32/rtc_lld.h +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -78,17 +78,22 @@ struct RTCDriver{ /* External declarations. */ /*===========================================================================*/ +extern RTCDriver RTCD; + + #ifdef __cplusplus extern "C" { #endif void rtc_lld_init(void); #if RTC_SUPPORTS_CALLBACKS - void rtc_lld_start(RTCDriver *rtcp, RTCConfig *rtccfgp); + void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp); void rtc_lld_stop(void); #endif /* RTC_SUPPORTS_CALLBACKS */ void rtc_lld_set_time(uint32_t tv_sec); uint32_t rtc_lld_get_sec(void); uint16_t rtc_lld_get_msec(void); + uint32_t rtc_lld_get_alarm(void); + void rtc_lld_set_alarm(uint32_t); #ifdef __cplusplus } #endif diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index bb0dc11f0..c6edca4a2 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -9,6 +9,7 @@ #include "ch.h" #include "hal.h" +#include "rtc_lld.h" #if HAL_USE_RTC || defined(__DOXYGEN__) @@ -45,7 +46,7 @@ void rtcInit(void){ * @param[in] rtcp - pointer to RTC driver structure. * @param[in] rtccfgp - pointer to RTC config structure. */ -void rtcStart(RTCDriver *rtcp, RTCConfig *rtccfgp){ +void rtcStart(RTCDriver *rtcp, const RTCConfig *rtccfgp){ chDbgCheck(((rtcp != NULL) && (rtccfgp != NULL)), "rtcStart"); rtc_lld_start(rtcp, rtccfgp); } -- cgit v1.2.3 From c8f60c27e1cdcd9d5a5592287d453d8d1fe0051f Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 31 Aug 2011 14:44:52 +0000 Subject: RTC. Small fixes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3271 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 80f0185ba..59699028d 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -10,16 +10,9 @@ #include "hal.h" - - - - // TODO: defines look in 4492 stm32f10x.h - - - /** The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection @@ -69,7 +62,7 @@ RTCDriver RTCD; static void rtc_lld_serve_interrupt(RTCDriver *rtcp){ chSysLockFromIsr(); -//TODO: do not forget to reset flags manually + if ((RTC->CRH & RTC_CRH_SECIE) && \ (RTC->CRL & RTC_CRL_SECF) && \ (rtcp->config->second_cb != NULL)){ @@ -88,6 +81,7 @@ static void rtc_lld_serve_interrupt(RTCDriver *rtcp){ rtcp->config->overflow_cb(rtcp); RTC->CRL &= ~RTC_CRL_OWF; } + chSysUnlockFromIsr(); } #endif /* RTC_SUPPORTS_CALLBACKS */ @@ -136,6 +130,10 @@ void rtc_lld_init(void){ while (!(RTC->CRL & RTC_CRL_RSF)) ; + /* disable all interrupts and clear all even flags just to be safe */ + RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE); + RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + RTCD.config = NULL; } -- cgit v1.2.3 From 7fd48a4a3f590d6cfe7cd98fe7dd96c7498f08e2 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 31 Aug 2011 15:27:46 +0000 Subject: RTC. Hal test added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3272 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/RTC/Makefile | 220 +++++++++++++++++ testhal/STM32F1xx/RTC/chconf.h | 509 ++++++++++++++++++++++++++++++++++++++++ testhal/STM32F1xx/RTC/halconf.h | 356 ++++++++++++++++++++++++++++ testhal/STM32F1xx/RTC/main.c | 62 +++++ testhal/STM32F1xx/RTC/main.h | 23 ++ testhal/STM32F1xx/RTC/mcuconf.h | 198 ++++++++++++++++ 6 files changed, 1368 insertions(+) create mode 100644 testhal/STM32F1xx/RTC/Makefile create mode 100644 testhal/STM32F1xx/RTC/chconf.h create mode 100644 testhal/STM32F1xx/RTC/halconf.h create mode 100644 testhal/STM32F1xx/RTC/main.c create mode 100644 testhal/STM32F1xx/RTC/main.h create mode 100644 testhal/STM32F1xx/RTC/mcuconf.h diff --git a/testhal/STM32F1xx/RTC/Makefile b/testhal/STM32F1xx/RTC/Makefile new file mode 100644 index 000000000..2f471c293 --- /dev/null +++ b/testhal/STM32F1xx/RTC/Makefile @@ -0,0 +1,220 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) +#-fno-inline +# Don't pay attention to the inline keyword. Normally this option is used to keep the compiler from expanding any functions inline. Note that if you are not optimizing, no functions can be expanded inline. +#-finline-functions +# Integrate all simple functions into their callers. The compiler heuristically decides which functions are simple enough to be worth integrating in this way. +# If all calls to a given function are integrated, and the function is declared static, then the function is normally not output as assembler code in its own right. +# Enabled at level '-O3'. + + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + #USE_OPT = -O1 -ggdb -fomit-frame-pointer -falign-functions=16 -fno-inline + #USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -fno-strict-aliasing + #USE_OPT = -O3 -ggdb -fomit-frame-pointer -falign-functions=16 + #USE_OPT = -Os -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c \ + + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. + +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk + + + diff --git a/testhal/STM32F1xx/RTC/chconf.h b/testhal/STM32F1xx/RTC/chconf.h new file mode 100644 index 000000000..d97168805 --- /dev/null +++ b/testhal/STM32F1xx/RTC/chconf.h @@ -0,0 +1,509 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 0//20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT FALSE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h new file mode 100644 index 000000000..219bfd99e --- /dev/null +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -0,0 +1,356 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(I2C_USE_WAIT) || defined(__DOXYGEN__) +#define I2C_USE_WAIT TRUE +#endif + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Switch to asynchronouse driver with callbacks. + */ +#if !defined(I2C_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) +#define I2C_SUPPORTS_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* RTC driver related settings. */ +/*===========================================================================*/ +/** + * @brief Switch to TRUE if you need callbacks from RTC. + */ +#if !defined(RTC_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) +#define RTC_SUPPORTS_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 9600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/RTC/main.c b/testhal/STM32F1xx/RTC/main.c new file mode 100644 index 000000000..b8c243810 --- /dev/null +++ b/testhal/STM32F1xx/RTC/main.c @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + + + +static void my_secondcb(RTCDriver *rtcp){ + (void)rtcp; + //palTogglePad(IOPORT3, GPIOC_LED); +} + +static void my_alarmcb(RTCDriver *rtcp){ + (void)rtcp; + palTogglePad(IOPORT3, GPIOC_LED); + rtcSetAlarm(rtcGetSec() + 10); +} + +static void my_overflowcb(RTCDriver *rtcp){ + (void)rtcp; + palTogglePad(IOPORT3, GPIOC_LED); + rtcSetAlarm(rtcGetSec() + 10); +} + +static const RTCConfig rtccfg={ + my_overflowcb, + my_secondcb, + my_alarmcb, +}; + + + +int main(void) { + halInit(); + chSysInit(); + + rtcSetAlarm(rtcGetSec() + 10); + rtcStart(&RTCD, &rtccfg); + + while (TRUE){ + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F1xx/RTC/main.h b/testhal/STM32F1xx/RTC/main.h new file mode 100644 index 000000000..31bd85a76 --- /dev/null +++ b/testhal/STM32F1xx/RTC/main.h @@ -0,0 +1,23 @@ +#ifndef MAIN_H_ +#define MAIN_H_ + +/****************************************************************** + * ãëîáàëüíûå ôëàãè + ******************************************************************/ +/* íàäî ëè ôèëüòðîâàòü äàííûå ñ äàò÷èêîâ */ +#define GET_FILTERED_DATA TRUE + +/* âêëþ÷èòü ñòðåññîâîå òåñòèðîâàíèå */ +#define ENABLE_IRQ_STORM FALSE + +// usefull macros +#define WATCHDOG_INIT {\ + DBGMCU->CR |= DBGMCU_CR_DBG_IWDG_STOP; /* stop watchdog timer in debugging mode */\ + IWDG->KR = 0x5555;/*unlock PR register*/\ + IWDG->PR = 16;/*set 1.6384s timeout*/\ + IWDG->KR = 0xCCCC;/*start watchdog*/} + +#define WATCHDOG_RELOAD {IWDG->KR = 0xAAAA;} + + +#endif /* MAIN_H_ */ diff --git a/testhal/STM32F1xx/RTC/mcuconf.h b/testhal/STM32F1xx/RTC/mcuconf.h new file mode 100644 index 000000000..fc7ce0053 --- /dev/null +++ b/testhal/STM32F1xx/RTC/mcuconf.h @@ -0,0 +1,198 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ +#include "main.h" +/* + * HAL driver system settings. + */ +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCO STM32_MCO_NOCLOCK + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 3 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_ERROR_HOOK() chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 15 +#define STM32_GPT_TIM4_IRQ_PRIORITY 15 +#define STM32_GPT_TIM5_IRQ_PRIORITY 15 +#define STM32_GPT_TIM8_IRQ_PRIORITY 15 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 2 +#define STM32_PWM_TIM2_IRQ_PRIORITY 2 +#define STM32_PWM_TIM3_IRQ_PRIORITY 2 +#define STM32_PWM_TIM4_IRQ_PRIORITY 2 +#define STM32_PWM_TIM5_IRQ_PRIORITY 2 +#define STM32_PWM_TIM8_IRQ_PRIORITY 2 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 9 +#define STM32_SERIAL_USART2_PRIORITY 10 +#define STM32_SERIAL_USART3_PRIORITY 2 +#define STM32_SERIAL_UART4_PRIORITY 2 +#define STM32_SERIAL_UART5_PRIORITY 2 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 10 +#define STM32_UART_USART2_IRQ_PRIORITY 10 +#define STM32_UART_USART3_IRQ_PRIORITY 10 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_I2C1_IRQ_PRIORITY 8 +#define STM32_I2C_I2C2_IRQ_PRIORITY 8 +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +/* I2C1 */ +#define STM32_I2C_I2C1_USE_GPT_TIM GPTD1 +#define STM32_I2C_I2C1_USE_POLLING_WAIT FALSE +/* I2C2 */ +#define STM32_I2C_I2C2_USE_GPT_TIM GPTD2 +#define STM32_I2C_I2C2_USE_POLLING_WAIT FALSE + +/* + * EXTI system settings. + */ +#define STM32_EXTI0_IRQ_PRIORITY 5 +#define STM32_EXTI1_IRQ_PRIORITY 5 +#define STM32_EXTI2_IRQ_PRIORITY 5 +#define STM32_EXTI3_IRQ_PRIORITY 5 +#define STM32_EXTI4_IRQ_PRIORITY 5 +#define STM32_EXTI9_5_IRQ_PRIORITY 5 +#define STM32_EXTI15_10_IRQ_PRIORITY 5 + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + + + + + + -- cgit v1.2.3 From 6cc29ee5c81b3c6f745ae80ab242514b073d3d3f Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 31 Aug 2011 15:30:25 +0000 Subject: RTC. Doxy file added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3273 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/dox/rtc.dox | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 os/hal/dox/rtc.dox diff --git a/os/hal/dox/rtc.dox b/os/hal/dox/rtc.dox new file mode 100644 index 000000000..3663374de --- /dev/null +++ b/os/hal/dox/rtc.dox @@ -0,0 +1,32 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup RTC RTC Driver + * @brief Real Time Clock Abstraction Layer + * @details This module defines an abstract interface for Real Time Clock cell. + * If you do not need callback functionality than disable + * @p RTC_SUPPORTS_CALLBACKS option in @p halconf.h. + * + * @pre In order to use the RTC driver the @p HAL_USE_RTC option + * must be enabled in @p halconf.h. + * + * @ingroup IO + */ -- cgit v1.2.3 From 3da3cc27891650180b1e725d1efb6f07005e9d3e Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 31 Aug 2011 15:31:32 +0000 Subject: RTC. Copyrights added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3274 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/rtc.h | 33 +++++++++++++++++++++++++++++---- os/hal/platforms/STM32/rtc_lld.c | 28 ++++++++++++++++++++++++---- os/hal/platforms/STM32/rtc_lld.h | 30 ++++++++++++++++++++++++++---- os/hal/src/rtc.c | 33 ++++++++++++++++++++++++--------- 4 files changed, 103 insertions(+), 21 deletions(-) diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h index 474862910..aa1a61f49 100644 --- a/os/hal/include/rtc.h +++ b/os/hal/include/rtc.h @@ -1,3 +1,23 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + /** * @file rtc.h * @brief RTC Driver macros and structures. @@ -58,10 +78,15 @@ typedef void (*rtccb_t)(RTCDriver *rtcp); extern "C" { #endif void rtcInit(void); -#if RTC_SUPPORTS_CALLBACKS - void rtcStart(RTCDriver *rtcp, const RTCConfig *rtccfgp); - void rtcStop(void); -#endif /* RTC_SUPPORTS_CALLBACKS */ + + #if RTC_SUPPORTS_CALLBACKS + void rtcStart(RTCDriver *rtcp, const RTCConfig *rtccfgp); + void rtcStop(void); + #else /* RTC_SUPPORTS_CALLBACKS */ + #define rtcStart(rtcp, rtccfgp){;} + #define rtcStop(){;} + #endif /* RTC_SUPPORTS_CALLBACKS */ + void rtcSetTime(uint32_t tv_sec); uint32_t rtcGetSec(void); uint16_t rtcGetMsec(void); diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 59699028d..ed458190d 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -1,3 +1,23 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + /** * @file STM32/rtc_lld.c * @brief STM32 RTC subsystem low level driver header. @@ -139,6 +159,7 @@ void rtc_lld_init(void){ /** * @brief Configure and start interrupt servicing routines. + * This function do nothing if callbacks disabled. * * @param[in] rtcp pointer to a @p RTCDriver object * @param[in] rtccfgp pointer to a @p RTCDriver config object @@ -174,7 +195,6 @@ void rtc_lld_stop(void){ #endif /* RTC_SUPPORTS_CALLBACKS */ - /** * @brief Set current time. * @@ -200,14 +220,14 @@ void rtc_lld_set_time(uint32_t tv_sec){ /** * @brief Return current time in UNIX notation. */ -uint32_t rtc_lld_get_sec(void){ +inline uint32_t rtc_lld_get_sec(void){ return ((RTC->CNTH << 16) + RTC->CNTL); } /** * @brief Return fractional part of current time (milliseconds). */ -uint16_t rtc_lld_get_msec(void){ +inline uint16_t rtc_lld_get_msec(void){ uint32_t time_frac = 0; time_frac = (((uint32_t)RTC->DIVH) << 16) + (RTC->DIVL); return(((STM32_LSECLK - time_frac) * 1000) / STM32_LSECLK); @@ -234,7 +254,7 @@ void rtc_lld_set_alarm(uint32_t tv_alarm){ * @brief Get current alarm date in UNIX notation. * @note Default value after reset is 0xFFFFFFFF */ -uint32_t rtc_lld_get_alarm(void){ +inline uint32_t rtc_lld_get_alarm(void){ return ((RTC->ALRH << 16) + RTC->ALRL); } diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h index f26315784..fe51df254 100644 --- a/os/hal/platforms/STM32/rtc_lld.h +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -1,3 +1,22 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ /** * @file STM32/rtc_lld.h @@ -85,10 +104,13 @@ extern RTCDriver RTCD; extern "C" { #endif void rtc_lld_init(void); -#if RTC_SUPPORTS_CALLBACKS - void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp); - void rtc_lld_stop(void); -#endif /* RTC_SUPPORTS_CALLBACKS */ + #if RTC_SUPPORTS_CALLBACKS + void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp); + void rtc_lld_stop(void); + #else /* RTC_SUPPORTS_CALLBACKS */ + #define rtc_lld_start(rtcp, rtccfgp){;} + #define rtc_lld_stop(){;} + #endif /* RTC_SUPPORTS_CALLBACKS */ void rtc_lld_set_time(uint32_t tv_sec); uint32_t rtc_lld_get_sec(void); uint16_t rtc_lld_get_msec(void); diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index c6edca4a2..0db21d4d5 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -1,3 +1,23 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + /** * @file rtc.c * @brief Real Time Clock Abstraction Layer code. @@ -40,12 +60,14 @@ void rtcInit(void){ rtc_lld_init(); } -#if RTC_SUPPORTS_CALLBACKS /** - * @brief Configure and start interrupt servicing routines. + * @brief Configure and start interrupt servicing routines. + * This function do nothing if callbacks disabled. + * * @param[in] rtcp - pointer to RTC driver structure. * @param[in] rtccfgp - pointer to RTC config structure. */ +#if RTC_SUPPORTS_CALLBACKS void rtcStart(RTCDriver *rtcp, const RTCConfig *rtccfgp){ chDbgCheck(((rtcp != NULL) && (rtccfgp != NULL)), "rtcStart"); rtc_lld_start(rtcp, rtccfgp); @@ -95,15 +117,8 @@ uint32_t rtcGetAlarm(void){ return rtc_lld_get_alarm(); } - - - - - #endif /* HAL_USE_RTC */ - - /** @} */ -- cgit v1.2.3 From 5e62285d1745cd498f89b1a42ae4b28b3ece59a2 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 31 Aug 2011 16:32:34 +0000 Subject: RTC. Final polishing. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3275 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/dox/rtc.dox | 2 ++ os/hal/include/rtc.h | 10 ------- os/hal/platforms/STM32/rtc_lld.c | 57 +++++++++++++++++++--------------------- os/hal/platforms/STM32/rtc_lld.h | 8 ++++++ os/hal/src/rtc.c | 6 ++--- testhal/STM32F1xx/RTC/halconf.h | 7 +++++ 6 files changed, 47 insertions(+), 43 deletions(-) diff --git a/os/hal/dox/rtc.dox b/os/hal/dox/rtc.dox index 3663374de..3572aca18 100644 --- a/os/hal/dox/rtc.dox +++ b/os/hal/dox/rtc.dox @@ -24,6 +24,8 @@ * @details This module defines an abstract interface for Real Time Clock cell. * If you do not need callback functionality than disable * @p RTC_SUPPORTS_CALLBACKS option in @p halconf.h. + * In @p halconf.h you also can select clock source for RTC in + * @p RTC_CLOCK_SOURCE option. * * @pre In order to use the RTC driver the @p HAL_USE_RTC option * must be enabled in @p halconf.h. diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h index aa1a61f49..ad66fcd8b 100644 --- a/os/hal/include/rtc.h +++ b/os/hal/include/rtc.h @@ -37,16 +37,6 @@ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ -/* TODO: move this to hal_lld_f103.h & mcuconf.h */ -#define STM32_LSECLK 32768 /**< Low speed external clock. */ - - -/* RCC_CFGR register bits definitions.*/ -#define STM32_RTC_NONE (0 << 8) /**< */ -#define STM32_RTC_LSE (1 << 8) /**< LSE oscillator clock used as RTC clock */ -#define STM32_RTC_LSI (2 << 8) /**< LSI oscillator clock used as RTC clock */ -#define STM32_RTC_HSE (3 << 8) /**< HSE oscillator clock divided by 128 used as RTC clock */ - /*===========================================================================*/ /* Driver pre-compile time settings. */ diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index ed458190d..ce483d3f9 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -30,31 +30,6 @@ #include "hal.h" -// TODO: defines look in 4492 stm32f10x.h - - -/** The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected -by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). -This selection -CANNOT -be modified without resetting the Backup domain. - -The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. -Consequently: -* If LSE is selected as RTC clock: -– The RTC continues to work even if the VDD supply is switched off, provided the -VBAT supply is maintained. -* If LSI is selected as Auto-Wakeup unit (AWU) clock: -– The AWU state is not guaranteed if the VDD supply is powered off. Refer to -Section 6.2.5: LSI clock on page 87 for more details on LSI calibration. -* If the HSE clock divided by 128 is used as the RTC clock: -– The RTC state is not guaranteed if the VDD supply is powered off or if the internal -voltage regulator is powered off (removing power from the 1.8 V domain). -– The DPB bit (Disable backup domain write protection) in the Power controller -register must be set to 1 (refer to Section 4.4.1: Power control register -(PWR_CR)). -*/ - #if HAL_USE_RTC || defined(__DOXYGEN__) /*===========================================================================*/ @@ -137,13 +112,37 @@ void rtc_lld_init(void){ PWR->CR |= PWR_CR_DBP; /* enable access */ if (!(RCC->BDCR & (RCC_BDCR_RTCEN | RCC_BDCR_LSEON))){ /* BKP domain was reseted */ - RCC->BDCR |= STM32_RTC_LSE; /* select clocking from LSE */ + RCC->BDCR |= RTC_CLOCK_SOURCE; /* select clocking from LSE */ RCC->BDCR |= RCC_BDCR_LSEON; /* switch LSE on */ while(!(RCC->BDCR & RCC_BDCR_LSEON)) /* wait for stabilization */ ; RCC->BDCR |= RCC_BDCR_RTCEN; /* run clock */ } + #if defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSE) + uint32_t preload = STM32_LSECLK - 1UL; + #elif defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSI) + uint32_t preload = STM32_LSICLK - 1UL; + #elif defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_HSE) + uint32_t preload = (STM32_HSICLK / 128UL) - 1UL; + #else + #error "RTC clock source not selected" + #endif /* RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE */ + + /* Write preload register only if value changed */ + if (preload != (((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLH){ + while(!(RTC->CRL & RTC_CRL_RTOFF)) + ; + + RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ + RTC->PRLH = (uint16_t)((preload >> 16) & 0b1111); /* write preloader */ + RTC->PRLL = (uint16_t)(preload & 0xFFFF); + RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ + ; + } + /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling * clocking on APB1, because these values only update when APB1 functioning.*/ RTC->CRL &= ~(RTC_CRL_RSF); @@ -181,7 +180,8 @@ void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp){ isr_flags |= RTC_CRH_SECIE; } - RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); /* clear all even flags*/ + /* clear all event flags just to be safe */ + RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); RTC->CRH |= isr_flags; } @@ -201,14 +201,11 @@ void rtc_lld_stop(void){ * @param[in] tv_sec time value in UNIX notation. */ void rtc_lld_set_time(uint32_t tv_sec){ - uint32_t preload = STM32_LSECLK - 1UL; while(!(RTC->CRL & RTC_CRL_RTOFF)) ; RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ - RTC->PRLH = (uint16_t)((preload >> 16) & 0b1111); /* write preloader */ - RTC->PRLL = (uint16_t)(preload & 0xFFFF); RTC->CNTH = (uint16_t)((tv_sec >> 16) & 0xFFFF); /* write time */ RTC->CNTL = (uint16_t)(tv_sec & 0xFFFF); RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h index fe51df254..a0490b29a 100644 --- a/os/hal/platforms/STM32/rtc_lld.h +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -47,6 +47,14 @@ #define RTC_SUPPORTS_CALLBACKS TRUE #endif +/** + * @brief Clock source selecting. LSE by default. + */ +#if !defined(RTC_CLOCK_SOURCE) || defined(__DOXYGEN__) +#define RTC_CLOCK_SOURCE RCC_BDCR_RTCSEL_LSE +#endif + + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index 0db21d4d5..f1aa03a34 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -92,14 +92,14 @@ void rtcSetTime(uint32_t tv_sec){ /** * @brief Return current time in UNIX notation. */ -uint32_t rtcGetSec(void){ +inline uint32_t rtcGetSec(void){ return rtc_lld_get_sec(); } /** * @brief Return fractional part of current time (milliseconds). */ -uint16_t rtcGetMsec(void){ +inline uint16_t rtcGetMsec(void){ return rtc_lld_get_msec(); } @@ -113,7 +113,7 @@ void rtcSetAlarm(uint32_t tv_alarm){ /** * @brief Get current alarm date in UNIX notation. */ -uint32_t rtcGetAlarm(void){ +inline uint32_t rtcGetAlarm(void){ return rtc_lld_get_alarm(); } diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h index 219bfd99e..553decda8 100644 --- a/testhal/STM32F1xx/RTC/halconf.h +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -212,6 +212,13 @@ #define RTC_SUPPORTS_CALLBACKS FALSE #endif +/** + * @brief Clock source selecting. LSE by default. + */ +#if !defined(RTC_CLOCK_SOURCE) || defined(__DOXYGEN__) +#define RTC_CLOCK_SOURCE RCC_BDCR_RTCSEL_LSE +#endif + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ -- cgit v1.2.3 From 7194b7a7fe49bab8d9422dbc2e78d1ae2d39dc9e Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 31 Aug 2011 17:49:18 +0000 Subject: RTC. Small code improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3276 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index ce483d3f9..3f8468bae 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -245,6 +245,11 @@ void rtc_lld_set_alarm(uint32_t tv_alarm){ while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ ; + +#if !(RTC_SUPPORTS_CALLBACKS) + RTC->CRL &= ~RTC_CRL_ALRF; + RTC->CRH |= RTC_CRH_ALRIE; +#endif /* !(RTC_SUPPORTS_CALLBACKS) */ } /** -- cgit v1.2.3 From 88f24294e2d23667667cf9c37bd6925550b1c714 Mon Sep 17 00:00:00 2001 From: barthess Date: Thu, 1 Sep 2011 17:31:10 +0000 Subject: RTC. Added deep sleep test git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3277 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/RTC/main.c | 42 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/testhal/STM32F1xx/RTC/main.c b/testhal/STM32F1xx/RTC/main.c index b8c243810..497b7f0cf 100644 --- a/testhal/STM32F1xx/RTC/main.c +++ b/testhal/STM32F1xx/RTC/main.c @@ -21,7 +21,46 @@ #include "ch.h" #include "hal.h" +#define TEST_DEEPSLEEP_ENABLE +#ifdef TEST_DEEPSLEEP_ENABLE + +static WORKING_AREA(blinkWA, 128); +static msg_t blink_thd(void *arg){ + (void)arg; + while (TRUE) { + chThdSleepMilliseconds(500); + palTogglePad(IOPORT3, GPIOC_LED); + } + return 0; +} + + + + +int main(void) { + halInit(); + chSysInit(); + + chThdCreateStatic(blinkWA, sizeof(blinkWA), NORMALPRIO, blink_thd, NULL); + /* set alarm in near future */ + rtcSetAlarm(rtcGetSec() + 60); + + while (TRUE){ + chThdSleepSeconds(10); + chSysLock(); + + /* going to anabiosis*/ + PWR->CR |= (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF); + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + } + return 0; +} + + + +#else /* TEST_DEEPSLEEP_ENABLE */ static void my_secondcb(RTCDriver *rtcp){ (void)rtcp; @@ -46,8 +85,6 @@ static const RTCConfig rtccfg={ my_alarmcb, }; - - int main(void) { halInit(); chSysInit(); @@ -60,3 +97,4 @@ int main(void) { } return 0; } +#endif /* TEST_DEEPSLEEP_ENABLE */ -- cgit v1.2.3 From ca3cc2d5554a99aad1c499fabb9ce3d72fd7aacb Mon Sep 17 00:00:00 2001 From: barthess Date: Thu, 1 Sep 2011 17:44:44 +0000 Subject: RTC. Readability improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3278 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/rtc.h | 4 ++-- os/hal/platforms/STM32/rtc_lld.c | 2 -- os/hal/platforms/STM32/rtc_lld.h | 9 ++------- 3 files changed, 4 insertions(+), 11 deletions(-) diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h index ad66fcd8b..0c545c3a6 100644 --- a/os/hal/include/rtc.h +++ b/os/hal/include/rtc.h @@ -73,8 +73,8 @@ extern "C" { void rtcStart(RTCDriver *rtcp, const RTCConfig *rtccfgp); void rtcStop(void); #else /* RTC_SUPPORTS_CALLBACKS */ - #define rtcStart(rtcp, rtccfgp){;} - #define rtcStop(){;} + #define rtcStart(rtcp, rtccfgp) + #define rtcStop() #endif /* RTC_SUPPORTS_CALLBACKS */ void rtcSetTime(uint32_t tv_sec); diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 3f8468bae..ba89a3c9e 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -163,7 +163,6 @@ void rtc_lld_init(void){ * @param[in] rtcp pointer to a @p RTCDriver object * @param[in] rtccfgp pointer to a @p RTCDriver config object */ -#if RTC_SUPPORTS_CALLBACKS void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp){ uint16_t isr_flags = 0; @@ -192,7 +191,6 @@ void rtc_lld_stop(void){ NVICDisableVector(RTC_IRQn); RTC->CRH = 0; } -#endif /* RTC_SUPPORTS_CALLBACKS */ /** diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h index a0490b29a..3b4f69665 100644 --- a/os/hal/platforms/STM32/rtc_lld.h +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -112,13 +112,8 @@ extern RTCDriver RTCD; extern "C" { #endif void rtc_lld_init(void); - #if RTC_SUPPORTS_CALLBACKS - void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp); - void rtc_lld_stop(void); - #else /* RTC_SUPPORTS_CALLBACKS */ - #define rtc_lld_start(rtcp, rtccfgp){;} - #define rtc_lld_stop(){;} - #endif /* RTC_SUPPORTS_CALLBACKS */ + void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp); + void rtc_lld_stop(void); void rtc_lld_set_time(uint32_t tv_sec); uint32_t rtc_lld_get_sec(void); uint16_t rtc_lld_get_msec(void); -- cgit v1.2.3 From ac429a2a76727c72d6a7b8273c9643560fcd6222 Mon Sep 17 00:00:00 2001 From: barthess Date: Thu, 1 Sep 2011 18:09:40 +0000 Subject: RTC. Added state checks. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3279 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.c | 6 +++--- os/hal/src/rtc.c | 6 ++++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index ba89a3c9e..1ddbc0903 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -241,13 +241,13 @@ void rtc_lld_set_alarm(uint32_t tv_alarm){ RTC->ALRL = (uint16_t)(tv_alarm & 0xFFFF); RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ - while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ - ; - #if !(RTC_SUPPORTS_CALLBACKS) RTC->CRL &= ~RTC_CRL_ALRF; RTC->CRH |= RTC_CRH_ALRIE; #endif /* !(RTC_SUPPORTS_CALLBACKS) */ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ + ; } /** diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index f1aa03a34..1341bb2dd 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -68,7 +68,8 @@ void rtcInit(void){ * @param[in] rtccfgp - pointer to RTC config structure. */ #if RTC_SUPPORTS_CALLBACKS -void rtcStart(RTCDriver *rtcp, const RTCConfig *rtccfgp){ +void rtcStartI(RTCDriver *rtcp, const RTCConfig *rtccfgp){ + chDbgCheckClassI(); chDbgCheck(((rtcp != NULL) && (rtccfgp != NULL)), "rtcStart"); rtc_lld_start(rtcp, rtccfgp); } @@ -76,7 +77,8 @@ void rtcStart(RTCDriver *rtcp, const RTCConfig *rtccfgp){ /** * @brief Stop interrupt servicing routines. */ -void rtcStop(void){ +void rtcStopI(void){ + chDbgCheckClassI(); rtc_lld_stop(); } #endif /* RTC_SUPPORTS_CALLBACKS */ -- cgit v1.2.3 From 919b3e56419cfaf533030e45c536a7640a1e53e5 Mon Sep 17 00:00:00 2001 From: barthess Date: Fri, 2 Sep 2011 13:27:37 +0000 Subject: RTC. Doxy comments improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3282 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 1ddbc0903..a6032e0a4 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -52,6 +52,8 @@ RTCDriver RTCD; * @brief Shared IRQ handler. * * @param[in] rtcp pointer to a @p RTCDriver object + * + * @notapi */ #if RTC_SUPPORTS_CALLBACKS @@ -106,6 +108,8 @@ CH_IRQ_HANDLER(RTC_IRQHandler) { /** * @brief Enable access to registers and initialize RTC if BKP domain * was previously reseted. + * + * @notapi */ void rtc_lld_init(void){ RCC->APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); /* enable clocking */ @@ -162,6 +166,8 @@ void rtc_lld_init(void){ * * @param[in] rtcp pointer to a @p RTCDriver object * @param[in] rtccfgp pointer to a @p RTCDriver config object + * + * @notapi */ void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp){ uint16_t isr_flags = 0; @@ -186,6 +192,8 @@ void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp){ /** * @brief Disable interrupt servicing routines. + * + * @notapi */ void rtc_lld_stop(void){ NVICDisableVector(RTC_IRQn); @@ -197,6 +205,8 @@ void rtc_lld_stop(void){ * @brief Set current time. * * @param[in] tv_sec time value in UNIX notation. + * + * @notapi */ void rtc_lld_set_time(uint32_t tv_sec){ @@ -214,6 +224,8 @@ void rtc_lld_set_time(uint32_t tv_sec){ /** * @brief Return current time in UNIX notation. + * + * @notapi */ inline uint32_t rtc_lld_get_sec(void){ return ((RTC->CNTH << 16) + RTC->CNTL); @@ -221,6 +233,8 @@ inline uint32_t rtc_lld_get_sec(void){ /** * @brief Return fractional part of current time (milliseconds). + * + * @notapi */ inline uint16_t rtc_lld_get_msec(void){ uint32_t time_frac = 0; @@ -230,6 +244,9 @@ inline uint16_t rtc_lld_get_msec(void){ /** * @brief Set alarm date in UNIX notation. + * @note Default value after BKP domain reset is 0xFFFFFFFF + * + * @notapi */ void rtc_lld_set_alarm(uint32_t tv_alarm){ @@ -252,7 +269,9 @@ void rtc_lld_set_alarm(uint32_t tv_alarm){ /** * @brief Get current alarm date in UNIX notation. - * @note Default value after reset is 0xFFFFFFFF + * @note Default value after BKP domain reset is 0xFFFFFFFF + * + * @notapi */ inline uint32_t rtc_lld_get_alarm(void){ return ((RTC->ALRH << 16) + RTC->ALRL); -- cgit v1.2.3 From 4e57582138fceee0792ef629715183f6647a5e93 Mon Sep 17 00:00:00 2001 From: barthess Date: Fri, 2 Sep 2011 13:32:19 +0000 Subject: I2C. Added forgotten copyrights. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3283 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 20 ++++++++++++++++++++ os/hal/platforms/STM32/i2c_lld.h | 20 ++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index d10cb4031..48bdb3e4e 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -1,3 +1,23 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + /** * @file STM32/i2c_lld.c * @brief STM32 I2C subsystem low level driver source. Slave mode not implemented. diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index 9bf56985c..548b5418e 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -1,3 +1,23 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + /** * @file STM32/i2c_lld.h * @brief STM32 I2C subsystem low level driver header. -- cgit v1.2.3 From c57e9ca9981e20e50630ace1656431ad84d73852 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Sep 2011 08:22:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3285 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/src/rtc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index 1341bb2dd..bd934b11b 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -29,8 +29,6 @@ #include "ch.h" #include "hal.h" -#include "rtc_lld.h" - #if HAL_USE_RTC || defined(__DOXYGEN__) /*===========================================================================*/ -- cgit v1.2.3 From 08dad7b1f54ff8eb6266e811533eecf53051249c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Sep 2011 08:23:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3286 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/templates/meta/driver.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/os/hal/templates/meta/driver.h b/os/hal/templates/meta/driver.h index b4b07170b..2af95b010 100644 --- a/os/hal/templates/meta/driver.h +++ b/os/hal/templates/meta/driver.h @@ -56,6 +56,11 @@ typedef enum { XXX_READY = 2, /**< Ready. */ } xxxstate_t; +/** + * @brief Type of a structure representing a XXX driver. + */ +typedef struct XXXDriver XXXDriver; + #include "xxx_lld.h" /*===========================================================================*/ -- cgit v1.2.3 From 792d85bcb5774e63100abef0125d5325312f916a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Sep 2011 12:35:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3287 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 3 +- os/hal/include/mac.h | 36 ++++++++++- os/hal/platforms/AT91SAM7/mac_lld.c | 74 +++++++++++++++-------- os/hal/platforms/AT91SAM7/mac_lld.h | 80 ++++++++++++++++++++----- os/hal/src/mac.c | 63 +++++++++++++++---- readme.txt | 8 +++ 6 files changed, 208 insertions(+), 56 deletions(-) diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index 8b2fd1854..a1c281341 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -222,6 +222,7 @@ msg_t lwip_thread(void *p) { EventListener el0, el1; struct ip_addr ip, gateway, netmask; static struct netif thisif; + static const MACConfig mac_config = {thisif.hwaddr}; /* Initializes the thing.*/ sys_init(); @@ -254,7 +255,7 @@ msg_t lwip_thread(void *p) { LWIP_GATEWAY(&gateway); LWIP_NETMASK(&netmask); } - macSetAddress(Ð1, thisif.hwaddr); + macStart(Ð1, &mac_config); netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input); netif_set_default(&thisif); diff --git a/os/hal/include/mac.h b/os/hal/include/mac.h index 37d6bbe9b..c716796f8 100644 --- a/os/hal/include/mac.h +++ b/os/hal/include/mac.h @@ -38,18 +38,48 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name MAC configuration options + * @{ + */ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ #if !CH_USE_SEMAPHORES || !CH_USE_EVENTS -#error "the MAC driver requires CH_USE_SEMAPHORES and CH_USE_EVENTS" +#error "the MAC driver requires CH_USE_SEMAPHORES" +#endif + +#if MAC_USE_EVENTS && !CH_USE_EVENTS +#error "the MAC driver requires CH_USE_EVENTS" #endif /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ +/** + * @brief Driver state machine possible states. + */ +typedef enum { + MAC_UNINIT = 0, /**< Not initialized. */ + MAC_STOP = 1, /**< Stopped. */ + MAC_ACTIVE = 2, /**< Active. */ +} macstate_t; + +/** + * @brief Type of a structure representing a MAC driver. + */ +typedef struct MACDriver MACDriver; + #include "mac_lld.h" /*===========================================================================*/ @@ -68,7 +98,7 @@ * * @api */ -#if CH_USE_EVENTS || defined(__DOXYGEN__) +#if MAC_USE_EVENTS || defined(__DOXYGEN__) #define macGetReceiveEventSource(macp) (&(macp)->rdevent) #endif @@ -113,6 +143,8 @@ extern "C" { #endif void macInit(void); void macObjectInit(MACDriver *macp); + void macStart(MACDriver *macp, const MACConfig *config); + void macStop(MACDriver *macp); void macSetAddress(MACDriver *macp, const uint8_t *p); msg_t macWaitTransmitDescriptor(MACDriver *macp, MACTransmitDescriptor *tdp, diff --git a/os/hal/platforms/AT91SAM7/mac_lld.c b/os/hal/platforms/AT91SAM7/mac_lld.c index 43055b94d..fc610fcc7 100644 --- a/os/hal/platforms/AT91SAM7/mac_lld.c +++ b/os/hal/platforms/AT91SAM7/mac_lld.c @@ -64,7 +64,6 @@ MACDriver ETH1; /*===========================================================================*/ #ifndef __DOXYGEN__ -static bool_t link_up; static uint8_t default_mac[] = {0xAA, 0x55, 0x13, 0x37, 0x01, 0x10}; @@ -102,7 +101,7 @@ static void serve_interrupt(void) { if (rsr & AT91C_EMAC_REC) { chSysLockFromIsr(); chSemResetI(Ð1.rdsem, 0); -#if CH_USE_EVENTS +#if MAC_USE_EVENTS chEvtBroadcastI(Ð1.rdevent); #endif chSysUnlockFromIsr(); @@ -135,6 +134,19 @@ static void cleanup(EMACDescriptor *from) { } } +/** + * @brief MAC address setup. + * + * @param[in] p pointer to a six bytes buffer containing the MAC + * address + */ +static void set_address(const uint8_t *p) { + + AT91C_BASE_EMAC->EMAC_SA1L = (AT91_REG)((p[3] << 24) | (p[2] << 16) | + (p[1] << 8) | p[0]); + AT91C_BASE_EMAC->EMAC_SA1H = (AT91_REG)((p[5] << 8) | p[4]); +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -163,11 +175,34 @@ CH_IRQ_HANDLER(irq_handler) { * @notapi */ void mac_lld_init(void) { - unsigned i; miiInit(); macObjectInit(Ð1); + /* + * Associated PHY initialization. + */ + miiReset(Ð1); + + /* + * EMAC pins setup. Note, PB18 is not included because it is + * used as #PD control and not as EF100. + */ + AT91C_BASE_PIOB->PIO_ASR = EMAC_PIN_MASK; + AT91C_BASE_PIOB->PIO_PDR = EMAC_PIN_MASK; + AT91C_BASE_PIOB->PIO_PPUDR = EMAC_PIN_MASK; +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + unsigned i; + /* * Buffers initialization. */ @@ -185,18 +220,9 @@ void mac_lld_init(void) { txptr = td; /* - * Associated PHY initialization. - */ - miiReset(Ð1); - - /* - * EMAC pins setup and clock enable. Note, PB18 is not included because it is - * used as #PD control and not as EF100. + * EMAC clock enable. */ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; - AT91C_BASE_PIOB->PIO_ASR = EMAC_PIN_MASK; - AT91C_BASE_PIOB->PIO_PDR = EMAC_PIN_MASK; - AT91C_BASE_PIOB->PIO_PPUDR = EMAC_PIN_MASK; /* * EMAC Initial setup. @@ -213,7 +239,10 @@ void mac_lld_init(void) { AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_CLRSTAT;/* Initial NCR settings.*/ - mac_lld_set_address(Ð1, default_mac); + if (macp->config->mac_address == NULL) + set_address(default_mac); + else + set_address(macp->config->mac_address); /* * PHY device identification. @@ -235,22 +264,15 @@ void mac_lld_init(void) { } /** - * @brief Low level MAC address setup. + * @brief Deactivates the MAC peripheral. * * @param[in] macp pointer to the @p MACDriver object - * @param[in] p pointer to a six bytes buffer containing the MAC - * address. If this parameter is set to @p NULL then - * a system default MAC is used. The MAC address must - * be aligned with the most significant byte first. * * @notapi */ -void mac_lld_set_address(MACDriver *macp, const uint8_t *p) { +void mac_lld_stop(MACDriver *macp) { (void)macp; - AT91C_BASE_EMAC->EMAC_SA1L = (AT91_REG)((p[3] << 24) | (p[2] << 16) | - (p[1] << 8) | p[0]); - AT91C_BASE_EMAC->EMAC_SA1H = (AT91_REG)((p[5] << 8) | p[4]); } /** @@ -272,7 +294,7 @@ msg_t max_lld_get_transmit_descriptor(MACDriver *macp, (void)macp; - if (!link_up) + if (!macp->link_up) return RDY_TIMEOUT; chSysLock(); @@ -505,7 +527,7 @@ bool_t mac_lld_poll_link_status(MACDriver *macp) { bmsr = miiGet(macp, MII_BMSR); if (!(bmsr & BMSR_LSTATUS)) { AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; - return link_up = FALSE; + return macp->link_up = FALSE; } ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); @@ -525,7 +547,7 @@ bool_t mac_lld_poll_link_status(MACDriver *macp) { } AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr; AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; - return link_up = TRUE; + return macp->link_up = TRUE; } #endif /* HAL_USE_MAC */ diff --git a/os/hal/platforms/AT91SAM7/mac_lld.h b/os/hal/platforms/AT91SAM7/mac_lld.h index 9f30e0426..97a8ba2ae 100644 --- a/os/hal/platforms/AT91SAM7/mac_lld.h +++ b/os/hal/platforms/AT91SAM7/mac_lld.h @@ -128,38 +128,85 @@ typedef struct { } EMACDescriptor; /** - * @brief Structure representing a MAC driver. + * @brief Driver configuration structure. */ typedef struct { - Semaphore tdsem; /**< Transmit semaphore. */ - Semaphore rdsem; /**< Receive semaphore. */ -#if CH_USE_EVENTS - EventSource rdevent; /**< Receive event source. */ + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; #endif /* End of the mandatory fields.*/ -} MACDriver; + /** + * @brief Link status flag. + */ + bool_t link_up; +}; /** * @brief Structure representing a transmit descriptor. */ typedef struct { - size_t offset; /**< Current write offset. */ - size_t size; /**< Available space size. */ + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; /* End of the mandatory fields.*/ - EMACDescriptor *physdesc; /**< Pointer to the physical - descriptor. */ + /** + * @brief Pointer to the physical descriptor. + */ + EMACDescriptor *physdesc; } MACTransmitDescriptor; /** * @brief Structure representing a receive descriptor. */ typedef struct { - size_t offset; /**< Current read offset. */ - size_t size; /**< Available data size. */ + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; /* End of the mandatory fields.*/ - EMACDescriptor *physdesc; /**< Pointer to the first - descriptor of the buffers - chain. */ + /** + * @brief Pointer to the first descriptor of the buffers chain. + */ + EMACDescriptor *physdesc; } MACReceiveDescriptor; /*===========================================================================*/ @@ -178,7 +225,8 @@ extern MACDriver ETH1; extern "C" { #endif void mac_lld_init(void); - void mac_lld_set_address(MACDriver *macp, const uint8_t *p); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); msg_t max_lld_get_transmit_descriptor(MACDriver *macp, MACTransmitDescriptor *tdp); size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, diff --git a/os/hal/src/mac.c b/os/hal/src/mac.c index 0f1c47576..edd15d087 100644 --- a/os/hal/src/mac.c +++ b/os/hal/src/mac.c @@ -21,8 +21,6 @@ /** * @file mac.c * @brief MAC Driver code. - * @note This function is implicitly invoked by @p halInit(), there is - * no need to explicitly initialize the driver. * * @addtogroup MAC * @{ @@ -59,6 +57,8 @@ /** * @brief MAC Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. * * @init */ @@ -76,28 +76,53 @@ void macInit(void) { */ void macObjectInit(MACDriver *macp) { + macp->state = MAC_STOP; + macp->config = NULL; chSemInit(&macp->tdsem, 0); chSemInit(&macp->rdsem, 0); -#if CH_USE_EVENTS +#if MAC_USE_EVENTS chEvtInit(&macp->rdevent); #endif } /** - * @brief MAC address setup. - * @pre This function must be invoked with the driver in the stopped - * state. If invoked on an active interface then it is ignored. + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] config pointer to the @p MACConfig object + * + * @api + */ +void macStart(MACDriver *macp, const MACConfig *config) { + + chDbgCheck((macp != NULL) && (config != NULL), "macStart"); + + chSysLock(); + chDbgAssert(macp->state == MAC_STOP, + "macStart(), #1", "invalid state"); + macp->config = config; + mac_lld_start(macp); + macp->state = MAC_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Deactivates the MAC peripheral. * * @param[in] macp pointer to the @p MACDriver object - * @param[in] p pointer to a six bytes buffer containing the MAC - * address. If this parameter is set to @p NULL then MAC - * a system default is used. * * @api */ -void macSetAddress(MACDriver *macp, const uint8_t *p) { +void macStop(MACDriver *macp) { + + chDbgCheck(macp != NULL, "macStop"); - mac_lld_set_address(macp, p); + chSysLock(); + chDbgAssert((macp->state == MAC_STOP) || (macp->state == MAC_ACTIVE), + "macStop(), #1", "invalid state"); + mac_lld_stop(macp); + macp->state = MAC_STOP; + chSysUnlock(); } /** @@ -124,6 +149,10 @@ msg_t macWaitTransmitDescriptor(MACDriver *macp, systime_t time) { msg_t msg; + chDbgCheck((macp != NULL) && (tdp != NULL), "macWaitTransmitDescriptor"); + chDbgAssert(macp->state == MAC_ACTIVE, "macWaitTransmitDescriptor(), #1", + "not active"); + while (((msg = max_lld_get_transmit_descriptor(macp, tdp)) != RDY_OK) && (time > 0)) { chSysLock(); @@ -149,6 +178,8 @@ msg_t macWaitTransmitDescriptor(MACDriver *macp, */ void macReleaseTransmitDescriptor(MACTransmitDescriptor *tdp) { + chDbgCheck((tdp != NULL), "macReleaseTransmitDescriptor"); + mac_lld_release_transmit_descriptor(tdp); } @@ -176,6 +207,10 @@ msg_t macWaitReceiveDescriptor(MACDriver *macp, systime_t time) { msg_t msg; + chDbgCheck((macp != NULL) && (rdp != NULL), "macWaitReceiveDescriptor"); + chDbgAssert(macp->state == MAC_ACTIVE, "macWaitReceiveDescriptor(), #1", + "not active"); + while (((msg = max_lld_get_receive_descriptor(macp, rdp)) != RDY_OK) && (time > 0)) { chSysLock(); @@ -202,6 +237,8 @@ msg_t macWaitReceiveDescriptor(MACDriver *macp, */ void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) { + chDbgCheck((rdp != NULL), "macReleaseReceiveDescriptor"); + mac_lld_release_receive_descriptor(rdp); } @@ -217,6 +254,10 @@ void macReleaseReceiveDescriptor(MACReceiveDescriptor *rdp) { */ bool_t macPollLinkStatus(MACDriver *macp) { + chDbgCheck((macp != NULL), "macPollLinkStatus"); + chDbgAssert(macp->state == MAC_ACTIVE, "macPollLinkStatus(), #1", + "not active"); + return mac_lld_poll_link_status(macp); } diff --git a/readme.txt b/readme.txt index e0c1066fa..f58237756 100644 --- a/readme.txt +++ b/readme.txt @@ -89,6 +89,14 @@ (backported to 2.2.4). - FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420) (backported to 2.2.4). +- NEW: New I2C driver model and STM32 implementation. + (evaluate the option to change the API to a synchronous model) +- NEW: New RTC driver model and STM32 implementation. + (API and functionality review) +- NEW: Improved MAC driver model, it now follows the same template of other + drivers. + (uIP demo to be adapted) + (implement macStop() in AT91SAM7X implementation) - NEW: New DMA helper driver for STM32, it simplifies the use of the DMA resources and hides most differences with the new enhanced DMA units found in the STM32F2xx sub-family. -- cgit v1.2.3 From d15f612b861af72fffb8ee2e4f3b95e991bfcf10 Mon Sep 17 00:00:00 2001 From: barthess Date: Sat, 3 Sep 2011 18:25:04 +0000 Subject: RTC. Tiny improvement in documentation. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3288 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/src/rtc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index bd934b11b..8f9025364 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -53,6 +53,9 @@ /** * @brief Enable access to registers and initialize RTC if BKP doamin * was previously reseted. + * + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. */ void rtcInit(void){ rtc_lld_init(); -- cgit v1.2.3 From 6798baae9674d251c07865662321e520c969669e Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 4 Sep 2011 18:49:14 +0000 Subject: Added board OLIMEX_STM32_103STK. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3289 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_STM32_103STK/board.c | 54 ++++++++++++ boards/OLIMEX_STM32_103STK/board.h | 162 ++++++++++++++++++++++++++++++++++++ boards/OLIMEX_STM32_103STK/board.mk | 5 ++ 3 files changed, 221 insertions(+) create mode 100644 boards/OLIMEX_STM32_103STK/board.c create mode 100644 boards/OLIMEX_STM32_103STK/board.h create mode 100644 boards/OLIMEX_STM32_103STK/board.mk diff --git a/boards/OLIMEX_STM32_103STK/board.c b/boards/OLIMEX_STM32_103STK/board.c new file mode 100644 index 000000000..b8b98c05f --- /dev/null +++ b/boards/OLIMEX_STM32_103STK/board.c @@ -0,0 +1,54 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/OLIMEX_STM32_103STK/board.h b/boards/OLIMEX_STM32_103STK/board.h new file mode 100644 index 000000000..a53695906 --- /dev/null +++ b/boards/OLIMEX_STM32_103STK/board.h @@ -0,0 +1,162 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the Olimex STM33-P103 proto board. + */ + +/* + * Board identifier. + */ +#define BOARD_OLIMEX_STM32_103STK +#define BOARD_NAME "Olimex STM32-103STK" + +/* + * Board frequencies. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define STM32F10X_MD + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON_WAKEUP 0 +#define GPIOC_BUTTON_TAMPER 13 +#define GPIOC_JOY 5 +#define GPIOC_JOY_CENTER_BUT 6 + +#define GPIOA_SPI1NSS 4 +#define GPIOB_SPI2NSS 12 + +#define GPIOC_MMCWP 2 +#define GPIOC_MMCCP 1 + +#define GPIOC_USB_P 4 +#define GPIOC_LCD_RES 7 +#define GPIOC_NRF_CE 8 +#define GPIOC_NRF_IRQ 9 +#define GPIOC_LCD_E 10 + +#define GPIOC_USB_DISC 11 +#define GPIOC_LED 12 + +#define GPIOB_ACCEL_IRQ 5 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * Everything input with pull-up except: + * PA0 - Normal input (BUTTON). + * PA2 - Alternate output (USART2 TX). + * PA3 - Normal input (USART2 RX). + */ +#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */ +#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup. + * Everything input with pull-up except: + * PB6,7 - Alternate open drain (I2C1). + * PB10,11 - Alternate open drain (I2C2). + * PB12 - Push Pull output (MMC SPI2 NSS). + * PB13 - Alternate output (MMC SPI2 SCK). + * PB14 - Normal input (MMC SPI2 MISO). + * PB15 - Alternate output (MMC SPI2 MOSI). + */ +#define VAL_GPIOBCRL 0xEE888888 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0xB4B3EE88 /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup. + * Everything input with pull-up except: + * PC4 - Normal input because there is an external resistor. + * PC5 - Analog input (joystick). + * PC6 - Normal input because there is an external resistor. + * PC7 - Normal input because there is an external resistor. + * PC10 - Push Pull output (CAN CNTRL). + * PC11 - Push Pull output (USB DISC). + * PC12 - Open Drain output (LED). + */ +#define VAL_GPIOCCRL 0x44048888 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x88863388 /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFFFF + +/* + * Port D setup. + * Everything input with pull-up except: + * PD0 - Normal input (XTAL). + * PD1 - Normal input (XTAL). + */ +#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */ +#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + * Everything input with pull-up except: + */ +#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ +#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/OLIMEX_STM32_103STK/board.mk b/boards/OLIMEX_STM32_103STK/board.mk new file mode 100644 index 000000000..383e1c490 --- /dev/null +++ b/boards/OLIMEX_STM32_103STK/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_103STK/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_103STK -- cgit v1.2.3 From c14c1959b1186bc79dd223f0a744a8220874bc5a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 5 Sep 2011 15:05:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3290 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/mac_lld.c | 260 +++++++++++++++++++++++++++++++++++++++ os/hal/platforms/STM32/mac_lld.h | 200 ++++++++++++++++++++++++++++++ os/hal/templates/mac_lld.c | 53 +++++--- os/hal/templates/mac_lld.h | 73 ++++++++--- 4 files changed, 549 insertions(+), 37 deletions(-) create mode 100644 os/hal/platforms/STM32/mac_lld.c create mode 100644 os/hal/platforms/STM32/mac_lld.h diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c new file mode 100644 index 000000000..37ca9e106 --- /dev/null +++ b/os/hal/platforms/STM32/mac_lld.c @@ -0,0 +1,260 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/mac_lld.c + * @brief STM32 low level MAC driver code. + * + * @addtogroup MAC + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "mii.h" +# +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define BUFFER_SLICE ((((MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Ethernet driver 1. + */ +MACDriver ETH1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +static stm32_eth_rx_descriptor_t *rxptr; +static stm32_eth_tx_descriptor_t *txptr; + +static stm32_eth_rx_descriptor_t rd[MAC_RECEIVE_BUFFERS]; +static stm32_eth_tx_descriptor_t td[MAC_TRANSMIT_BUFFERS]; + +static uint32_t rb[MAC_RECEIVE_BUFFERS * BUFFER_SLICE]; +static uint32_t tb[MAC_TRANSMIT_BUFFERS * BUFFER_SLICE]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) { + unsigned i; + + macObjectInit(Ð1); + + /* Descriptor tables are initialized in linked mode, note that the first + word is not initialized here but in mac_lld_start().*/ + for (i = 0; i < MAC_RECEIVE_BUFFERS; i++) { + rd[i].rdes1 = RDES1_RCH | MAC_BUFFERS_SIZE; + rd[i].rdes2 = (uint32_t)&rb[i * BUFFER_SLICE]; + rd[i].rdes3 = (uint32_t)&rb[((i + 1) % MAC_RECEIVE_BUFFERS) * + BUFFER_SLICE]; + } + for (i = 0; i < MAC_TRANSMIT_BUFFERS; i++) { + td[i].tdes1 = 0; + td[i].tdes2 = (uint32_t)&tb[i * BUFFER_SLICE]; + td[i].tdes3 = (uint32_t)&tb[((i + 1) % MAC_TRANSMIT_BUFFERS) * + BUFFER_SLICE]; + } +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + unsigned i; + + /* Resets the state of all descriptors.*/ + for (i = 0; i < MAC_RECEIVE_BUFFERS; i++) + rd[i].rdes0 = RDES0_OWN; + rxptr = (stm32_eth_rx_descriptor_t *)rd; + for (i = 0; i < MAC_TRANSMIT_BUFFERS; i++) + td[i].tdes0 = TDES0_TCH; + txptr = (stm32_eth_tx_descriptor_t *)td; + + /* Soft reset of the MAC core and wait until the reset is complete.*/ + ETH->DMABMR |= ETH_DMABMR_SR; + while (ETH->DMABMR & ETH_DMABMR_SR) + ; + + /* Descriptor chains pointers.*/ + ETH->DMARDLAR = (uint32_t)rd; + ETH->DMATDLAR = (uint32_t)rd; + + /* Clear DMA status.*/ +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { + +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t max_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) { + + return RDY_OK; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer cointaining the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) { + + return 0; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { + +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t max_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) { + + return RDY_TIMEOUT; +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) { + + return 0; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { + +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool_t mac_lld_poll_link_status(MACDriver *macp) { + +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h new file mode 100644 index 000000000..8647bd296 --- /dev/null +++ b/os/hal/platforms/STM32/mac_lld.h @@ -0,0 +1,200 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/mac_lld.h + * @brief STM32 low level MAC driver header. + * + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_LLD_H_ +#define _MAC_LLD_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Number of available transmit buffers. + */ +#if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) +#define MAC_TRANSMIT_BUFFERS 2 +#endif + +/** + * @brief Number of available receive buffers. + */ +#if !defined(MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) +#define MAC_RECEIVE_BUFFERS 2 +#endif + +/** + * @brief Maximum supported frame size. + */ +#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define MAC_BUFFERS_SIZE 1518 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an STM32 Ethernet receive descriptor. + */ +typedef struct { + volatile uint32_t rdes0; + volatile uint32_t rdes1; + volatile uint32_t rdes2; + volatile uint32_t rdes3; +} stm32_eth_rx_descriptor_t; + +/** + * @brief Type of an STM32 Ethernet transmit descriptor. + */ +typedef struct { + volatile uint32_t tdes0; + volatile uint32_t tdes1; + volatile uint32_t tdes2; + volatile uint32_t tdes3; +} stm32_eth_tx_descriptor_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; +#endif + /* End of the mandatory fields.*/ +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct { + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct { + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern MACDriver ETH1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t max_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t max_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool_t mac_lld_poll_link_status(MACDriver *macp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/templates/mac_lld.c b/os/hal/templates/mac_lld.c index 62b8765d0..ecd7f82bd 100644 --- a/os/hal/templates/mac_lld.c +++ b/os/hal/templates/mac_lld.c @@ -39,6 +39,11 @@ /* Driver exported variables. */ /*===========================================================================*/ +/** + * @brief Ethernet driver 1. + */ +MACDriver ETH1; + /*===========================================================================*/ /* Driver local variables. */ /*===========================================================================*/ @@ -65,16 +70,24 @@ void mac_lld_init(void) { } /** - * @brief Low level MAC address setup. + * @brief Configures and activates the MAC peripheral. * * @param[in] macp pointer to the @p MACDriver object - * @param[in] p pointer to a six bytes buffer containing the MAC - * address. If this parameter is set to @p NULL then - * a system default MAC is used. * * @notapi */ -void mac_lld_set_address(MACDriver *macp, const uint8_t *p) { +void mac_lld_start(MACDriver *macp) { + +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { } @@ -86,7 +99,7 @@ void mac_lld_set_address(MACDriver *macp, const uint8_t *p) { * @param[in] macp pointer to the @p MACDriver object * @param[out] tdp pointer to a @p MACTransmitDescriptor structure * @return The operation status. - * @retval RDY_OK a descriptor was obtained. + * @retval RDY_OK the descriptor has been obtained. * @retval RDY_TIMEOUT descriptor not available. * * @notapi @@ -101,7 +114,7 @@ msg_t max_lld_get_transmit_descriptor(MACDriver *macp, * @brief Writes to a transmit descriptor's stream. * * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be + * @param[in] buf pointer to the buffer cointaining the data to be * written * @param[in] size number of bytes to be written * @return The number of bytes written into the descriptor's @@ -122,7 +135,7 @@ size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, * @brief Releases a transmit descriptor and starts the transmission of the * enqueued data as a single frame. * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure * * @notapi */ @@ -133,10 +146,10 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { /** * @brief Returns a receive descriptor. * - * @param[in] macp pointer to a @p MACDriver object + * @param[in] macp pointer to the @p MACDriver object * @param[out] rdp pointer to a @p MACReceiveDescriptor structure * @return The operation status. - * @retval RDY_OK a descriptor was obtained. + * @retval RDY_OK the descriptor has been obtained. * @retval RDY_TIMEOUT descriptor not available. * * @notapi @@ -144,18 +157,19 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { msg_t max_lld_get_receive_descriptor(MACDriver *macp, MACReceiveDescriptor *rdp) { - return RDY_OK; + return RDY_TIMEOUT; } /** * @brief Reads from a receive descriptor's stream. * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to a buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's stream, - * this value can be less than the amount specified in - * the parameter @p size if there are no more bytes to read. + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. * * @notapi */ @@ -171,7 +185,7 @@ size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, * @details The descriptor and its buffer are made available for more incoming * frames. * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure * * @notapi */ @@ -182,7 +196,7 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { /** * @brief Updates and returns the link status. * - * @param[in] macp pointer to a @p MACDriver object + * @param[in] macp pointer to the @p MACDriver object * @return The link status. * @retval TRUE if the link is active. * @retval FALSE if the link is down. @@ -191,7 +205,6 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { */ bool_t mac_lld_poll_link_status(MACDriver *macp) { - return FALSE; } #endif /* HAL_USE_MAC */ diff --git a/os/hal/templates/mac_lld.h b/os/hal/templates/mac_lld.h index e103128a9..765ac247e 100644 --- a/os/hal/templates/mac_lld.h +++ b/os/hal/templates/mac_lld.h @@ -48,38 +48,72 @@ /*===========================================================================*/ /** - * @brief Structure representing a MAC driver. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. + * @brief Driver configuration structure. */ typedef struct { - Semaphore tdsem; /**< Transmit semaphore. */ - Semaphore rdsem; /**< Receive semaphore. */ -#if CH_USE_EVENTS - EventSource rdevent; /**< Receive event source. */ + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; #endif /* End of the mandatory fields.*/ -} MACDriver; +}; /** * @brief Structure representing a transmit descriptor. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. */ typedef struct { - size_t offset; /**< Current write offset. */ - size_t size; /**< Available space size. */ + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; /* End of the mandatory fields.*/ } MACTransmitDescriptor; /** * @brief Structure representing a receive descriptor. - * @note Implementations may extend this structure to contain more, - * architecture dependent, fields. */ typedef struct { - size_t offset; /**< Current read offset. */ - size_t size; /**< Available data size. */ + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; /* End of the mandatory fields.*/ } MACReceiveDescriptor; @@ -91,11 +125,16 @@ typedef struct { /* External declarations. */ /*===========================================================================*/ +#if !defined(__DOXYGEN__) +extern MACDriver ETH1; +#endif + #ifdef __cplusplus extern "C" { #endif void mac_lld_init(void); - void mac_lld_set_address(MACDriver *macp, const uint8_t *p); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); msg_t max_lld_get_transmit_descriptor(MACDriver *macp, MACTransmitDescriptor *tdp); size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, -- cgit v1.2.3 From cd04106a830e70037225f9c7e312984a97447a3f Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 6 Sep 2011 14:06:43 +0000 Subject: Added date/time of build in "info" screen. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3291 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/various/shell.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/os/various/shell.c b/os/various/shell.c index d47df283d..5f2fc760b 100644 --- a/os/various/shell.c +++ b/os/various/shell.c @@ -103,6 +103,11 @@ static void cmd_info(BaseChannel *chp, int argc, char *argv[]) { #ifdef BOARD_NAME chprintf(chp, "Board: %s\r\n", BOARD_NAME); #endif +#ifdef __DATE__ +#ifdef __TIME__ + chprintf(chp, "Build time: %s%s%s\r\n", __DATE__, " - ", __TIME__); +#endif +#endif } static void cmd_systime(BaseChannel *chp, int argc, char *argv[]) { -- cgit v1.2.3 From b8ad6dbae6914316f731c99324ccb5052018dfbf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 6 Sep 2011 14:59:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3292 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/mii.h | 1 + os/hal/platforms/STM32/mac_lld.c | 68 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/os/hal/include/mii.h b/os/hal/include/mii.h index 89ba69810..969f4a9d5 100644 --- a/os/hal/include/mii.h +++ b/os/hal/include/mii.h @@ -178,6 +178,7 @@ #define MII_DM9161_ID 0x0181b8a0 #define MII_AM79C875_ID 0x00225540 #define MII_KS8721_ID 0x00221610 +#define MII_STE101P_ID 0x00061C50 #endif /* _MII_H_ */ diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c index 37ca9e106..01a28a8b4 100644 --- a/os/hal/platforms/STM32/mac_lld.c +++ b/os/hal/platforms/STM32/mac_lld.c @@ -29,7 +29,7 @@ #include "ch.h" #include "hal.h" #include "mii.h" -# + #if HAL_USE_MAC || defined(__DOXYGEN__) /*===========================================================================*/ @@ -38,6 +38,20 @@ #define BUFFER_SLICE ((((MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) +/* MII divider optimal value.*/ +#if (STM32_HCLK >= 60000000) +#define MACMIIDR_CR ETH_MACMIIAR_CR_Div42 +#elif (STM32_HCLK >= 35000000) +#define MACMIIDR_CR ETH_MACMIIAR_CR_Div26 +#elif (STM32_HCLK >= 20000000) +#define MACMIIDR_CR ETH_MACMIIAR_CR_Div16 +#else +#error "STM32_HCLK below minimum frequency for ETH operations (20MHz)" +#endif + +/* PHY address.*/ +#define MACMIIDR_PA (32 << 11) + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -64,6 +78,55 @@ static uint32_t tb[MAC_TRANSMIT_BUFFERS * BUFFER_SLICE]; /* Driver local functions. */ /*===========================================================================*/ +/** + * @brief Writes a PHY register. + * + * @param[in] reg register number + * @param[in] value new register value + */ +static void mii_write_phy(uint16_t reg, uint16_t value) { + uint32_t miiar; + + miiar = ETH->MACMIIAR | ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; + miiar = (miiar & ~ETH_MACMIIAR_MR) | (reg << 6); + ETH->MACMIIDR = value; + ETH->MACMIIAR = miiar; + while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) + ; +} + +/** + * @brief Reads a PHY register. + * + * @param[in] reg register number + */ +static uint16_t mii_read_phy(uint16_t reg) { + uint32_t miiar; + + miiar = ETH->MACMIIAR | ETH_MACMIIAR_MB; + miiar = (miiar & ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_MW)) | (reg << 6); + ETH->MACMIIAR = miiar; + while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) + ; + return (uint16_t)ETH->MACMIIDR; +} + +/** + * @brief MII/RMII interface initialization. + */ +static void mii_init(void) { + uint32_t i; + + for (i = 0; i < 31; i++) { + ETH->MACMIIDR = (i << 6) | MACMIIDR_CR; + if ((mii_read_phy(MII_PHYSID1) == (PHY_ID >> 16)) && + (mii_read_phy(MII_PHYSID2) == (PHY_ID & 0xFFF0))) + return; + } + /* Wrong or defective board.*/ + chSysHalt(); +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -121,6 +184,9 @@ void mac_lld_start(MACDriver *macp) { while (ETH->DMABMR & ETH_DMABMR_SR) ; + /* MII initialization.*/ + mii_init(); + /* Descriptor chains pointers.*/ ETH->DMARDLAR = (uint32_t)rd; ETH->DMATDLAR = (uint32_t)rd; -- cgit v1.2.3 From d0771593893ef9f8a9ae4ab689c569b88e3631a9 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Sep 2011 12:53:27 +0000 Subject: RTC. rtcStart() and rtcStop() functions replaced by rtcSetCallback() git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3293 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/rtc.h | 7 +--- os/hal/platforms/STM32/rtc_lld.c | 87 +++++++++++++++++++++++++--------------- os/hal/platforms/STM32/rtc_lld.h | 22 ++++------ os/hal/src/rtc.c | 29 ++++++-------- 4 files changed, 77 insertions(+), 68 deletions(-) diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h index 0c545c3a6..e0a2c50c5 100644 --- a/os/hal/include/rtc.h +++ b/os/hal/include/rtc.h @@ -70,11 +70,8 @@ extern "C" { void rtcInit(void); #if RTC_SUPPORTS_CALLBACKS - void rtcStart(RTCDriver *rtcp, const RTCConfig *rtccfgp); - void rtcStop(void); - #else /* RTC_SUPPORTS_CALLBACKS */ - #define rtcStart(rtcp, rtccfgp) - #define rtcStop() + void rtcSetCallback(RTCDriver *rtcp, rtccb_t overflowcb, + rtccb_t secondcb, rtccb_t alarmcb); #endif /* RTC_SUPPORTS_CALLBACKS */ void rtcSetTime(uint32_t tv_sec); diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index a6032e0a4..4f404ab27 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -62,20 +62,20 @@ static void rtc_lld_serve_interrupt(RTCDriver *rtcp){ if ((RTC->CRH & RTC_CRH_SECIE) && \ (RTC->CRL & RTC_CRL_SECF) && \ - (rtcp->config->second_cb != NULL)){ - rtcp->config->second_cb(rtcp); + (rtcp->second_cb != NULL)){ + rtcp->second_cb(rtcp); RTC->CRL &= ~RTC_CRL_SECF; } if ((RTC->CRH & RTC_CRH_ALRIE) && \ (RTC->CRL & RTC_CRL_ALRF) && \ - (rtcp->config->alarm_cb != NULL)){ - rtcp->config->alarm_cb(rtcp); + (rtcp->alarm_cb != NULL)){ + rtcp->alarm_cb(rtcp); RTC->CRL &= ~RTC_CRL_ALRF; } if ((RTC->CRH & RTC_CRH_OWIE) && \ (RTC->CRL & RTC_CRL_OWF) && \ - (rtcp->config->overflow_cb != NULL)){ - rtcp->config->overflow_cb(rtcp); + (rtcp->overflow_cb != NULL)){ + rtcp->overflow_cb(rtcp); RTC->CRL &= ~RTC_CRL_OWF; } @@ -157,49 +157,72 @@ void rtc_lld_init(void){ RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE); RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); - RTCD.config = NULL; +#if RTC_SUPPORTS_CALLBACKS + RTCD.alarm_cb = NULL; + RTCD.overflow_cb = NULL; + RTCD.second_cb = NULL; +#endif /* RTC_SUPPORTS_CALLBACKS */ } /** - * @brief Configure and start interrupt servicing routines. - * This function do nothing if callbacks disabled. + * @brief Enables and disables callbacks on the fly. * - * @param[in] rtcp pointer to a @p RTCDriver object - * @param[in] rtccfgp pointer to a @p RTCDriver config object + * @details Pass callback function(s) in argument(s) to enable callback(s). + * Pass NULL to disable callback. + * + * @pre To use this function you must set @p RTC_SUPPORTS_CALLBACKS + * to @p TRUE. + * + * @param[in] rtcp pointer to RTC driver structure. + * @param[in] overflowcb overflow callback function. + * @param[in] secondcb every second callback function. + * @param[in] alarmcb alarm callback function. * * @notapi */ -void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp){ - uint16_t isr_flags = 0; +#if RTC_SUPPORTS_CALLBACKS +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t overflowcb, + rtccb_t secondcb, rtccb_t alarmcb){ - NVICEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); + uint16_t isr_flags = 0; - rtcp->config = rtccfgp; - if (rtcp->config->overflow_cb != NULL){ + if (overflowcb != NULL){ + rtcp->overflow_cb = *overflowcb; isr_flags |= RTC_CRH_OWIE; } - if (rtcp->config->alarm_cb != NULL){ + else{ + rtcp->overflow_cb = NULL; + isr_flags &= ~RTC_CRH_OWIE; + } + + if (alarmcb != NULL){ + rtcp->alarm_cb = *alarmcb; isr_flags |= RTC_CRH_ALRIE; } - if (rtcp->config->second_cb != NULL){ - isr_flags |= RTC_CRH_SECIE; + else{ + rtcp->alarm_cb = NULL; + isr_flags &= ~RTC_CRH_ALRIE; } - /* clear all event flags just to be safe */ - RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); - RTC->CRH |= isr_flags; -} + if (secondcb != NULL){ + rtcp->second_cb = *secondcb; + isr_flags |= RTC_CRH_SECIE; + } + else{ + rtcp->second_cb = NULL; + isr_flags &= ~RTC_CRH_SECIE; + } -/** - * @brief Disable interrupt servicing routines. - * - * @notapi - */ -void rtc_lld_stop(void){ - NVICDisableVector(RTC_IRQn); - RTC->CRH = 0; + if(isr_flags != 0){ + NVICEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); + RTC->CRH |= isr_flags; + } + else{ + NVICDisableVector(RTC_IRQn); + RTC->CRH = 0; + } } - +#endif /* RTC_SUPPORTS_CALLBACKS */ /** * @brief Set current time. diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h index 3b4f69665..2ec4427d5 100644 --- a/os/hal/platforms/STM32/rtc_lld.h +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -66,10 +66,12 @@ /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ + /** - * @brief Structure representing an RTC driver config. + * @brief Structure representing an RTC driver. */ -typedef struct { +struct RTCDriver{ +#if RTC_SUPPORTS_CALLBACKS /** * @brief Overflow callback. Set it to NULL if not used. */ @@ -84,17 +86,7 @@ typedef struct { * @brief Alarm callback. Set it to NULL if not used. */ rtccb_t alarm_cb; -}RTCConfig; - - -/** - * @brief Structure representing an RTC driver. - */ -struct RTCDriver{ - /** - * @brief Pointer to RCT config. - */ - const RTCConfig *config; +#endif /* RTC_SUPPORTS_CALLBACKS */ }; /*===========================================================================*/ @@ -112,8 +104,8 @@ extern RTCDriver RTCD; extern "C" { #endif void rtc_lld_init(void); - void rtc_lld_start(RTCDriver *rtcp, const RTCConfig *rtccfgp); - void rtc_lld_stop(void); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t overflow_cb, + rtccb_t second_cb, rtccb_t alarm_cb); void rtc_lld_set_time(uint32_t tv_sec); uint32_t rtc_lld_get_sec(void); uint16_t rtc_lld_get_msec(void); diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index 8f9025364..ab916cf52 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -61,26 +61,23 @@ void rtcInit(void){ rtc_lld_init(); } +#if RTC_SUPPORTS_CALLBACKS /** - * @brief Configure and start interrupt servicing routines. - * This function do nothing if callbacks disabled. + * @brief Enables and disables callbacks on the fly. + * @details Pass callback function(s) in argument(s) to enable callback(s). + * Pass NULL to disable callback. + * @pre To use this function you must set @p RTC_SUPPORTS_CALLBACKS + * to @p TRUE. * * @param[in] rtcp - pointer to RTC driver structure. - * @param[in] rtccfgp - pointer to RTC config structure. - */ -#if RTC_SUPPORTS_CALLBACKS -void rtcStartI(RTCDriver *rtcp, const RTCConfig *rtccfgp){ - chDbgCheckClassI(); - chDbgCheck(((rtcp != NULL) && (rtccfgp != NULL)), "rtcStart"); - rtc_lld_start(rtcp, rtccfgp); -} - -/** - * @brief Stop interrupt servicing routines. + * @param[in] overflowcb - overflow callback function. + * @param[in] secondcb - every second callback function. + * @param[in] alarmcb - alarm callback function. */ -void rtcStopI(void){ - chDbgCheckClassI(); - rtc_lld_stop(); +void rtcSetCallback(RTCDriver *rtcp, rtccb_t overflowcb, + rtccb_t secondcb, rtccb_t alarmcb){ + chDbgCheck((rtcp != NULL), "rtcStart"); + rtc_lld_set_callback(rtcp, overflowcb, secondcb, alarmcb); } #endif /* RTC_SUPPORTS_CALLBACKS */ -- cgit v1.2.3 From 076c1733859a4e00b75fbf57d9faa5d437a33822 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Sep 2011 12:54:11 +0000 Subject: RTC. Test code updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3294 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/RTC/halconf.h | 2 +- testhal/STM32F1xx/RTC/main.c | 22 ++++++++-------------- 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h index 553decda8..58023ba58 100644 --- a/testhal/STM32F1xx/RTC/halconf.h +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -209,7 +209,7 @@ * @brief Switch to TRUE if you need callbacks from RTC. */ #if !defined(RTC_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) -#define RTC_SUPPORTS_CALLBACKS FALSE +#define RTC_SUPPORTS_CALLBACKS TRUE #endif /** diff --git a/testhal/STM32F1xx/RTC/main.c b/testhal/STM32F1xx/RTC/main.c index 497b7f0cf..d68919ecf 100644 --- a/testhal/STM32F1xx/RTC/main.c +++ b/testhal/STM32F1xx/RTC/main.c @@ -21,7 +21,7 @@ #include "ch.h" #include "hal.h" -#define TEST_DEEPSLEEP_ENABLE +//#define TEST_DEEPSLEEP_ENABLE #ifdef TEST_DEEPSLEEP_ENABLE @@ -62,36 +62,30 @@ int main(void) { #else /* TEST_DEEPSLEEP_ENABLE */ -static void my_secondcb(RTCDriver *rtcp){ +static void my_overflowcb(RTCDriver *rtcp){ (void)rtcp; - //palTogglePad(IOPORT3, GPIOC_LED); + palTogglePad(IOPORT3, GPIOC_LED); + rtcSetAlarm(rtcGetSec() + 10); } -static void my_alarmcb(RTCDriver *rtcp){ +static void my_secondcb(RTCDriver *rtcp){ (void)rtcp; - palTogglePad(IOPORT3, GPIOC_LED); - rtcSetAlarm(rtcGetSec() + 10); + //palTogglePad(IOPORT3, GPIOC_LED); } -static void my_overflowcb(RTCDriver *rtcp){ +static void my_alarmcb(RTCDriver *rtcp){ (void)rtcp; palTogglePad(IOPORT3, GPIOC_LED); rtcSetAlarm(rtcGetSec() + 10); } -static const RTCConfig rtccfg={ - my_overflowcb, - my_secondcb, - my_alarmcb, -}; int main(void) { halInit(); chSysInit(); rtcSetAlarm(rtcGetSec() + 10); - rtcStart(&RTCD, &rtccfg); - + rtcSetCallback(&RTCD, NULL, my_secondcb, my_alarmcb); while (TRUE){ chThdSleepMilliseconds(500); } -- cgit v1.2.3 From 9d91559dd2a9c79c061487b5d36c5b1665b597d7 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Sep 2011 12:58:34 +0000 Subject: RTC. Minor comments inprovement. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3295 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.h | 1 + 1 file changed, 1 insertion(+) diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h index 2ec4427d5..c2c6f676b 100644 --- a/os/hal/platforms/STM32/rtc_lld.h +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -69,6 +69,7 @@ /** * @brief Structure representing an RTC driver. + * @note This driver if dummy when callbacks disabled. */ struct RTCDriver{ #if RTC_SUPPORTS_CALLBACKS -- cgit v1.2.3 From 9ff43d016e507151e59d2acbf33b701178bbfc90 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 10 Sep 2011 09:52:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3302 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../plugins/org.chibios.tools.eclipse.debug_1.0.5.jar | Bin 34867 -> 0 bytes .../plugins/org.chibios.tools.eclipse.debug_1.0.7.jar | Bin 0 -> 34937 bytes 2 files changed, 0 insertions(+), 0 deletions(-) delete mode 100644 tools/eclipse/plugins/org.chibios.tools.eclipse.debug_1.0.5.jar create mode 100644 tools/eclipse/plugins/org.chibios.tools.eclipse.debug_1.0.7.jar diff --git a/tools/eclipse/plugins/org.chibios.tools.eclipse.debug_1.0.5.jar b/tools/eclipse/plugins/org.chibios.tools.eclipse.debug_1.0.5.jar deleted file mode 100644 index dd46cfc15..000000000 Binary files a/tools/eclipse/plugins/org.chibios.tools.eclipse.debug_1.0.5.jar and /dev/null differ diff --git a/tools/eclipse/plugins/org.chibios.tools.eclipse.debug_1.0.7.jar b/tools/eclipse/plugins/org.chibios.tools.eclipse.debug_1.0.7.jar new file mode 100644 index 000000000..fd5622085 Binary files /dev/null and b/tools/eclipse/plugins/org.chibios.tools.eclipse.debug_1.0.7.jar differ -- cgit v1.2.3 From ff11f4aa9a4815f3cf4d2a3becba0101cd684a6d Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 11 Sep 2011 18:19:03 +0000 Subject: I2C. Remove const qualifier from pointer to I2CSlaveConfig. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3306 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index 548b5418e..aa11bb543 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -212,7 +212,7 @@ struct I2CDriver{ /** * @brief Current slave configuration data. */ - const I2CSlaveConfig *id_slave_config; + I2CSlaveConfig *id_slave_config; __IO size_t txbytes; /*!< @brief Number of bytes to be transmitted. */ __IO size_t rxbytes; /*!< @brief Number of bytes to be received. */ -- cgit v1.2.3 From a08f38d06c5dabf25751bac2deb4259e67fac530 Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 11 Sep 2011 18:30:56 +0000 Subject: I2C. Remove const qualifier from pointer to I2CSlaveConfig. Step 2. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3307 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2c.h | 4 ++-- os/hal/src/i2c.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index acf09ec9c..96f85460d 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -256,11 +256,11 @@ extern "C" { void i2cObjectInit(I2CDriver *i2cp); void i2cStart(I2CDriver *i2cp, const I2CConfig *config); void i2cStop(I2CDriver *i2cp); - void i2cMasterTransmit(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, + void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, uint16_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes); - void i2cMasterReceive(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, + void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes); void i2cMasterStart(I2CDriver *i2cp); void i2cMasterStop(I2CDriver *i2cp); diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 9ce2cc76f..68735b037 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -166,7 +166,7 @@ void i2cStop(I2CDriver *i2cp) { * you want transmit only */ void i2cMasterTransmit(I2CDriver *i2cp, - const I2CSlaveConfig *i2cscfg, + I2CSlaveConfig *i2cscfg, uint16_t slave_addr, uint8_t *txbuf, size_t txbytes, @@ -210,7 +210,7 @@ void i2cMasterTransmit(I2CDriver *i2cp, * @param[in] rxbuf pointer to receive buffer */ void i2cMasterReceive(I2CDriver *i2cp, - const I2CSlaveConfig *i2cscfg, + I2CSlaveConfig *i2cscfg, uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes){ -- cgit v1.2.3 From cf7747f0407db08d59ecb0570dd66f867a07063e Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 11 Sep 2011 20:21:45 +0000 Subject: I2C. Remove const qualifier from pointer to I2CSlaveConfig. Step 3. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3308 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2c.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index 96f85460d..95bbfa8b4 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -105,7 +105,7 @@ typedef enum { * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the * callback */ -typedef void (*i2ccallback_t)(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg); +typedef void (*i2ccallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg); /** @@ -116,8 +116,7 @@ typedef void (*i2ccallback_t)(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg); * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the * callback */ -typedef void (*i2cerrorcallback_t)(I2CDriver *i2cp, - const I2CSlaveConfig *i2cscfg); +typedef void (*i2cerrorcallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg); /** -- cgit v1.2.3 From 7148a664b5c73138a504cd61a1882cfb91ba3b7a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 12 Sep 2011 13:40:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3309 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/dox/ext.dox | 84 ++++++ os/hal/hal.mk | 1 + os/hal/include/ext.h | 101 +++++++ os/hal/include/hal.h | 1 + os/hal/platforms/STM32/ext_lld.c | 390 ++++++++++++++++++++++++ os/hal/platforms/STM32/ext_lld.h | 265 ++++++++++++++++ os/hal/platforms/STM32F1xx/platform.mk | 1 + os/hal/src/ext.c | 121 ++++++++ os/hal/src/hal.c | 3 + os/hal/templates/ext_lld.c | 99 ++++++ os/hal/templates/ext_lld.h | 125 ++++++++ testhal/STM32F1xx/ADC/readme.txt | 2 +- testhal/STM32F1xx/CAN/readme.txt | 2 +- testhal/STM32F1xx/EXT/Makefile | 203 +++++++++++++ testhal/STM32F1xx/EXT/chconf.h | 535 +++++++++++++++++++++++++++++++++ testhal/STM32F1xx/EXT/halconf.h | 332 ++++++++++++++++++++ testhal/STM32F1xx/EXT/main.c | 79 +++++ testhal/STM32F1xx/EXT/mcuconf.h | 154 ++++++++++ testhal/STM32F1xx/EXT/readme.txt | 26 ++ testhal/STM32F1xx/GPT/run | 8 - testhal/STM32F1xx/IRQ_STORM/readme.txt | 2 +- testhal/STM32F1xx/PWM-ICU/readme.txt | 2 +- testhal/STM32F1xx/SDIO/readme.txt | 2 +- testhal/STM32F1xx/SPI/readme.txt | 2 +- testhal/STM32F1xx/UART/readme.txt | 2 +- 25 files changed, 2527 insertions(+), 15 deletions(-) create mode 100644 os/hal/dox/ext.dox create mode 100644 os/hal/include/ext.h create mode 100644 os/hal/platforms/STM32/ext_lld.c create mode 100644 os/hal/platforms/STM32/ext_lld.h create mode 100644 os/hal/src/ext.c create mode 100644 os/hal/templates/ext_lld.c create mode 100644 os/hal/templates/ext_lld.h create mode 100644 testhal/STM32F1xx/EXT/Makefile create mode 100644 testhal/STM32F1xx/EXT/chconf.h create mode 100644 testhal/STM32F1xx/EXT/halconf.h create mode 100644 testhal/STM32F1xx/EXT/main.c create mode 100644 testhal/STM32F1xx/EXT/mcuconf.h create mode 100644 testhal/STM32F1xx/EXT/readme.txt delete mode 100644 testhal/STM32F1xx/GPT/run diff --git a/os/hal/dox/ext.dox b/os/hal/dox/ext.dox new file mode 100644 index 000000000..5a66830e9 --- /dev/null +++ b/os/hal/dox/ext.dox @@ -0,0 +1,84 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup EXT EXT Driver + * @brief Generic EXT Driver. + * @details This module implements a generic EXT (EXTernal) driver. + * @pre In order to use the EXT driver the @p HAL_USE_EXT option + * must be enabled in @p halconf.h. + * + * @section ext_1 Driver State Machine + * The driver implements a state machine internally, not all the driver + * functionalities can be used in any moment, any transition not explicitly + * shown in the following diagram has to be considered an error and shall + * be captured by an assertion (if enabled). + * @if LATEX_PDF + * @dot + digraph example { + size="5, 7"; + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + uninit [label="EXT_UNINIT", style="bold"]; + stop [label="EXT_STOP\nLow Power"]; + active [label="EXT_ACTIVE"]; + + uninit -> stop [label="extInit()"]; + stop -> stop [label="\nextStop()"]; + stop -> active [label="\nextStart()"]; + active -> stop [label="\nextStop()"]; + active -> active [label="\nextStart()"]; + } + * @enddot + * @else + * @dot + digraph example { + rankdir="LR"; + + node [shape=circle, fontname=Sans, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; + edge [fontname=Sans, fontsize=8]; + + uninit [label="EXT_UNINIT", style="bold"]; + stop [label="EXT_STOP\nLow Power"]; + active [label="EXT_ACTIVE"]; + + uninit -> stop [label="extInit()"]; + stop -> stop [label="\nextStop()"]; + stop -> active [label="\nextStart()"]; + active -> stop [label="\nextStop()"]; + active -> active [label="\nextStart()"]; + } + * @enddot + * @endif + * + * @section ext_2 EXT Operations. + * This driver abstracts generic external interrupt sources, a callback + * is invoked when a programmable transition is detected on one of the + * configured channels. Several channel modes are possible. + * - EXT_CH_MODE_DISABLED, channel not used. + * - EXT_CH_MODE_RISING_EDGE, callback on a rising edge. + * - EXT_CH_MODE_FALLING_EDGE, callback on a falling edge. + * - EXT_CH_MODE_BOTH_EDGES, callback on a both edges. + * . + * @ingroup IO + */ diff --git a/os/hal/hal.mk b/os/hal/hal.mk index 87a3c6dc3..dddb73f85 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -3,6 +3,7 @@ HALSRC = ${CHIBIOS}/os/hal/src/hal.c \ ${CHIBIOS}/os/hal/src/adc.c \ ${CHIBIOS}/os/hal/src/can.c \ + ${CHIBIOS}/os/hal/src/ext.c \ ${CHIBIOS}/os/hal/src/gpt.c \ ${CHIBIOS}/os/hal/src/i2c.c \ ${CHIBIOS}/os/hal/src/icu.c \ diff --git a/os/hal/include/ext.h b/os/hal/include/ext.h new file mode 100644 index 000000000..83191b030 --- /dev/null +++ b/os/hal/include/ext.h @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ext.h + * @brief EXT Driver macros and structures. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_H_ +#define _EXT_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name EXT channels modes + * @{ + */ +#define EXT_CH_MODE_DISABLED 0 /**< @brief Channel disabled. */ +#define EXT_CH_MODE_RISING_EDGE 1 /**< @brief Rising edge callback. */ +#define EXT_CH_MODE_FALLING_EDGE 2 /**< @brief Falling edge callback. */ +/** @brief Both edges callback.*/ +#define EXT_CH_MODE_BOTH_EDGES (EXT_CH_MODE_RISING_EDGE | \ + EXT_CH_MODE_FALLING_EDGE) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + EXT_UNINIT = 0, /**< Not initialized. */ + EXT_STOP = 1, /**< Stopped. */ + EXT_ACTIVE = 2, /**< Active. */ +} extstate_t; + +/** + * @brief Type of a structure representing a EXT driver. + */ +typedef struct EXTDriver EXTDriver; + +#include "ext_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void extInit(void); + void extObjectInit(EXTDriver *extp); + void extStart(EXTDriver *extp, const EXTConfig *config); + void extStop(EXTDriver *extp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_H_ */ + +/** @} */ diff --git a/os/hal/include/hal.h b/os/hal/include/hal.h index b92789b02..8d7214325 100644 --- a/os/hal/include/hal.h +++ b/os/hal/include/hal.h @@ -37,6 +37,7 @@ #include "pal.h" #include "adc.h" #include "can.h" +#include "ext.h" #include "gpt.h" #include "i2c.h" #include "icu.h" diff --git a/os/hal/platforms/STM32/ext_lld.c b/os/hal/platforms/STM32/ext_lld.c new file mode 100644 index 000000000..fc203fa60 --- /dev/null +++ b/os/hal/platforms/STM32/ext_lld.c @@ -0,0 +1,390 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/ext_lld.c + * @brief STM32 EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI0_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 0); + EXTD1.config->channels[0].cb(&EXTD1, 0); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 1); + EXTD1.config->channels[1].cb(&EXTD1, 1); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 2); + EXTD1.config->channels[2].cb(&EXTD1, 2); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 3); + EXTD1.config->channels[3].cb(&EXTD1, 3); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI4_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 4); + EXTD1.config->channels[4].cb(&EXTD1, 4); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR; + EXTI->PR = pr; + if (pr & (1 << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1 << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1 << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1 << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1 << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR; + EXTI->PR = pr; + if (pr & (1 << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1 << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1 << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1 << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1 << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1 << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +CH_IRQ_HANDLER(PVD_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 16); + EXTD1.config->channels[16].cb(&EXTD1, 16); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC). + * + * @isr + */ +CH_IRQ_HANDLER(RTCAlarm_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 17); + EXTD1.config->channels[17].cb(&EXTD1, 17); + + CH_IRQ_EPILOGUE(); +} + +#if STM32_HAS_USB || defined(__DOXYGEN__) +/** + * @brief EXTI[18] interrupt handler (USB). + * + * @isr + */ +CH_IRQ_HANDLER(USBWakeUp_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_HAS_USB */ + +#if STM32_HAS_OTG1 || defined(__DOXYGEN__) +/** + * @brief EXTI[18] interrupt handler (OTG1). + * + * @isr + */ +CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_HAS_OTG1 */ + +#if STM32_HAS_ETH || defined(__DOXYGEN__) +/** + * @brief EXTI[19] interrupt handler (ETH). + * + * @isr + */ +CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_HAS_ETH */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ + extObjectInit(&EXTD1); +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + unsigned i; + uint32_t imr, emr, rtsr, ftsr; + + if (extp->state == EXT_STOP) { + /* Clock activation.*/ + NVICEnableVector(EXTI0_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); + NVICEnableVector(EXTI1_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); + NVICEnableVector(EXTI2_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); + NVICEnableVector(EXTI3_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); + NVICEnableVector(EXTI4_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); + NVICEnableVector(EXTI9_5_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); + NVICEnableVector(EXTI15_10_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); + NVICEnableVector(PVD_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); + NVICEnableVector(RTCAlarm_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); +#if STM32_HAS_USB + NVICEnableVector(USBWakeUp_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); +#endif +#if STM32_HAS_OTG1 + NVICEnableVector(OTG_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); +#endif +#if STM32_HAS_ETH + NVICEnableVector(ETH_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); +#endif + } + /* Configuration.*/ + imr = emr = rtsr = ftsr = 0; + for (i = 0; i < EXT_MAX_CHANNELS; i++) { + if (extp->config->channels[i].mode != EXT_CH_MODE_DISABLED) { + if (extp->config->channels[i].cb != NULL) + imr |= (1 << i); + else + emr |= (1 << i); + if (extp->config->channels[i].mode & EXT_CH_MODE_RISING_EDGE) + rtsr |= (1 << i); + if (extp->config->channels[i].mode & EXT_CH_MODE_FALLING_EDGE) + ftsr |= (1 << i); + } + } + AFIO->EXTICR[0] = extp->config->exti[0]; + AFIO->EXTICR[1] = extp->config->exti[1]; + AFIO->EXTICR[2] = extp->config->exti[2]; + AFIO->EXTICR[3] = extp->config->exti[3]; + EXTI->SWIER = 0; + EXTI->RTSR = rtsr; + EXTI->FTSR = ftsr; + EXTI->PR = EXT_CHANNELS_MASK; + EXTI->EMR = emr; + EXTI->IMR = imr; +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + if (extp->state == EXT_ACTIVE) { + NVICDisableVector(EXTI0_IRQn); + NVICDisableVector(EXTI1_IRQn); + NVICDisableVector(EXTI2_IRQn); + NVICDisableVector(EXTI3_IRQn); + NVICDisableVector(EXTI4_IRQn); + NVICDisableVector(EXTI9_5_IRQn); + NVICDisableVector(EXTI15_10_IRQn); + NVICDisableVector(PVD_IRQn); + NVICDisableVector(RTCAlarm_IRQn); +#if STM32_HAS_USB + NVICDisableVector(USBWakeUp_IRQn); +#endif +#if STM32_HAS_OTG1 + NVICDisableVector(OTG_FS_WKUP_IRQn); +#endif +#if STM32_HAS_ETH + NVICDisableVector(ETH_WKUP_IRQn); +#endif + } + EXTI->EMR = 0; + EXTI->IMR = 0; + EXTI->PR = EXT_CHANNELS_MASK; +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/STM32/ext_lld.h b/os/hal/platforms/STM32/ext_lld.h new file mode 100644 index 000000000..45e863d9c --- /dev/null +++ b/os/hal/platforms/STM32/ext_lld.h @@ -0,0 +1,265 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/ext_lld.h + * @brief STM32 EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + * @note The number of available channels varies depending on the STM32 + * subfamily: + * - STM32F10X_CL, 20 channels. + * - STM32F2XX, 23 channels. + * - STM32L1XX_MD, 23 channels. + * - All other STM32F10X_xx, 19 channels. + * . + */ +#if defined(STM32F10X_CL) || defined(__DOXYGEN__) +#define EXT_MAX_CHANNELS 20 +#elif defined(STM32F2XX) +#define EXT_MAX_CHANNELS 23 +#else +#define EXT_MAX_CHANNELS 19 +#endif + +/** + * @brief Mask of the available channels. + */ +#define EXT_CHANNELS_MASK (EXT_MAX_CHANNELS - 1) + +/** + * @name EXTI configuration helpers + * @{ + */ +/** + * @brief EXTI-GPIO association macro. + * @details Helper macro to associate a GPIO to each of the Mx EXTI inputs. + */ +#define EXT_MODE_EXTI(m0, m1, m2, m3, m4, m5, m6, m7, \ + m8, m9, m10, m11, m12, m13, m14, m15) \ + { \ + ((m0) << 0) | ((m1) << 4) | ((m2) << 8) | ((m3) << 12), \ + ((m4) << 0) | ((m5) << 4) | ((m6) << 8) | ((m7) << 12), \ + ((m8) << 0) | ((m9) << 4) | ((m10) << 8) | ((m11) << 12), \ + ((m12) << 0) | ((m13) << 4) | ((m14) << 8) | ((m15) << 12) \ + } + +#define EXT_MODE_GPIOA 0 /**< @brief GPIOA identifier. */ +#define EXT_MODE_GPIOB 1 /**< @brief GPIOB identifier. */ +#define EXT_MODE_GPIOC 2 /**< @brief GPIOC identifier. */ +#define EXT_MODE_GPIOD 3 /**< @brief GPIOD identifier. */ +#define EXT_MODE_GPIOE 4 /**< @brief GPIOE identifier. */ +#define EXT_MODE_GPIOF 5 /**< @brief GPIOF identifier. */ +#define EXT_MODE_GPIOG 6 /**< @brief GPIOG identifier. */ +#define EXT_MODE_GPIOH 7 /**< @brief GPIOH identifier. */ +#define EXT_MODE_GPIOI 8 /**< @brief GPIOI identifier. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 (PVD) interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 (RTC) interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 (USB) interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 (ETH) interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + * @details In the STM32 implementation a @p NULL callback pointer is + * valid and configures the channel as an event sources instead + * of an interrupt source. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief Initialization values for EXTICRx registers. + */ + uint16_t exti[4]; +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk index 26f13cd81..89179f65f 100644 --- a/os/hal/platforms/STM32F1xx/platform.mk +++ b/os/hal/platforms/STM32F1xx/platform.mk @@ -2,6 +2,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \ diff --git a/os/hal/src/ext.c b/os/hal/src/ext.c new file mode 100644 index 000000000..d68758684 --- /dev/null +++ b/os/hal/src/ext.c @@ -0,0 +1,121 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ext.c + * @brief EXT Driver code. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief EXT Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void extInit(void) { + + ext_lld_init(); +} + +/** + * @brief Initializes the standard part of a @p EXTDriver structure. + * + * @param[out] extp pointer to the @p EXTDriver object + * + * @init + */ +void extObjectInit(EXTDriver *extp) { + + extp->state = EXT_STOP; + extp->config = NULL; +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] config pointer to the @p EXTConfig object + * + * @api + */ +void extStart(EXTDriver *extp, const EXTConfig *config) { + + chDbgCheck((extp != NULL) && (config != NULL), "extStart"); + + chSysLock(); + chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), + "extStart(), #1", "invalid state"); + extp->config = config; + ext_lld_start(extp); + extp->state = EXT_ACTIVE; + chSysUnlock(); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @api + */ +void extStop(EXTDriver *extp) { + + chDbgCheck(extp != NULL, "extStop"); + + chSysLock(); + chDbgAssert((extp->state == EXT_STOP) || (extp->state == EXT_ACTIVE), + "extStop(), #1", "invalid state"); + ext_lld_stop(extp); + extp->state = EXT_STOP; + chSysUnlock(); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/src/hal.c b/os/hal/src/hal.c index 3c8fb2fe6..d5a8082e9 100644 --- a/os/hal/src/hal.c +++ b/os/hal/src/hal.c @@ -71,6 +71,9 @@ void halInit(void) { #if HAL_USE_CAN || defined(__DOXYGEN__) canInit(); #endif +#if HAL_USE_EXT || defined(__DOXYGEN__) + extInit(); +#endif #if HAL_USE_GPT || defined(__DOXYGEN__) gptInit(); #endif diff --git a/os/hal/templates/ext_lld.c b/os/hal/templates/ext_lld.c new file mode 100644 index 000000000..1aa9477a6 --- /dev/null +++ b/os/hal/templates/ext_lld.c @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/ext_lld.c + * @brief EXT Driver subsystem low level driver source template. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + + if (extp->state == EXT_STOP) { + /* Clock activation.*/ + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + if (extp->state == EXT_ACTIVE) { + /* Clock deactivation.*/ + + } +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/templates/ext_lld.h b/os/hal/templates/ext_lld.h new file mode 100644 index 000000000..eb5a624a4 --- /dev/null +++ b/os/hal/templates/ext_lld.h @@ -0,0 +1,125 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/ext_lld.h + * @brief EXT Driver subsystem low level driver header template. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Available number of EXT channels. + */ +#define EXT_MAX_CHANNELS 20 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + uint32_t mode; /**< @brief Channel mode. */ + extcallback_t cb; /**< @brief Channel callback. */ +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/ADC/readme.txt b/testhal/STM32F1xx/ADC/readme.txt index e0cf0adea..9d6bbd192 100644 --- a/testhal/STM32F1xx/ADC/readme.txt +++ b/testhal/STM32F1xx/ADC/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo will on an Olimex STM32-P103 board. +The demo runs on an Olimex STM32-P103 board. ** The Demo ** diff --git a/testhal/STM32F1xx/CAN/readme.txt b/testhal/STM32F1xx/CAN/readme.txt index 3b92f4fa3..81ef4c60a 100644 --- a/testhal/STM32F1xx/CAN/readme.txt +++ b/testhal/STM32F1xx/CAN/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo will on an Olimex STM32-P103 board. +The demo runs on an Olimex STM32-P103 board. ** The Demo ** diff --git a/testhal/STM32F1xx/EXT/Makefile b/testhal/STM32F1xx/EXT/Makefile new file mode 100644 index 000000000..32cec391d --- /dev/null +++ b/testhal/STM32F1xx/EXT/Makefile @@ -0,0 +1,203 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/EXT/chconf.h b/testhal/STM32F1xx/EXT/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F1xx/EXT/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/EXT/halconf.h b/testhal/STM32F1xx/EXT/halconf.h new file mode 100644 index 000000000..514b29884 --- /dev/null +++ b/testhal/STM32F1xx/EXT/halconf.h @@ -0,0 +1,332 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/EXT/main.c b/testhal/STM32F1xx/EXT/main.c new file mode 100644 index 000000000..ce21c1fd8 --- /dev/null +++ b/testhal/STM32F1xx/EXT/main.c @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_DISABLED, NULL}, + }, + EXT_MODE_EXTI(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) +}; + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palClearPad(GPIOC, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(GPIOC, GPIOC_LED); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F1xx/EXT/mcuconf.h b/testhal/STM32F1xx/EXT/mcuconf.h new file mode 100644 index 000000000..88a5aa33b --- /dev/null +++ b/testhal/STM32F1xx/EXT/mcuconf.h @@ -0,0 +1,154 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCO STM32_MCO_NOCLOCK + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F1xx/EXT/readme.txt b/testhal/STM32F1xx/EXT/readme.txt new file mode 100644 index 000000000..514c0d5c6 --- /dev/null +++ b/testhal/STM32F1xx/EXT/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 EXT driver. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/GPT/run b/testhal/STM32F1xx/GPT/run deleted file mode 100644 index 818d0e307..000000000 --- a/testhal/STM32F1xx/GPT/run +++ /dev/null @@ -1,8 +0,0 @@ -soft_reset_halt -wait_halt -poll -flash probe 0 -stm32x mass_erase 0 -flash write_bank 0 ch.bin 0 -soft_reset_halt -resume diff --git a/testhal/STM32F1xx/IRQ_STORM/readme.txt b/testhal/STM32F1xx/IRQ_STORM/readme.txt index 32aad05b5..d06bff965 100644 --- a/testhal/STM32F1xx/IRQ_STORM/readme.txt +++ b/testhal/STM32F1xx/IRQ_STORM/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo will on an Olimex STM32-P103 board. +The demo runs on an Olimex STM32-P103 board. ** The Demo ** diff --git a/testhal/STM32F1xx/PWM-ICU/readme.txt b/testhal/STM32F1xx/PWM-ICU/readme.txt index 97476205d..520f2feeb 100644 --- a/testhal/STM32F1xx/PWM-ICU/readme.txt +++ b/testhal/STM32F1xx/PWM-ICU/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo will on an Olimex STM32-P103 board. +The demo runs on an Olimex STM32-P103 board. ** The Demo ** diff --git a/testhal/STM32F1xx/SDIO/readme.txt b/testhal/STM32F1xx/SDIO/readme.txt index caeb7bce7..de5af6948 100644 --- a/testhal/STM32F1xx/SDIO/readme.txt +++ b/testhal/STM32F1xx/SDIO/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo will on an Olimex ST_STM3210E_EVAL board. +The demo runs on an Olimex ST_STM3210E_EVAL board. ** The Demo ** diff --git a/testhal/STM32F1xx/SPI/readme.txt b/testhal/STM32F1xx/SPI/readme.txt index 590fd8299..b3d53c5a2 100644 --- a/testhal/STM32F1xx/SPI/readme.txt +++ b/testhal/STM32F1xx/SPI/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo will on an Olimex STM32-P103 board. +The demo runs on an Olimex STM32-P103 board. ** The Demo ** diff --git a/testhal/STM32F1xx/UART/readme.txt b/testhal/STM32F1xx/UART/readme.txt index fc111a298..0fc5de144 100644 --- a/testhal/STM32F1xx/UART/readme.txt +++ b/testhal/STM32F1xx/UART/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo will on an Olimex STM32-P103 board. +The demo runs on an Olimex STM32-P103 board. ** The Demo ** -- cgit v1.2.3 From d3e15bccfc41af4e4d3972003ff06b69de2225bc Mon Sep 17 00:00:00 2001 From: barthess Date: Mon, 12 Sep 2011 15:50:35 +0000 Subject: I2C. Revert const qualifier to the pointer to I2CSlaveConfig. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3310 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2c.h | 9 +++++---- os/hal/platforms/STM32/i2c_lld.c | 2 +- os/hal/platforms/STM32/i2c_lld.h | 2 +- os/hal/src/i2c.c | 4 ++-- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index 95bbfa8b4..acf09ec9c 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -105,7 +105,7 @@ typedef enum { * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the * callback */ -typedef void (*i2ccallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg); +typedef void (*i2ccallback_t)(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg); /** @@ -116,7 +116,8 @@ typedef void (*i2ccallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg); * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the * callback */ -typedef void (*i2cerrorcallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg); +typedef void (*i2cerrorcallback_t)(I2CDriver *i2cp, + const I2CSlaveConfig *i2cscfg); /** @@ -255,11 +256,11 @@ extern "C" { void i2cObjectInit(I2CDriver *i2cp); void i2cStart(I2CDriver *i2cp, const I2CConfig *config); void i2cStop(I2CDriver *i2cp); - void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, + void i2cMasterTransmit(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, uint16_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes); - void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, + void i2cMasterReceive(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes); void i2cMasterStart(I2CDriver *i2cp); void i2cMasterStop(I2CDriver *i2cp); diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 48bdb3e4e..202669f8e 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -40,7 +40,7 @@ * Note: * When the STOP, START or PEC bit is set, the software must NOT perform * any write access to I2C_CR1 before this bit is cleared by hardware. - * Otherwise there is a risk of setting a second STOP, START or PEC request. + * Otherwise there is a risk of setting a second STOP, START or PEC request. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index aa11bb543..548b5418e 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -212,7 +212,7 @@ struct I2CDriver{ /** * @brief Current slave configuration data. */ - I2CSlaveConfig *id_slave_config; + const I2CSlaveConfig *id_slave_config; __IO size_t txbytes; /*!< @brief Number of bytes to be transmitted. */ __IO size_t rxbytes; /*!< @brief Number of bytes to be received. */ diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 68735b037..9ce2cc76f 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -166,7 +166,7 @@ void i2cStop(I2CDriver *i2cp) { * you want transmit only */ void i2cMasterTransmit(I2CDriver *i2cp, - I2CSlaveConfig *i2cscfg, + const I2CSlaveConfig *i2cscfg, uint16_t slave_addr, uint8_t *txbuf, size_t txbytes, @@ -210,7 +210,7 @@ void i2cMasterTransmit(I2CDriver *i2cp, * @param[in] rxbuf pointer to receive buffer */ void i2cMasterReceive(I2CDriver *i2cp, - I2CSlaveConfig *i2cscfg, + const I2CSlaveConfig *i2cscfg, uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes){ -- cgit v1.2.3 From 3db4f2d2353f7f87f5112fb8d152e87733bd9ae0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 12 Sep 2011 18:27:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3311 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/EXT/main.c | 83 ++++++++++++++++++++++++++++++++------------ 1 file changed, 60 insertions(+), 23 deletions(-) diff --git a/testhal/STM32F1xx/EXT/main.c b/testhal/STM32F1xx/EXT/main.c index ce21c1fd8..a438c3035 100644 --- a/testhal/STM32F1xx/EXT/main.c +++ b/testhal/STM32F1xx/EXT/main.c @@ -21,29 +21,71 @@ #include "ch.h" #include "hal.h" -static const EXTConfig extcfg = { - { - {EXT_CH_MODE_DISABLED, NULL}, - }, - EXT_MODE_EXTI(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) -}; +static VirtualTimer vt; -/* - * Red LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { +/* LED set to OFF after 200mS.*/ +static void ledoff(void *arg) { (void)arg; - chRegSetThreadName("blinker"); - while (TRUE) { - palClearPad(GPIOC, GPIOC_LED); - chThdSleepMilliseconds(500); - palSetPad(GPIOC, GPIOC_LED); - chThdSleepMilliseconds(500); - } + palSetPad(GPIOC, GPIOC_LED); +} + +/* Triggered when the button is pressed or released. The LED is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + (void)channel; + palClearPad(GPIOC, GPIOC_LED); + chSysLockFromIsr(); + if (!chVTIsArmedI(&vt)) + chVTSetI(&vt, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* Triggered when the LED goes OFF.*/ +static void extcb2(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + (void)channel; } +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_RISING_EDGE, extcb2}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + }, + EXT_MODE_EXTI(EXT_MODE_GPIOA, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + EXT_MODE_GPIOC, + 0, + 0, + 0) +}; + /* * Application entry point. */ @@ -64,11 +106,6 @@ int main(void) { */ extStart(&EXTD1, &extcfg); - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - /* * Normal main() thread activity, in this demo it does nothing except * sleeping in a loop and check the button state. -- cgit v1.2.3 From bc571ccd326886a8cbbde85de66b6fab91336193 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 12 Sep 2011 19:15:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3312 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h | 26 +++++++++++++------ demos/ARM7-AT91SAM7S-GCC/halconf.h | 22 ++++++++++------ demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h | 22 ++++++++++------ demos/ARM7-AT91SAM7X-GCC/halconf.h | 22 ++++++++++------ demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 22 ++++++++++------ demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 22 ++++++++++------ demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 22 ++++++++++------ demos/ARM7-LPC214x-G++/halconf.h | 22 ++++++++++------ demos/ARM7-LPC214x-GCC/halconf.h | 22 ++++++++++------ demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h | 22 ++++++++++------ demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h | 22 ++++++++++------ demos/ARMCM3-STM32F100-DISCOVERY/halconf.h | 22 ++++++++++------ demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h | 15 +++++++++++ demos/ARMCM3-STM32F103-FATFS/halconf.h | 22 ++++++++++------ demos/ARMCM3-STM32F103-FATFS/mcuconf.h | 15 +++++++++++ demos/ARMCM3-STM32F103-G++/halconf.h | 22 ++++++++++------ demos/ARMCM3-STM32F103-G++/mcuconf.h | 15 +++++++++++ demos/ARMCM3-STM32F103/halconf.h | 22 ++++++++++------ demos/ARMCM3-STM32F103/mcuconf.h | 15 +++++++++++ demos/ARMCM3-STM32F103ZG-FATFS/halconf.h | 22 ++++++++++------ demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h | 15 +++++++++++ demos/ARMCM3-STM32F107/halconf.h | 22 ++++++++++------ demos/ARMCM3-STM32F107/mcuconf.h | 15 +++++++++++ demos/ARMCM3-STM32L152-DISCOVERY/halconf.h | 22 ++++++++++------ demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h | 15 +++++++++++ demos/AVR-AT90CANx-GCC/halconf.h | 22 ++++++++++------ demos/AVR-ATmega128-GCC/halconf.h | 22 ++++++++++------ demos/MSP430-MSP430x1611-GCC/halconf.h | 22 ++++++++++------ demos/PPC-SPC563-GCC/halconf.h | 22 ++++++++++------ demos/Posix-GCC/halconf.h | 22 ++++++++++------ demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h | 22 ++++++++++------ demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h | 22 ++++++++++------ demos/STM8S-STM8S208-RC/halconf.h | 22 ++++++++++------ demos/Win32-MinGW/halconf.h | 22 ++++++++++------ os/hal/templates/halconf.h | 30 ++++++++++++++++++++++ test/coverage/halconf.h | 22 ++++++++++------ testhal/LPC11xx/IRQ_STORM/halconf.h | 22 ++++++++++------ testhal/LPC13xx/IRQ_STORM/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/ADC/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/ADC/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/CAN/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/CAN/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/EXT/halconf.h | 15 +++++------ testhal/STM32F1xx/EXT/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/GPT/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/GPT/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/I2C/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/I2C/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/IRQ_STORM/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/IRQ_STORM/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/PWM-ICU/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/PWM-ICU/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/RTC/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/RTC/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/SDIO/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/SDIO/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/SPI/halconf.h | 22 ++++++++++------ testhal/STM32F1xx/SPI/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/UART/halconf.h | 15 +++++------ testhal/STM32F1xx/UART/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/USB_CDC/halconf.h | 15 +++++------ testhal/STM32F1xx/USB_CDC/mcuconf.h | 15 +++++++++++ testhal/STM32F1xx/USB_MSC/halconf.h | 15 +++++------ testhal/STM32F1xx/USB_MSC/mcuconf.h | 15 +++++++++++ testhal/STM8S/SPI/demo/halconf.h | 15 +++++------ 65 files changed, 915 insertions(+), 352 deletions(-) diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h index 33ecee26a..73a4f41ce 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -170,6 +177,10 @@ #define CAN_USE_SLEEP_MODE TRUE #endif +/*===========================================================================*/ +/* EXT driver related settings. */ +/*===========================================================================*/ + /*===========================================================================*/ /* I2C driver related settings. */ /*===========================================================================*/ @@ -185,6 +196,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +252,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7S-GCC/halconf.h b/demos/ARM7-AT91SAM7S-GCC/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/ARM7-AT91SAM7S-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h index 33ecee26a..1e0fad045 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index d3124c4d3..43d87bc9a 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index d3124c4d3..43d87bc9a 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index 33ecee26a..1e0fad045 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h index 33ecee26a..1e0fad045 100644 --- a/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h index 33ecee26a..1e0fad045 100644 --- a/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h index 0ed6eed8b..be7a4d74f 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h index 0f8ca6ee3..d92b02937 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h @@ -59,6 +59,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/demos/ARMCM3-STM32F103-FATFS/halconf.h b/demos/ARMCM3-STM32F103-FATFS/halconf.h index 33ecee26a..1e0fad045 100644 --- a/demos/ARMCM3-STM32F103-FATFS/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F103-FATFS/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS/mcuconf.h index 558c0773d..32e0c7964 100644 --- a/demos/ARMCM3-STM32F103-FATFS/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/demos/ARMCM3-STM32F103-G++/halconf.h b/demos/ARMCM3-STM32F103-G++/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/ARMCM3-STM32F103-G++/halconf.h +++ b/demos/ARMCM3-STM32F103-G++/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F103-G++/mcuconf.h b/demos/ARMCM3-STM32F103-G++/mcuconf.h index 558c0773d..32e0c7964 100644 --- a/demos/ARMCM3-STM32F103-G++/mcuconf.h +++ b/demos/ARMCM3-STM32F103-G++/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/demos/ARMCM3-STM32F103/halconf.h b/demos/ARMCM3-STM32F103/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/ARMCM3-STM32F103/halconf.h +++ b/demos/ARMCM3-STM32F103/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F103/mcuconf.h b/demos/ARMCM3-STM32F103/mcuconf.h index 88a5aa33b..6d9091165 100644 --- a/demos/ARMCM3-STM32F103/mcuconf.h +++ b/demos/ARMCM3-STM32F103/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h index 682167d84..d9fa44340 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h +++ b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h index aeee83a56..078a38f24 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h +++ b/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/demos/ARMCM3-STM32F107/halconf.h b/demos/ARMCM3-STM32F107/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/ARMCM3-STM32F107/halconf.h +++ b/demos/ARMCM3-STM32F107/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F107/mcuconf.h b/demos/ARMCM3-STM32F107/mcuconf.h index 9cc350652..8516c02a1 100644 --- a/demos/ARMCM3-STM32F107/mcuconf.h +++ b/demos/ARMCM3-STM32F107/mcuconf.h @@ -67,6 +67,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h index 3895ff70a..82a304cbc 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h index a5b77611e..a87325ff7 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h @@ -70,6 +70,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index e3ea70d99..0b74e6678 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index e3ea70d99..0b74e6678 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h index 13ccb9fa8..cb2f9d152 100644 --- a/demos/PPC-SPC563-GCC/halconf.h +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h index 7c6d8a758..9bd348124 100644 --- a/demos/Posix-GCC/halconf.h +++ b/demos/Posix-GCC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h index d36e56ec7..7cd6b72fc 100644 --- a/demos/STM8S-STM8S208-RC/halconf.h +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index 7c6d8a758..9bd348124 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/os/hal/templates/halconf.h b/os/hal/templates/halconf.h index 0e616d3d5..43bc0440f 100644 --- a/os/hal/templates/halconf.h +++ b/os/hal/templates/halconf.h @@ -59,6 +59,13 @@ #define HAL_USE_CAN TRUE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -183,6 +190,22 @@ #endif /** @} */ +/*===========================================================================*/ +/** + * @name EXT driver related setting + * @{ + */ +/*===========================================================================*/ +/** @} */ + +/*===========================================================================*/ +/** + * @name GPT driver related setting + * @{ + */ +/*===========================================================================*/ +/** @} */ + /*===========================================================================*/ /** * @name I2C driver related setting @@ -204,6 +227,13 @@ * @{ */ /*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif /** @} */ /*===========================================================================*/ diff --git a/test/coverage/halconf.h b/test/coverage/halconf.h index 2829fb066..99f45746f 100644 --- a/test/coverage/halconf.h +++ b/test/coverage/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/LPC11xx/IRQ_STORM/halconf.h b/testhal/LPC11xx/IRQ_STORM/halconf.h index 249e2a621..5379d81c0 100644 --- a/testhal/LPC11xx/IRQ_STORM/halconf.h +++ b/testhal/LPC11xx/IRQ_STORM/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/LPC13xx/IRQ_STORM/halconf.h b/testhal/LPC13xx/IRQ_STORM/halconf.h index 249e2a621..5379d81c0 100644 --- a/testhal/LPC13xx/IRQ_STORM/halconf.h +++ b/testhal/LPC13xx/IRQ_STORM/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/ADC/halconf.h b/testhal/STM32F1xx/ADC/halconf.h index b42f9088b..22af05ce2 100644 --- a/testhal/STM32F1xx/ADC/halconf.h +++ b/testhal/STM32F1xx/ADC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/ADC/mcuconf.h b/testhal/STM32F1xx/ADC/mcuconf.h index 558c0773d..32e0c7964 100644 --- a/testhal/STM32F1xx/ADC/mcuconf.h +++ b/testhal/STM32F1xx/ADC/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/CAN/halconf.h b/testhal/STM32F1xx/CAN/halconf.h index a7ae76b45..8c316c95a 100644 --- a/testhal/STM32F1xx/CAN/halconf.h +++ b/testhal/STM32F1xx/CAN/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN TRUE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/CAN/mcuconf.h b/testhal/STM32F1xx/CAN/mcuconf.h index 558c0773d..32e0c7964 100644 --- a/testhal/STM32F1xx/CAN/mcuconf.h +++ b/testhal/STM32F1xx/CAN/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/EXT/halconf.h b/testhal/STM32F1xx/EXT/halconf.h index 514b29884..fcb3c814c 100644 --- a/testhal/STM32F1xx/EXT/halconf.h +++ b/testhal/STM32F1xx/EXT/halconf.h @@ -192,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -241,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/EXT/mcuconf.h b/testhal/STM32F1xx/EXT/mcuconf.h index 88a5aa33b..6d9091165 100644 --- a/testhal/STM32F1xx/EXT/mcuconf.h +++ b/testhal/STM32F1xx/EXT/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/GPT/halconf.h b/testhal/STM32F1xx/GPT/halconf.h index b4361f9b9..834b03a78 100644 --- a/testhal/STM32F1xx/GPT/halconf.h +++ b/testhal/STM32F1xx/GPT/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/GPT/mcuconf.h b/testhal/STM32F1xx/GPT/mcuconf.h index eb0774a23..8c0187fc0 100644 --- a/testhal/STM32F1xx/GPT/mcuconf.h +++ b/testhal/STM32F1xx/GPT/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/I2C/halconf.h b/testhal/STM32F1xx/I2C/halconf.h index da52785c0..36213b63a 100644 --- a/testhal/STM32F1xx/I2C/halconf.h +++ b/testhal/STM32F1xx/I2C/halconf.h @@ -54,6 +54,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -199,6 +206,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -248,14 +262,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/I2C/mcuconf.h b/testhal/STM32F1xx/I2C/mcuconf.h index 809c3abd2..446af067e 100644 --- a/testhal/STM32F1xx/I2C/mcuconf.h +++ b/testhal/STM32F1xx/I2C/mcuconf.h @@ -58,6 +58,21 @@ #define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/IRQ_STORM/halconf.h b/testhal/STM32F1xx/IRQ_STORM/halconf.h index 249e2a621..5379d81c0 100644 --- a/testhal/STM32F1xx/IRQ_STORM/halconf.h +++ b/testhal/STM32F1xx/IRQ_STORM/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/IRQ_STORM/mcuconf.h b/testhal/STM32F1xx/IRQ_STORM/mcuconf.h index 2341d5626..94328b5fa 100644 --- a/testhal/STM32F1xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32F1xx/IRQ_STORM/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/PWM-ICU/halconf.h b/testhal/STM32F1xx/PWM-ICU/halconf.h index 9656ff0aa..62a94fbb0 100644 --- a/testhal/STM32F1xx/PWM-ICU/halconf.h +++ b/testhal/STM32F1xx/PWM-ICU/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/PWM-ICU/mcuconf.h b/testhal/STM32F1xx/PWM-ICU/mcuconf.h index 558c0773d..32e0c7964 100644 --- a/testhal/STM32F1xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32F1xx/PWM-ICU/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h index 58023ba58..820d18046 100644 --- a/testhal/STM32F1xx/RTC/halconf.h +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -54,6 +54,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -223,6 +230,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -272,14 +286,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/RTC/mcuconf.h b/testhal/STM32F1xx/RTC/mcuconf.h index fc7ce0053..beefe5cba 100644 --- a/testhal/STM32F1xx/RTC/mcuconf.h +++ b/testhal/STM32F1xx/RTC/mcuconf.h @@ -58,6 +58,21 @@ #define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/SDIO/halconf.h b/testhal/STM32F1xx/SDIO/halconf.h index 682167d84..d9fa44340 100644 --- a/testhal/STM32F1xx/SDIO/halconf.h +++ b/testhal/STM32F1xx/SDIO/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/SDIO/mcuconf.h b/testhal/STM32F1xx/SDIO/mcuconf.h index 658924fc2..1af95abfd 100644 --- a/testhal/STM32F1xx/SDIO/mcuconf.h +++ b/testhal/STM32F1xx/SDIO/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/SPI/halconf.h b/testhal/STM32F1xx/SPI/halconf.h index eaf7f9673..ab5556545 100644 --- a/testhal/STM32F1xx/SPI/halconf.h +++ b/testhal/STM32F1xx/SPI/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -185,6 +192,13 @@ /* MAC driver related settings. */ /*===========================================================================*/ +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + /*===========================================================================*/ /* MMC_SPI driver related settings. */ /*===========================================================================*/ @@ -234,14 +248,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/SPI/mcuconf.h b/testhal/STM32F1xx/SPI/mcuconf.h index 558c0773d..32e0c7964 100644 --- a/testhal/STM32F1xx/SPI/mcuconf.h +++ b/testhal/STM32F1xx/SPI/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/UART/halconf.h b/testhal/STM32F1xx/UART/halconf.h index d353272b7..c3d3fd11f 100644 --- a/testhal/STM32F1xx/UART/halconf.h +++ b/testhal/STM32F1xx/UART/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -234,14 +241,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/UART/mcuconf.h b/testhal/STM32F1xx/UART/mcuconf.h index c8dd60ca1..b0a57b539 100644 --- a/testhal/STM32F1xx/UART/mcuconf.h +++ b/testhal/STM32F1xx/UART/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/USB_CDC/halconf.h b/testhal/STM32F1xx/USB_CDC/halconf.h index 3895ff70a..982141c90 100644 --- a/testhal/STM32F1xx/USB_CDC/halconf.h +++ b/testhal/STM32F1xx/USB_CDC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -234,14 +241,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/USB_CDC/mcuconf.h b/testhal/STM32F1xx/USB_CDC/mcuconf.h index 558c0773d..32e0c7964 100644 --- a/testhal/STM32F1xx/USB_CDC/mcuconf.h +++ b/testhal/STM32F1xx/USB_CDC/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM32F1xx/USB_MSC/halconf.h b/testhal/STM32F1xx/USB_MSC/halconf.h index 2302e0179..351d410eb 100644 --- a/testhal/STM32F1xx/USB_MSC/halconf.h +++ b/testhal/STM32F1xx/USB_MSC/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -234,14 +241,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/USB_MSC/mcuconf.h b/testhal/STM32F1xx/USB_MSC/mcuconf.h index 558c0773d..32e0c7964 100644 --- a/testhal/STM32F1xx/USB_MSC/mcuconf.h +++ b/testhal/STM32F1xx/USB_MSC/mcuconf.h @@ -60,6 +60,21 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + /* * GPT driver system settings. */ diff --git a/testhal/STM8S/SPI/demo/halconf.h b/testhal/STM8S/SPI/demo/halconf.h index eaf7f9673..34f8f64d6 100644 --- a/testhal/STM8S/SPI/demo/halconf.h +++ b/testhal/STM8S/SPI/demo/halconf.h @@ -55,6 +55,13 @@ #define HAL_USE_CAN FALSE #endif +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + /** * @brief Enables the GPT subsystem. */ @@ -234,14 +241,6 @@ #define MMC_USE_SPI_POLLING TRUE #endif -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ -- cgit v1.2.3 From b86e5efeeb17af6937319d0fd874fc64b0c1ccb4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 12 Sep 2011 19:27:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3313 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h | 5 +---- demos/ARM7-AT91SAM7S-GCC/halconf.h | 5 +---- demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h | 5 +---- demos/ARM7-AT91SAM7X-GCC/halconf.h | 5 +---- demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 5 +---- demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 5 +---- demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 5 +---- demos/ARM7-LPC214x-G++/halconf.h | 5 +---- demos/ARM7-LPC214x-GCC/halconf.h | 5 +---- demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h | 5 +---- demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h | 5 +---- demos/ARMCM3-STM32F100-DISCOVERY/halconf.h | 5 +---- demos/ARMCM3-STM32F103-FATFS/halconf.h | 5 +---- demos/ARMCM3-STM32F103-G++/halconf.h | 5 +---- demos/ARMCM3-STM32F103/halconf.h | 5 +---- demos/ARMCM3-STM32F103ZG-FATFS/halconf.h | 5 +---- demos/ARMCM3-STM32F107/halconf.h | 5 +---- demos/ARMCM3-STM32L152-DISCOVERY/halconf.h | 5 +---- demos/AVR-AT90CANx-GCC/halconf.h | 5 +---- demos/AVR-ATmega128-GCC/halconf.h | 5 +---- demos/MSP430-MSP430x1611-GCC/halconf.h | 5 +---- demos/PPC-SPC563-GCC/halconf.h | 5 +---- demos/Posix-GCC/halconf.h | 5 +---- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h | 5 +---- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h | 5 +---- demos/STM8S-STM8S208-RC/halconf.h | 5 +---- demos/Win32-MinGW/halconf.h | 5 +---- os/hal/templates/halconf.h | 11 ++++++++++- test/coverage/halconf.h | 5 +---- testhal/LPC11xx/IRQ_STORM/halconf.h | 5 +---- testhal/LPC13xx/IRQ_STORM/halconf.h | 5 +---- testhal/STM32F1xx/ADC/halconf.h | 5 +---- testhal/STM32F1xx/CAN/halconf.h | 5 +---- testhal/STM32F1xx/EXT/halconf.h | 5 +---- testhal/STM32F1xx/GPT/halconf.h | 5 +---- testhal/STM32F1xx/I2C/halconf.h | 5 +---- testhal/STM32F1xx/IRQ_STORM/halconf.h | 5 +---- testhal/STM32F1xx/PWM-ICU/halconf.h | 5 +---- testhal/STM32F1xx/RTC/halconf.h | 5 +---- testhal/STM32F1xx/SDIO/halconf.h | 5 +---- testhal/STM32F1xx/SPI/halconf.h | 5 +---- testhal/STM32F1xx/UART/halconf.h | 5 +---- testhal/STM32F1xx/USB_CDC/halconf.h | 5 +---- testhal/STM32F1xx/USB_MSC/halconf.h | 5 +---- testhal/STM8S/SPI/demo/halconf.h | 5 +---- 45 files changed, 54 insertions(+), 177 deletions(-) diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h index 73a4f41ce..5f2bc4485 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h @@ -255,6 +255,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -326,10 +327,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7S-GCC/halconf.h b/demos/ARM7-AT91SAM7S-GCC/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/ARM7-AT91SAM7S-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h index 1e0fad045..560a77dbe 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index 43d87bc9a..f1d93c6f2 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index 43d87bc9a..f1d93c6f2 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index 1e0fad045..560a77dbe 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h index 1e0fad045..560a77dbe 100644 --- a/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h index 1e0fad045..560a77dbe 100644 --- a/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h index be7a4d74f..e8acd1f13 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-FATFS/halconf.h b/demos/ARMCM3-STM32F103-FATFS/halconf.h index 1e0fad045..560a77dbe 100644 --- a/demos/ARMCM3-STM32F103-FATFS/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-G++/halconf.h b/demos/ARMCM3-STM32F103-G++/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/ARMCM3-STM32F103-G++/halconf.h +++ b/demos/ARMCM3-STM32F103-G++/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103/halconf.h b/demos/ARMCM3-STM32F103/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/ARMCM3-STM32F103/halconf.h +++ b/demos/ARMCM3-STM32F103/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h index d9fa44340..9aa7cd21e 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h +++ b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F107/halconf.h b/demos/ARMCM3-STM32F107/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/ARMCM3-STM32F107/halconf.h +++ b/demos/ARMCM3-STM32F107/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h index 82a304cbc..2a5f1806e 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index 0b74e6678..8ec0c2a35 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index 0b74e6678..8ec0c2a35 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h index cb2f9d152..aca6c2f61 100644 --- a/demos/PPC-SPC563-GCC/halconf.h +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h index 9bd348124..aa145ef4d 100644 --- a/demos/Posix-GCC/halconf.h +++ b/demos/Posix-GCC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h index 7cd6b72fc..b9bee3656 100644 --- a/demos/STM8S-STM8S208-RC/halconf.h +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index 9bd348124..aa145ef4d 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/os/hal/templates/halconf.h b/os/hal/templates/halconf.h index 43bc0440f..2e28bea73 100644 --- a/os/hal/templates/halconf.h +++ b/os/hal/templates/halconf.h @@ -221,6 +221,14 @@ #endif /** @} */ +/*===========================================================================*/ +/** + * @name ICU driver related setting + * @{ + */ +/*===========================================================================*/ +/** @} */ + /*===========================================================================*/ /** * @name MAC driver related setting @@ -311,6 +319,7 @@ * @{ */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -367,13 +376,13 @@ #endif /** @} */ - /*===========================================================================*/ /** * @name SERIAL_USB driver related setting * @{ */ /*===========================================================================*/ + /** * @brief Serial over USB buffers size. * @details Configuration parameter, the buffer size must be a multiple of diff --git a/test/coverage/halconf.h b/test/coverage/halconf.h index 99f45746f..95b25b63e 100644 --- a/test/coverage/halconf.h +++ b/test/coverage/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/LPC11xx/IRQ_STORM/halconf.h b/testhal/LPC11xx/IRQ_STORM/halconf.h index 5379d81c0..f5e7cc1ed 100644 --- a/testhal/LPC11xx/IRQ_STORM/halconf.h +++ b/testhal/LPC11xx/IRQ_STORM/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/LPC13xx/IRQ_STORM/halconf.h b/testhal/LPC13xx/IRQ_STORM/halconf.h index 5379d81c0..f5e7cc1ed 100644 --- a/testhal/LPC13xx/IRQ_STORM/halconf.h +++ b/testhal/LPC13xx/IRQ_STORM/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/ADC/halconf.h b/testhal/STM32F1xx/ADC/halconf.h index 22af05ce2..62cc1e67d 100644 --- a/testhal/STM32F1xx/ADC/halconf.h +++ b/testhal/STM32F1xx/ADC/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/CAN/halconf.h b/testhal/STM32F1xx/CAN/halconf.h index 8c316c95a..f73d58cf1 100644 --- a/testhal/STM32F1xx/CAN/halconf.h +++ b/testhal/STM32F1xx/CAN/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/EXT/halconf.h b/testhal/STM32F1xx/EXT/halconf.h index fcb3c814c..d7df1593a 100644 --- a/testhal/STM32F1xx/EXT/halconf.h +++ b/testhal/STM32F1xx/EXT/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/GPT/halconf.h b/testhal/STM32F1xx/GPT/halconf.h index 834b03a78..ff9202a66 100644 --- a/testhal/STM32F1xx/GPT/halconf.h +++ b/testhal/STM32F1xx/GPT/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/I2C/halconf.h b/testhal/STM32F1xx/I2C/halconf.h index 36213b63a..834d54572 100644 --- a/testhal/STM32F1xx/I2C/halconf.h +++ b/testhal/STM32F1xx/I2C/halconf.h @@ -265,6 +265,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -336,10 +337,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/IRQ_STORM/halconf.h b/testhal/STM32F1xx/IRQ_STORM/halconf.h index 5379d81c0..f5e7cc1ed 100644 --- a/testhal/STM32F1xx/IRQ_STORM/halconf.h +++ b/testhal/STM32F1xx/IRQ_STORM/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/PWM-ICU/halconf.h b/testhal/STM32F1xx/PWM-ICU/halconf.h index 62a94fbb0..e5eeb8b7a 100644 --- a/testhal/STM32F1xx/PWM-ICU/halconf.h +++ b/testhal/STM32F1xx/PWM-ICU/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h index 820d18046..93367c2d2 100644 --- a/testhal/STM32F1xx/RTC/halconf.h +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -289,6 +289,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -360,10 +361,6 @@ #define SPI_USE_MUTUAL_EXCLUSION FALSE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/SDIO/halconf.h b/testhal/STM32F1xx/SDIO/halconf.h index d9fa44340..9aa7cd21e 100644 --- a/testhal/STM32F1xx/SDIO/halconf.h +++ b/testhal/STM32F1xx/SDIO/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/SPI/halconf.h b/testhal/STM32F1xx/SPI/halconf.h index ab5556545..a825e65c5 100644 --- a/testhal/STM32F1xx/SPI/halconf.h +++ b/testhal/STM32F1xx/SPI/halconf.h @@ -251,6 +251,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -322,10 +323,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/UART/halconf.h b/testhal/STM32F1xx/UART/halconf.h index c3d3fd11f..2dd31e012 100644 --- a/testhal/STM32F1xx/UART/halconf.h +++ b/testhal/STM32F1xx/UART/halconf.h @@ -244,6 +244,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -315,10 +316,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/USB_CDC/halconf.h b/testhal/STM32F1xx/USB_CDC/halconf.h index 982141c90..c502005f2 100644 --- a/testhal/STM32F1xx/USB_CDC/halconf.h +++ b/testhal/STM32F1xx/USB_CDC/halconf.h @@ -244,6 +244,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -315,10 +316,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM32F1xx/USB_MSC/halconf.h b/testhal/STM32F1xx/USB_MSC/halconf.h index 351d410eb..f772d653a 100644 --- a/testhal/STM32F1xx/USB_MSC/halconf.h +++ b/testhal/STM32F1xx/USB_MSC/halconf.h @@ -244,6 +244,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -315,10 +316,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/testhal/STM8S/SPI/demo/halconf.h b/testhal/STM8S/SPI/demo/halconf.h index 34f8f64d6..af1c8e1a4 100644 --- a/testhal/STM8S/SPI/demo/halconf.h +++ b/testhal/STM8S/SPI/demo/halconf.h @@ -244,6 +244,7 @@ /*===========================================================================*/ /* SDC driver related settings. */ /*===========================================================================*/ + /** * @brief Number of initialization attempts before rejecting the card. * @note Attempts are performed at 10mS intevals. @@ -315,10 +316,6 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - #endif /* _HALCONF_H_ */ /** @} */ -- cgit v1.2.3 From fbac4d253d67cc5b1ec39166ce1abb8124b1e3a8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 13 Sep 2011 12:40:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3314 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/ext.h | 30 ++++++++++++++++++++--- os/hal/platforms/STM32/ext_lld.c | 51 +++++++++++++++++++++++++++++++++++----- os/hal/platforms/STM32/ext_lld.h | 2 ++ os/hal/src/ext.c | 46 ++++++++++++++++++++++++++++++++++++ os/hal/templates/ext_lld.c | 24 +++++++++++++++++++ os/hal/templates/ext_lld.h | 2 ++ testhal/STM32F1xx/EXT/main.c | 13 ++++++---- 7 files changed, 154 insertions(+), 14 deletions(-) diff --git a/os/hal/include/ext.h b/os/hal/include/ext.h index 83191b030..5d904cf4e 100644 --- a/os/hal/include/ext.h +++ b/os/hal/include/ext.h @@ -39,12 +39,14 @@ * @name EXT channels modes * @{ */ +#define EXT_CH_MODE_EDGES_MASK 3 /**< @brief Mask of edges field. */ #define EXT_CH_MODE_DISABLED 0 /**< @brief Channel disabled. */ #define EXT_CH_MODE_RISING_EDGE 1 /**< @brief Rising edge callback. */ #define EXT_CH_MODE_FALLING_EDGE 2 /**< @brief Falling edge callback. */ -/** @brief Both edges callback.*/ -#define EXT_CH_MODE_BOTH_EDGES (EXT_CH_MODE_RISING_EDGE | \ - EXT_CH_MODE_FALLING_EDGE) +#define EXT_CH_MODE_BOTH_EDGES 3 /**< @brief Both edges callback. */ + +#define EXT_CH_MODE_AUTOSTART 4 /**< @brief Channel started + automatically on driver start. */ /** @} */ /*===========================================================================*/ @@ -79,6 +81,26 @@ typedef struct EXTDriver EXTDriver; /* Driver macros. */ /*===========================================================================*/ +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @iclass + */ +#define extChannelEnableI(extp, channel) ext_lld_channel_enable(extp, channel) + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @iclass + */ +#define extChannelDisableI(extp, channel) ext_lld_channel_disable(extp, channel) + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ @@ -90,6 +112,8 @@ extern "C" { void extObjectInit(EXTDriver *extp); void extStart(EXTDriver *extp, const EXTConfig *config); void extStop(EXTDriver *extp); + void extChannelEnable(EXTDriver *extp, expchannel_t channel); + void extChannelDisable(EXTDriver *extp, expchannel_t channel); #ifdef __cplusplus } #endif diff --git a/os/hal/platforms/STM32/ext_lld.c b/os/hal/platforms/STM32/ext_lld.c index fc203fa60..712ed5a39 100644 --- a/os/hal/platforms/STM32/ext_lld.c +++ b/os/hal/platforms/STM32/ext_lld.c @@ -328,7 +328,7 @@ void ext_lld_start(EXTDriver *extp) { /* Configuration.*/ imr = emr = rtsr = ftsr = 0; for (i = 0; i < EXT_MAX_CHANNELS; i++) { - if (extp->config->channels[i].mode != EXT_CH_MODE_DISABLED) { + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { if (extp->config->channels[i].cb != NULL) imr |= (1 << i); else @@ -344,11 +344,11 @@ void ext_lld_start(EXTDriver *extp) { AFIO->EXTICR[2] = extp->config->exti[2]; AFIO->EXTICR[3] = extp->config->exti[3]; EXTI->SWIER = 0; - EXTI->RTSR = rtsr; - EXTI->FTSR = ftsr; - EXTI->PR = EXT_CHANNELS_MASK; - EXTI->EMR = emr; - EXTI->IMR = imr; + EXTI->RTSR = rtsr; + EXTI->FTSR = ftsr; + EXTI->PR = EXT_CHANNELS_MASK; + EXTI->EMR = emr; + EXTI->IMR = imr; } /** @@ -385,6 +385,45 @@ void ext_lld_stop(EXTDriver *extp) { EXTI->PR = EXT_CHANNELS_MASK; } +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + if (extp->config->channels[channel].cb != NULL) + EXTI->IMR |= (1 << channel); + else + EXTI->EMR |= (1 << channel); + if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) + EXTI->RTSR |= (1 << channel); + if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) + EXTI->FTSR |= (1 << channel); +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + + EXTI->IMR &= ~(1 << channel); + EXTI->EMR &= ~(1 << channel); + EXTI->RTSR &= ~(1 << channel); + EXTI->FTSR &= ~(1 << channel); + EXTI->PR = (1 << channel); +} + #endif /* HAL_USE_EXT */ /** @} */ diff --git a/os/hal/platforms/STM32/ext_lld.h b/os/hal/platforms/STM32/ext_lld.h index 45e863d9c..17ea09fb8 100644 --- a/os/hal/platforms/STM32/ext_lld.h +++ b/os/hal/platforms/STM32/ext_lld.h @@ -254,6 +254,8 @@ extern "C" { void ext_lld_init(void); void ext_lld_start(EXTDriver *extp); void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); #ifdef __cplusplus } #endif diff --git a/os/hal/src/ext.c b/os/hal/src/ext.c index d68758684..1c83cd2e6 100644 --- a/os/hal/src/ext.c +++ b/os/hal/src/ext.c @@ -78,6 +78,8 @@ void extObjectInit(EXTDriver *extp) { /** * @brief Configures and activates the EXT peripheral. + * @post After activation all EXT channels are in the disabled state, + * use @p extChannelEnable() in order to activate them. * * @param[in] extp pointer to the @p EXTDriver object * @param[in] config pointer to the @p EXTConfig object @@ -116,6 +118,50 @@ void extStop(EXTDriver *extp) { chSysUnlock(); } +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @api + */ +void extChannelEnable(EXTDriver *extp, expchannel_t channel) { + + chDbgCheck((extp != NULL) && + (channel < EXT_MAX_CHANNELS) && + (extp->config->channels[channel].mode != EXT_CH_MODE_DISABLED), + "extChannelEnable"); + + chSysLock(); + chDbgAssert(extp->state == EXT_ACTIVE, + "extChannelEnable(), #1", "invalid state"); + extChannelEnableI(extp, channel); + chSysUnlock(); +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @api + */ +void extChannelDisable(EXTDriver *extp, expchannel_t channel) { + + chDbgCheck((extp != NULL) && + (channel < EXT_MAX_CHANNELS) && + (extp->config->channels[channel].mode != EXT_CH_MODE_DISABLED), + "extChannelDisable"); + + chSysLock(); + chDbgAssert(extp->state == EXT_ACTIVE, + "extChannelDisable(), #1", "invalid state"); + extChannelDisableI(extp, channel); + chSysUnlock(); +} + #endif /* HAL_USE_EXT */ /** @} */ diff --git a/os/hal/templates/ext_lld.c b/os/hal/templates/ext_lld.c index 1aa9477a6..45bc1c3dc 100644 --- a/os/hal/templates/ext_lld.c +++ b/os/hal/templates/ext_lld.c @@ -94,6 +94,30 @@ void ext_lld_stop(EXTDriver *extp) { } } +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + +} + #endif /* HAL_USE_EXT */ /** @} */ diff --git a/os/hal/templates/ext_lld.h b/os/hal/templates/ext_lld.h index eb5a624a4..494cef1b9 100644 --- a/os/hal/templates/ext_lld.h +++ b/os/hal/templates/ext_lld.h @@ -114,6 +114,8 @@ extern "C" { void ext_lld_init(void); void ext_lld_start(EXTDriver *extp); void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); #ifdef __cplusplus } #endif diff --git a/testhal/STM32F1xx/EXT/main.c b/testhal/STM32F1xx/EXT/main.c index a438c3035..fc82a7786 100644 --- a/testhal/STM32F1xx/EXT/main.c +++ b/testhal/STM32F1xx/EXT/main.c @@ -51,7 +51,7 @@ static void extcb2(EXTDriver *extp, expchannel_t channel) { static const EXTConfig extcfg = { { - {EXT_CH_MODE_BOTH_EDGES, extcb1}, + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART, extcb1}, {EXT_CH_MODE_DISABLED, NULL}, {EXT_CH_MODE_DISABLED, NULL}, {EXT_CH_MODE_DISABLED, NULL}, @@ -63,7 +63,7 @@ static const EXTConfig extcfg = { {EXT_CH_MODE_DISABLED, NULL}, {EXT_CH_MODE_DISABLED, NULL}, {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_RISING_EDGE, extcb2}, + {EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART, extcb2}, {EXT_CH_MODE_DISABLED, NULL}, {EXT_CH_MODE_DISABLED, NULL}, {EXT_CH_MODE_DISABLED, NULL}, @@ -107,10 +107,13 @@ int main(void) { extStart(&EXTD1, &extcfg); /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. */ while (TRUE) { - chThdSleepMilliseconds(500); + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); } } -- cgit v1.2.3 From ff435ba9f475e9bb537dd912a71431a779543e24 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 14 Sep 2011 16:53:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3315 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/mac_lld.c | 36 +-- os/hal/platforms/STM32/mac_lld.h | 77 ++++- os/hal/platforms/STM32F1xx/platform.mk | 1 + testhal/STM32F1xx/MAC/.cproject | 211 +++++++++++++ testhal/STM32F1xx/MAC/.project | 85 ++++++ testhal/STM32F1xx/MAC/Makefile | 203 +++++++++++++ testhal/STM32F1xx/MAC/chconf.h | 535 +++++++++++++++++++++++++++++++++ testhal/STM32F1xx/MAC/halconf.h | 328 ++++++++++++++++++++ testhal/STM32F1xx/MAC/main.c | 119 ++++++++ testhal/STM32F1xx/MAC/mcuconf.h | 182 +++++++++++ testhal/STM32F1xx/MAC/readme.txt | 26 ++ 11 files changed, 1784 insertions(+), 19 deletions(-) create mode 100644 testhal/STM32F1xx/MAC/.cproject create mode 100644 testhal/STM32F1xx/MAC/.project create mode 100644 testhal/STM32F1xx/MAC/Makefile create mode 100644 testhal/STM32F1xx/MAC/chconf.h create mode 100644 testhal/STM32F1xx/MAC/halconf.h create mode 100644 testhal/STM32F1xx/MAC/main.c create mode 100644 testhal/STM32F1xx/MAC/mcuconf.h create mode 100644 testhal/STM32F1xx/MAC/readme.txt diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c index 01a28a8b4..1bec4d879 100644 --- a/os/hal/platforms/STM32/mac_lld.c +++ b/os/hal/platforms/STM32/mac_lld.c @@ -49,9 +49,6 @@ #error "STM32_HCLK below minimum frequency for ETH operations (20MHz)" #endif -/* PHY address.*/ -#define MACMIIDR_PA (32 << 11) - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -83,14 +80,14 @@ static uint32_t tb[MAC_TRANSMIT_BUFFERS * BUFFER_SLICE]; * * @param[in] reg register number * @param[in] value new register value + * + * @notapi */ -static void mii_write_phy(uint16_t reg, uint16_t value) { - uint32_t miiar; +void _stm32_eth_write_phy(uint32_t reg, uint32_t value) { - miiar = ETH->MACMIIAR | ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; - miiar = (miiar & ~ETH_MACMIIAR_MR) | (reg << 6); ETH->MACMIIDR = value; - ETH->MACMIIAR = miiar; + ETH->MACMIIAR = BOARD_PHY_ADDR | (reg << 6) | MACMIIDR_CR | + ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) ; } @@ -99,21 +96,23 @@ static void mii_write_phy(uint16_t reg, uint16_t value) { * @brief Reads a PHY register. * * @param[in] reg register number + * + * @notapi */ -static uint16_t mii_read_phy(uint16_t reg) { - uint32_t miiar; +static uint32_t _stm32_eth_read_phy(uint32_t reg) { - miiar = ETH->MACMIIAR | ETH_MACMIIAR_MB; - miiar = (miiar & ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_MW)) | (reg << 6); - ETH->MACMIIAR = miiar; + ETH->MACMIIAR = BOARD_PHY_ADDR | (reg << 6) | MACMIIDR_CR | + ETH_MACMIIAR_MB; while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) ; - return (uint16_t)ETH->MACMIIDR; + return ETH->MACMIIDR; } + /** * @brief MII/RMII interface initialization. */ +#if 0 static void mii_init(void) { uint32_t i; @@ -126,6 +125,7 @@ static void mii_init(void) { /* Wrong or defective board.*/ chSysHalt(); } +#endif /*===========================================================================*/ /* Driver interrupt handlers. */ @@ -148,7 +148,7 @@ void mac_lld_init(void) { /* Descriptor tables are initialized in linked mode, note that the first word is not initialized here but in mac_lld_start().*/ for (i = 0; i < MAC_RECEIVE_BUFFERS; i++) { - rd[i].rdes1 = RDES1_RCH | MAC_BUFFERS_SIZE; + rd[i].rdes1 = STM32_RDES1_RCH | MAC_BUFFERS_SIZE; rd[i].rdes2 = (uint32_t)&rb[i * BUFFER_SLICE]; rd[i].rdes3 = (uint32_t)&rb[((i + 1) % MAC_RECEIVE_BUFFERS) * BUFFER_SLICE]; @@ -173,10 +173,10 @@ void mac_lld_start(MACDriver *macp) { /* Resets the state of all descriptors.*/ for (i = 0; i < MAC_RECEIVE_BUFFERS; i++) - rd[i].rdes0 = RDES0_OWN; + rd[i].rdes0 = STM32_RDES0_OWN; rxptr = (stm32_eth_rx_descriptor_t *)rd; for (i = 0; i < MAC_TRANSMIT_BUFFERS; i++) - td[i].tdes0 = TDES0_TCH; + td[i].tdes0 = STM32_TDES0_TCH; txptr = (stm32_eth_tx_descriptor_t *)td; /* Soft reset of the MAC core and wait until the reset is complete.*/ @@ -185,7 +185,7 @@ void mac_lld_start(MACDriver *macp) { ; /* MII initialization.*/ - mii_init(); +// mii_init(); /* Descriptor chains pointers.*/ ETH->DMARDLAR = (uint32_t)rd; diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h index 8647bd296..f21f4c129 100644 --- a/os/hal/platforms/STM32/mac_lld.h +++ b/os/hal/platforms/STM32/mac_lld.h @@ -1,6 +1,6 @@ /* ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. + 2011 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -35,6 +35,81 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @name RDES0 constants + * @{ + */ +#define STM32_RDES0_OWN 0x80000000 +#define STM32_RDES0_AFM 0x40000000 +#define STM32_RDES0_FL_MASK 0x3FFF0000 +#define STM32_RDES0_ES 0x00008000 +#define STM32_RDES0_DESERR 0x00004000 +#define STM32_RDES0_SAF 0x00002000 +#define STM32_RDES0_LE 0x00001000 +#define STM32_RDES0_OE 0x00000800 +#define STM32_RDES0_VLAN 0x00000400 +#define STM32_RDES0_FS 0x00000200 +#define STM32_RDES0_LS 0x00000100 +#define STM32_RDES0_IPHCE 0x00000080 +#define STM32_RDES0_LCO 0x00000040 +#define STM32_RDES0_FT 0x00000020 +#define STM32_RDES0_RWT 0x00000010 +#define STM32_RDES0_RE 0x00000008 +#define STM32_RDES0_DE 0x00000004 +#define STM32_RDES0_CE 0x00000002 +#define STM32_RDES0_PCE 0x00000001 +/** @} */ + +/** + * @name RDES1 constants + * @{ + */ +#define STM32_RDES1_DIC 0x80000000 +#define STM32_RDES1_RBS2_MASK 0x1FFF0000 +#define STM32_RDES1_RER 0x00008000 +#define STM32_RDES1_RCH 0x00004000 +#define STM32_RDES1_RBS1_MASK 0x00001FFF +/** @} */ + +/** + * @name TDES0 constants + * @{ + */ +#define STM32_TDES0_OWN 0x80000000 +#define STM32_TDES0_IC 0x40000000 +#define STM32_TDES0_LS 0x20000000 +#define STM32_TDES0_FS 0x10000000 +#define STM32_TDES0_DC 0x08000000 +#define STM32_TDES0_DP 0x04000000 +#define STM32_TDES0_TTSE 0x02000000 +#define STM32_TDES0_CIC_MASK 0x00C00000 +#define STM32_TDES0_TER 0x00200000 +#define STM32_TDES0_TCH 0x00100000 +#define STM32_TDES0_TTSS 0x00020000 +#define STM32_TDES0_IHE 0x00010000 +#define STM32_TDES0_ES 0x00008000 +#define STM32_TDES0_JT 0x00004000 +#define STM32_TDES0_FF 0x00002000 +#define STM32_TDES0_IPE 0x00001000 +#define STM32_TDES0_LCA 0x00000800 +#define STM32_TDES0_NC 0x00000400 +#define STM32_TDES0_LCO 0x00000200 +#define STM32_TDES0_EC 0x00000100 +#define STM32_TDES0_VF 0x00000080 +#define STM32_TDES0_CC_MASK 0x00000078 +#define STM32_TDES0_ED 0x00000004 +#define STM32_TDES0_UF 0x00000002 +#define STM32_TDES0_DB 0x00000001 +/** @} */ + +/** + * @name TDES1 constants + * @{ + */ +#define STM32_TDES1_TBS2_MASK 0x1FFF0000 +#define STM32_TDES1_TBS1_MASK 0x00001FFF +/** @} */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk index 89179f65f..1a8c42bc7 100644 --- a/os/hal/platforms/STM32F1xx/platform.mk +++ b/os/hal/platforms/STM32F1xx/platform.mk @@ -6,6 +6,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ diff --git a/testhal/STM32F1xx/MAC/.cproject b/testhal/STM32F1xx/MAC/.cproject new file mode 100644 index 000000000..baff32962 --- /dev/null +++ b/testhal/STM32F1xx/MAC/.cproject @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F1xx/MAC/.project b/testhal/STM32F1xx/MAC/.project new file mode 100644 index 000000000..a1d329f97 --- /dev/null +++ b/testhal/STM32F1xx/MAC/.project @@ -0,0 +1,85 @@ + + + TEST-STM32-MAC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + C:/Projects/ChibiOS-RT/os + + + diff --git a/testhal/STM32F1xx/MAC/Makefile b/testhal/STM32F1xx/MAC/Makefile new file mode 100644 index 000000000..7712f2057 --- /dev/null +++ b/testhal/STM32F1xx/MAC/Makefile @@ -0,0 +1,203 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P107/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/MAC/chconf.h b/testhal/STM32F1xx/MAC/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F1xx/MAC/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/MAC/halconf.h b/testhal/STM32F1xx/MAC/halconf.h new file mode 100644 index 000000000..0b8b13660 --- /dev/null +++ b/testhal/STM32F1xx/MAC/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/MAC/main.c b/testhal/STM32F1xx/MAC/main.c new file mode 100644 index 000000000..fc82a7786 --- /dev/null +++ b/testhal/STM32F1xx/MAC/main.c @@ -0,0 +1,119 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt; + +/* LED set to OFF after 200mS.*/ +static void ledoff(void *arg) { + + (void)arg; + palSetPad(GPIOC, GPIOC_LED); +} + +/* Triggered when the button is pressed or released. The LED is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + (void)channel; + palClearPad(GPIOC, GPIOC_LED); + chSysLockFromIsr(); + if (!chVTIsArmedI(&vt)) + chVTSetI(&vt, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* Triggered when the LED goes OFF.*/ +static void extcb2(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + (void)channel; +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART, extcb2}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + }, + EXT_MODE_EXTI(EXT_MODE_GPIOA, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + EXT_MODE_GPIOC, + 0, + 0, + 0) +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); + } +} diff --git a/testhal/STM32F1xx/MAC/mcuconf.h b/testhal/STM32F1xx/MAC/mcuconf.h new file mode 100644 index 000000000..8516c02a1 --- /dev/null +++ b/testhal/STM32F1xx/MAC/mcuconf.h @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_ACTIVATE_PLL1 TRUE +#define STM32_ACTIVATE_PLL2 TRUE +#define STM32_ACTIVATE_PLL3 TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 +#define STM32_PREDIV1_VALUE 5 +#define STM32_PLLMUL_VALUE 9 +#define STM32_PREDIV2_VALUE 5 +#define STM32_PLL2MUL_VALUE 8 +#define STM32_PLL3MUL_VALUE 10 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3 +#define STM32_MCO STM32_MCO_PLL3 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F1xx/MAC/readme.txt b/testhal/STM32F1xx/MAC/readme.txt new file mode 100644 index 000000000..5c40b1c3f --- /dev/null +++ b/testhal/STM32F1xx/MAC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - MAC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P107 board. + +** The Demo ** + +The application demonstrates the use of the STM32 MAC driver. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From 0bc5166a21ee2ff41c1b1ae8cc2d543a542cf2c3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 14 Sep 2011 17:44:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3316 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/MAC/.cproject | 211 ---------------------------------------- testhal/STM32F1xx/MAC/.project | 85 ---------------- 2 files changed, 296 deletions(-) delete mode 100644 testhal/STM32F1xx/MAC/.cproject delete mode 100644 testhal/STM32F1xx/MAC/.project diff --git a/testhal/STM32F1xx/MAC/.cproject b/testhal/STM32F1xx/MAC/.cproject deleted file mode 100644 index baff32962..000000000 --- a/testhal/STM32F1xx/MAC/.cproject +++ /dev/null @@ -1,211 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/testhal/STM32F1xx/MAC/.project b/testhal/STM32F1xx/MAC/.project deleted file mode 100644 index a1d329f97..000000000 --- a/testhal/STM32F1xx/MAC/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - TEST-STM32-MAC - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - mingw32-make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - false - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - C:/Projects/ChibiOS-RT/os - - - -- cgit v1.2.3 From 061a1d4844a0eeffca59ae09b2799cc8ff24e05b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 14 Sep 2011 18:35:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3317 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/DMAv1/sdc_lld.c | 730 -------------------------------- os/hal/platforms/STM32/DMAv1/sdc_lld.h | 203 --------- os/hal/platforms/STM32/DMAv1/spi_lld.c | 445 ------------------- os/hal/platforms/STM32/DMAv1/spi_lld.h | 285 ------------- os/hal/platforms/STM32/DMAv1/uart_lld.c | 557 ------------------------ os/hal/platforms/STM32/DMAv1/uart_lld.h | 318 -------------- os/hal/platforms/STM32/sdc_lld.c | 730 ++++++++++++++++++++++++++++++++ os/hal/platforms/STM32/sdc_lld.h | 203 +++++++++ os/hal/platforms/STM32/spi_lld.c | 445 +++++++++++++++++++ os/hal/platforms/STM32/spi_lld.h | 285 +++++++++++++ os/hal/platforms/STM32/uart_lld.c | 557 ++++++++++++++++++++++++ os/hal/platforms/STM32/uart_lld.h | 318 ++++++++++++++ 12 files changed, 2538 insertions(+), 2538 deletions(-) delete mode 100644 os/hal/platforms/STM32/DMAv1/sdc_lld.c delete mode 100644 os/hal/platforms/STM32/DMAv1/sdc_lld.h delete mode 100644 os/hal/platforms/STM32/DMAv1/spi_lld.c delete mode 100644 os/hal/platforms/STM32/DMAv1/spi_lld.h delete mode 100644 os/hal/platforms/STM32/DMAv1/uart_lld.c delete mode 100644 os/hal/platforms/STM32/DMAv1/uart_lld.h create mode 100644 os/hal/platforms/STM32/sdc_lld.c create mode 100644 os/hal/platforms/STM32/sdc_lld.h create mode 100644 os/hal/platforms/STM32/spi_lld.c create mode 100644 os/hal/platforms/STM32/spi_lld.h create mode 100644 os/hal/platforms/STM32/uart_lld.c create mode 100644 os/hal/platforms/STM32/uart_lld.h diff --git a/os/hal/platforms/STM32/DMAv1/sdc_lld.c b/os/hal/platforms/STM32/DMAv1/sdc_lld.c deleted file mode 100644 index b9e02a815..000000000 --- a/os/hal/platforms/STM32/DMAv1/sdc_lld.c +++ /dev/null @@ -1,730 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/sdc_lld.c - * @brief STM32 SDC subsystem low level driver source. - * - * @addtogroup SDC - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SDCD1 driver identifier.*/ -SDCDriver SDCD1; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -#if STM32_SDC_UNALIGNED_SUPPORT -/** - * @brief Buffer for temporary storage during unaligned transfers. - */ -static union { - uint32_t alignment; - uint8_t buf[SDC_BLOCK_SIZE]; -} u; -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer, it must be aligned to - * four bytes boundary - * @param[in] n number of blocks to read - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * read. - * @retval TRUE operation failed, the state of the buffer is uncertain. - * - * @notapi - */ -static bool_t sdc_lld_read_multiple(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n) { - uint32_t resp[1]; - - /* Checks for errors and waits for the card to be ready for reading.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return TRUE; - - /* Prepares the DMA channel for reading.*/ - dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); - dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, - (n * SDC_BLOCK_SIZE) / sizeof (uint32_t)); - dmaStreamSetMode(STM32_DMA2_STREAM4, - STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_PSIZE_WORD | - STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); - - /* Setting up data transfer. - Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; - SDIO->DLEN = n * SDC_BLOCK_SIZE; - SDIO->DCTRL = SDIO_DCTRL_DTDIR | - SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - /* DMA channel activation.*/ - dmaStreamEnable(STM32_DMA2_STREAM4); - - /* Read multiple blocks command.*/ - if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) - startblk *= SDC_BLOCK_SIZE; - if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_MULTIPLE_BLOCK, - startblk, resp) || - SDC_R1_ERROR(resp[0])) - goto error; - - chSysLock(); - if (SDIO->MASK != 0) { - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_read_multiple(), #1", "not NULL"); - sdcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_read_multiple(), #2", "not NULL"); - } - if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { - chSysUnlock(); - goto error; - } - dmaStreamDisable(STM32_DMA2_STREAM4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->DCTRL = 0; - chSysUnlock(); - - return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); -error: - dmaStreamDisable(STM32_DMA2_STREAM4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = 0; - SDIO->DCTRL = 0; - return TRUE; -} - -/** - * @brief Reads one block. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer, it must be aligned to - * four bytes boundary - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * read. - * @retval TRUE operation failed, the state of the buffer is uncertain. - * - * @notapi - */ -static bool_t sdc_lld_read_single(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf) { - uint32_t resp[1]; - - /* Checks for errors and waits for the card to be ready for reading.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return TRUE; - - /* Prepares the DMA channel for reading.*/ - dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); - dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, - SDC_BLOCK_SIZE / sizeof (uint32_t)); - dmaStreamSetMode(STM32_DMA2_STREAM4, - STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_PSIZE_WORD | - STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); - - /* Setting up data transfer. - Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; - SDIO->DLEN = SDC_BLOCK_SIZE; - SDIO->DCTRL = SDIO_DCTRL_DTDIR | - SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - /* DMA channel activation.*/ - dmaStreamEnable(STM32_DMA2_STREAM4); - - /* Read single block command.*/ - if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) - startblk *= SDC_BLOCK_SIZE; - if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_SINGLE_BLOCK, - startblk, resp) || - SDC_R1_ERROR(resp[0])) - goto error; - - chSysLock(); - if (SDIO->MASK != 0) { - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_read_single(), #1", "not NULL"); - sdcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_read_single(), #2", "not NULL"); - } - if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { - chSysUnlock(); - goto error; - } - dmaStreamDisable(STM32_DMA2_STREAM4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->DCTRL = 0; - chSysUnlock(); - - return FALSE; -error: - dmaStreamDisable(STM32_DMA2_STREAM4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = 0; - SDIO->DCTRL = 0; - return TRUE; -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer, it must be aligned to - * four bytes boundary - * @param[in] n number of blocks to write - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * written. - * @retval TRUE operation failed. - * - * @notapi - */ -static bool_t sdc_lld_write_multiple(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n) { - uint32_t resp[1]; - - /* Checks for errors and waits for the card to be ready for writing.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return TRUE; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); - dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, - (n * SDC_BLOCK_SIZE) / sizeof (uint32_t)); - dmaStreamSetMode(STM32_DMA2_STREAM4, - STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_WORD | - STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); - - /* Write multiple blocks command.*/ - if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) - startblk *= SDC_BLOCK_SIZE; - if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_MULTIPLE_BLOCK, - startblk, resp) || - SDC_R1_ERROR(resp[0])) - return TRUE; - - /* Setting up data transfer. - Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | - SDIO_MASK_STBITERRIE; - SDIO->DLEN = n * SDC_BLOCK_SIZE; - SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - /* DMA channel activation.*/ - dmaStreamEnable(STM32_DMA2_STREAM4); - - /* Note the mask is checked before going to sleep because the interrupt - may have occurred before reaching the critical zone.*/ - chSysLock(); - if (SDIO->MASK != 0) { - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_write_multiple(), #1", "not NULL"); - sdcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_write_multiple(), #2", "not NULL"); - } - if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { - chSysUnlock(); - goto error; - } - dmaStreamDisable(STM32_DMA2_STREAM4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->DCTRL = 0; - chSysUnlock(); - - return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); -error: - dmaStreamDisable(STM32_DMA2_STREAM4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = 0; - SDIO->DCTRL = 0; - return TRUE; -} - -/** - * @brief Writes one block. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer, it must be aligned to - * four bytes boundary - * @param[in] n number of blocks to write - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * written. - * @retval TRUE operation failed. - * - * @notapi - */ -static bool_t sdc_lld_write_single(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf) { - uint32_t resp[1]; - - /* Checks for errors and waits for the card to be ready for writing.*/ - if (_sdc_wait_for_transfer_state(sdcp)) - return TRUE; - - /* Prepares the DMA channel for writing.*/ - dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); - dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, - SDC_BLOCK_SIZE / sizeof (uint32_t)); - dmaStreamSetMode(STM32_DMA2_STREAM4, - STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | - STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_WORD | - STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); - - /* Write single block command.*/ - if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) - startblk *= SDC_BLOCK_SIZE; - if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_BLOCK, - startblk, resp) || - SDC_R1_ERROR(resp[0])) - return TRUE; - - /* Setting up data transfer. - Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | - SDIO_MASK_STBITERRIE; - SDIO->DLEN = SDC_BLOCK_SIZE; - SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - /* DMA channel activation.*/ - dmaStreamEnable(STM32_DMA2_STREAM4); - - /* Note the mask is checked before going to sleep because the interrupt - may have occurred before reaching the critical zone.*/ - chSysLock(); - if (SDIO->MASK != 0) { - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_write_single(), #1", "not NULL"); - sdcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_write_single(), #2", "not NULL"); - } - if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { - chSysUnlock(); - goto error; - } - dmaStreamDisable(STM32_DMA2_STREAM4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->DCTRL = 0; - chSysUnlock(); - - return FALSE; -error: - dmaStreamDisable(STM32_DMA2_STREAM4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = 0; - SDIO->DCTRL = 0; - return TRUE; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief SDIO IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(SDIO_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - if (SDCD1.thread != NULL) { - chSchReadyI(SDCD1.thread); - SDCD1.thread = NULL; - } - chSysUnlockFromIsr(); - - /* Disables the source but the status flags are not reset because the - read/write functions need to check them.*/ - SDIO->MASK = 0; - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SDC driver initialization. - * - * @notapi - */ -void sdc_lld_init(void) { - - sdcObjectInit(&SDCD1); - SDCD1.thread = NULL; -} - -/** - * @brief Configures and activates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object, must be @p NULL, - * this driver does not require any configuration - * - * @notapi - */ -void sdc_lld_start(SDCDriver *sdcp) { - - if (sdcp->state == SDC_STOP) { - /* Note, the DMA must be enabled before the IRQs.*/ - dmaStreamAllocate(STM32_DMA2_STREAM4, 0, NULL, NULL); - dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO); - NVICEnableVector(SDIO_IRQn, - CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); - RCC->AHBENR |= RCC_AHBENR_SDIOEN; - } - /* Configuration, card clock is initially stopped.*/ - SDIO->POWER = 0; - SDIO->CLKCR = 0; - SDIO->DCTRL = 0; - SDIO->DTIMER = STM32_SDC_DATATIMEOUT; -} - -/** - * @brief Deactivates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop(SDCDriver *sdcp) { - - if ((sdcp->state == SDC_READY) || (sdcp->state == SDC_ACTIVE)) { - SDIO->POWER = 0; - SDIO->CLKCR = 0; - SDIO->DCTRL = 0; - SDIO->DTIMER = 0; - - /* Clock deactivation.*/ - NVICDisableVector(SDIO_IRQn); - dmaStreamRelease(STM32_DMA2_STREAM4); - } -} - -/** - * @brief Starts the SDIO clock and sets it to init mode (400KHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start_clk(SDCDriver *sdcp) { - - (void)sdcp; - /* Initial clock setting: 400KHz, 1bit mode.*/ - SDIO->CLKCR = STM32_SDIO_DIV_LS; - SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1; - SDIO->CLKCR |= SDIO_CLKCR_CLKEN; -} - -/** - * @brief Sets the SDIO clock to data mode (25MHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_set_data_clk(SDCDriver *sdcp) { - - (void)sdcp; - SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS; -} - -/** - * @brief Stops the SDIO clock. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop_clk(SDCDriver *sdcp) { - - (void)sdcp; - SDIO->CLKCR = 0; - SDIO->POWER = 0; -} - -/** - * @brief Switches the bus to 4 bits mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] mode bus mode - * - * @notapi - */ -void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { - uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS; - - (void)sdcp; - switch (mode) { - case SDC_MODE_1BIT: - SDIO->CLKCR = clk; - break; - case SDC_MODE_4BIT: - SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0; - break; - case SDC_MODE_8BIT: - SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1; - } -} - -/** - * @brief Sends an SDIO command with no response expected. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * - * @notapi - */ -void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { - - (void)sdcp; - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN; - while ((SDIO->STA & SDIO_STA_CMDSENT) == 0) - ; - SDIO->ICR = SDIO_ICR_CMDSENTC; -} - -/** - * @brief Sends an SDIO command with a short response expected. - * @note The CRC is not verified. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * @return The operation status. - * @retval FALSE the operation succeeded. - * @retval TRUE the operation failed because timeout, CRC check or - * other errors. - * - * @notapi - */ -bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - (void)sdcp; - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; - while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; - if ((sta & (SDIO_STA_CTIMEOUT)) != 0) - return TRUE; - *resp = SDIO->RESP1; - return FALSE; -} - -/** - * @brief Sends an SDIO command with a short response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * @return The operation status. - * @retval FALSE the operation succeeded. - * @retval TRUE the operation failed because timeout, CRC check or - * other errors. - * - * @notapi - */ -bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - (void)sdcp; - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; - while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; - if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) - return TRUE; - *resp = SDIO->RESP1; - return FALSE; -} - -/** - * @brief Sends an SDIO command with a long response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (four words) - * @return The operation status. - * @retval FALSE the operation succeeded. - * @retval TRUE the operation failed because timeout, CRC check or - * other errors. - * - * @notapi - */ -bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - - uint32_t sta; - - (void)sdcp; - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 | - SDIO_CMD_CPSMEN; - while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; - if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) - return TRUE; - *resp = SDIO->RESP1; - return FALSE; -} - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] n number of blocks to read - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * read. - * @retval TRUE operation failed, the state of the buffer is uncertain. - * - * @notapi - */ -bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n) { - -#if STM32_SDC_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < n; i++) { - if (sdc_lld_read_single(sdcp, startblk, u.buf)) - return TRUE; - memcpy(buf, u.buf, SDC_BLOCK_SIZE); - buf += SDC_BLOCK_SIZE; - startblk++; - } - return FALSE; - } -#endif - if (n == 1) - return sdc_lld_read_single(sdcp, startblk, buf); - return sdc_lld_read_multiple(sdcp, startblk, buf, n); -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * written. - * @retval TRUE operation failed. - * - * @notapi - */ -bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n) { - - #if STM32_SDC_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < n; i++) { - memcpy(u.buf, buf, SDC_BLOCK_SIZE); - buf += SDC_BLOCK_SIZE; - if (sdc_lld_write_single(sdcp, startblk, u.buf)) - return TRUE; - startblk++; - } - return FALSE; - } -#endif - if (n == 1) - return sdc_lld_write_single(sdcp, startblk, buf); - return sdc_lld_write_multiple(sdcp, startblk, buf, n); -} - -#endif /* HAL_USE_SDC */ - -/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/sdc_lld.h b/os/hal/platforms/STM32/DMAv1/sdc_lld.h deleted file mode 100644 index eea76dadd..000000000 --- a/os/hal/platforms/STM32/DMAv1/sdc_lld.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/sdc_lld.h - * @brief STM32 SDC subsystem low level driver header. - * - * @addtogroup SDC - * @{ - */ - -#ifndef _SDC_LLD_H_ -#define _SDC_LLD_H_ - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief SDIO data timeout in SDIO clock cycles. - */ -#if !defined(STM32_SDC_DATATIMEOUT) || defined(__DOXYGEN__) -#define STM32_SDC_DATATIMEOUT 0x000FFFFF -#endif - -/** - * @brief SDIO DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#endif - -/** - * @brief SDIO interrupt priority level setting. - */ -#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#endif - -/** - * @brief SDIO support for unaligned transfers. - */ -#if !defined(STM32_SDC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) -#define STM32_SDC_UNALIGNED_SUPPORT TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_HAS_SDIO -#error "SDIO not present in the selected device" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/* - * SDIO clock divider. - */ -#if STM32_HCLK > 48000000 -#define STM32_SDIO_DIV_HS 0x01 -#define STM32_SDIO_DIV_LS 0xB2 -#else -#define STM32_SDIO_DIV_HS 0x00 -#define STM32_SDIO_DIV_LS 0x76 -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of SDIO bus mode. - */ -typedef enum { - SDC_MODE_1BIT = 0, - SDC_MODE_4BIT, - SDC_MODE_8BIT -} sdcbusmode_t; - -/** - * @brief Type of card flags. - */ -typedef uint32_t sdcmode_t; - -/** - * @brief Type of a structure representing an SDC driver. - */ -typedef struct SDCDriver SDCDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} SDCConfig; - -/** - * @brief Structure representing an SDC driver. - */ -struct SDCDriver { - /** - * @brief Driver state. - */ - sdcstate_t state; - /** - * @brief Current configuration data. - */ - const SDCConfig *config; - /** - * @brief Various flags regarding the mounted card. - */ - sdcmode_t cardmode; - /** - * @brief Card CID. - */ - uint32_t cid[4]; - /** - * @brief Card CSD. - */ - uint32_t csd[4]; - /** - * @brief Card RCA. - */ - uint32_t rca; - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion IRQ. - */ - Thread *thread; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern SDCDriver SDCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sdc_lld_init(void); - void sdc_lld_start(SDCDriver *sdcp); - void sdc_lld_stop(SDCDriver *sdcp); - void sdc_lld_start_clk(SDCDriver *sdcp); - void sdc_lld_set_data_clk(SDCDriver *sdcp); - void sdc_lld_stop_clk(SDCDriver *sdcp); - void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); - void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); - bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n); - bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n); - bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp); - bool_t sdc_lld_is_write_protected(SDCDriver *sdcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SDC */ - -#endif /* _SDC_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/spi_lld.c b/os/hal/platforms/STM32/DMAv1/spi_lld.c deleted file mode 100644 index 9302b0102..000000000 --- a/os/hal/platforms/STM32/DMAv1/spi_lld.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/spi_lld.c - * @brief STM32 SPI subsystem low level driver source. - * - * @addtogroup SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SPI1 driver identifier.*/ -#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** @brief SPI2 driver identifier.*/ -#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/** @brief SPI3 driver identifier.*/ -#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) -SPIDriver SPID3; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -static uint16_t dummytx; -static uint16_t dummyrx; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Stops the SPI DMA channels. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -#define dma_stop(spip) { \ - dmaStreamDisable(spip->dmatx); \ - dmaStreamDisable(spip->dmarx); \ -} - -/** - * @brief Starts the SPI DMA channels. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -#define dma_start(spip) { \ - dmaChannelEnable((spip)->dmarx); \ - dmaChannelEnable((spip)->dmatx); \ -} - -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - if ((flags & STM32_DMA_ISR_TEIF) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)flags; -#endif - - /* Stop everything.*/ - dma_stop(spip); - - /* Portable SPI ISR code defined in the high level driver, note, it is - a macro.*/ - _spi_isr_code(spip); -} - -/** - * @brief Shared end-of-tx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - (void)spip; - if ((flags & STM32_DMA_ISR_TEIF) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)spip; - (void)flags; -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) { - - dummytx = 0xFFFF; - -#if STM32_SPI_USE_SPI1 - spiObjectInit(&SPID1); - SPID1.thread = NULL; - SPID1.spi = SPI1; - SPID1.dmarx = STM32_DMA1_STREAM2; - SPID1.dmatx = STM32_DMA1_STREAM3; -#endif - -#if STM32_SPI_USE_SPI2 - spiObjectInit(&SPID2); - SPID2.thread = NULL; - SPID2.spi = SPI2; - SPID2.dmarx = STM32_DMA1_STREAM4; - SPID2.dmatx = STM32_DMA1_STREAM5; -#endif - -#if STM32_SPI_USE_SPI3 - spiObjectInit(&SPID3); - SPID3.thread = NULL; - SPID3.spi = SPI3; - SPID3.dmarx = STM32_DMA2_STREAM1; - SPID3.dmatx = STM32_DMA2_STREAM2; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) { - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (spip->state == SPI_STOP) { -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) { - bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM2, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM3, - STM32_SPI_SPI1_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; - } -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM4, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM5, - STM32_SPI_SPI2_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); - RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; - } -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM1, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM2, - STM32_SPI_SPI3_IRQ_PRIORITY, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, - (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); - RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; - } -#endif - - /* DMA setup.*/ - dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); - dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); - } - - /* More DMA setup.*/ - if ((spip->config->cr1 & SPI_CR1_DFF) == 0) - spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MSIZE_BYTE; /* 8 bits transfers. */ - else - spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD; /* 16 bits transfers. */ - - /* SPI setup and enable.*/ - spip->spi->CR1 = 0; - spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | - SPI_CR1_SSI; - spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; - spip->spi->CR1 |= SPI_CR1_SPE; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) { - - /* If in ready state then disables the SPI clock.*/ - if (spip->state == SPI_READY) { - - /* SPI disable.*/ - spip->spi->CR1 = 0; - -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) { - dmaStreamRelease(STM32_DMA1_STREAM2); - dmaStreamRelease(STM32_DMA1_STREAM3); - RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN; - } -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - dmaStreamRelease(STM32_DMA1_STREAM4); - dmaStreamRelease(STM32_DMA1_STREAM5); - RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN; - } -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - dmaStreamRelease(STM32_DMA1_STREAM1); - dmaStreamRelease(STM32_DMA1_STREAM2); - RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN; - } -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) { - - palClearPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) { - - palSetPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | STM32_DMA_CR_EN); - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_EN); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | - STM32_DMA_CR_EN); - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_EN); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - dmaStreamSetMemory0(spip->dmarx, &dummyrx); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | STM32_DMA_CR_EN); - dmaStreamSetMemory0(spip->dmatx, txbuf); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_EN); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - dmaStreamSetMemory0(spip->dmarx, rxbuf); - dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | - STM32_DMA_CR_EN); - dmaStreamSetMemory0(spip->dmatx, &dummytx); - dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_EN); -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - - spip->spi->DR = frame; - while ((spip->spi->SR & SPI_SR_RXNE) == 0) - ; - return spip->spi->DR; -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/spi_lld.h b/os/hal/platforms/STM32/DMAv1/spi_lld.h deleted file mode 100644 index c8c1e0661..000000000 --- a/os/hal/platforms/STM32/DMAv1/spi_lld.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/spi_lld.h - * @brief STM32 SPI subsystem low level driver header. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for SPI1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI1 TRUE -#endif - -/** - * @brief SPI2 driver enable switch. - * @details If set to @p TRUE the support for SPI2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI2 TRUE -#endif - -/** - * @brief SPI3 driver enable switch. - * @details If set to @p TRUE the support for SPI3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI3 FALSE -#endif - -/** - * @brief SPI1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI2 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI3 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 -#error "SPI1 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 -#error "SPI driver activated but no SPI peripheral assigned" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SPI initialization data. - */ - uint16_t cr1; -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -struct SPIDriver{ - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - Thread *thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spi; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) -extern SPIDriver SPID3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/uart_lld.c b/os/hal/platforms/STM32/DMAv1/uart_lld.c deleted file mode 100644 index a9303744d..000000000 --- a/os/hal/platforms/STM32/DMAv1/uart_lld.c +++ /dev/null @@ -1,557 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/uart_lld.c - * @brief STM32 low level UART driver code. - * - * @addtogroup UART - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 UART driver identifier.*/ -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -UARTDriver UARTD1; -#endif - -/** @brief USART2 UART driver identifier.*/ -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -UARTDriver UARTD2; -#endif - -/** @brief USART3 UART driver identifier.*/ -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -UARTDriver UARTD3; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Status bits translation. - * - * @param[in] sr USART SR register value - * - * @return The error flags. - */ -static uartflags_t translate_errors(uint16_t sr) { - uartflags_t sts = 0; - - if (sr & USART_SR_ORE) - sts |= UART_OVERRUN_ERROR; - if (sr & USART_SR_PE) - sts |= UART_PARITY_ERROR; - if (sr & USART_SR_FE) - sts |= UART_FRAMING_ERROR; - if (sr & USART_SR_NE) - sts |= UART_NOISE_ERROR; - if (sr & USART_SR_LBD) - sts |= UART_BREAK_DETECTED; - return sts; -} - -/** - * @brief Puts the receiver in the UART_RX_IDLE state. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void set_rx_idle_loop(UARTDriver *uartp) { - uint32_t mode; - - /* RX DMA channel preparation, if the char callback is defined then the - TCIE interrupt is enabled too.*/ - if (uartp->config->rxchar_cb == NULL) - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TEIE; - else - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE; - dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, 1); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_stop(UARTDriver *uartp) { - - /* Stops RX and TX DMA channels.*/ - dmaStreamDisable(uartp->dmarx); - dmaStreamClearInterrupt(uartp->dmarx); - dmaStreamDisable(uartp->dmatx); - dmaStreamClearInterrupt(uartp->dmatx); - - /* Stops USART operations.*/ - uartp->usart->CR1 = 0; - uartp->usart->CR2 = 0; - uartp->usart->CR3 = 0; -} - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_start(UARTDriver *uartp) { - uint16_t cr1; - USART_TypeDef *u = uartp->usart; - - /* Defensive programming, starting from a clean state.*/ - usart_stop(uartp); - - /* Baud rate setting.*/ - if (uartp->usart == USART1) - u->BRR = STM32_PCLK2 / uartp->config->speed; - else - u->BRR = STM32_PCLK1 / uartp->config->speed; - - /* Resetting eventual pending status flags.*/ - (void)u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ - u->SR = 0; - - /* Note that some bits are enforced because required for correct driver - operations.*/ - if (uartp->config->txend2_cb == NULL) - cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; - else - cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE | - USART_CR1_TCIE; - u->CR1 = uartp->config->cr1 | cr1; - u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; - u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | - USART_CR3_EIE; - - /* Starting the receiver idle loop.*/ - set_rx_idle_loop(uartp); -} - -/** - * @brief RX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & STM32_DMA_ISR_TEIF) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - if (uartp->rxstate == UART_RX_IDLE) { - /* Receiver in idle state, a callback is generated, if enabled, for each - received character and then the driver stays in the same state.*/ - if (uartp->config->rxchar_cb != NULL) - uartp->config->rxchar_cb(uartp, uartp->rxbuf); - } - else { - /* Receiver in active state, a callback is generated, if enabled, after - a completed transfer.*/ - dmaStreamDisable(uartp->dmarx); - uartp->rxstate = UART_RX_COMPLETE; - if (uartp->config->rxend_cb != NULL) - uartp->config->rxend_cb(uartp); - /* If the callback didn't explicitly change state then the receiver - automatically returns to the idle state.*/ - if (uartp->rxstate == UART_RX_COMPLETE) { - uartp->rxstate = UART_RX_IDLE; - set_rx_idle_loop(uartp); - } - } -} - -/** - * @brief TX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & STM32_DMA_ISR_TEIF) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - dmaStreamDisable(uartp->dmatx); - /* A callback is generated, if enabled, after a completed transfer.*/ - uartp->txstate = UART_TX_COMPLETE; - if (uartp->config->txend1_cb != NULL) - uartp->config->txend1_cb(uartp); - /* If the callback didn't explicitly change state then the transmitter - automatically returns to the idle state.*/ - if (uartp->txstate == UART_TX_COMPLETE) - uartp->txstate = UART_TX_IDLE; -} - -/** - * @brief USART common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void serve_usart_irq(UARTDriver *uartp) { - uint16_t sr; - USART_TypeDef *u = uartp->usart; - - sr = u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ - if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE | - USART_SR_FE | USART_SR_PE)) { - u->SR = ~USART_SR_LBD; - if (uartp->config->rxerr_cb != NULL) - uartp->config->rxerr_cb(uartp, translate_errors(sr)); - } - if (sr & USART_SR_TC) { - u->SR = ~USART_SR_TC; - /* End of transmission, a callback is generated.*/ - if (uartp->config->txend2_cb != NULL) - uartp->config->txend2_cb(uartp); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -/** - * @brief USART1 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(USART1_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART1 */ - -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -/** - * @brief USART2 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(USART2_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART2 */ - -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -/** - * @brief USART3 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(USART3_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART3 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level UART driver initialization. - * - * @notapi - */ -void uart_lld_init(void) { - -#if STM32_UART_USE_USART1 - uartObjectInit(&UARTD1); - UARTD1.usart = USART1; - UARTD1.dmarx = STM32_DMA1_STREAM5; - UARTD1.dmatx = STM32_DMA1_STREAM4; -#endif - -#if STM32_UART_USE_USART2 - uartObjectInit(&UARTD2); - UARTD2.usart = USART2; - UARTD2.dmarx = STM32_DMA1_STREAM6; - UARTD2.dmatx = STM32_DMA1_STREAM7; -#endif - -#if STM32_UART_USE_USART3 - uartObjectInit(&UARTD3); - UARTD3.usart = USART3; - UARTD3.dmarx = STM32_DMA1_STREAM3; - UARTD3.dmatx = STM32_DMA1_STREAM2; -#endif -} - -/** - * @brief Configures and activates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_start(UARTDriver *uartp) { - - if (uartp->state == UART_STOP) { -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM4, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM5, - STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); - RCC->APB2ENR |= RCC_APB2ENR_USART1EN; - NVICEnableVector(USART1_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM6, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM7, - STM32_UART_USART2_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); - RCC->APB1ENR |= RCC_APB1ENR_USART2EN; - NVICEnableVector(USART2_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM2, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM3, - STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, - (void *)uartp); - chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); - RCC->APB1ENR |= RCC_APB1ENR_USART3EN; - NVICEnableVector(USART3_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); - } -#endif - - /* Static DMA setup, the transfer size depends on the USART settings, - it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ - uartp->dmamode = STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); - if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) - uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; - dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); - dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR); - uartp->rxbuf = 0; - } - - uartp->rxstate = UART_RX_IDLE; - uartp->txstate = UART_TX_IDLE; - usart_start(uartp); -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_stop(UARTDriver *uartp) { - - if (uartp->state == UART_READY) { - usart_stop(uartp); - -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - dmaStreamRelease(STM32_DMA1_STREAM4); - dmaStreamRelease(STM32_DMA1_STREAM5); - NVICDisableVector(USART1_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; - return; - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - dmaStreamRelease(STM32_DMA1_STREAM6); - dmaStreamRelease(STM32_DMA1_STREAM7); - NVICDisableVector(USART2_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; - return; - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - dmaStreamRelease(STM32_DMA1_STREAM2); - dmaStreamRelease(STM32_DMA1_STREAM3); - NVICDisableVector(USART3_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; - return; - } -#endif - } -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { - - /* TX DMA channel preparation and start.*/ - dmaStreamSetMemory0(uartp->dmatx, txbuf); - dmaStreamSetTransactionSize(uartp->dmatx, n); - dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE); - dmaStreamEnable(uartp->dmatx); -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * - * @notapi - */ -size_t uart_lld_stop_send(UARTDriver *uartp) { - - dmaStreamDisable(uartp->dmatx); - dmaStreamClearInterrupt(uartp->dmatx); - return dmaStreamGetTransactionSize(uartp->dmatx); -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { - - /* Stopping previous activity (idle state).*/ - dmaStreamDisable(uartp->dmarx); - dmaStreamClearInterrupt(uartp->dmarx); - - /* RX DMA channel preparation and start.*/ - dmaStreamSetMemory0(uartp->dmarx, rxbuf); - dmaStreamSetTransactionSize(uartp->dmarx, n); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE); - dmaStreamEnable(uartp->dmarx); -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * - * @notapi - */ -size_t uart_lld_stop_receive(UARTDriver *uartp) { - size_t n; - - dmaStreamDisable(uartp->dmarx); - dmaStreamClearInterrupt(uartp->dmarx); - n = dmaStreamGetTransactionSize(uartp->dmarx); - set_rx_idle_loop(uartp); - return n; -} - -#endif /* HAL_USE_UART */ - -/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/uart_lld.h b/os/hal/platforms/STM32/DMAv1/uart_lld.h deleted file mode 100644 index aff7f52ba..000000000 --- a/os/hal/platforms/STM32/DMAv1/uart_lld.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/uart_lld.h - * @brief STM32 low level UART driver header. - * - * @addtogroup UART - * @{ - */ - -#ifndef _UART_LLD_H_ -#define _UART_LLD_H_ - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UART driver on USART1 enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART1 TRUE -#endif - -/** - * @brief UART driver on USART2 enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART2 TRUE -#endif - -/** - * @brief UART driver on USART3 enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART3 TRUE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_DMA_PRIORITY 0 -#endif - -/** - * @brief USART2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_DMA_PRIORITY 0 -#endif -/** - * @brief USART3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_DMA_PRIORITY 0 -#endif - -/** - * @brief USART1 DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ - !STM32_UART_USE_USART3 -#error "UART driver activated but no USART/UART peripheral assigned" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief UART driver condition flags type. - */ -typedef uint32_t uartflags_t; - -/** - * @brief Structure representing an UART driver. - */ -typedef struct UARTDriver UARTDriver; - -/** - * @brief Generic UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -typedef void (*uartcb_t)(UARTDriver *uartp); - -/** - * @brief Character received UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] c received character - */ -typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); - -/** - * @brief Receive error UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] e receive error mask - */ -typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief End of transmission buffer callback. - */ - uartcb_t txend1_cb; - /** - * @brief Physical end of transmission callback. - */ - uartcb_t txend2_cb; - /** - * @brief Receive buffer filled callback. - */ - uartcb_t rxend_cb; - /** - * @brief Character received while out if the @p UART_RECEIVE state. - */ - uartccb_t rxchar_cb; - /** - * @brief Receive error callback. - */ - uartecb_t rxerr_cb; - /* End of the mandatory fields.*/ - /** - * @brief Bit rate. - */ - uint32_t speed; - /** - * @brief Initialization value for the CR1 register. - */ - uint16_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint16_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint16_t cr3; -} UARTConfig; - -/** - * @brief Structure representing an UART driver. - */ -struct UARTDriver { - /** - * @brief Driver state. - */ - uartstate_t state; - /** - * @brief Transmitter state. - */ - uarttxstate_t txstate; - /** - * @brief Receiver state. - */ - uartrxstate_t rxstate; - /** - * @brief Current configuration data. - */ - const UARTConfig *config; -#if defined(UART_DRIVER_EXT_FIELDS) - UART_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the USART registers block. - */ - USART_TypeDef *usart; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief Default receive buffer while into @p UART_RX_IDLE state. - */ - volatile uint16_t rxbuf; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) -extern UARTDriver UARTD1; -#endif - -#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) -extern UARTDriver UARTD2; -#endif - -#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) -extern UARTDriver UARTD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void uart_lld_init(void); - void uart_lld_start(UARTDriver *uartp); - void uart_lld_stop(UARTDriver *uartp); - void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); - size_t uart_lld_stop_send(UARTDriver *uartp); - void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); - size_t uart_lld_stop_receive(UARTDriver *uartp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_UART */ - -#endif /* _UART_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c new file mode 100644 index 000000000..b9e02a815 --- /dev/null +++ b/os/hal/platforms/STM32/sdc_lld.c @@ -0,0 +1,730 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/sdc_lld.c + * @brief STM32 SDC subsystem low level driver source. + * + * @addtogroup SDC + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SDCD1 driver identifier.*/ +SDCDriver SDCD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +#if STM32_SDC_UNALIGNED_SUPPORT +/** + * @brief Buffer for temporary storage during unaligned transfers. + */ +static union { + uint32_t alignment; + uint8_t buf[SDC_BLOCK_SIZE]; +} u; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer, it must be aligned to + * four bytes boundary + * @param[in] n number of blocks to read + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @notapi + */ +static bool_t sdc_lld_read_multiple(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for reading.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for reading.*/ + dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); + dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, + (n * SDC_BLOCK_SIZE) / sizeof (uint32_t)); + dmaStreamSetMode(STM32_DMA2_STREAM4, + STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_PSIZE_WORD | + STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); + + /* Setting up data transfer. + Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; + SDIO->DLEN = n * SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DTDIR | + SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaStreamEnable(STM32_DMA2_STREAM4); + + /* Read multiple blocks command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_MULTIPLE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + goto error; + + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_multiple(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_multiple(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); +error: + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/** + * @brief Reads one block. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer, it must be aligned to + * four bytes boundary + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @notapi + */ +static bool_t sdc_lld_read_single(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for reading.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for reading.*/ + dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); + dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, + SDC_BLOCK_SIZE / sizeof (uint32_t)); + dmaStreamSetMode(STM32_DMA2_STREAM4, + STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_PSIZE_WORD | + STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); + + /* Setting up data transfer. + Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; + SDIO->DLEN = SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DTDIR | + SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaStreamEnable(STM32_DMA2_STREAM4); + + /* Read single block command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_SINGLE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + goto error; + + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_single(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_single(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return FALSE; +error: + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer, it must be aligned to + * four bytes boundary + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @notapi + */ +static bool_t sdc_lld_write_multiple(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for writing.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for writing.*/ + dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); + dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, + (n * SDC_BLOCK_SIZE) / sizeof (uint32_t)); + dmaStreamSetMode(STM32_DMA2_STREAM4, + STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_WORD | + STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); + + /* Write multiple blocks command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_MULTIPLE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + return TRUE; + + /* Setting up data transfer. + Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | + SDIO_MASK_STBITERRIE; + SDIO->DLEN = n * SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaStreamEnable(STM32_DMA2_STREAM4); + + /* Note the mask is checked before going to sleep because the interrupt + may have occurred before reaching the critical zone.*/ + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_multiple(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_multiple(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); +error: + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/** + * @brief Writes one block. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer, it must be aligned to + * four bytes boundary + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @notapi + */ +static bool_t sdc_lld_write_single(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for writing.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for writing.*/ + dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf); + dmaStreamSetTransactionSize(STM32_DMA2_STREAM4, + SDC_BLOCK_SIZE / sizeof (uint32_t)); + dmaStreamSetMode(STM32_DMA2_STREAM4, + STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_WORD | + STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC); + + /* Write single block command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + return TRUE; + + /* Setting up data transfer. + Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | + SDIO_MASK_STBITERRIE; + SDIO->DLEN = SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaStreamEnable(STM32_DMA2_STREAM4); + + /* Note the mask is checked before going to sleep because the interrupt + may have occurred before reaching the critical zone.*/ + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_single(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_single(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return FALSE; +error: + dmaStreamDisable(STM32_DMA2_STREAM4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief SDIO IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(SDIO_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + if (SDCD1.thread != NULL) { + chSchReadyI(SDCD1.thread); + SDCD1.thread = NULL; + } + chSysUnlockFromIsr(); + + /* Disables the source but the status flags are not reset because the + read/write functions need to check them.*/ + SDIO->MASK = 0; + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SDC driver initialization. + * + * @notapi + */ +void sdc_lld_init(void) { + + sdcObjectInit(&SDCD1); + SDCD1.thread = NULL; +} + +/** + * @brief Configures and activates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object, must be @p NULL, + * this driver does not require any configuration + * + * @notapi + */ +void sdc_lld_start(SDCDriver *sdcp) { + + if (sdcp->state == SDC_STOP) { + /* Note, the DMA must be enabled before the IRQs.*/ + dmaStreamAllocate(STM32_DMA2_STREAM4, 0, NULL, NULL); + dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO); + NVICEnableVector(SDIO_IRQn, + CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); + RCC->AHBENR |= RCC_AHBENR_SDIOEN; + } + /* Configuration, card clock is initially stopped.*/ + SDIO->POWER = 0; + SDIO->CLKCR = 0; + SDIO->DCTRL = 0; + SDIO->DTIMER = STM32_SDC_DATATIMEOUT; +} + +/** + * @brief Deactivates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop(SDCDriver *sdcp) { + + if ((sdcp->state == SDC_READY) || (sdcp->state == SDC_ACTIVE)) { + SDIO->POWER = 0; + SDIO->CLKCR = 0; + SDIO->DCTRL = 0; + SDIO->DTIMER = 0; + + /* Clock deactivation.*/ + NVICDisableVector(SDIO_IRQn); + dmaStreamRelease(STM32_DMA2_STREAM4); + } +} + +/** + * @brief Starts the SDIO clock and sets it to init mode (400KHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_start_clk(SDCDriver *sdcp) { + + (void)sdcp; + /* Initial clock setting: 400KHz, 1bit mode.*/ + SDIO->CLKCR = STM32_SDIO_DIV_LS; + SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1; + SDIO->CLKCR |= SDIO_CLKCR_CLKEN; +} + +/** + * @brief Sets the SDIO clock to data mode (25MHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_set_data_clk(SDCDriver *sdcp) { + + (void)sdcp; + SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS; +} + +/** + * @brief Stops the SDIO clock. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop_clk(SDCDriver *sdcp) { + + (void)sdcp; + SDIO->CLKCR = 0; + SDIO->POWER = 0; +} + +/** + * @brief Switches the bus to 4 bits mode. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] mode bus mode + * + * @notapi + */ +void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { + uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS; + + (void)sdcp; + switch (mode) { + case SDC_MODE_1BIT: + SDIO->CLKCR = clk; + break; + case SDC_MODE_4BIT: + SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0; + break; + case SDC_MODE_8BIT: + SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1; + } +} + +/** + * @brief Sends an SDIO command with no response expected. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * + * @notapi + */ +void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN; + while ((SDIO->STA & SDIO_STA_CMDSENT) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDSENTC; +} + +/** + * @brief Sends an SDIO command with a short response expected. + * @note The CRC is not verified. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed because timeout, CRC check or + * other errors. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sta; + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; + if ((sta & (SDIO_STA_CTIMEOUT)) != 0) + return TRUE; + *resp = SDIO->RESP1; + return FALSE; +} + +/** + * @brief Sends an SDIO command with a short response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed because timeout, CRC check or + * other errors. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sta; + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; + if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) + return TRUE; + *resp = SDIO->RESP1; + return FALSE; +} + +/** + * @brief Sends an SDIO command with a long response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (four words) + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed because timeout, CRC check or + * other errors. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + + uint32_t sta; + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 | + SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; + if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) + return TRUE; + *resp = SDIO->RESP1; + return FALSE; +} + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] n number of blocks to read + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @notapi + */ +bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + +#if STM32_SDC_UNALIGNED_SUPPORT + if (((unsigned)buf & 3) != 0) { + uint32_t i; + for (i = 0; i < n; i++) { + if (sdc_lld_read_single(sdcp, startblk, u.buf)) + return TRUE; + memcpy(buf, u.buf, SDC_BLOCK_SIZE); + buf += SDC_BLOCK_SIZE; + startblk++; + } + return FALSE; + } +#endif + if (n == 1) + return sdc_lld_read_single(sdcp, startblk, buf); + return sdc_lld_read_multiple(sdcp, startblk, buf, n); +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @notapi + */ +bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + + #if STM32_SDC_UNALIGNED_SUPPORT + if (((unsigned)buf & 3) != 0) { + uint32_t i; + for (i = 0; i < n; i++) { + memcpy(u.buf, buf, SDC_BLOCK_SIZE); + buf += SDC_BLOCK_SIZE; + if (sdc_lld_write_single(sdcp, startblk, u.buf)) + return TRUE; + startblk++; + } + return FALSE; + } +#endif + if (n == 1) + return sdc_lld_write_single(sdcp, startblk, buf); + return sdc_lld_write_multiple(sdcp, startblk, buf, n); +} + +#endif /* HAL_USE_SDC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h new file mode 100644 index 000000000..eea76dadd --- /dev/null +++ b/os/hal/platforms/STM32/sdc_lld.h @@ -0,0 +1,203 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/sdc_lld.h + * @brief STM32 SDC subsystem low level driver header. + * + * @addtogroup SDC + * @{ + */ + +#ifndef _SDC_LLD_H_ +#define _SDC_LLD_H_ + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SDIO data timeout in SDIO clock cycles. + */ +#if !defined(STM32_SDC_DATATIMEOUT) || defined(__DOXYGEN__) +#define STM32_SDC_DATATIMEOUT 0x000FFFFF +#endif + +/** + * @brief SDIO DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#endif + +/** + * @brief SDIO interrupt priority level setting. + */ +#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#endif + +/** + * @brief SDIO support for unaligned transfers. + */ +#if !defined(STM32_SDC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) +#define STM32_SDC_UNALIGNED_SUPPORT TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_HAS_SDIO +#error "SDIO not present in the selected device" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/* + * SDIO clock divider. + */ +#if STM32_HCLK > 48000000 +#define STM32_SDIO_DIV_HS 0x01 +#define STM32_SDIO_DIV_LS 0xB2 +#else +#define STM32_SDIO_DIV_HS 0x00 +#define STM32_SDIO_DIV_LS 0x76 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of SDIO bus mode. + */ +typedef enum { + SDC_MODE_1BIT = 0, + SDC_MODE_4BIT, + SDC_MODE_8BIT +} sdcbusmode_t; + +/** + * @brief Type of card flags. + */ +typedef uint32_t sdcmode_t; + +/** + * @brief Type of a structure representing an SDC driver. + */ +typedef struct SDCDriver SDCDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} SDCConfig; + +/** + * @brief Structure representing an SDC driver. + */ +struct SDCDriver { + /** + * @brief Driver state. + */ + sdcstate_t state; + /** + * @brief Current configuration data. + */ + const SDCConfig *config; + /** + * @brief Various flags regarding the mounted card. + */ + sdcmode_t cardmode; + /** + * @brief Card CID. + */ + uint32_t cid[4]; + /** + * @brief Card CSD. + */ + uint32_t csd[4]; + /** + * @brief Card RCA. + */ + uint32_t rca; + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion IRQ. + */ + Thread *thread; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern SDCDriver SDCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sdc_lld_init(void); + void sdc_lld_start(SDCDriver *sdcp); + void sdc_lld_stop(SDCDriver *sdcp); + void sdc_lld_start_clk(SDCDriver *sdcp); + void sdc_lld_set_data_clk(SDCDriver *sdcp); + void sdc_lld_stop_clk(SDCDriver *sdcp); + void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); + void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); + bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n); + bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n); + bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp); + bool_t sdc_lld_is_write_protected(SDCDriver *sdcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SDC */ + +#endif /* _SDC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c new file mode 100644 index 000000000..9302b0102 --- /dev/null +++ b/os/hal/platforms/STM32/spi_lld.c @@ -0,0 +1,445 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/spi_lld.c + * @brief STM32 SPI subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SPI1 driver identifier.*/ +#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** @brief SPI2 driver identifier.*/ +#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/** @brief SPI3 driver identifier.*/ +#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) +SPIDriver SPID3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +static uint16_t dummytx; +static uint16_t dummyrx; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Stops the SPI DMA channels. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +#define dma_stop(spip) { \ + dmaStreamDisable(spip->dmatx); \ + dmaStreamDisable(spip->dmarx); \ +} + +/** + * @brief Starts the SPI DMA channels. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +#define dma_start(spip) { \ + dmaChannelEnable((spip)->dmarx); \ + dmaChannelEnable((spip)->dmatx); \ +} + +/** + * @brief Shared end-of-rx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + if ((flags & STM32_DMA_ISR_TEIF) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)flags; +#endif + + /* Stop everything.*/ + dma_stop(spip); + + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); +} + +/** + * @brief Shared end-of-tx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + (void)spip; + if ((flags & STM32_DMA_ISR_TEIF) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)spip; + (void)flags; +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + + dummytx = 0xFFFF; + +#if STM32_SPI_USE_SPI1 + spiObjectInit(&SPID1); + SPID1.thread = NULL; + SPID1.spi = SPI1; + SPID1.dmarx = STM32_DMA1_STREAM2; + SPID1.dmatx = STM32_DMA1_STREAM3; +#endif + +#if STM32_SPI_USE_SPI2 + spiObjectInit(&SPID2); + SPID2.thread = NULL; + SPID2.spi = SPI2; + SPID2.dmarx = STM32_DMA1_STREAM4; + SPID2.dmatx = STM32_DMA1_STREAM5; +#endif + +#if STM32_SPI_USE_SPI3 + spiObjectInit(&SPID3); + SPID3.thread = NULL; + SPID3.spi = SPI3; + SPID3.dmarx = STM32_DMA2_STREAM1; + SPID3.dmatx = STM32_DMA2_STREAM2; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + /* If in stopped state then enables the SPI and DMA clocks.*/ + if (spip->state == SPI_STOP) { +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) { + bool_t b; + b = dmaStreamAllocate(STM32_DMA1_STREAM2, + STM32_SPI_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(STM32_DMA1_STREAM3, + STM32_SPI_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + } +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) { + bool_t b; + b = dmaStreamAllocate(STM32_DMA1_STREAM4, + STM32_SPI_SPI2_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(STM32_DMA1_STREAM5, + STM32_SPI_SPI2_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); + RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; + } +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) { + bool_t b; + b = dmaStreamAllocate(STM32_DMA1_STREAM1, + STM32_SPI_SPI3_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(STM32_DMA1_STREAM2, + STM32_SPI_SPI3_IRQ_PRIORITY, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, + (void *)spip); + chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); + RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; + } +#endif + + /* DMA setup.*/ + dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); + dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); + } + + /* More DMA setup.*/ + if ((spip->config->cr1 & SPI_CR1_DFF) == 0) + spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_TEIE | + STM32_DMA_CR_PSIZE_BYTE | + STM32_DMA_CR_MSIZE_BYTE; /* 8 bits transfers. */ + else + spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_TEIE | + STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MSIZE_HWORD; /* 16 bits transfers. */ + + /* SPI setup and enable.*/ + spip->spi->CR1 = 0; + spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | + SPI_CR1_SSI; + spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; + spip->spi->CR1 |= SPI_CR1_SPE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + /* If in ready state then disables the SPI clock.*/ + if (spip->state == SPI_READY) { + + /* SPI disable.*/ + spip->spi->CR1 = 0; + +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) { + dmaStreamRelease(STM32_DMA1_STREAM2); + dmaStreamRelease(STM32_DMA1_STREAM3); + RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN; + } +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) { + dmaStreamRelease(STM32_DMA1_STREAM4); + dmaStreamRelease(STM32_DMA1_STREAM5); + RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN; + } +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) { + dmaStreamRelease(STM32_DMA1_STREAM1); + dmaStreamRelease(STM32_DMA1_STREAM2); + RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN; + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + dmaStreamSetMemory0(spip->dmarx, &dummyrx); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | STM32_DMA_CR_EN); + dmaStreamSetMemory0(spip->dmatx, &dummytx); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_EN); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | + STM32_DMA_CR_EN); + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_MINC | STM32_DMA_CR_EN); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + dmaStreamSetMemory0(spip->dmarx, &dummyrx); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | STM32_DMA_CR_EN); + dmaStreamSetMemory0(spip->dmatx, txbuf); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_MINC | STM32_DMA_CR_EN); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + dmaStreamSetMemory0(spip->dmarx, rxbuf); + dmaStreamSetTransactionSize(spip->dmarx, n); + dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | + STM32_DMA_CR_EN); + dmaStreamSetMemory0(spip->dmatx, &dummytx); + dmaStreamSetTransactionSize(spip->dmatx, n); + dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_EN); +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->spi->DR = frame; + while ((spip->spi->SR & SPI_SR_RXNE) == 0) + ; + return spip->spi->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h new file mode 100644 index 000000000..c8c1e0661 --- /dev/null +++ b/os/hal/platforms/STM32/spi_lld.h @@ -0,0 +1,285 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/spi_lld.h + * @brief STM32 SPI subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI1 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for SPI2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI2 TRUE +#endif + +/** + * @brief SPI3 driver enable switch. + * @details If set to @p TRUE the support for SPI3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI3 FALSE +#endif + +/** + * @brief SPI1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI2 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI3 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 +#error "SPI1 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 +#error "SPI2 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 +#error "SPI3 not present in the selected device" +#endif + +#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SPI initialization data. + */ + uint16_t cr1; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver{ + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPIx registers block. + */ + SPI_TypeDef *spi; + /** + * @brief Receive DMA channel. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) +extern SPIDriver SPID3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/uart_lld.c b/os/hal/platforms/STM32/uart_lld.c new file mode 100644 index 000000000..a9303744d --- /dev/null +++ b/os/hal/platforms/STM32/uart_lld.c @@ -0,0 +1,557 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/uart_lld.c + * @brief STM32 low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 UART driver identifier.*/ +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief USART2 UART driver identifier.*/ +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/** @brief USART3 UART driver identifier.*/ +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] sr USART SR register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint16_t sr) { + uartflags_t sts = 0; + + if (sr & USART_SR_ORE) + sts |= UART_OVERRUN_ERROR; + if (sr & USART_SR_PE) + sts |= UART_PARITY_ERROR; + if (sr & USART_SR_FE) + sts |= UART_FRAMING_ERROR; + if (sr & USART_SR_NE) + sts |= UART_NOISE_ERROR; + if (sr & USART_SR_LBD) + sts |= UART_BREAK_DETECTED; + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void set_rx_idle_loop(UARTDriver *uartp) { + uint32_t mode; + + /* RX DMA channel preparation, if the char callback is defined then the + TCIE interrupt is enabled too.*/ + if (uartp->config->rxchar_cb == NULL) + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TEIE; + else + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TEIE | + STM32_DMA_CR_TCIE; + dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, 1); + dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_stop(UARTDriver *uartp) { + + /* Stops RX and TX DMA channels.*/ + dmaStreamDisable(uartp->dmarx); + dmaStreamClearInterrupt(uartp->dmarx); + dmaStreamDisable(uartp->dmatx); + dmaStreamClearInterrupt(uartp->dmatx); + + /* Stops USART operations.*/ + uartp->usart->CR1 = 0; + uartp->usart->CR2 = 0; + uartp->usart->CR3 = 0; +} + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_start(UARTDriver *uartp) { + uint16_t cr1; + USART_TypeDef *u = uartp->usart; + + /* Defensive programming, starting from a clean state.*/ + usart_stop(uartp); + + /* Baud rate setting.*/ + if (uartp->usart == USART1) + u->BRR = STM32_PCLK2 / uartp->config->speed; + else + u->BRR = STM32_PCLK1 / uartp->config->speed; + + /* Resetting eventual pending status flags.*/ + (void)u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ + u->SR = 0; + + /* Note that some bits are enforced because required for correct driver + operations.*/ + if (uartp->config->txend2_cb == NULL) + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; + else + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE | + USART_CR1_TCIE; + u->CR1 = uartp->config->cr1 | cr1; + u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; + u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | + USART_CR3_EIE; + + /* Starting the receiver idle loop.*/ + set_rx_idle_loop(uartp); +} + +/** + * @brief RX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & STM32_DMA_ISR_TEIF) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + if (uartp->config->rxchar_cb != NULL) + uartp->config->rxchar_cb(uartp, uartp->rxbuf); + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + dmaStreamDisable(uartp->dmarx); + uartp->rxstate = UART_RX_COMPLETE; + if (uartp->config->rxend_cb != NULL) + uartp->config->rxend_cb(uartp); + /* If the callback didn't explicitly change state then the receiver + automatically returns to the idle state.*/ + if (uartp->rxstate == UART_RX_COMPLETE) { + uartp->rxstate = UART_RX_IDLE; + set_rx_idle_loop(uartp); + } + } +} + +/** + * @brief TX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & STM32_DMA_ISR_TEIF) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + dmaStreamDisable(uartp->dmatx); + /* A callback is generated, if enabled, after a completed transfer.*/ + uartp->txstate = UART_TX_COMPLETE; + if (uartp->config->txend1_cb != NULL) + uartp->config->txend1_cb(uartp); + /* If the callback didn't explicitly change state then the transmitter + automatically returns to the idle state.*/ + if (uartp->txstate == UART_TX_COMPLETE) + uartp->txstate = UART_TX_IDLE; +} + +/** + * @brief USART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void serve_usart_irq(UARTDriver *uartp) { + uint16_t sr; + USART_TypeDef *u = uartp->usart; + + sr = u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ + if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE | + USART_SR_FE | USART_SR_PE)) { + u->SR = ~USART_SR_LBD; + if (uartp->config->rxerr_cb != NULL) + uartp->config->rxerr_cb(uartp, translate_errors(sr)); + } + if (sr & USART_SR_TC) { + u->SR = ~USART_SR_TC; + /* End of transmission, a callback is generated.*/ + if (uartp->config->txend2_cb != NULL) + uartp->config->txend2_cb(uartp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART1 */ + +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +/** + * @brief USART2 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART2 */ + +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +/** + * @brief USART3 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +#if STM32_UART_USE_USART1 + uartObjectInit(&UARTD1); + UARTD1.usart = USART1; + UARTD1.dmarx = STM32_DMA1_STREAM5; + UARTD1.dmatx = STM32_DMA1_STREAM4; +#endif + +#if STM32_UART_USE_USART2 + uartObjectInit(&UARTD2); + UARTD2.usart = USART2; + UARTD2.dmarx = STM32_DMA1_STREAM6; + UARTD2.dmatx = STM32_DMA1_STREAM7; +#endif + +#if STM32_UART_USE_USART3 + uartObjectInit(&UARTD3); + UARTD3.usart = USART3; + UARTD3.dmarx = STM32_DMA1_STREAM3; + UARTD3.dmatx = STM32_DMA1_STREAM2; +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + bool_t b; + b = dmaStreamAllocate(STM32_DMA1_STREAM4, + STM32_UART_USART1_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); + b = dmaStreamAllocate(STM32_DMA1_STREAM5, + STM32_UART_USART1_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + NVICEnableVector(USART1_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + bool_t b; + b = dmaStreamAllocate(STM32_DMA1_STREAM6, + STM32_UART_USART2_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(STM32_DMA1_STREAM7, + STM32_UART_USART2_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); + RCC->APB1ENR |= RCC_APB1ENR_USART2EN; + NVICEnableVector(USART2_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + bool_t b; + b = dmaStreamAllocate(STM32_DMA1_STREAM2, + STM32_UART_USART3_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); + b = dmaStreamAllocate(STM32_DMA1_STREAM3, + STM32_UART_USART3_IRQ_PRIORITY, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (void *)uartp); + chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); + RCC->APB1ENR |= RCC_APB1ENR_USART3EN; + NVICEnableVector(USART3_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); + } +#endif + + /* Static DMA setup, the transfer size depends on the USART settings, + it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ + uartp->dmamode = STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); + if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) + uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); + dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR); + uartp->rxbuf = 0; + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + usart_start(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + usart_stop(uartp); + +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + dmaStreamRelease(STM32_DMA1_STREAM4); + dmaStreamRelease(STM32_DMA1_STREAM5); + NVICDisableVector(USART1_IRQn); + RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; + return; + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + dmaStreamRelease(STM32_DMA1_STREAM6); + dmaStreamRelease(STM32_DMA1_STREAM7); + NVICDisableVector(USART2_IRQn); + RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; + return; + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + dmaStreamRelease(STM32_DMA1_STREAM2); + dmaStreamRelease(STM32_DMA1_STREAM3); + NVICDisableVector(USART3_IRQn); + RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { + + /* TX DMA channel preparation and start.*/ + dmaStreamSetMemory0(uartp->dmatx, txbuf); + dmaStreamSetTransactionSize(uartp->dmatx, n); + dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_MINC | STM32_DMA_CR_TEIE | + STM32_DMA_CR_TCIE); + dmaStreamEnable(uartp->dmatx); +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + + dmaStreamDisable(uartp->dmatx); + dmaStreamClearInterrupt(uartp->dmatx); + return dmaStreamGetTransactionSize(uartp->dmatx); +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { + + /* Stopping previous activity (idle state).*/ + dmaStreamDisable(uartp->dmarx); + dmaStreamClearInterrupt(uartp->dmarx); + + /* RX DMA channel preparation and start.*/ + dmaStreamSetMemory0(uartp->dmarx, rxbuf); + dmaStreamSetTransactionSize(uartp->dmarx, n); + dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MINC | STM32_DMA_CR_TEIE | + STM32_DMA_CR_TCIE); + dmaStreamEnable(uartp->dmarx); +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + size_t n; + + dmaStreamDisable(uartp->dmarx); + dmaStreamClearInterrupt(uartp->dmarx); + n = dmaStreamGetTransactionSize(uartp->dmarx); + set_rx_idle_loop(uartp); + return n; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/platforms/STM32/uart_lld.h b/os/hal/platforms/STM32/uart_lld.h new file mode 100644 index 000000000..aff7f52ba --- /dev/null +++ b/os/hal/platforms/STM32/uart_lld.h @@ -0,0 +1,318 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/uart_lld.h + * @brief STM32 low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef _UART_LLD_H_ +#define _UART_LLD_H_ + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART driver on USART1 enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART1 TRUE +#endif + +/** + * @brief UART driver on USART2 enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART2 TRUE +#endif + +/** + * @brief UART driver on USART3 enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART3 TRUE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#endif + +/** + * @brief USART2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_DMA_PRIORITY 0 +#endif +/** + * @brief USART3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_DMA_PRIORITY 0 +#endif + +/** + * @brief USART1 DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ + !STM32_UART_USE_USART3 +#error "UART driver activated but no USART/UART peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Bit rate. + */ + uint32_t speed; + /** + * @brief Initialization value for the CR1 register. + */ + uint16_t cr1; + /** + * @brief Initialization value for the CR2 register. + */ + uint16_t cr2; + /** + * @brief Initialization value for the CR3 register. + */ + uint16_t cr3; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the USART registers block. + */ + USART_TypeDef *usart; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief Receive DMA channel. + */ + const stm32_dma_stream_t *dmarx; + /** + * @brief Transmit DMA channel. + */ + const stm32_dma_stream_t *dmatx; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* _UART_LLD_H_ */ + +/** @} */ -- cgit v1.2.3 From adb989bc17a879e51dbd9aeb471089af1f9d73e2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 14 Sep 2011 18:59:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3318 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/adc_lld.c | 4 ++-- os/hal/platforms/STM32F1xx/adc_lld.h | 4 ++-- os/hal/platforms/STM32F1xx/hal_lld.c | 4 ++-- os/hal/platforms/STM32F1xx/hal_lld.h | 4 ++-- os/hal/platforms/STM32F1xx/platform.mk | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/adc_lld.c b/os/hal/platforms/STM32F1xx/adc_lld.c index 52d43daa9..cc4d25ea1 100644 --- a/os/hal/platforms/STM32F1xx/adc_lld.c +++ b/os/hal/platforms/STM32F1xx/adc_lld.c @@ -19,8 +19,8 @@ */ /** - * @file STM32/adc_lld.c - * @brief STM32 ADC subsystem low level driver source. + * @file STM32F1xx/adc_lld.c + * @brief STM32F1xx ADC subsystem low level driver source. * * @addtogroup ADC * @{ diff --git a/os/hal/platforms/STM32F1xx/adc_lld.h b/os/hal/platforms/STM32F1xx/adc_lld.h index 43b16b738..7180c2b83 100644 --- a/os/hal/platforms/STM32F1xx/adc_lld.h +++ b/os/hal/platforms/STM32F1xx/adc_lld.h @@ -19,8 +19,8 @@ */ /** - * @file STM32/adc_lld.h - * @brief STM32 ADC subsystem low level driver header. + * @file STM32F1xx/adc_lld.h + * @brief STM32F1xx ADC subsystem low level driver header. * * @addtogroup ADC * @{ diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c index 081499b83..ba13544f4 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.c +++ b/os/hal/platforms/STM32F1xx/hal_lld.c @@ -19,8 +19,8 @@ */ /** - * @file STM32/hal_lld.c - * @brief STM32 HAL subsystem low level driver source. + * @file STM32F1xx/hal_lld.c + * @brief STM32F1xx HAL subsystem low level driver source. * * @addtogroup HAL * @{ diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index 44e179f49..77c954e9a 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -19,8 +19,8 @@ */ /** - * @file STM32/hal_lld.h - * @brief STM32 HAL subsystem low level driver header. + * @file STM32F1xx/hal_lld.h + * @brief STM32F1xx HAL subsystem low level driver header. * @pre This module requires the following macros to be defined in the * @p board.h file: * - STM32_LSECLK. diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk index 1a8c42bc7..51601731e 100644 --- a/os/hal/platforms/STM32F1xx/platform.mk +++ b/os/hal/platforms/STM32F1xx/platform.mk @@ -9,10 +9,10 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/sdc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/uart_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/rtc_lld.c -- cgit v1.2.3 From 46538d795be83d1d54b132e7d57213cb6d975c51 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 15 Sep 2011 14:43:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3319 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_STM32_P107/board.h | 5 +++ os/hal/platforms/STM32/mac_lld.c | 89 +++++++++++++++++++++++++++++----------- os/hal/platforms/STM32/mac_lld.h | 2 +- testhal/STM32F1xx/MAC/main.c | 72 +------------------------------- 4 files changed, 73 insertions(+), 95 deletions(-) diff --git a/boards/OLIMEX_STM32_P107/board.h b/boards/OLIMEX_STM32_P107/board.h index 373123880..f4b273283 100644 --- a/boards/OLIMEX_STM32_P107/board.h +++ b/boards/OLIMEX_STM32_P107/board.h @@ -42,6 +42,11 @@ */ #define STM32F10X_CL +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_STE101P_ID + /* * IO pins assignments. */ diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c index 1bec4d879..98f1839c0 100644 --- a/os/hal/platforms/STM32/mac_lld.c +++ b/os/hal/platforms/STM32/mac_lld.c @@ -56,12 +56,14 @@ /** * @brief Ethernet driver 1. */ -MACDriver ETH1; +MACDriver ETHD1; /*===========================================================================*/ /* Driver local variables. */ /*===========================================================================*/ +static uint32_t phyaddr; + static stm32_eth_rx_descriptor_t *rxptr; static stm32_eth_tx_descriptor_t *txptr; @@ -80,13 +82,11 @@ static uint32_t tb[MAC_TRANSMIT_BUFFERS * BUFFER_SLICE]; * * @param[in] reg register number * @param[in] value new register value - * - * @notapi */ -void _stm32_eth_write_phy(uint32_t reg, uint32_t value) { +static void mii_write_phy(uint32_t reg, uint32_t value) { ETH->MACMIIDR = value; - ETH->MACMIIAR = BOARD_PHY_ADDR | (reg << 6) | MACMIIDR_CR | + ETH->MACMIIAR = phyaddr | (reg << 6) | MACMIIDR_CR | ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) ; @@ -96,12 +96,10 @@ void _stm32_eth_write_phy(uint32_t reg, uint32_t value) { * @brief Reads a PHY register. * * @param[in] reg register number - * - * @notapi */ -static uint32_t _stm32_eth_read_phy(uint32_t reg) { +static uint32_t mii_read_phy(uint32_t reg) { - ETH->MACMIIAR = BOARD_PHY_ADDR | (reg << 6) | MACMIIDR_CR | + ETH->MACMIIAR = phyaddr | (reg << 6) | MACMIIDR_CR | ETH_MACMIIAR_MB; while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) ; @@ -110,22 +108,22 @@ static uint32_t _stm32_eth_read_phy(uint32_t reg) { /** - * @brief MII/RMII interface initialization. + * @brief PHY address detection. */ -#if 0 -static void mii_init(void) { +static void mii_find_phy(void) { uint32_t i; for (i = 0; i < 31; i++) { ETH->MACMIIDR = (i << 6) | MACMIIDR_CR; - if ((mii_read_phy(MII_PHYSID1) == (PHY_ID >> 16)) && - (mii_read_phy(MII_PHYSID2) == (PHY_ID & 0xFFF0))) + if ((mii_read_phy(MII_PHYSID1) == (BOARD_PHY_ID >> 16)) && + (mii_read_phy(MII_PHYSID2) == (BOARD_PHY_ID & 0xFFF0))) { + phyaddr = i << 11; return; + } } /* Wrong or defective board.*/ chSysHalt(); } -#endif /*===========================================================================*/ /* Driver interrupt handlers. */ @@ -143,7 +141,7 @@ static void mii_init(void) { void mac_lld_init(void) { unsigned i; - macObjectInit(Ð1); + macObjectInit(ÐD1); /* Descriptor tables are initialized in linked mode, note that the first word is not initialized here but in mac_lld_start().*/ @@ -159,6 +157,36 @@ void mac_lld_init(void) { td[i].tdes3 = (uint32_t)&tb[((i + 1) % MAC_TRANSMIT_BUFFERS) * BUFFER_SLICE]; } + + /* MAC clocks activation.*/ + RCC->AHBENR |= RCC_AHBENR_ETHMACEN | + RCC_AHBENR_ETHMACTXEN | + RCC_AHBENR_ETHMACRXEN; + + /* Reset of the MAC core.*/ + RCC->AHBRSTR = RCC_AHBRSTR_ETHMACRST; + RCC->AHBRSTR = 0; + + /* Find PHY address.*/ + mii_find_phy(); + +#if defined(BOARD_PHY_RESET) + /* PHY board-specific reset procedure.*/ + BOARD_PHY_RESET(); +#else + /* PHY soft reset procedure.*/ + mii_write_phy(MII_BMCR, BMCR_RESET); + while (mii_read_phy(MII_BMCR) & BMCR_RESET) + ; +#endif + + /* PHY in power down mode until the driver will be started.*/ + mii_write_phy(MII_BMCR, BMCR_PDOWN); + + /* MAC clocks stopped again.*/ + RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN | + RCC_AHBENR_ETHMACTXEN | + RCC_AHBENR_ETHMACRXEN); } /** @@ -179,19 +207,28 @@ void mac_lld_start(MACDriver *macp) { td[i].tdes0 = STM32_TDES0_TCH; txptr = (stm32_eth_tx_descriptor_t *)td; - /* Soft reset of the MAC core and wait until the reset is complete.*/ - ETH->DMABMR |= ETH_DMABMR_SR; - while (ETH->DMABMR & ETH_DMABMR_SR) - ; - - /* MII initialization.*/ -// mii_init(); + /* MAC clocks activation.*/ + RCC->AHBENR |= RCC_AHBENR_ETHMACEN | + RCC_AHBENR_ETHMACTXEN | + RCC_AHBENR_ETHMACRXEN; /* Descriptor chains pointers.*/ ETH->DMARDLAR = (uint32_t)rd; ETH->DMATDLAR = (uint32_t)rd; - /* Clear DMA status.*/ + /* MAC configuration: + ETH_MACCR_TE - Transmitter enable. + ETH_MACCR_RE - Receiver enable. + Note that the complete setup of the MAC is performed when the link + status is detected.*/ + ETH->MACCR = ETH_MACCR_TE | ETH_MACCR_TE; + + ETH->MACFFR = 0; + ETH->MACHTHR = 0; + ETH->MACHTLR = 0; + ETH->MACHTLR = 0; + ETH->MACFCR = 0; + ETH->MACVLANTR = 0; } /** @@ -203,6 +240,10 @@ void mac_lld_start(MACDriver *macp) { */ void mac_lld_stop(MACDriver *macp) { + /* MAC clocks stopped.*/ + RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN | + RCC_AHBENR_ETHMACTXEN | + RCC_AHBENR_ETHMACRXEN); } /** diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h index f21f4c129..3e00639cc 100644 --- a/os/hal/platforms/STM32/mac_lld.h +++ b/os/hal/platforms/STM32/mac_lld.h @@ -242,7 +242,7 @@ typedef struct { /*===========================================================================*/ #if !defined(__DOXYGEN__) -extern MACDriver ETH1; +extern MACDriver ETHD1; #endif #ifdef __cplusplus diff --git a/testhal/STM32F1xx/MAC/main.c b/testhal/STM32F1xx/MAC/main.c index fc82a7786..6e6081162 100644 --- a/testhal/STM32F1xx/MAC/main.c +++ b/testhal/STM32F1xx/MAC/main.c @@ -21,71 +21,6 @@ #include "ch.h" #include "hal.h" -static VirtualTimer vt; - -/* LED set to OFF after 200mS.*/ -static void ledoff(void *arg) { - - (void)arg; - palSetPad(GPIOC, GPIOC_LED); -} - -/* Triggered when the button is pressed or released. The LED is set to ON.*/ -static void extcb1(EXTDriver *extp, expchannel_t channel) { - - (void)extp; - (void)channel; - palClearPad(GPIOC, GPIOC_LED); - chSysLockFromIsr(); - if (!chVTIsArmedI(&vt)) - chVTSetI(&vt, MS2ST(200), ledoff, NULL); - chSysUnlockFromIsr(); -} - -/* Triggered when the LED goes OFF.*/ -static void extcb2(EXTDriver *extp, expchannel_t channel) { - - (void)extp; - (void)channel; -} - -static const EXTConfig extcfg = { - { - {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART, extcb1}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART, extcb2}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - }, - EXT_MODE_EXTI(EXT_MODE_GPIOA, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - EXT_MODE_GPIOC, - 0, - 0, - 0) -}; - /* * Application entry point. */ @@ -104,16 +39,13 @@ int main(void) { /* * Activates the EXT driver 1. */ - extStart(&EXTD1, &extcfg); +/* macStart(ÐD1, NULL);*/ /* * Normal main() thread activity, in this demo it enables and disables the * button EXT channel using 5 seconds intervals. */ while (TRUE) { - chThdSleepMilliseconds(5000); - extChannelDisable(&EXTD1, 0); - chThdSleepMilliseconds(5000); - extChannelEnable(&EXTD1, 0); + chThdSleepMilliseconds(500); } } -- cgit v1.2.3 From 3a94137eb38857d9780a5ef65be30736804dea46 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 Sep 2011 17:38:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3320 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/DMAv1/stm32_dma.c | 8 +++--- os/hal/platforms/STM32/GPIOv1/pal_lld.c | 2 +- os/hal/platforms/STM32/GPIOv2/pal_lld.c | 16 ++++++------ os/hal/platforms/STM32/USBv1/usb_lld.c | 6 ++--- os/hal/platforms/STM32/can_lld.c | 4 +-- os/hal/platforms/STM32/gpt_lld.c | 42 ++++++++++++++------------------ os/hal/platforms/STM32/i2c_lld.c | 15 ++++-------- os/hal/platforms/STM32/icu_lld.c | 42 ++++++++++++++------------------ os/hal/platforms/STM32/mac_lld.c | 19 ++++----------- os/hal/platforms/STM32/pwm_lld.c | 42 ++++++++++++++------------------ os/hal/platforms/STM32/sdc_lld.c | 3 ++- os/hal/platforms/STM32/serial_lld.c | 20 +++++++-------- os/hal/platforms/STM32/spi_lld.c | 12 ++++----- os/hal/platforms/STM32/uart_lld.c | 12 ++++----- os/hal/platforms/STM32F1xx/adc_lld.c | 8 +++--- os/hal/platforms/STM32F1xx/hal_lld.c | 6 ++--- os/hal/platforms/STM32F1xx/hal_lld.h | 3 ++- os/hal/platforms/STM32L1xx/hal_lld.h | 3 ++- readme.txt | 3 +++ testhal/STM32F1xx/PWM-ICU/Makefile | 3 +++ 20 files changed, 121 insertions(+), 148 deletions(-) diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.c b/os/hal/platforms/STM32/DMAv1/stm32_dma.c index 1df93bb2f..29ee02360 100644 --- a/os/hal/platforms/STM32/DMAv1/stm32_dma.c +++ b/os/hal/platforms/STM32/DMAv1/stm32_dma.c @@ -437,10 +437,10 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, /* Enabling DMA clocks required by the current streams set.*/ if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) - RCC->AHBENR |= RCC_AHBENR_DMA1EN; + rccEnableDMA1(FALSE); #if STM32_HAS_DMA2 if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) - RCC->AHBENR |= RCC_AHBENR_DMA2EN; + rccEnableDMA2(FALSE); #endif /* Putting the stream in a safe state.*/ @@ -484,10 +484,10 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { /* Shutting down clocks that are no more required, if any.*/ if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) - RCC->AHBENR &= ~RCC_AHBENR_DMA1EN; + rccDisableDMA1(FALSE); #if STM32_HAS_DMA2 if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) - RCC->AHBENR &= ~RCC_AHBENR_DMA2EN; + rccDisableDMA2(FALSE); #endif } diff --git a/os/hal/platforms/STM32/GPIOv1/pal_lld.c b/os/hal/platforms/STM32/GPIOv1/pal_lld.c index 81846fa58..274d8b6c0 100644 --- a/os/hal/platforms/STM32/GPIOv1/pal_lld.c +++ b/os/hal/platforms/STM32/GPIOv1/pal_lld.c @@ -79,7 +79,7 @@ void _pal_lld_init(const PALConfig *config) { /* * Enables the GPIO related clocks. */ - RCC->APB2ENR |= APB2_EN_MASK; + rccEnableAPB2(APB2_EN_MASK, FALSE); /* * Initial GPIO setup. diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/os/hal/platforms/STM32/GPIOv2/pal_lld.c index c84df64f6..8f84f225e 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.c +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.c @@ -32,15 +32,14 @@ #if HAL_USE_PAL || defined(__DOXYGEN__) #if defined(STM32L1XX_MD) -#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ - RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ +#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN) -#define AHB_LPEN_MASK AHB_EN_MASK #elif defined(STM32F2XX) -#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ +#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ RCC_AHB1ENR_GPIOIEN) #define AHB1_LPEN_MASK AHB1_EN_MASK #else @@ -92,8 +91,7 @@ void _pal_lld_init(const PALConfig *config) { * Enables the GPIO related clocks. */ #if defined(STM32L1XX_MD) - RCC->AHBENR |= AHB_EN_MASK; - RCC->AHBLPENR |= AHB_LPEN_MASK; + rccEnableAHB(AHB_EN_MASK, TRUE); #elif defined(STM32F2XX) RCC->AHB1ENR |= AHB1_EN_MASK; RCC->AHB1LPENR |= AHB1_LPEN_MASK; diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.c b/os/hal/platforms/STM32/USBv1/usb_lld.c index 34b8d9bf0..b22f8f0da 100644 --- a/os/hal/platforms/STM32/USBv1/usb_lld.c +++ b/os/hal/platforms/STM32/USBv1/usb_lld.c @@ -330,7 +330,7 @@ void usb_lld_start(USBDriver *usbp) { #if STM32_USB_USE_USB1 if (&USBD1 == usbp) { /* USB clock enabled.*/ - RCC->APB1ENR |= RCC_APB1ENR_USBEN; + rccEnableUSB(FALSE); /* Powers up the transceiver while holding the USB in reset state.*/ STM32_USB->CNTR = CNTR_FRES; /* Enabling the USB IRQ vectors, this also gives enough time to allow @@ -360,12 +360,12 @@ void usb_lld_stop(USBDriver *usbp) { /* If in ready state then disables the USB clock.*/ if (usbp->state == USB_STOP) { -#if STM32_ADC_USE_ADC1 +#if STM32_USB_USE_USB1 if (&USBD1 == usbp) { NVICDisableVector(19); NVICDisableVector(20); STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES; - RCC->APB1ENR &= ~RCC_APB1ENR_USBEN; + rccDisableUSB(FALSE); } #endif } diff --git a/os/hal/platforms/STM32/can_lld.c b/os/hal/platforms/STM32/can_lld.c index e180a87cb..64ccb3af3 100644 --- a/os/hal/platforms/STM32/can_lld.c +++ b/os/hal/platforms/STM32/can_lld.c @@ -192,7 +192,7 @@ void can_lld_start(CANDriver *canp) { CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); NVICEnableVector(CAN1_SCE_IRQn, CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY)); - RCC->APB1ENR |= RCC_APB1ENR_CAN1EN; + rccEnableCAN1(FALSE); } #endif @@ -276,7 +276,7 @@ void can_lld_stop(CANDriver *canp) { NVICDisableVector(USB_LP_CAN1_RX0_IRQn); NVICDisableVector(CAN1_RX1_IRQn); NVICDisableVector(CAN1_SCE_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_CAN1EN; + rccDisableCAN1(FALSE); } #endif } diff --git a/os/hal/platforms/STM32/gpt_lld.c b/os/hal/platforms/STM32/gpt_lld.c index f7a9226ad..0fd5dde73 100644 --- a/os/hal/platforms/STM32/gpt_lld.c +++ b/os/hal/platforms/STM32/gpt_lld.c @@ -268,9 +268,8 @@ void gpt_lld_start(GPTDriver *gptp) { /* Clock activation.*/ #if STM32_GPT_USE_TIM1 if (&GPTD1 == gptp) { - RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; - RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST; - RCC->APB2RSTR = 0; + rccEnableTIM1(FALSE); + rccResetTIM1(); NVICEnableVector(TIM1_UP_IRQn, CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY)); gptp->clock = STM32_TIMCLK2; @@ -278,9 +277,8 @@ void gpt_lld_start(GPTDriver *gptp) { #endif #if STM32_GPT_USE_TIM2 if (&GPTD2 == gptp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST; - RCC->APB1RSTR = 0; + rccEnableTIM2(FALSE); + rccResetTIM2(); NVICEnableVector(TIM2_IRQn, CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY)); gptp->clock = STM32_TIMCLK1; @@ -288,9 +286,8 @@ void gpt_lld_start(GPTDriver *gptp) { #endif #if STM32_GPT_USE_TIM3 if (&GPTD3 == gptp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST; - RCC->APB1RSTR = 0; + rccEnableTIM3(FALSE); + rccResetTIM3(); NVICEnableVector(TIM3_IRQn, CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY)); gptp->clock = STM32_TIMCLK1; @@ -298,9 +295,8 @@ void gpt_lld_start(GPTDriver *gptp) { #endif #if STM32_GPT_USE_TIM4 if (&GPTD4 == gptp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST; - RCC->APB1RSTR = 0; + rccEnableTIM4(FALSE); + rccResetTIM4(); NVICEnableVector(TIM4_IRQn, CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY)); gptp->clock = STM32_TIMCLK1; @@ -309,9 +305,8 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM5 if (&GPTD5 == gptp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST; - RCC->APB1RSTR = 0; + rccEnableTIM5(FALSE); + rccResetTIM5(); NVICEnableVector(TIM5_IRQn, CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY)); gptp->clock = STM32_TIMCLK1; @@ -320,9 +315,8 @@ void gpt_lld_start(GPTDriver *gptp) { #if STM32_GPT_USE_TIM8 if (&GPTD8 == gptp) { - RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; - RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST; - RCC->APB2RSTR = 0; + rccEnableTIM8(FALSE); + rccResetTIM8(); NVICEnableVector(TIM8_UP_IRQn, CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY)); gptp->clock = STM32_TIMCLK2; @@ -359,37 +353,37 @@ void gpt_lld_stop(GPTDriver *gptp) { #if STM32_GPT_USE_TIM1 if (&GPTD1 == gptp) { NVICDisableVector(TIM1_UP_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN; + rccDisableTIM1(FALSE); } #endif #if STM32_GPT_USE_TIM2 if (&GPTD2 == gptp) { NVICDisableVector(TIM2_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN; + rccDisableTIM2(FALSE); } #endif #if STM32_GPT_USE_TIM3 if (&GPTD3 == gptp) { NVICDisableVector(TIM3_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN; + rccDisableTIM3(FALSE); } #endif #if STM32_GPT_USE_TIM4 if (&GPTD4 == gptp) { NVICDisableVector(TIM4_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN; + rccDisableTIM4(FALSE); } #endif #if STM32_GPT_USE_TIM5 if (&GPTD5 == gptp) { NVICDisableVector(TIM5_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN; + rccDisableTIM5(FALSE); } #endif #if STM32_GPT_USE_TIM8 if (&GPTD8 == gptp) { NVICDisableVector(TIM8_UP_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN; + rccDisableTIM8(FALSE); } #endif } diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 202669f8e..317fc57dd 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -497,8 +497,6 @@ CH_IRQ_HANDLER(VectorC8) { void i2c_lld_init(void) { #if STM32_I2C_USE_I2C1 - RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; /* reset I2C 1 */ - RCC->APB1RSTR = 0; i2cObjectInit(&I2CD1); I2CD1.id_i2c = I2C1; @@ -512,8 +510,6 @@ void i2c_lld_init(void) { #endif /* STM32_I2C_USE_I2C */ #if STM32_I2C_USE_I2C2 - RCC->APB1RSTR = RCC_APB1RSTR_I2C2RST; /* reset I2C 2 */ - RCC->APB1RSTR = 0; i2cObjectInit(&I2CD2); I2CD2.id_i2c = I2C2; @@ -542,7 +538,7 @@ void i2c_lld_start(I2CDriver *i2cp) { #endif /* I2C_SUPPORTS_CALLBACKS */ NVICEnableVector(I2C1_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); - RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; /* I2C 1 clock enable */ + rccEnableI2C1(FALSE); } #endif #if STM32_I2C_USE_I2C2 @@ -553,7 +549,7 @@ void i2c_lld_start(I2CDriver *i2cp) { #endif /* I2C_SUPPORTS_CALLBACKS */ NVICEnableVector(I2C2_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); - RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; /* I2C 2 clock enable */ + rccEnableI2C2(FALSE); } #endif } @@ -569,8 +565,7 @@ void i2c_lld_reset(I2CDriver *i2cp){ chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY), "i2c_lld_reset: invalid state"); - RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; /* reset I2C 1 */ - RCC->APB1RSTR = 0; + rccResetI2C1(); } @@ -699,14 +694,14 @@ void i2c_lld_stop(I2CDriver *i2cp) { if (&I2CD1 == i2cp) { NVICDisableVector(I2C1_EV_IRQn); NVICDisableVector(I2C1_ER_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN; + rccDisableI2C1(FALSE); } #endif #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { NVICDisableVector(I2C2_EV_IRQn); NVICDisableVector(I2C2_ER_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN; + rccDisableI2C2(FALSE); } #endif } diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c index 054ce1e3d..eaf98ec12 100644 --- a/os/hal/platforms/STM32/icu_lld.c +++ b/os/hal/platforms/STM32/icu_lld.c @@ -287,9 +287,8 @@ void icu_lld_start(ICUDriver *icup) { /* Clock activation and timer reset.*/ #if STM32_ICU_USE_TIM1 if (&ICUD1 == icup) { - RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; - RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST; - RCC->APB2RSTR = 0; + rccEnableTIM1(FALSE); + rccResetTIM1(); NVICEnableVector(TIM1_CC_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); clock = STM32_TIMCLK2; @@ -297,9 +296,8 @@ void icu_lld_start(ICUDriver *icup) { #endif #if STM32_ICU_USE_TIM2 if (&ICUD2 == icup) { - RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST; - RCC->APB1RSTR = 0; + rccEnableTIM2(FALSE); + rccResetTIM2(); NVICEnableVector(TIM2_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY)); clock = STM32_TIMCLK1; @@ -307,9 +305,8 @@ void icu_lld_start(ICUDriver *icup) { #endif #if STM32_ICU_USE_TIM3 if (&ICUD3 == icup) { - RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST; - RCC->APB1RSTR = 0; + rccEnableTIM3(FALSE); + rccResetTIM3(); NVICEnableVector(TIM3_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY)); clock = STM32_TIMCLK1; @@ -317,9 +314,8 @@ void icu_lld_start(ICUDriver *icup) { #endif #if STM32_ICU_USE_TIM4 if (&ICUD4 == icup) { - RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST; - RCC->APB1RSTR = 0; + rccEnableTIM4(FALSE); + rccResetTIM4(); NVICEnableVector(TIM4_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY)); clock = STM32_TIMCLK1; @@ -328,9 +324,8 @@ void icu_lld_start(ICUDriver *icup) { #if STM32_ICU_USE_TIM5 if (&ICUD5 == icup) { - RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST; - RCC->APB1RSTR = 0; + rccEnableTIM5(FALSE); + rccResetTIM5(); NVICEnableVector(TIM5_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY)); clock = STM32_TIMCLK1; @@ -338,9 +333,8 @@ void icu_lld_start(ICUDriver *icup) { #endif #if STM32_ICU_USE_TIM8 if (&ICUD8 == icup) { - RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; - RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST; - RCC->APB2RSTR = 0; + rccEnableTIM5(FALSE); + rccResetTIM5(); NVICEnableVector(TIM8_CC_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); clock = STM32_TIMCLK2; @@ -402,38 +396,38 @@ void icu_lld_stop(ICUDriver *icup) { #if STM32_ICU_USE_TIM1 if (&ICUD1 == icup) { NVICDisableVector(TIM1_CC_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN; + rccDisableTIM1(FALSE); } #endif #if STM32_ICU_USE_TIM2 if (&ICUD2 == icup) { NVICDisableVector(TIM2_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN; + rccDisableTIM2(FALSE); } #endif #if STM32_ICU_USE_TIM3 if (&ICUD3 == icup) { NVICDisableVector(TIM3_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN; + rccDisableTIM3(FALSE); } #endif #if STM32_ICU_USE_TIM4 if (&ICUD4 == icup) { NVICDisableVector(TIM4_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN; + rccDisableTIM4(FALSE); } #endif #if STM32_ICU_USE_TIM5 if (&ICUD5 == icup) { NVICDisableVector(TIM5_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN; + rccDisableTIM5(FALSE); } #endif } #if STM32_ICU_USE_TIM8 if (&ICUD8 == icup) { NVICDisableVector(TIM8_CC_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN; + rccDisableTIM8(FALSE); } #endif } diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c index 98f1839c0..99fba21ff 100644 --- a/os/hal/platforms/STM32/mac_lld.c +++ b/os/hal/platforms/STM32/mac_lld.c @@ -159,13 +159,10 @@ void mac_lld_init(void) { } /* MAC clocks activation.*/ - RCC->AHBENR |= RCC_AHBENR_ETHMACEN | - RCC_AHBENR_ETHMACTXEN | - RCC_AHBENR_ETHMACRXEN; + rccEnableETH(FALSE); /* Reset of the MAC core.*/ - RCC->AHBRSTR = RCC_AHBRSTR_ETHMACRST; - RCC->AHBRSTR = 0; + rccResetETH(); /* Find PHY address.*/ mii_find_phy(); @@ -184,9 +181,7 @@ void mac_lld_init(void) { mii_write_phy(MII_BMCR, BMCR_PDOWN); /* MAC clocks stopped again.*/ - RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN | - RCC_AHBENR_ETHMACTXEN | - RCC_AHBENR_ETHMACRXEN); + rccDisableETH(FALSE); } /** @@ -208,9 +203,7 @@ void mac_lld_start(MACDriver *macp) { txptr = (stm32_eth_tx_descriptor_t *)td; /* MAC clocks activation.*/ - RCC->AHBENR |= RCC_AHBENR_ETHMACEN | - RCC_AHBENR_ETHMACTXEN | - RCC_AHBENR_ETHMACRXEN; + rccEnableETH(FALSE); /* Descriptor chains pointers.*/ ETH->DMARDLAR = (uint32_t)rd; @@ -241,9 +234,7 @@ void mac_lld_start(MACDriver *macp) { void mac_lld_stop(MACDriver *macp) { /* MAC clocks stopped.*/ - RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN | - RCC_AHBENR_ETHMACTXEN | - RCC_AHBENR_ETHMACRXEN); + rccDisableETH(FALSE); } /** diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index efe215458..901474091 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -348,9 +348,8 @@ void pwm_lld_start(PWMDriver *pwmp) { /* Clock activation and timer reset.*/ #if STM32_PWM_USE_TIM1 if (&PWMD1 == pwmp) { - RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; - RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST; - RCC->APB2RSTR = 0; + rccEnableTIM1(FALSE); + rccResetTIM1(); NVICEnableVector(TIM1_UP_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); NVICEnableVector(TIM1_CC_IRQn, @@ -360,9 +359,8 @@ void pwm_lld_start(PWMDriver *pwmp) { #endif #if STM32_PWM_USE_TIM2 if (&PWMD2 == pwmp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST; - RCC->APB1RSTR = 0; + rccEnableTIM2(FALSE); + rccResetTIM2(); NVICEnableVector(TIM2_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY)); clock = STM32_TIMCLK1; @@ -370,9 +368,8 @@ void pwm_lld_start(PWMDriver *pwmp) { #endif #if STM32_PWM_USE_TIM3 if (&PWMD3 == pwmp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST; - RCC->APB1RSTR = 0; + rccEnableTIM3(FALSE); + rccResetTIM3(); NVICEnableVector(TIM3_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY)); clock = STM32_TIMCLK1; @@ -380,9 +377,8 @@ void pwm_lld_start(PWMDriver *pwmp) { #endif #if STM32_PWM_USE_TIM4 if (&PWMD4 == pwmp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST; - RCC->APB1RSTR = 0; + rccEnableTIM4(FALSE); + rccResetTIM4(); NVICEnableVector(TIM4_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY)); clock = STM32_TIMCLK1; @@ -391,9 +387,8 @@ void pwm_lld_start(PWMDriver *pwmp) { #if STM32_PWM_USE_TIM5 if (&PWMD5 == pwmp) { - RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; - RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST; - RCC->APB1RSTR = 0; + rccEnableTIM5(FALSE); + rccResetTIM5(); NVICEnableVector(TIM5_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY)); clock = STM32_TIMCLK1; @@ -401,9 +396,8 @@ void pwm_lld_start(PWMDriver *pwmp) { #endif #if STM32_PWM_USE_TIM8 if (&PWMD8 == pwmp) { - RCC->APB2ENR |= RCC_APB2ENR_TIM8EN; - RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST; - RCC->APB2RSTR = 0; + rccEnableTIM8(FALSE); + rccResetTIM8(); NVICEnableVector(TIM8_UP_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); NVICEnableVector(TIM8_CC_IRQn, @@ -552,38 +546,38 @@ void pwm_lld_stop(PWMDriver *pwmp) { if (&PWMD1 == pwmp) { NVICDisableVector(TIM1_UP_IRQn); NVICDisableVector(TIM1_CC_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN; + rccDisableTIM1(FALSE); } #endif #if STM32_PWM_USE_TIM2 if (&PWMD2 == pwmp) { NVICDisableVector(TIM2_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN; + rccDisableTIM2(FALSE); } #endif #if STM32_PWM_USE_TIM3 if (&PWMD3 == pwmp) { NVICDisableVector(TIM3_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN; + rccDisableTIM3(FALSE); } #endif #if STM32_PWM_USE_TIM4 if (&PWMD4 == pwmp) { NVICDisableVector(TIM4_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN; + rccDisableTIM4(FALSE); } #endif #if STM32_PWM_USE_TIM5 if (&PWMD5 == pwmp) { NVICDisableVector(TIM5_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN; + rccDisableTIM5(FALSE); } #endif #if STM32_PWM_USE_TIM8 if (&PWMD8 == pwmp) { NVICDisableVector(TIM8_UP_IRQn); NVICDisableVector(TIM8_CC_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN; + rccDisableTIM8(FALSE); } #endif } diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c index b9e02a815..2ce3cd0fb 100644 --- a/os/hal/platforms/STM32/sdc_lld.c +++ b/os/hal/platforms/STM32/sdc_lld.c @@ -443,7 +443,7 @@ void sdc_lld_start(SDCDriver *sdcp) { dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO); NVICEnableVector(SDIO_IRQn, CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); - RCC->AHBENR |= RCC_AHBENR_SDIOEN; + rccEnableSDIO(FALSE); } /* Configuration, card clock is initially stopped.*/ SDIO->POWER = 0; @@ -470,6 +470,7 @@ void sdc_lld_stop(SDCDriver *sdcp) { /* Clock deactivation.*/ NVICDisableVector(SDIO_IRQn); dmaStreamRelease(STM32_DMA2_STREAM4); + rccDisableSDIO(FALSE); } } diff --git a/os/hal/platforms/STM32/serial_lld.c b/os/hal/platforms/STM32/serial_lld.c index 5aaa60de9..ce412dedb 100644 --- a/os/hal/platforms/STM32/serial_lld.c +++ b/os/hal/platforms/STM32/serial_lld.c @@ -376,35 +376,35 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { if (sdp->state == SD_STOP) { #if STM32_SERIAL_USE_USART1 if (&SD1 == sdp) { - RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + rccEnableUSART1(FALSE); NVICEnableVector(USART1_IRQn, CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY)); } #endif #if STM32_SERIAL_USE_USART2 if (&SD2 == sdp) { - RCC->APB1ENR |= RCC_APB1ENR_USART2EN; + rccEnableUSART2(FALSE); NVICEnableVector(USART2_IRQn, CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY)); } #endif #if STM32_SERIAL_USE_USART3 if (&SD3 == sdp) { - RCC->APB1ENR |= RCC_APB1ENR_USART3EN; + rccEnableUSART3(FALSE); NVICEnableVector(USART3_IRQn, CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY)); } #endif #if STM32_SERIAL_USE_UART4 if (&SD4 == sdp) { - RCC->APB1ENR |= RCC_APB1ENR_UART4EN; + rccEnableUART4(FALSE); NVICEnableVector(UART4_IRQn, CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY)); } #endif #if STM32_SERIAL_USE_UART5 if (&SD5 == sdp) { - RCC->APB1ENR |= RCC_APB1ENR_UART5EN; + rccEnableUART5(FALSE); NVICEnableVector(UART5_IRQn, CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); } @@ -428,35 +428,35 @@ void sd_lld_stop(SerialDriver *sdp) { usart_deinit(sdp->usart); #if STM32_SERIAL_USE_USART1 if (&SD1 == sdp) { - RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; + rccDisableUSART1(FALSE); NVICDisableVector(USART1_IRQn); return; } #endif #if STM32_SERIAL_USE_USART2 if (&SD2 == sdp) { - RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; + rccDisableUSART2(FALSE); NVICDisableVector(USART2_IRQn); return; } #endif #if STM32_SERIAL_USE_USART3 if (&SD3 == sdp) { - RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; + rccDisableUSART3(FALSE); NVICDisableVector(USART3_IRQn); return; } #endif #if STM32_SERIAL_USE_UART4 if (&SD4 == sdp) { - RCC->APB1ENR &= ~RCC_APB1ENR_UART4EN; + rccDisableUART4(FALSE); NVICDisableVector(UART4_IRQn); return; } #endif #if STM32_SERIAL_USE_UART5 if (&SD5 == sdp) { - RCC->APB1ENR &= ~RCC_APB1ENR_UART5EN; + rccDisableUART5(FALSE); NVICDisableVector(UART5_IRQn); return; } diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index 9302b0102..7041ef854 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -192,7 +192,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + rccEnableSPI1(FALSE); } #endif #if STM32_SPI_USE_SPI2 @@ -208,7 +208,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); - RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; + rccEnableSPI2(FALSE); } #endif #if STM32_SPI_USE_SPI3 @@ -224,7 +224,7 @@ void spi_lld_start(SPIDriver *spip) { (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); - RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; + rccEnableSPI3(FALSE); } #endif @@ -272,21 +272,21 @@ void spi_lld_stop(SPIDriver *spip) { if (&SPID1 == spip) { dmaStreamRelease(STM32_DMA1_STREAM2); dmaStreamRelease(STM32_DMA1_STREAM3); - RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN; + rccDisableSPI1(FALSE); } #endif #if STM32_SPI_USE_SPI2 if (&SPID2 == spip) { dmaStreamRelease(STM32_DMA1_STREAM4); dmaStreamRelease(STM32_DMA1_STREAM5); - RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN; + rccDisableSPI2(FALSE); } #endif #if STM32_SPI_USE_SPI3 if (&SPID3 == spip) { dmaStreamRelease(STM32_DMA1_STREAM1); dmaStreamRelease(STM32_DMA1_STREAM2); - RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN; + rccDisableSPI3(FALSE); } #endif } diff --git a/os/hal/platforms/STM32/uart_lld.c b/os/hal/platforms/STM32/uart_lld.c index a9303744d..3841be8fa 100644 --- a/os/hal/platforms/STM32/uart_lld.c +++ b/os/hal/platforms/STM32/uart_lld.c @@ -362,7 +362,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); - RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + rccEnableUSART1(FALSE); NVICEnableVector(USART1_IRQn, CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); } @@ -381,7 +381,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); - RCC->APB1ENR |= RCC_APB1ENR_USART2EN; + rccEnableUSART2(FALSE); NVICEnableVector(USART2_IRQn, CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); } @@ -400,7 +400,7 @@ void uart_lld_start(UARTDriver *uartp) { (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); - RCC->APB1ENR |= RCC_APB1ENR_USART3EN; + rccEnableUSART3(FALSE); NVICEnableVector(USART3_IRQn, CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); } @@ -438,7 +438,7 @@ void uart_lld_stop(UARTDriver *uartp) { dmaStreamRelease(STM32_DMA1_STREAM4); dmaStreamRelease(STM32_DMA1_STREAM5); NVICDisableVector(USART1_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; + rccDisableUSART1(FALSE); return; } #endif @@ -448,7 +448,7 @@ void uart_lld_stop(UARTDriver *uartp) { dmaStreamRelease(STM32_DMA1_STREAM6); dmaStreamRelease(STM32_DMA1_STREAM7); NVICDisableVector(USART2_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; + rccDisableUSART2(FALSE); return; } #endif @@ -458,7 +458,7 @@ void uart_lld_stop(UARTDriver *uartp) { dmaStreamRelease(STM32_DMA1_STREAM2); dmaStreamRelease(STM32_DMA1_STREAM3); NVICDisableVector(USART3_IRQn); - RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; + rccDisableUSART3(FALSE); return; } #endif diff --git a/os/hal/platforms/STM32F1xx/adc_lld.c b/os/hal/platforms/STM32F1xx/adc_lld.c index cc4d25ea1..ac74251f8 100644 --- a/os/hal/platforms/STM32F1xx/adc_lld.c +++ b/os/hal/platforms/STM32F1xx/adc_lld.c @@ -100,7 +100,7 @@ void adc_lld_init(void) { STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; /* Temporary activation.*/ - RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; + rccEnableADC1(FALSE); ADC1->CR1 = 0; ADC1->CR2 = ADC_CR2_ADON; @@ -116,7 +116,7 @@ void adc_lld_init(void) { /* Return the ADC in low power mode.*/ ADC1->CR2 = 0; - RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; + rccDisableADC1(FALSE); #endif } @@ -140,7 +140,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; + rccEnableADC1(FALSE); } #endif @@ -167,7 +167,7 @@ void adc_lld_stop(ADCDriver *adcp) { ADC1->CR1 = 0; ADC1->CR2 = 0; dmaStreamRelease(adcp->dmastp); - RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; + rccDisableADC1(FALSE); } #endif } diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c index ba13544f4..6b5cc1459 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.c +++ b/os/hal/platforms/STM32F1xx/hal_lld.c @@ -59,10 +59,8 @@ void hal_lld_init(void) { /* Reset of all peripherals.*/ - RCC->APB1RSTR = 0xFFFFFFFF; - RCC->APB2RSTR = 0xFFFFFFFF; - RCC->APB1RSTR = 0; - RCC->APB2RSTR = 0; + rccResetAPB1(0xFFFFFFFF); + rccResetAPB2(0xFFFFFFFF); /* SysTick initialization using the system clock.*/ SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index 77c954e9a..659fd3fb1 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -578,8 +578,9 @@ #define FALSE 0 #define TRUE (!FALSE) -/* STM32 DMA support code.*/ +/* STM32 DMA and RCC helpers.*/ #include "stm32_dma.h" +#include "stm32_rcc.h" #ifdef __cplusplus extern "C" { diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 97cfde0b7..e650be5d7 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -787,8 +787,9 @@ /* External declarations. */ /*===========================================================================*/ -/* STM32 DMA support code.*/ +/* STM32 DMA and RCC helpers.*/ #include "stm32_dma.h" +#include "stm32_rcc.h" #ifdef __cplusplus extern "C" { diff --git a/readme.txt b/readme.txt index f58237756..b90ececf5 100644 --- a/readme.txt +++ b/readme.txt @@ -97,6 +97,9 @@ drivers. (uIP demo to be adapted) (implement macStop() in AT91SAM7X implementation) +- NEW: New RCC helper driver for STM32F1xx and STM32L1xx, it simplifies + the use of the RCC resources and hides most differences found among the + various STM32 sub-families. - NEW: New DMA helper driver for STM32, it simplifies the use of the DMA resources and hides most differences with the new enhanced DMA units found in the STM32F2xx sub-family. diff --git a/testhal/STM32F1xx/PWM-ICU/Makefile b/testhal/STM32F1xx/PWM-ICU/Makefile index 93cf17eff..f93aeb073 100644 --- a/testhal/STM32F1xx/PWM-ICU/Makefile +++ b/testhal/STM32F1xx/PWM-ICU/Makefile @@ -61,6 +61,9 @@ include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk include $(CHIBIOS)/os/kernel/kernel.mk #include $(CHIBIOS)/test/test.mk +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = $(PORTSRC) \ -- cgit v1.2.3 From 06d3e6325be3061cc281b3aa49fcb983998fc4cb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 Sep 2011 17:56:55 +0000 Subject: STM32 RCC helper driver implemented. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3321 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/stm32_rcc.h | 864 +++++++++++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/hal_lld.c | 7 +- os/hal/platforms/STM32L1xx/stm32_rcc.h | 552 +++++++++++++++++++++ 3 files changed, 1419 insertions(+), 4 deletions(-) create mode 100644 os/hal/platforms/STM32F1xx/stm32_rcc.h create mode 100644 os/hal/platforms/STM32L1xx/stm32_rcc.h diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h new file mode 100644 index 000000000..56fa0905c --- /dev/null +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -0,0 +1,864 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F1xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f10x.h. + * + * @addtogroup STM32_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @brief ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) +/** @} */ + +/** + * @brief CAN peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) +/** @} */ + +/** + * @brief DMA peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetDMA1() + +/** + * @brief Enables the DMA2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetDMA2() +/** @} */ + +/** + * @brief ETH peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableETH(lp) rccEnableAHB(RCC_AHBENR_ETHMACEN | \ + RCC_AHBENR_ETHMACTXEN | \ + RCC_AHBENR_ETHMACRXEN, lp) + +/** + * @brief Disables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableETH(lp) rccDisableAHB(RCC_AHBENR_ETHMACEN | \ + RCC_AHBENR_ETHMACTXEN | \ + RCC_AHBENR_ETHMACRXEN, lp) + +/** + * @brief Resets the ETH peripheral. + * + * @api + */ +#define rccResetETH() rccResetAHB(RCC_AHBRSTR_ETHMACRST) +/** @} */ + +/** + * @brief I2c peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @brief SDIO peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDIO(lp) rccEnableAHB(RCC_AHBENR_SDIOEN, lp) + +/** + * @brief Disables the SDIO peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDIO(lp) rccDisableAHB(RCC_AHBENR_SDIOEN, lp) + +/** + * @brief Resets the SDIO peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetSDIO() +/** @} */ + +/** + * @brief SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +/** @} */ + +/** + * @brief TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Disables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Resets the TIM5 peripheral. + * + * @api + */ +#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) +/** @} */ + +/** + * @brief USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) + +/** + * @brief Enables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) +/** @} */ + +/** + * @brief USB peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Disables the USB peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c index 9a8265365..c59aa3f1c 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.c +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -59,10 +59,9 @@ void hal_lld_init(void) { /* Reset of all peripherals.*/ -// RCC->APB1RSTR = 0xFFFFFFFF; -// RCC->APB2RSTR = 0xFFFFFFFF; -// RCC->APB1RSTR = 0; -// RCC->APB2RSTR = 0; + rccResetAHB(!RCC_AHBRSTR_FLITFRST); + rccResetAPB1(!0); + rccResetAPB2(!RCC_APB2RSTR_SYSCFGRST); /* SysTick initialization using the system clock.*/ SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/platforms/STM32L1xx/stm32_rcc.h new file mode 100644 index 000000000..abad4f96b --- /dev/null +++ b/os/hal/platforms/STM32L1xx/stm32_rcc.h @@ -0,0 +1,552 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32L1xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32l1xx.h. + * + * @addtogroup STM32_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ + if (lp) \ + RCC->APB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ + if (lp) \ + RCC->APB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ + if (lp) \ + RCC->APB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ + if (lp) \ + RCC->AHBLPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ + if (lp) \ + RCC->AHBLPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @brief ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) +/** @} */ + +/** + * @brief DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST) +/** @} */ + +/** + * @brief I2c peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @brief SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) +/** @} */ + +/** + * @brief TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) +/** @} */ + +/** + * @brief USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) +/** @} */ + +/** + * @brief USB peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Disables the USB peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp) + +/** + * @brief Resets the USB peripheral. + * + * @api + */ +#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ -- cgit v1.2.3 From eea844796a2cdbea9f4ddf51f9766ff3964984b6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Sep 2011 06:48:56 +0000 Subject: Fixed paths in IAR project for STM32L152-Discovery board. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3322 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32L_DISCOVERY/board.h | 24 ++++++++++++------------ demos/ARMCM3-STM32L152-DISCOVERY/halconf.h | 6 +++--- demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp | 27 ++++++++++++++++++++------- demos/ARMCM3-STM32L152-DISCOVERY/main.c | 2 +- 4 files changed, 36 insertions(+), 23 deletions(-) diff --git a/boards/ST_STM32L_DISCOVERY/board.h b/boards/ST_STM32L_DISCOVERY/board.h index d95480c15..845113f57 100644 --- a/boards/ST_STM32L_DISCOVERY/board.h +++ b/boards/ST_STM32L_DISCOVERY/board.h @@ -105,8 +105,8 @@ PIN_PUDR_FLOATING(14) | \ PIN_PUDR_FLOATING(15))) #define VAL_GPIOA_ODR 0xFFFFFFFF -#define VAL_GPIOA_AFRL 0x00000000 -#define VAL_GPIOA_AFRH 0x00000000 +#define VAL_GPIOA_AFRL 0x00000000 +#define VAL_GPIOA_AFRH 0x00000000 /* * Port B setup. @@ -127,8 +127,8 @@ PIN_PUDR_FLOATING(GPIOB_LED4) | \ PIN_PUDR_FLOATING(GPIOB_LED3))) #define VAL_GPIOB_ODR 0xFFFFFF3F -#define VAL_GPIOB_AFRL 0x00000000 -#define VAL_GPIOB_AFRH 0x00000000 +#define VAL_GPIOB_AFRL 0x00000000 +#define VAL_GPIOB_AFRH 0x00000000 /* * Port C setup. @@ -142,8 +142,8 @@ #define VAL_GPIOC_PUPDR (~(PIN_PUDR_FLOATING(15) | \ PIN_PUDR_FLOATING(14))) #define VAL_GPIOC_ODR 0xFFFFFFFF -#define VAL_GPIOC_AFRL 0x00000000 -#define VAL_GPIOC_AFRH 0x00000000 +#define VAL_GPIOC_AFRL 0x00000000 +#define VAL_GPIOC_AFRH 0x00000000 /* * Port D setup. @@ -154,8 +154,8 @@ #define VAL_GPIOD_OSPEEDR 0xFFFFFFFF #define VAL_GPIOD_PUPDR 0xFFFFFFFF #define VAL_GPIOD_ODR 0xFFFFFFFF -#define VAL_GPIOD_AFRL 0x00000000 -#define VAL_GPIOD_AFRH 0x00000000 +#define VAL_GPIOD_AFRL 0x00000000 +#define VAL_GPIOD_AFRH 0x00000000 /* * Port E setup. @@ -166,8 +166,8 @@ #define VAL_GPIOE_OSPEEDR 0xFFFFFFFF #define VAL_GPIOE_PUPDR 0xFFFFFFFF #define VAL_GPIOE_ODR 0xFFFFFFFF -#define VAL_GPIOE_AFRL 0x00000000 -#define VAL_GPIOE_AFRH 0x00000000 +#define VAL_GPIOE_AFRL 0x00000000 +#define VAL_GPIOE_AFRH 0x00000000 /* * Port H setup. @@ -178,8 +178,8 @@ #define VAL_GPIOH_OSPEEDR 0xFFFFFFFF #define VAL_GPIOH_PUPDR 0xFFFFFFFF #define VAL_GPIOH_ODR 0xFFFFFFFF -#define VAL_GPIOH_AFRL 0x00000000 -#define VAL_GPIOH_AFRH 0x00000000 +#define VAL_GPIOH_AFRL 0x00000000 +#define VAL_GPIOH_AFRH 0x00000000 #if !defined(_FROM_ASM_) #ifdef __cplusplus diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h index 2a5f1806e..b9bee3656 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h @@ -115,14 +115,14 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL FALSE +#define HAL_USE_SERIAL TRUE #endif /** * @brief Enables the SERIAL over USB subsystem. */ #if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB TRUE +#define HAL_USE_SERIAL_USB FALSE #endif /** @@ -143,7 +143,7 @@ * @brief Enables the USB subsystem. */ #if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB TRUE +#define HAL_USE_USB FALSE #endif /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp index 88946580b..d84ff7beb 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp +++ b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp @@ -295,9 +295,14 @@ CCIncludePath2 $PROJ_DIR$\..\ $PROJ_DIR$\..\..\..\os\kernel\include + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\CMSIS\include $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32L1xx $PROJ_DIR$\..\..\..\os\hal\include + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32 + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1 + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2 + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USBv1 $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx $PROJ_DIR$\..\..\..\boards\ST_STM32L_DISCOVERY $PROJ_DIR$\..\..\..\test @@ -1198,9 +1203,14 @@ CCIncludePath2 $PROJ_DIR$\..\ $PROJ_DIR$\..\..\..\os\kernel\include + $PROJ_DIR$\..\..\..\os\ports\common\ARMCMx\CMSIS\include $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32L1xx $PROJ_DIR$\..\..\..\os\hal\include + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32 + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1 + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2 + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\USBv1 $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx $PROJ_DIR$\..\..\..\boards\ST_STM32L_DISCOVERY $PROJ_DIR$\..\..\..\test @@ -2028,9 +2038,6 @@ platform - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\core_cm3.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\hal_lld.c @@ -2038,16 +2045,22 @@ $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\hal_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\pal_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\pal_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.h $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\stm32l1xx.h diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/main.c b/demos/ARMCM3-STM32L152-DISCOVERY/main.c index 6f0ea53a0..3eaddc5fc 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32L152-DISCOVERY/main.c @@ -61,7 +61,7 @@ int main(void) { /* * Activates the serial driver 1 using the driver default configuration. */ -// sdStart(&SD1, NULL); + sdStart(&SD1, NULL); /* * If the user button is pressed after the reset then the test suite is -- cgit v1.2.3 From 4ff96215eddade6e541f1a97af5364e754ccee7c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Sep 2011 08:45:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3323 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32L_DISCOVERY/board.h | 68 ++++++++++++++++++++++++++++----- demos/ARMCM3-STM32L152-DISCOVERY/main.c | 11 ++++-- os/hal/platforms/STM32/GPIOv2/pal_lld.h | 30 ++++++++++++++- 3 files changed, 93 insertions(+), 16 deletions(-) diff --git a/boards/ST_STM32L_DISCOVERY/board.h b/boards/ST_STM32L_DISCOVERY/board.h index 845113f57..9e6802b26 100644 --- a/boards/ST_STM32L_DISCOVERY/board.h +++ b/boards/ST_STM32L_DISCOVERY/board.h @@ -95,15 +95,39 @@ * PA15 - JTDI (alternate 0). */ #define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ PIN_MODE_ALTERNATE(13) | \ PIN_MODE_ALTERNATE(14) | \ PIN_MODE_ALTERNATE(15)) #define VAL_GPIOA_OTYPER 0x00000000 #define VAL_GPIOA_OSPEEDR 0xFFFFFFFF -#define VAL_GPIOA_PUPDR (~(PIN_PUDR_FLOATING(GPIOA_BUTTON) | \ - PIN_PUDR_FLOATING(13) | \ - PIN_PUDR_FLOATING(14) | \ - PIN_PUDR_FLOATING(15))) +#define VAL_GPIOA_PUPDR (PIN_PUDR_PULLUP(GPIOA_BUTTON) | \ + PIN_PUDR_PULLUP(1) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_PULLUP(3) | \ + PIN_PUDR_PULLUP(4) | \ + PIN_PUDR_PULLUP(5) | \ + PIN_PUDR_PULLUP(6) | \ + PIN_PUDR_PULLUP(7) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_PULLUP(9) | \ + PIN_PUDR_PULLUP(10) | \ + PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_PULLUP(12) | \ + PIN_PUDR_FLOATING(13) | \ + PIN_PUDR_FLOATING(14) | \ + PIN_PUDR_FLOATING(15)) #define VAL_GPIOA_ODR 0xFFFFFFFF #define VAL_GPIOA_AFRL 0x00000000 #define VAL_GPIOA_AFRH 0x00000000 @@ -116,16 +140,40 @@ * PB6 - GPIOB_LED4 (output push-pull). * PB7 - GPIOB_LED3 (output push-pull). */ -#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(3) | \ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_ALTERNATE(3) | \ PIN_MODE_ALTERNATE(4) | \ + PIN_MODE_INPUT(5) | \ PIN_MODE_OUTPUT(GPIOB_LED4) | \ - PIN_MODE_OUTPUT(GPIOB_LED3)) + PIN_MODE_OUTPUT(GPIOB_LED3) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) #define VAL_GPIOB_OTYPER 0x00000000 #define VAL_GPIOB_OSPEEDR 0xFFFFFFFF -#define VAL_GPIOB_PUPDR (~(PIN_PUDR_FLOATING(3) | \ - PIN_PUDR_FLOATING(4) | \ - PIN_PUDR_FLOATING(GPIOB_LED4) | \ - PIN_PUDR_FLOATING(GPIOB_LED3))) +#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLUP(0) | \ + PIN_PUDR_PULLUP(1) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_FLOATING(3) | \ + PIN_PUDR_FLOATING(4) | \ + PIN_PUDR_PULLUP(5) | \ + PIN_PUDR_FLOATING(GPIOB_LED4) | \ + PIN_PUDR_FLOATING(GPIOB_LED3) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_PULLUP(9) | \ + PIN_PUDR_PULLUP(10) | \ + PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_PULLUP(12) | \ + PIN_PUDR_PULLUP(13) | \ + PIN_PUDR_PULLUP(14) | \ + PIN_PUDR_PULLUP(15)) #define VAL_GPIOB_ODR 0xFFFFFF3F #define VAL_GPIOB_AFRL 0x00000000 #define VAL_GPIOB_AFRH 0x00000000 diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/main.c b/demos/ARMCM3-STM32L152-DISCOVERY/main.c index 3eaddc5fc..a21d12dae 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32L152-DISCOVERY/main.c @@ -60,16 +60,19 @@ int main(void) { /* * Activates the serial driver 1 using the driver default configuration. + * PA9 and PA10 are routed to USART1. */ sdStart(&SD1, NULL); + palSetPadMode(GPIOA, 9, PAL_MODE_ALT_OUTPUT_PUSHPULL(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALT_INPUT(7)); /* * If the user button is pressed after the reset then the test suite is * executed immediately before activating the various device drivers in * order to not alter the benchmark scores. */ -// if (palReadPad(GPIOA, GPIOA_BUTTON)) -// TestThread(&SD1); + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); /* * Initializes the SPI driver 1. @@ -106,8 +109,8 @@ int main(void) { * driver 1. */ while (TRUE) { -// if (palReadPad(GPIOA, GPIOA_BUTTON)) -// TestThread(&SD1); + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); chThdSleepMilliseconds(500); } } diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h index 0f9f22441..aa8dc2d73 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -95,6 +95,32 @@ #define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \ PAL_STM32_PUDR_PULLDOWN) +/** + * @brief Alternate input high-Z pad. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALT_INPUT(n) (PAL_STM32_MODE_INPUT | \ + PAL_STM32_ALTERNATE(n)) + +/** + * @brief Alternate input pad with weak pull up resistor. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALT_INPUT_PULLUP(n) (PAL_STM32_MODE_INPUT | \ + PAL_STM32_PUDR_PULLUP | \ + PAL_STM32_ALTERNATE(n)) + +/** + * @brief Alternate input pad with weak pull down resistor. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALT_INPUT_PULLDOWN(n) (PAL_STM32_MODE_INPUT | \ + PAL_STM32_PUDR_PULLDOWN | \ + PAL_STM32_ALTERNATE(n)) + /** * @brief Analog input mode. */ @@ -117,7 +143,7 @@ * * @param[in] n alternate function selector */ -#define PAL_MODE_ALTERNATE_PUSHPULL(n) (PAL_STM32_MODE_ALTERNATE | \ +#define PAL_MODE_ALT_OUTPUT_PUSHPULL(n) (PAL_STM32_MODE_ALTERNATE | \ PAL_STM32_OTYPE_PUSHPULL | \ PAL_STM32_ALTERNATE(n)) @@ -126,7 +152,7 @@ * * @param[in] n alternate function selector */ -#define PAL_MODE_ALTERNATE_OPENDRAIN(n) (PAL_STM32_MODE_ALTERNATE | \ +#define PAL_MODE_ALT_OUTPUT_OPENDRAIN(n) (PAL_STM32_MODE_ALTERNATE | \ PAL_STM32_OTYPE_OPENDRAIN | \ PAL_STM32_ALTERNATE(n)) -- cgit v1.2.3 From 93bea8080848c1526d302b577390e197ce030081 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Sep 2011 09:06:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3324 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.h | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index e650be5d7..2815febb1 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -195,6 +195,57 @@ #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE +/** + * @name Platform specific friendly IRQ names + */ +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ +#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ +#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ +#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ +#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ +#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ +#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ +#define ADC1_IRQHandler Vector88 /**< ADC1. */ +#define USB_HP_IRQHandler Vector8C /**< USB High Priority. */ +#define USB_LP_IRQHandler Vector90 /**< USB Low Priority. */ +#define DAC_IRQHandler Vector94 /**< DAC. */ +#define COMP_IRQHandler Vector98 /**< COMP. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM9_IRQHandler VectorA0 /**< TIM9. */ +#define TIM10_IRQHandler VectorA4 /**< TIM10. */ +#define TIM11_IRQHandler VectorA8 /**< TIM11. */ +#define LCD_IRQHandler VectorAC /**< LCD. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTCAlarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define USBWakeUp_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ +#define TIM6_IRQHandler VectorEC /**< TIM6. */ +#define TIM7_IRQHandler VectorF0 /**< TIM7. */ +/** @} */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ -- cgit v1.2.3 From 17ab902203a60ac1c70aebf41facc0f278babfd5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Sep 2011 09:16:10 +0000 Subject: STM32L152 report added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3325 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/reports/STM32L152-32-GCC.txt | 163 +++++++++++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/platform.mk | 6 +- 2 files changed, 166 insertions(+), 3 deletions(-) create mode 100644 docs/reports/STM32L152-32-GCC.txt diff --git a/docs/reports/STM32L152-32-GCC.txt b/docs/reports/STM32L152-32-GCC.txt new file mode 100644 index 000000000..3c9370693 --- /dev/null +++ b/docs/reports/STM32L152-32-GCC.txt @@ -0,0 +1,163 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +Settings: SYSCLK=48, ACR=0x11 (1 wait state) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.3.3unstable +*** Compiler: GCC 4.6.0 +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32L Ultra Low Power Medium Density +*** Test Board: ST STM32L-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 131582 msgs/S, 263164 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 107944 msgs/S, 215888 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 107944 msgs/S, 215888 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 454112 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 80216 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 114552 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 33101 reschedules/S, 198606 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 229080 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 350672 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 344308 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 468312 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 309196 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/os/hal/platforms/STM32L1xx/platform.mk b/os/hal/platforms/STM32L1xx/platform.mk index 348722671..e51234323 100644 --- a/os/hal/platforms/STM32L1xx/platform.mk +++ b/os/hal/platforms/STM32L1xx/platform.mk @@ -1,12 +1,12 @@ # List of all the STM32L1xx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c -- cgit v1.2.3 From f90db59d00378a4999389b75cb66a38db2eb9aa1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Sep 2011 11:34:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3326 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/GPIOv2/pal_lld.h | 8 +- testhal/STM32L1xx/SPI/Makefile | 204 ++++++++++++ testhal/STM32L1xx/SPI/chconf.h | 535 ++++++++++++++++++++++++++++++++ testhal/STM32L1xx/SPI/halconf.h | 328 ++++++++++++++++++++ testhal/STM32L1xx/SPI/main.c | 142 +++++++++ testhal/STM32L1xx/SPI/mcuconf.h | 185 +++++++++++ testhal/STM32L1xx/SPI/readme.txt | 26 ++ 7 files changed, 1424 insertions(+), 4 deletions(-) create mode 100644 testhal/STM32L1xx/SPI/Makefile create mode 100644 testhal/STM32L1xx/SPI/chconf.h create mode 100644 testhal/STM32L1xx/SPI/halconf.h create mode 100644 testhal/STM32L1xx/SPI/main.c create mode 100644 testhal/STM32L1xx/SPI/mcuconf.h create mode 100644 testhal/STM32L1xx/SPI/readme.txt diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h index aa8dc2d73..4c82141e3 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -55,10 +55,10 @@ #define PAL_STM32_OTYPE_OPENDRAIN (1 << 2) #define PAL_STM32_OSPEED_MASK (3 << 3) -#define PAL_STM32_OSPEED_400K (0 << 3) -#define PAL_STM32_OSPEED_2M (1 << 3) -#define PAL_STM32_OSPEED_10M (2 << 3) -#define PAL_STM32_OSPEED_40M (3 << 3) +#define PAL_STM32_OSPEED_LOWEST (0 << 3) +#define PAL_STM32_OSPEED_MID1 (1 << 3) +#define PAL_STM32_OSPEED_MID2 (2 << 3) +#define PAL_STM32_OSPEED_HIGHEST (3 << 3) #define PAL_STM32_PUDR_MASK (3 << 5) #define PAL_STM32_PUDR_FLOATING (0 << 5) diff --git a/testhal/STM32L1xx/SPI/Makefile b/testhal/STM32L1xx/SPI/Makefile new file mode 100644 index 000000000..73c1d3811 --- /dev/null +++ b/testhal/STM32L1xx/SPI/Makefile @@ -0,0 +1,204 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/testhal/STM32L1xx/SPI/chconf.h b/testhal/STM32L1xx/SPI/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32L1xx/SPI/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/SPI/halconf.h b/testhal/STM32L1xx/SPI/halconf.h new file mode 100644 index 000000000..a825e65c5 --- /dev/null +++ b/testhal/STM32L1xx/SPI/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/SPI/main.c b/testhal/STM32L1xx/SPI/main.c new file mode 100644 index 000000000..b5466bcae --- /dev/null +++ b/testhal/STM32L1xx/SPI/main.c @@ -0,0 +1,142 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (16MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 12, + 0 +}; + +/* + * Low speed SPI configuration (256KHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOA, + 12, + SPI_CR1_BR_2 | SPI_CR1_BR_1 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palClearPad(GPIOB, GPIOB_LED4); /* LED ON. */ + spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palSetPad(GPIOB, GPIOB_LED4); /* LED OFF. */ + spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI1 I/O pins setup. + */ + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* NSS. */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALT_OUTPUT_PUSHPULL(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALT_INPUT(5) | + PAL_STM32_OSPEED_HIGHEST); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALT_OUTPUT_PUSHPULL(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ + palSetPad(GPIOB, 12); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32L1xx/SPI/mcuconf.h b/testhal/STM32L1xx/SPI/mcuconf.h new file mode 100644 index 000000000..a87325ff7 --- /dev/null +++ b/testhal/STM32L1xx/SPI/mcuconf.h @@ -0,0 +1,185 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_1P8 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/SPI/readme.txt b/testhal/STM32L1xx/SPI/readme.txt new file mode 100644 index 000000000..eead6ffd9 --- /dev/null +++ b/testhal/STM32L1xx/SPI/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx SPI driver. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From 68a4911f7341c86752e50d1d2498698fa2c466db Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Sep 2011 15:12:48 +0000 Subject: SPI driver working on STM32L. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3327 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/SPI/main.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/testhal/STM32L1xx/SPI/main.c b/testhal/STM32L1xx/SPI/main.c index b5466bcae..14e97bd20 100644 --- a/testhal/STM32L1xx/SPI/main.c +++ b/testhal/STM32L1xx/SPI/main.c @@ -36,7 +36,7 @@ static const SPIConfig hs_spicfg = { */ static const SPIConfig ls_spicfg = { NULL, - GPIOA, + GPIOB, 12, SPI_CR1_BR_2 | SPI_CR1_BR_1 }; @@ -56,14 +56,14 @@ static msg_t spi_thread_1(void *p) { (void)p; chRegSetThreadName("SPI thread 1"); while (TRUE) { - spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ palClearPad(GPIOB, GPIOB_LED4); /* LED ON. */ - spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ - spiSelect(&SPID1); /* Slave Select assertion. */ - spiExchange(&SPID1, 512, + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, txbuf, rxbuf); /* Atomic transfer operations. */ - spiUnselect(&SPID1); /* Slave Select de-assertion. */ - spiReleaseBus(&SPID1); /* Ownership release. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ } return 0; } @@ -77,14 +77,14 @@ static msg_t spi_thread_2(void *p) { (void)p; chRegSetThreadName("SPI thread 2"); while (TRUE) { - spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ palSetPad(GPIOB, GPIOB_LED4); /* LED OFF. */ - spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ - spiSelect(&SPID1); /* Slave Select assertion. */ - spiExchange(&SPID1, 512, + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, txbuf, rxbuf); /* Atomic transfer operations. */ - spiUnselect(&SPID1); /* Slave Select de-assertion. */ - spiReleaseBus(&SPID1); /* Ownership release. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ } return 0; } @@ -112,8 +112,7 @@ int main(void) { PAL_STM32_OSPEED_HIGHEST); /* NSS. */ palSetPadMode(GPIOB, 13, PAL_MODE_ALT_OUTPUT_PUSHPULL(5) | PAL_STM32_OSPEED_HIGHEST); /* SCK. */ - palSetPadMode(GPIOB, 14, PAL_MODE_ALT_INPUT(5) | - PAL_STM32_OSPEED_HIGHEST); /* MISO. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALT_INPUT(5)); /* MISO. */ palSetPadMode(GPIOB, 15, PAL_MODE_ALT_OUTPUT_PUSHPULL(5) | PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ palSetPad(GPIOB, 12); -- cgit v1.2.3 From eefe7fbc1bd9cf3f50e580ff44f977a08dafa107 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Sep 2011 15:50:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3328 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/SPI/Makefile | 2 - testhal/STM32L1xx/UART/Makefile | 202 ++++++++++++++ testhal/STM32L1xx/UART/chconf.h | 535 ++++++++++++++++++++++++++++++++++++++ testhal/STM32L1xx/UART/halconf.h | 321 +++++++++++++++++++++++ testhal/STM32L1xx/UART/main.c | 147 +++++++++++ testhal/STM32L1xx/UART/mcuconf.h | 185 +++++++++++++ testhal/STM32L1xx/UART/readme.txt | 26 ++ 7 files changed, 1416 insertions(+), 2 deletions(-) create mode 100644 testhal/STM32L1xx/UART/Makefile create mode 100644 testhal/STM32L1xx/UART/chconf.h create mode 100644 testhal/STM32L1xx/UART/halconf.h create mode 100644 testhal/STM32L1xx/UART/main.c create mode 100644 testhal/STM32L1xx/UART/mcuconf.h create mode 100644 testhal/STM32L1xx/UART/readme.txt diff --git a/testhal/STM32L1xx/SPI/Makefile b/testhal/STM32L1xx/SPI/Makefile index 73c1d3811..5efd8bf02 100644 --- a/testhal/STM32L1xx/SPI/Makefile +++ b/testhal/STM32L1xx/SPI/Makefile @@ -72,8 +72,6 @@ CSRC = $(PORTSRC) \ $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global diff --git a/testhal/STM32L1xx/UART/Makefile b/testhal/STM32L1xx/UART/Makefile new file mode 100644 index 000000000..5efd8bf02 --- /dev/null +++ b/testhal/STM32L1xx/UART/Makefile @@ -0,0 +1,202 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/testhal/STM32L1xx/UART/chconf.h b/testhal/STM32L1xx/UART/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32L1xx/UART/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/UART/halconf.h b/testhal/STM32L1xx/UART/halconf.h new file mode 100644 index 000000000..2dd31e012 --- /dev/null +++ b/testhal/STM32L1xx/UART/halconf.h @@ -0,0 +1,321 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/UART/main.c b/testhal/STM32L1xx/UART/main.c new file mode 100644 index 000000000..87efcab74 --- /dev/null +++ b/testhal/STM32L1xx/UART/main.c @@ -0,0 +1,147 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt1, vt2; + +static void restart(void *p) { + + (void)p; + uartStartSendI(&UARTD1, 14, "Hello World!\r\n"); +} + +static void ledoff(void *p) { + + (void)p; + palSetPad(GPIOB, GPIOB_LED4); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; + palClearPad(GPIOB, GPIOB_LED4); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + palSetPad(GPIOB, GPIOB_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt1)) + chVTResetI(&vt1); + chVTSetI(&vt1, MS2ST(5000), restart, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + /* Flashing the LED each time a character is received.*/ + palClearPad(GPIOB, GPIOB_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt2)) + chVTResetI(&vt2); + chVTSetI(&vt2, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + 0, + USART_CR2_LINEN, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + * PA9 and PA10 are routed to USART1. + */ + uartStart(&UARTD1, &uart_cfg_1); + palSetPadMode(GPIOA, 9, PAL_MODE_ALT_OUTPUT_PUSHPULL(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALT_INPUT(7)); + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&UARTD1, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32L1xx/UART/mcuconf.h b/testhal/STM32L1xx/UART/mcuconf.h new file mode 100644 index 000000000..a210c468b --- /dev/null +++ b/testhal/STM32L1xx/UART/mcuconf.h @@ -0,0 +1,185 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_1P8 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/UART/readme.txt b/testhal/STM32L1xx/UART/readme.txt new file mode 100644 index 000000000..e52a79d4a --- /dev/null +++ b/testhal/STM32L1xx/UART/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - UART driver demo for STM32F1xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx UART driver. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From baabff16e61179d497fe986d63e325e83272d4ed Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Sep 2011 16:56:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3329 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/DMAv1/stm32_dma.h | 10 +++++----- testhal/STM32L1xx/UART/chconf.h | 12 ++++++------ testhal/STM32L1xx/UART/main.c | 9 ++++----- 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.h b/os/hal/platforms/STM32/DMAv1/stm32_dma.h index 473bbe851..ca9c429f7 100644 --- a/os/hal/platforms/STM32/DMAv1/stm32_dma.h +++ b/os/hal/platforms/STM32/DMAv1/stm32_dma.h @@ -63,11 +63,11 @@ #define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4]) #define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5]) #define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6]) -#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[8]) -#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[9]) -#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[10]) -#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[11]) -#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[12]) +#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[7]) +#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[8]) +#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[9]) +#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[10]) +#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[11]) /** @} */ /** diff --git a/testhal/STM32L1xx/UART/chconf.h b/testhal/STM32L1xx/UART/chconf.h index a5d129956..9dd831c96 100644 --- a/testhal/STM32L1xx/UART/chconf.h +++ b/testhal/STM32L1xx/UART/chconf.h @@ -361,7 +361,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#define CH_DBG_SYSTEM_STATE_CHECK FALSE #endif /** @@ -372,7 +372,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS TRUE +#define CH_DBG_ENABLE_CHECKS FALSE #endif /** @@ -384,7 +384,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS TRUE +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** @@ -395,7 +395,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE TRUE +#define CH_DBG_ENABLE_TRACE FALSE #endif /** @@ -409,7 +409,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -421,7 +421,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/testhal/STM32L1xx/UART/main.c b/testhal/STM32L1xx/UART/main.c index 87efcab74..1039b781d 100644 --- a/testhal/STM32L1xx/UART/main.c +++ b/testhal/STM32L1xx/UART/main.c @@ -32,7 +32,7 @@ static void restart(void *p) { static void ledoff(void *p) { (void)p; - palSetPad(GPIOB, GPIOB_LED4); + palClearPad(GPIOB, GPIOB_LED4); } /* @@ -42,7 +42,7 @@ static void ledoff(void *p) { static void txend1(UARTDriver *uartp) { (void)uartp; - palClearPad(GPIOB, GPIOB_LED4); + palSetPad(GPIOB, GPIOB_LED4); } /* @@ -51,7 +51,7 @@ static void txend1(UARTDriver *uartp) { static void txend2(UARTDriver *uartp) { (void)uartp; - palSetPad(GPIOB, GPIOB_LED4); + palClearPad(GPIOB, GPIOB_LED4); chSysLockFromIsr(); if (chVTIsArmedI(&vt1)) chVTResetI(&vt1); @@ -78,7 +78,7 @@ static void rxchar(UARTDriver *uartp, uint16_t c) { (void)uartp; (void)c; /* Flashing the LED each time a character is received.*/ - palClearPad(GPIOB, GPIOB_LED4); + palSetPad(GPIOB, GPIOB_LED4); chSysLockFromIsr(); if (chVTIsArmedI(&vt2)) chVTResetI(&vt2); @@ -143,5 +143,4 @@ int main(void) { while (TRUE) { chThdSleepMilliseconds(500); } - return 0; } -- cgit v1.2.3 From 278fc39f993660a8d7ebf4df4a89f6beb10c7f7b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Sep 2011 17:53:57 +0000 Subject: UART driver tested with STM32L. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3330 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32L152-DISCOVERY/main.c | 4 ++-- os/hal/platforms/STM32/GPIOv2/pal_lld.h | 40 ++------------------------------- testhal/STM32L1xx/SPI/main.c | 6 ++--- testhal/STM32L1xx/UART/main.c | 4 ++-- 4 files changed, 9 insertions(+), 45 deletions(-) diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/main.c b/demos/ARMCM3-STM32L152-DISCOVERY/main.c index a21d12dae..c5b0dd974 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32L152-DISCOVERY/main.c @@ -63,8 +63,8 @@ int main(void) { * PA9 and PA10 are routed to USART1. */ sdStart(&SD1, NULL); - palSetPadMode(GPIOA, 9, PAL_MODE_ALT_OUTPUT_PUSHPULL(7)); - palSetPadMode(GPIOA, 10, PAL_MODE_ALT_INPUT(7)); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); /* * If the user button is pressed after the reset then the test suite is diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h index 4c82141e3..6c799c14c 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -95,32 +95,6 @@ #define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \ PAL_STM32_PUDR_PULLDOWN) -/** - * @brief Alternate input high-Z pad. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALT_INPUT(n) (PAL_STM32_MODE_INPUT | \ - PAL_STM32_ALTERNATE(n)) - -/** - * @brief Alternate input pad with weak pull up resistor. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALT_INPUT_PULLUP(n) (PAL_STM32_MODE_INPUT | \ - PAL_STM32_PUDR_PULLUP | \ - PAL_STM32_ALTERNATE(n)) - -/** - * @brief Alternate input pad with weak pull down resistor. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALT_INPUT_PULLDOWN(n) (PAL_STM32_MODE_INPUT | \ - PAL_STM32_PUDR_PULLDOWN | \ - PAL_STM32_ALTERNATE(n)) - /** * @brief Analog input mode. */ @@ -139,21 +113,11 @@ PAL_STM32_OTYPE_OPENDRAIN) /** - * @brief Alternate push-pull output. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALT_OUTPUT_PUSHPULL(n) (PAL_STM32_MODE_ALTERNATE | \ - PAL_STM32_OTYPE_PUSHPULL | \ - PAL_STM32_ALTERNATE(n)) - -/** - * @brief Alternate push-pull output. + * @brief Alternate function. * * @param[in] n alternate function selector */ -#define PAL_MODE_ALT_OUTPUT_OPENDRAIN(n) (PAL_STM32_MODE_ALTERNATE | \ - PAL_STM32_OTYPE_OPENDRAIN | \ +#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \ PAL_STM32_ALTERNATE(n)) /*===========================================================================*/ diff --git a/testhal/STM32L1xx/SPI/main.c b/testhal/STM32L1xx/SPI/main.c index 14e97bd20..7a96f0e22 100644 --- a/testhal/STM32L1xx/SPI/main.c +++ b/testhal/STM32L1xx/SPI/main.c @@ -110,10 +110,10 @@ int main(void) { */ palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); /* NSS. */ - palSetPadMode(GPIOB, 13, PAL_MODE_ALT_OUTPUT_PUSHPULL(5) | + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | PAL_STM32_OSPEED_HIGHEST); /* SCK. */ - palSetPadMode(GPIOB, 14, PAL_MODE_ALT_INPUT(5)); /* MISO. */ - palSetPadMode(GPIOB, 15, PAL_MODE_ALT_OUTPUT_PUSHPULL(5) | + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ palSetPad(GPIOB, 12); diff --git a/testhal/STM32L1xx/UART/main.c b/testhal/STM32L1xx/UART/main.c index 1039b781d..30f4c3326 100644 --- a/testhal/STM32L1xx/UART/main.c +++ b/testhal/STM32L1xx/UART/main.c @@ -129,8 +129,8 @@ int main(void) { * PA9 and PA10 are routed to USART1. */ uartStart(&UARTD1, &uart_cfg_1); - palSetPadMode(GPIOA, 9, PAL_MODE_ALT_OUTPUT_PUSHPULL(7)); - palSetPadMode(GPIOA, 10, PAL_MODE_ALT_INPUT(7)); + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); /* * Starts the transmission, it will be handled entirely in background. -- cgit v1.2.3 From 62b5054dfabcf9e26bf8e65db351db896c552e75 Mon Sep 17 00:00:00 2001 From: barthess Date: Sat, 17 Sep 2011 21:06:25 +0000 Subject: Shell. Added possibility to create statically allocated shell thread. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3331 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/various/shell.c | 26 ++++++++++++++++++++++++++ os/various/shell.h | 2 ++ 2 files changed, 28 insertions(+) diff --git a/os/various/shell.c b/os/various/shell.c index 5f2fc760b..1fe03fc1e 100644 --- a/os/various/shell.c +++ b/os/various/shell.c @@ -220,6 +220,8 @@ void shellInit(void) { /** * @brief Spawns a new shell. * + * @pre @p CH_USE_MALLOC_HEAP and @p CH_USE_DYNAMIC must be enabled. + * * @param[in] scp pointer to a @p ShellConfig object * @param[in] size size of the shell working area to be allocated * @param[in] prio the priority level for the new shell @@ -227,10 +229,34 @@ void shellInit(void) { * @return A pointer to the shell thread. * @retval NULL thread creation failed because memory allocation. */ +#if CH_USE_HEAP && CH_USE_DYNAMIC Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) { return chThdCreateFromHeap(NULL, size, prio, shell_thread, (void *)scp); } +#endif + +/** + * @brief Create statically allocated shell thread. + * + * @param[in] scp pointer to a @p ShellConfig object + * @param[in] wsp pointer to a working area dedicated to the shell thread stack + * @param[in] size size of the shell working area to be allocated + * @param[in] prio the priority level for the new shell + * + * @return A pointer to the shell thread. + */ +Thread *shellCreateStatic(const ShellConfig *scp, void *wsp, + size_t size, tprio_t prio) { + + return chThdCreateStatic(wsp, size, prio, shell_thread, (void *)scp); +} + + + + + + /** * @brief Reads a whole line from the input channel. diff --git a/os/various/shell.h b/os/various/shell.h index 075d4e264..2946df947 100644 --- a/os/various/shell.h +++ b/os/various/shell.h @@ -80,6 +80,8 @@ extern "C" { #endif void shellInit(void); Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio); + Thread *shellCreateStatic(const ShellConfig *scp, void *wsp, + size_t size, tprio_t prio); bool_t shellGetLine(BaseChannel *chp, char *line, unsigned size); #ifdef __cplusplus } -- cgit v1.2.3 From e48232fcd63b629d9d3f3941b981d9d7c89d2c24 Mon Sep 17 00:00:00 2001 From: barthess Date: Sat, 17 Sep 2011 23:22:24 +0000 Subject: EXT. Added test to waking up from stop mode. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3332 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/EXT_WAKEUP/Makefile | 205 ++++++++++++ testhal/STM32F1xx/EXT_WAKEUP/chconf.h | 535 ++++++++++++++++++++++++++++++++ testhal/STM32F1xx/EXT_WAKEUP/halconf.h | 328 ++++++++++++++++++++ testhal/STM32F1xx/EXT_WAKEUP/main.c | 161 ++++++++++ testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h | 169 ++++++++++ testhal/STM32F1xx/EXT_WAKEUP/readme.txt | 26 ++ 6 files changed, 1424 insertions(+) create mode 100644 testhal/STM32F1xx/EXT_WAKEUP/Makefile create mode 100644 testhal/STM32F1xx/EXT_WAKEUP/chconf.h create mode 100644 testhal/STM32F1xx/EXT_WAKEUP/halconf.h create mode 100644 testhal/STM32F1xx/EXT_WAKEUP/main.c create mode 100644 testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h create mode 100644 testhal/STM32F1xx/EXT_WAKEUP/readme.txt diff --git a/testhal/STM32F1xx/EXT_WAKEUP/Makefile b/testhal/STM32F1xx/EXT_WAKEUP/Makefile new file mode 100644 index 000000000..5f91baee0 --- /dev/null +++ b/testhal/STM32F1xx/EXT_WAKEUP/Makefile @@ -0,0 +1,205 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/EXT_WAKEUP/chconf.h b/testhal/STM32F1xx/EXT_WAKEUP/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F1xx/EXT_WAKEUP/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h new file mode 100644 index 000000000..0bf380473 --- /dev/null +++ b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 9600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/EXT_WAKEUP/main.c b/testhal/STM32F1xx/EXT_WAKEUP/main.c new file mode 100644 index 000000000..36442fa58 --- /dev/null +++ b/testhal/STM32F1xx/EXT_WAKEUP/main.c @@ -0,0 +1,161 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +#include "shell.h" +#include "chprintf.h" + + + +/* Wake up callback.*/ +static void extcb2(EXTDriver *extp, expchannel_t channel) { + + (void)extp; + (void)channel; + + chSysLockFromIsr(); + /* we MUST reinit clocks after waking up*/ + stm32_clock_init(); + + extChannelDisableI(&EXTD1, 10); + chSysUnlockFromIsr(); +} + + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_FALLING_EDGE, extcb2}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + }, + EXT_MODE_EXTI(0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + EXT_MODE_GPIOA, + 0, + 0, + 0, + 0, + 0) +}; + + + +static void cmd_reboot(BaseChannel *chp, int argc, char *argv[]){ + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: rboot\r\n"); + return; + } + chprintf(chp, "rebooting...\r\n"); + SCB->SCR |= SCB_AIRCR_SYSRESETREQ_Msk; +} + +static void cmd_sleep(BaseChannel *chp, int argc, char *argv[]){ + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: sleep\r\n"); + return; + } + chprintf(chp, "going to sleep...\r\ntype any character to wake up..."); + + chThdSleepMilliseconds(200); // timeout to print message in terminal + extChannelEnable(&EXTD1, 10); + chThdSleepMilliseconds(5); + + PWR->CR |= (PWR_CR_CSBF | PWR_CR_CWUF); + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); +} + + +static const ShellCommand commands[] = { + {"reboot", cmd_reboot}, + {"sleep", cmd_sleep}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseChannel *)&SD1, + commands +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* Activates the serial driver using the driver default configuration. */ + sdStart(&SD1, NULL); + + /* Shell manager initialization. */ + shellInit(); + palSetPadMode(IOPORT1, 9, PAL_MODE_STM32_ALTERNATE_PUSHPULL); + palSetPadMode(IOPORT1, 10, PAL_MODE_INPUT); + + static WORKING_AREA(waShell, 512); + shellCreateStatic(&shell_cfg1, waShell, sizeof(waShell), NORMALPRIO); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + chThdSleepMilliseconds(250); + palTogglePad(IOPORT3, GPIOC_LED); + } +} diff --git a/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h new file mode 100644 index 000000000..78ed01659 --- /dev/null +++ b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h @@ -0,0 +1,169 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCO STM32_MCO_NOCLOCK + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F1xx/EXT_WAKEUP/readme.txt b/testhal/STM32F1xx/EXT_WAKEUP/readme.txt new file mode 100644 index 000000000..514c0d5c6 --- /dev/null +++ b/testhal/STM32F1xx/EXT_WAKEUP/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex STM32-P103 board. + +** The Demo ** + +The application demonstrates the use of the STM32 EXT driver. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From c86f3377feac7c6342974cf6e147067bf33d4782 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Sep 2011 09:15:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3333 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/GPT/main.c | 4 +- testhal/STM32L1xx/GPT/Makefile | 202 +++++++++++++++ testhal/STM32L1xx/GPT/chconf.h | 535 +++++++++++++++++++++++++++++++++++++++ testhal/STM32L1xx/GPT/halconf.h | 328 ++++++++++++++++++++++++ testhal/STM32L1xx/GPT/main.c | 94 +++++++ testhal/STM32L1xx/GPT/mcuconf.h | 185 ++++++++++++++ testhal/STM32L1xx/GPT/readme.txt | 26 ++ 7 files changed, 1372 insertions(+), 2 deletions(-) create mode 100644 testhal/STM32L1xx/GPT/Makefile create mode 100644 testhal/STM32L1xx/GPT/chconf.h create mode 100644 testhal/STM32L1xx/GPT/halconf.h create mode 100644 testhal/STM32L1xx/GPT/main.c create mode 100644 testhal/STM32L1xx/GPT/mcuconf.h create mode 100644 testhal/STM32L1xx/GPT/readme.txt diff --git a/testhal/STM32F1xx/GPT/main.c b/testhal/STM32F1xx/GPT/main.c index 57b2977d1..09b3ba9b3 100644 --- a/testhal/STM32F1xx/GPT/main.c +++ b/testhal/STM32F1xx/GPT/main.c @@ -77,9 +77,9 @@ int main(void) { * Initializes the GPT drivers 1 and 2. */ gptStart(&GPTD1, &gpt1cfg); - gptPolledDelay(&GPTD1, 10); /* Small dealy.*/ + gptPolledDelay(&GPTD1, 10); /* Small delay.*/ gptStart(&GPTD2, &gpt2cfg); - gptPolledDelay(&GPTD2, 10); /* Small dealy.*/ + gptPolledDelay(&GPTD2, 10); /* Small delay.*/ /* * Normal main() thread activity, it changes the GPT1 period every diff --git a/testhal/STM32L1xx/GPT/Makefile b/testhal/STM32L1xx/GPT/Makefile new file mode 100644 index 000000000..5efd8bf02 --- /dev/null +++ b/testhal/STM32L1xx/GPT/Makefile @@ -0,0 +1,202 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/testhal/STM32L1xx/GPT/chconf.h b/testhal/STM32L1xx/GPT/chconf.h new file mode 100644 index 000000000..9dd831c96 --- /dev/null +++ b/testhal/STM32L1xx/GPT/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/GPT/halconf.h b/testhal/STM32L1xx/GPT/halconf.h new file mode 100644 index 000000000..ff9202a66 --- /dev/null +++ b/testhal/STM32L1xx/GPT/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/GPT/main.c b/testhal/STM32L1xx/GPT/main.c new file mode 100644 index 000000000..b7e84e557 --- /dev/null +++ b/testhal/STM32L1xx/GPT/main.c @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/* + * GPT1 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + + (void)gptp; + palSetPad(GPIOB, GPIOB_LED4); + chSysLockFromIsr(); + gptStartOneShotI(&GPTD3, 200); /* 0.02 second pulse.*/ + chSysUnlockFromIsr(); +} + +/* + * GPT2 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + + (void)gptp; + palClearPad(GPIOB, GPIOB_LED4); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 10000, /* 10KHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 10000, /* 10KHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the GPT drivers 2 and 3. + */ + gptStart(&GPTD2, &gpt2cfg); + gptPolledDelay(&GPTD2, 10); /* Small delay.*/ + gptStart(&GPTD3, &gpt3cfg); + gptPolledDelay(&GPTD3, 10); /* Small delay.*/ + + /* + * Normal main() thread activity, it changes the GPT1 period every + * five seconds. + */ + while (TRUE) { + gptStartContinuous(&GPTD2, 5000); + chThdSleepMilliseconds(5000); + gptStartContinuous(&GPTD2, 2500); + chThdSleepMilliseconds(5000); + } +} diff --git a/testhal/STM32L1xx/GPT/mcuconf.h b/testhal/STM32L1xx/GPT/mcuconf.h new file mode 100644 index 000000000..b07cb9f6d --- /dev/null +++ b/testhal/STM32L1xx/GPT/mcuconf.h @@ -0,0 +1,185 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_1P8 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/GPT/readme.txt b/testhal/STM32L1xx/GPT/readme.txt new file mode 100644 index 000000000..e1302e645 --- /dev/null +++ b/testhal/STM32L1xx/GPT/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - GPT driver demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx GPT driver. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From e2d701317cc34a5fb669fe816c13364bd136005e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Sep 2011 09:44:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3334 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/GPT/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testhal/STM32L1xx/GPT/main.c b/testhal/STM32L1xx/GPT/main.c index b7e84e557..90e06879a 100644 --- a/testhal/STM32L1xx/GPT/main.c +++ b/testhal/STM32L1xx/GPT/main.c @@ -22,7 +22,7 @@ #include "hal.h" /* - * GPT1 callback. + * GPT2 callback. */ static void gpt2cb(GPTDriver *gptp) { @@ -34,7 +34,7 @@ static void gpt2cb(GPTDriver *gptp) { } /* - * GPT2 callback. + * GPT3 callback. */ static void gpt3cb(GPTDriver *gptp) { -- cgit v1.2.3 From 634578f7c1dd2e63a4664d6bf0438f05236a4311 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Sep 2011 09:57:10 +0000 Subject: Fixed bug 3411180. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3335 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/ADC/Makefile | 2 +- testhal/STM32F1xx/CAN/Makefile | 2 +- testhal/STM32F1xx/GPT/Makefile | 2 +- testhal/STM32F1xx/IRQ_STORM/Makefile | 2 +- testhal/STM32F1xx/PWM-ICU/Makefile | 2 +- testhal/STM32F1xx/SDIO/Makefile | 2 +- testhal/STM32F1xx/SPI/Makefile | 2 +- testhal/STM32F1xx/UART/Makefile | 2 +- testhal/STM32L1xx/GPT/Makefile | 2 +- testhal/STM32L1xx/SPI/Makefile | 2 +- testhal/STM32L1xx/UART/Makefile | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/testhal/STM32F1xx/ADC/Makefile b/testhal/STM32F1xx/ADC/Makefile index f93aeb073..9ae228410 100644 --- a/testhal/STM32F1xx/ADC/Makefile +++ b/testhal/STM32F1xx/ADC/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/CAN/Makefile b/testhal/STM32F1xx/CAN/Makefile index f93aeb073..9ae228410 100644 --- a/testhal/STM32F1xx/CAN/Makefile +++ b/testhal/STM32F1xx/CAN/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/GPT/Makefile b/testhal/STM32F1xx/GPT/Makefile index f93aeb073..9ae228410 100644 --- a/testhal/STM32F1xx/GPT/Makefile +++ b/testhal/STM32F1xx/GPT/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/IRQ_STORM/Makefile b/testhal/STM32F1xx/IRQ_STORM/Makefile index f93aeb073..9ae228410 100644 --- a/testhal/STM32F1xx/IRQ_STORM/Makefile +++ b/testhal/STM32F1xx/IRQ_STORM/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/PWM-ICU/Makefile b/testhal/STM32F1xx/PWM-ICU/Makefile index f93aeb073..9ae228410 100644 --- a/testhal/STM32F1xx/PWM-ICU/Makefile +++ b/testhal/STM32F1xx/PWM-ICU/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/SDIO/Makefile b/testhal/STM32F1xx/SDIO/Makefile index c56c5eadb..71c4ec604 100644 --- a/testhal/STM32F1xx/SDIO/Makefile +++ b/testhal/STM32F1xx/SDIO/Makefile @@ -204,4 +204,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/SPI/Makefile b/testhal/STM32F1xx/SPI/Makefile index f93aeb073..9ae228410 100644 --- a/testhal/STM32F1xx/SPI/Makefile +++ b/testhal/STM32F1xx/SPI/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/UART/Makefile b/testhal/STM32F1xx/UART/Makefile index f93aeb073..9ae228410 100644 --- a/testhal/STM32F1xx/UART/Makefile +++ b/testhal/STM32F1xx/UART/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/GPT/Makefile b/testhal/STM32L1xx/GPT/Makefile index 5efd8bf02..9209b441d 100644 --- a/testhal/STM32L1xx/GPT/Makefile +++ b/testhal/STM32L1xx/GPT/Makefile @@ -199,4 +199,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/SPI/Makefile b/testhal/STM32L1xx/SPI/Makefile index 5efd8bf02..9209b441d 100644 --- a/testhal/STM32L1xx/SPI/Makefile +++ b/testhal/STM32L1xx/SPI/Makefile @@ -199,4 +199,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/UART/Makefile b/testhal/STM32L1xx/UART/Makefile index 5efd8bf02..9209b441d 100644 --- a/testhal/STM32L1xx/UART/Makefile +++ b/testhal/STM32L1xx/UART/Makefile @@ -199,4 +199,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk -- cgit v1.2.3 From 0022c9cd552909ecbd7dac0f2034cbb776d7fd7e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Sep 2011 09:59:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3337 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/readme.txt b/readme.txt index b90ececf5..752703c1d 100644 --- a/readme.txt +++ b/readme.txt @@ -73,6 +73,8 @@ ***************************************************************************** *** 2.3.3 *** +- FIX: Some ARMCMx makefiles refer the file rules.mk in the ARM7 port (bug + 3411180)(backported to 2.2.8). - FIX: Fixed wrong check on CH_DBG_ENABLE_STACK_CHECK setting (bug 3387671) (backported to 2.2.7). - FIX: Fixed wrong APB1 frequency check (bug 3361039)(backported to 2.2.7). -- cgit v1.2.3 From acd4d7c7725e15fdca0422cab7a86b792eb6c245 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Sep 2011 10:07:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3338 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/GPT/mcuconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testhal/STM32L1xx/GPT/mcuconf.h b/testhal/STM32L1xx/GPT/mcuconf.h index b07cb9f6d..d214c9d12 100644 --- a/testhal/STM32L1xx/GPT/mcuconf.h +++ b/testhal/STM32L1xx/GPT/mcuconf.h @@ -123,7 +123,7 @@ #define STM32_PWM_USE_ADVANCED FALSE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM8 FALSE -- cgit v1.2.3 From 94edbcb6cb917c1e5c34384c134cd661dda81d7a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Sep 2011 10:18:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3339 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32L_DISCOVERY/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/ST_STM32L_DISCOVERY/board.h b/boards/ST_STM32L_DISCOVERY/board.h index 9e6802b26..46e2965fd 100644 --- a/boards/ST_STM32L_DISCOVERY/board.h +++ b/boards/ST_STM32L_DISCOVERY/board.h @@ -36,7 +36,7 @@ * NOTE: The HSE crystal is not fitted by default on the board. */ #define STM32_LSECLK 32768 -#define STM32_HSECLK 0 +#define STM32_HSECLK 8000000 /* * MCU type as defined in the ST header file stm32l1xx.h. -- cgit v1.2.3 From 373735d5290c3d0869fe014e4bd93e5d4824c89b Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 18 Sep 2011 11:50:31 +0000 Subject: EXT_WAKEUP test minor improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3340 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/EXT_WAKEUP/main.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/testhal/STM32F1xx/EXT_WAKEUP/main.c b/testhal/STM32F1xx/EXT_WAKEUP/main.c index 36442fa58..26c8f9433 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/main.c +++ b/testhal/STM32F1xx/EXT_WAKEUP/main.c @@ -17,7 +17,6 @@ You should have received a copy of the GNU General Public License along with this program. If not, see . */ - #include "ch.h" #include "hal.h" @@ -87,7 +86,7 @@ static void cmd_reboot(BaseChannel *chp, int argc, char *argv[]){ return; } chprintf(chp, "rebooting...\r\n"); - SCB->SCR |= SCB_AIRCR_SYSRESETREQ_Msk; + NVIC_SystemReset(); } static void cmd_sleep(BaseChannel *chp, int argc, char *argv[]){ @@ -96,9 +95,9 @@ static void cmd_sleep(BaseChannel *chp, int argc, char *argv[]){ chprintf(chp, "Usage: sleep\r\n"); return; } - chprintf(chp, "going to sleep...\r\ntype any character to wake up..."); + chprintf(chp, "Going to sleep. Type any character to wake up.\r\n"); - chThdSleepMilliseconds(200); // timeout to print message in terminal + chThdSleepMilliseconds(200); // time to print out message in terminal extChannelEnable(&EXTD1, 10); chThdSleepMilliseconds(5); @@ -154,8 +153,10 @@ int main(void) { * Normal main() thread activity, in this demo it enables and disables the * button EXT channel using 5 seconds intervals. */ + + chThdSleepMilliseconds(2000); // timeuot to differ reboot and wake up from sleep while (TRUE) { - chThdSleepMilliseconds(250); + chThdSleepMilliseconds(100); palTogglePad(IOPORT3, GPIOC_LED); } } -- cgit v1.2.3 From 07f868d3792cadd6377fdb5039c7cbf27f68bd92 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Sep 2011 18:23:50 +0000 Subject: GPT driver tested on STM32L. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3341 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/GPIOv2/pal_lld.h | 16 +++++----------- testhal/STM32F1xx/GPT/main.c | 2 ++ testhal/STM32L1xx/GPT/Makefile | 2 +- testhal/STM32L1xx/GPT/main.c | 4 ++++ 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h index 6c799c14c..a73f80c7a 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -135,13 +135,7 @@ typedef struct { volatile uint32_t PUPDR; volatile uint32_t IDR; volatile uint32_t ODR; - volatile union { - uint32_t W; - struct { - uint16_t set; - uint16_t clear; - } H; - } BSRR; + volatile uint32_t BSRR; volatile uint32_t LCKR; volatile uint32_t AFRL; volatile uint32_t AFRH; @@ -375,7 +369,7 @@ typedef GPIO_TypeDef * ioportid_t; * * @notapi */ -#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits)) +#define pal_lld_setport(port, bits) ((port)->BSRR = (uint32_t)(bits)) /** * @brief Clears a bits mask on a I/O port. @@ -392,7 +386,7 @@ typedef GPIO_TypeDef * ioportid_t; * * @notapi */ -#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) +#define pal_lld_clearport(port, bits) ((port)->BSRR = (uint32_t)(bits) << 16) /** * @brief Writes a group of bits. @@ -413,8 +407,8 @@ typedef GPIO_TypeDef * ioportid_t; * @notapi */ #define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) | \ - (((bits) & (mask)) << (offset))) + ((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \ + (((bits) & (mask)) << (offset))) /** * @brief Pads group mode setup. diff --git a/testhal/STM32F1xx/GPT/main.c b/testhal/STM32F1xx/GPT/main.c index 09b3ba9b3..e3e0797f8 100644 --- a/testhal/STM32F1xx/GPT/main.c +++ b/testhal/STM32F1xx/GPT/main.c @@ -86,8 +86,10 @@ int main(void) { * five seconds. */ while (TRUE) { + gptStopTimer(&GPTD1); gptStartContinuous(&GPTD1, 5000); chThdSleepMilliseconds(5000); + gptStopTimer(&GPTD1); gptStartContinuous(&GPTD1, 2500); chThdSleepMilliseconds(5000); } diff --git a/testhal/STM32L1xx/GPT/Makefile b/testhal/STM32L1xx/GPT/Makefile index 9209b441d..10a6ed0e8 100644 --- a/testhal/STM32L1xx/GPT/Makefile +++ b/testhal/STM32L1xx/GPT/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C++ specific options here (added to USE_OPT). diff --git a/testhal/STM32L1xx/GPT/main.c b/testhal/STM32L1xx/GPT/main.c index 90e06879a..49247bac6 100644 --- a/testhal/STM32L1xx/GPT/main.c +++ b/testhal/STM32L1xx/GPT/main.c @@ -86,8 +86,12 @@ int main(void) { * five seconds. */ while (TRUE) { + palSetPad(GPIOB, GPIOB_LED3); + gptStopTimer(&GPTD2); gptStartContinuous(&GPTD2, 5000); chThdSleepMilliseconds(5000); + palClearPad(GPIOB, GPIOB_LED3); + gptStopTimer(&GPTD2); gptStartContinuous(&GPTD2, 2500); chThdSleepMilliseconds(5000); } -- cgit v1.2.3 From e1afd2700be6c631f1e74766525724cf95588c3e Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 18 Sep 2011 21:08:42 +0000 Subject: Added RCC helper support to RTC driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3342 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.c | 2 +- os/hal/platforms/STM32F1xx/stm32_rcc.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 4f404ab27..62e114e66 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -112,7 +112,7 @@ CH_IRQ_HANDLER(RTC_IRQHandler) { * @notapi */ void rtc_lld_init(void){ - RCC->APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); /* enable clocking */ + rccEnableBKP(FALSE); /* enable interface clocking */ PWR->CR |= PWR_CR_DBP; /* enable access */ if (!(RCC->BDCR & (RCC_BDCR_RTCEN | RCC_BDCR_LSEON))){ /* BKP domain was reseted */ diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h index 56fa0905c..7735b2034 100644 --- a/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -202,6 +202,38 @@ #define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) /** @} */ +/** + * @brief Bakup domain interface specific RCC operations + * @{ + */ +/** + * @brief Enables the BKP interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableBKP(lp) rccEnableAPB1(RCC_APB1ENR_BKPEN, lp); + +/** + * @brief Disables BKP interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableBKP(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp); + +/** + * @brief Resets the Backup Domain. + * + * @api + */ +#define rccResetBKP(lp) rccResetAPB1(RCC_APB1ENR_BKPRST); +/** @} */ + /** * @brief CAN peripherals specific RCC operations * @{ -- cgit v1.2.3 From bf6ca955f1c2248138d51df53bb3767bd8c63a4b Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 18 Sep 2011 22:35:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3343 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/EXT_WAKEUP/halconf.h | 2 +- testhal/STM32F1xx/EXT_WAKEUP/main.c | 1 + testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h | 20 ++++++++++---------- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h index 0bf380473..ca1d81b24 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h @@ -289,7 +289,7 @@ * default configuration. */ #if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 9600 +#define SERIAL_DEFAULT_BITRATE 38400 #endif /** diff --git a/testhal/STM32F1xx/EXT_WAKEUP/main.c b/testhal/STM32F1xx/EXT_WAKEUP/main.c index 26c8f9433..23c208873 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/main.c +++ b/testhal/STM32F1xx/EXT_WAKEUP/main.c @@ -86,6 +86,7 @@ static void cmd_reboot(BaseChannel *chp, int argc, char *argv[]){ return; } chprintf(chp, "rebooting...\r\n"); + chThdSleepMilliseconds(100); // time to print out message in terminal NVIC_SystemReset(); } diff --git a/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h index 78ed01659..26a7a4945 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h @@ -35,21 +35,21 @@ /* * HAL driver system settings. */ -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 +#define STM32_SW STM32_SW_HSI +//#define STM32_PLLSRC STM32_PLLSRC_HSE +//#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +//#define STM32_PLLMUL_VALUE 9 #define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_USBPRE STM32_USBPRE_DIV1P5 +//#define STM32_USBPRE STM32_USBPRE_DIV1P5 #define STM32_MCO STM32_MCO_NOCLOCK /* * ADC driver system settings. */ -#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() @@ -57,7 +57,7 @@ /* * CAN driver system settings. */ -#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 /* @@ -163,7 +163,7 @@ /* * USB driver system settings. */ -#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_USE_USB1 FALSE #define STM32_USB_LOW_POWER_ON_SUSPEND FALSE #define STM32_USB_USB1_HP_IRQ_PRIORITY 6 #define STM32_USB_USB1_LP_IRQ_PRIORITY 14 -- cgit v1.2.3 From ebb4159a648daef06f9adeaf5a39ec57496408be Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 18 Sep 2011 22:39:46 +0000 Subject: EXT_WAKEUP test minor improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3344 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/EXT_WAKEUP/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testhal/STM32F1xx/EXT_WAKEUP/main.c b/testhal/STM32F1xx/EXT_WAKEUP/main.c index 23c208873..f12a54207 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/main.c +++ b/testhal/STM32F1xx/EXT_WAKEUP/main.c @@ -32,7 +32,7 @@ static void extcb2(EXTDriver *extp, expchannel_t channel) { (void)channel; chSysLockFromIsr(); - /* we MUST reinit clocks after waking up*/ + /* we MUST reinit clocks after waking up if use HSE or HSI+PLL */ stm32_clock_init(); extChannelDisableI(&EXTD1, 10); -- cgit v1.2.3 From 2ce24aa56732a6b80efa461f8a6db4f37fa4215a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Sep 2011 08:56:23 +0000 Subject: PWM and ICU drivers tested on STM32L. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3345 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/GPT/readme.txt | 4 + testhal/STM32L1xx/PWM-ICU/Makefile | 202 +++++++++++++ testhal/STM32L1xx/PWM-ICU/chconf.h | 535 +++++++++++++++++++++++++++++++++++ testhal/STM32L1xx/PWM-ICU/halconf.h | 328 +++++++++++++++++++++ testhal/STM32L1xx/PWM-ICU/main.c | 140 +++++++++ testhal/STM32L1xx/PWM-ICU/mcuconf.h | 185 ++++++++++++ testhal/STM32L1xx/PWM-ICU/readme.txt | 31 ++ testhal/STM32L1xx/SPI/readme.txt | 5 + testhal/STM32L1xx/UART/readme.txt | 6 + 9 files changed, 1436 insertions(+) create mode 100644 testhal/STM32L1xx/PWM-ICU/Makefile create mode 100644 testhal/STM32L1xx/PWM-ICU/chconf.h create mode 100644 testhal/STM32L1xx/PWM-ICU/halconf.h create mode 100644 testhal/STM32L1xx/PWM-ICU/main.c create mode 100644 testhal/STM32L1xx/PWM-ICU/mcuconf.h create mode 100644 testhal/STM32L1xx/PWM-ICU/readme.txt diff --git a/testhal/STM32L1xx/GPT/readme.txt b/testhal/STM32L1xx/GPT/readme.txt index e1302e645..7b561e8f8 100644 --- a/testhal/STM32L1xx/GPT/readme.txt +++ b/testhal/STM32L1xx/GPT/readme.txt @@ -10,6 +10,10 @@ The demo will on an STMicroelectronics STM32L-Discovery board. The application demonstrates the use of the STM32L1xx GPT driver. +** Board Setup ** + +None required. + ** Build Procedure ** The demo has been tested by using the free Codesourcery GCC-based toolchain diff --git a/testhal/STM32L1xx/PWM-ICU/Makefile b/testhal/STM32L1xx/PWM-ICU/Makefile new file mode 100644 index 000000000..10a6ed0e8 --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/Makefile @@ -0,0 +1,202 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/PWM-ICU/chconf.h b/testhal/STM32L1xx/PWM-ICU/chconf.h new file mode 100644 index 000000000..9dd831c96 --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/PWM-ICU/halconf.h b/testhal/STM32L1xx/PWM-ICU/halconf.h new file mode 100644 index 000000000..e5eeb8b7a --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/PWM-ICU/main.c b/testhal/STM32L1xx/PWM-ICU/main.c new file mode 100644 index 000000000..bc33ecb0e --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/main.c @@ -0,0 +1,140 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(GPIOB, GPIOB_LED4); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(GPIOB, GPIOB_LED4); +} + +static PWMConfig pwmcfg = { + 10000, /* 10KHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(GPIOB, GPIOB_LED3); + last_width = icuGetWidthI(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(GPIOB, GPIOB_LED3); + last_period = icuGetPeriodI(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10KHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 2 and ICU driver 3. + * GPIOA15 is the PWM output. + * GPIOC6 is the ICU input. + * The two pins have to be externally connected together. + */ + pwmStart(&PWMD2, &pwmcfg); + palSetPadMode(GPIOA, 15, PAL_MODE_ALTERNATE(1)); + icuStart(&ICUD3, &icucfg); + palSetPadMode(GPIOC, 6, PAL_MODE_ALTERNATE(2)); + icuEnable(&ICUD3); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD2, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD2, 0); + pwmStop(&PWMD2); + icuDisable(&ICUD3); + icuStop(&ICUD3); + palClearPad(GPIOB, GPIOB_LED3); + palClearPad(GPIOB, GPIOB_LED4); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32L1xx/PWM-ICU/mcuconf.h b/testhal/STM32L1xx/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..ac551ee4f --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/mcuconf.h @@ -0,0 +1,185 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_1P8 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/PWM-ICU/readme.txt b/testhal/STM32L1xx/PWM-ICU/readme.txt new file mode 100644 index 000000000..f55cf8471 --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx PWM-ICU drivers. + +** Board Setup ** + +- Remove the LCD module. +- Connect PA15 and PC6 together. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/SPI/readme.txt b/testhal/STM32L1xx/SPI/readme.txt index eead6ffd9..1d0499baa 100644 --- a/testhal/STM32L1xx/SPI/readme.txt +++ b/testhal/STM32L1xx/SPI/readme.txt @@ -10,6 +10,11 @@ The demo runs on an STMicroelectronics STM32L-Discovery board. The application demonstrates the use of the STM32L1xx SPI driver. +** Board Setup ** + +- Remove the LCD module. +- Connect PB14 and PB15 together for SPI loop-back. + ** Build Procedure ** The demo has been tested by using the free Codesourcery GCC-based toolchain diff --git a/testhal/STM32L1xx/UART/readme.txt b/testhal/STM32L1xx/UART/readme.txt index e52a79d4a..ac65242ac 100644 --- a/testhal/STM32L1xx/UART/readme.txt +++ b/testhal/STM32L1xx/UART/readme.txt @@ -10,6 +10,12 @@ The demo runs on an STMicroelectronics STM32L-Discovery board. The application demonstrates the use of the STM32L1xx UART driver. +** Board Setup ** + +- Remove the LCD module. +- Connect an RS232 transceiver to pins PA9(TX) and PA10(RX). +- Connect a terminal emulator to the transceiver (38400-N-8-1). + ** Build Procedure ** The demo has been tested by using the free Codesourcery GCC-based toolchain -- cgit v1.2.3 From 3b722ddd33c72c9101bd622a0ae6f8699d1fd46a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Sep 2011 09:33:03 +0000 Subject: IRQ_STORM test added to STM32L. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3346 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/GPT/Makefile | 2 +- testhal/STM32L1xx/IRQ_STORM/Makefile | 202 ++ testhal/STM32L1xx/IRQ_STORM/chconf.h | 535 +++ testhal/STM32L1xx/IRQ_STORM/halconf.h | 328 ++ testhal/STM32L1xx/IRQ_STORM/main.c | 326 ++ testhal/STM32L1xx/IRQ_STORM/main.lst | 6048 ++++++++++++++++++++++++++++++++ testhal/STM32L1xx/IRQ_STORM/mcuconf.h | 185 + testhal/STM32L1xx/IRQ_STORM/readme.txt | 31 + testhal/STM32L1xx/PWM-ICU/Makefile | 2 +- 9 files changed, 7657 insertions(+), 2 deletions(-) create mode 100644 testhal/STM32L1xx/IRQ_STORM/Makefile create mode 100644 testhal/STM32L1xx/IRQ_STORM/chconf.h create mode 100644 testhal/STM32L1xx/IRQ_STORM/halconf.h create mode 100644 testhal/STM32L1xx/IRQ_STORM/main.c create mode 100644 testhal/STM32L1xx/IRQ_STORM/main.lst create mode 100644 testhal/STM32L1xx/IRQ_STORM/mcuconf.h create mode 100644 testhal/STM32L1xx/IRQ_STORM/readme.txt diff --git a/testhal/STM32L1xx/GPT/Makefile b/testhal/STM32L1xx/GPT/Makefile index 10a6ed0e8..9209b441d 100644 --- a/testhal/STM32L1xx/GPT/Makefile +++ b/testhal/STM32L1xx/GPT/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C++ specific options here (added to USE_OPT). diff --git a/testhal/STM32L1xx/IRQ_STORM/Makefile b/testhal/STM32L1xx/IRQ_STORM/Makefile new file mode 100644 index 000000000..9209b441d --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/Makefile @@ -0,0 +1,202 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/IRQ_STORM/chconf.h b/testhal/STM32L1xx/IRQ_STORM/chconf.h new file mode 100644 index 000000000..9dd831c96 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/IRQ_STORM/halconf.h b/testhal/STM32L1xx/IRQ_STORM/halconf.h new file mode 100644 index 000000000..f5e7cc1ed --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/IRQ_STORM/main.c b/testhal/STM32L1xx/IRQ_STORM/main.c new file mode 100644 index 000000000..d3c7a6521 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/main.c @@ -0,0 +1,326 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIOB, GPIOB_LED4); + } + } + } +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chIOPut(&SD1, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chIOPut(&SD1, *p++); + } + chIOWriteTimeout(&SD1, (uint8_t *)"\r\n", 2, TIME_INFINITE); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chIOPut(&SD1, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chIOPut(&SD1, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 1 and GPT drivers 2 and 3. + */ + sdStart(&SD1, NULL); /* Default is 38400-8-N-1.*/ + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); + gptStart(&GPTD2, &gpt2cfg); + gptStart(&GPTD3, &gpt3cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); +#ifdef __GNUC__ + print("*** GCC Version: "); + println(__VERSION__); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 20; interval -= interval / 10) { + gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } + return 0; +} diff --git a/testhal/STM32L1xx/IRQ_STORM/main.lst b/testhal/STM32L1xx/IRQ_STORM/main.lst new file mode 100644 index 000000000..7b4c43cc3 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/main.lst @@ -0,0 +1,6048 @@ +ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 1 + + + 1 .syntax unified + 2 .cpu cortex-m3 + 3 .fpu softvfp + 4 .eabi_attribute 20, 1 + 5 .eabi_attribute 21, 1 + 6 .eabi_attribute 23, 3 + 7 .eabi_attribute 24, 1 + 8 .eabi_attribute 25, 1 + 9 .eabi_attribute 26, 1 + 10 .eabi_attribute 30, 2 + 11 .eabi_attribute 18, 4 + 12 .thumb + 13 .file "main.c" + 14 .text + 15 .Ltext0: + 16 .cfi_sections .debug_frame + 17 .section .text.println,"ax",%progbits + 18 .align 2 + 19 .p2align 4,,15 + 20 .thumb + 21 .thumb_func + 22 .type println, %function + 23 println: + 24 .LFB66: + 25 .file 1 "main.c" + 26 .loc 1 177 0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 0 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 .LVL0: + 31 0000 38B5 push {r3, r4, r5, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 16 + 34 .cfi_offset 14, -4 + 35 .cfi_offset 5, -8 + 36 .cfi_offset 4, -12 + 37 .cfi_offset 3, -16 + 38 .loc 1 179 0 + 39 0002 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 + 40 0004 0A4D ldr r5, .L8 + 41 0006 0446 mov r4, r0 + 42 0008 49B1 cbz r1, .L2 + 43 .LVL1: + 44 .L3: + 45 .loc 1 180 0 + 46 000a 2B68 ldr r3, [r5, #0] + 47 000c 0848 ldr r0, .L8 + 48 000e 1B69 ldr r3, [r3, #16] + 49 0010 4FF0FF32 mov r2, #-1 + 50 0014 9847 blx r3 + 51 .loc 1 179 0 + 52 0016 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 53 001a 0029 cmp r1, #0 + 54 001c F5D1 bne .L3 + 55 .L2: + 56 .loc 1 182 0 + 57 001e 2B68 ldr r3, [r5, #0] + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 2 + + + 58 0020 0449 ldr r1, .L8+4 + 59 0022 9C69 ldr r4, [r3, #24] + 60 0024 0222 movs r2, #2 + 61 0026 4FF0FF33 mov r3, #-1 + 62 002a 0148 ldr r0, .L8 + 63 002c A047 blx r4 + 64 .loc 1 183 0 + 65 002e 38BD pop {r3, r4, r5, pc} + 66 .L9: + 67 .align 2 + 68 .L8: + 69 0030 00000000 .word SD1 + 70 0034 00000000 .word .LC0 + 71 .cfi_endproc + 72 .LFE66: + 73 .size println, .-println + 74 0038 AFF30080 .section .text.gpt3cb,"ax",%progbits + 74 AFF30080 + 75 .align 2 + 76 .p2align 4,,15 + 77 .thumb + 78 .thumb_func + 79 .type gpt3cb, %function + 80 gpt3cb: + 81 .LFB64: + 82 .loc 1 138 0 + 83 .cfi_startproc + 84 @ args = 0, pretend = 0, frame = 0 + 85 @ frame_needed = 0, uses_anonymous_args = 0 + 86 .LVL2: + 87 0000 08B5 push {r3, lr} + 88 .LCFI1: + 89 .cfi_def_cfa_offset 8 + 90 .cfi_offset 14, -4 + 91 .cfi_offset 3, -8 + 92 .LBB34: + 93 .loc 1 142 0 + 94 0002 2023 movs r3, #32 + 95 .LVL3: + 96 @ 142 "main.c" 1 + 97 0004 83F31188 msr BASEPRI, r3 + 98 @ 0 "" 2 + 99 .LVL4: + 100 .thumb + 101 .LBE34: + 102 .loc 1 143 0 + 103 0008 0548 ldr r0, .L12 + 104 .LVL5: + 105 000a 0021 movs r1, #0 + 106 000c FFF7FEFF bl chMBPostI + 107 .LVL6: + 108 .loc 1 144 0 + 109 0010 10B1 cbz r0, .L11 + 110 .loc 1 145 0 + 111 0012 044B ldr r3, .L12+4 + 112 0014 0122 movs r2, #1 + 113 0016 1A60 str r2, [r3, #0] + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 3 + + + 114 .L11: + 115 .LBB35: + 116 .loc 1 146 0 + 117 0018 0023 movs r3, #0 + 118 .LVL7: + 119 @ 146 "main.c" 1 + 120 001a 83F31188 msr BASEPRI, r3 + 121 @ 0 "" 2 + 122 .LVL8: + 123 .thumb + 124 .LBE35: + 125 .loc 1 147 0 + 126 001e 08BD pop {r3, pc} + 127 .L13: + 128 .align 2 + 129 .L12: + 130 0020 78000000 .word .LANCHOR0+120 + 131 0024 00000000 .word .LANCHOR1 + 132 .cfi_endproc + 133 .LFE64: + 134 .size gpt3cb, .-gpt3cb + 135 0028 AFF30080 .section .text.gpt2cb,"ax",%progbits + 135 AFF30080 + 136 .align 2 + 137 .p2align 4,,15 + 138 .thumb + 139 .thumb_func + 140 .type gpt2cb, %function + 141 gpt2cb: + 142 .LFB63: + 143 .loc 1 124 0 + 144 .cfi_startproc + 145 @ args = 0, pretend = 0, frame = 0 + 146 @ frame_needed = 0, uses_anonymous_args = 0 + 147 .LVL9: + 148 0000 08B5 push {r3, lr} + 149 .LCFI2: + 150 .cfi_def_cfa_offset 8 + 151 .cfi_offset 14, -4 + 152 .cfi_offset 3, -8 + 153 .LBB36: + 154 .loc 1 128 0 + 155 0002 2023 movs r3, #32 + 156 .LVL10: + 157 @ 128 "main.c" 1 + 158 0004 83F31188 msr BASEPRI, r3 + 159 @ 0 "" 2 + 160 .LVL11: + 161 .thumb + 162 .LBE36: + 163 .loc 1 129 0 + 164 0008 0548 ldr r0, .L16 + 165 .LVL12: + 166 000a 0121 movs r1, #1 + 167 000c FFF7FEFF bl chMBPostI + 168 .LVL13: + 169 .loc 1 130 0 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 4 + + + 170 0010 10B1 cbz r0, .L15 + 171 .loc 1 131 0 + 172 0012 044B ldr r3, .L16+4 + 173 0014 0122 movs r2, #1 + 174 0016 1A60 str r2, [r3, #0] + 175 .L15: + 176 .LBB37: + 177 .loc 1 132 0 + 178 0018 0023 movs r3, #0 + 179 .LVL14: + 180 @ 132 "main.c" 1 + 181 001a 83F31188 msr BASEPRI, r3 + 182 @ 0 "" 2 + 183 .LVL15: + 184 .thumb + 185 .LBE37: + 186 .loc 1 133 0 + 187 001e 08BD pop {r3, pc} + 188 .L17: + 189 .align 2 + 190 .L16: + 191 0020 00000000 .word .LANCHOR0 + 192 0024 00000000 .word .LANCHOR1 + 193 .cfi_endproc + 194 .LFE63: + 195 .size gpt2cb, .-gpt2cb + 196 0028 AFF30080 .section .text.WorkerThread,"ax",%progbits + 196 AFF30080 + 197 .align 2 + 198 .p2align 4,,15 + 199 .thumb + 200 .thumb_func + 201 .type WorkerThread, %function + 202 WorkerThread: + 203 .LFB62: + 204 .loc 1 65 0 + 205 .cfi_startproc + 206 @ args = 0, pretend = 0, frame = 8 + 207 @ frame_needed = 0, uses_anonymous_args = 0 + 208 .LVL16: + 209 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 210 .LCFI3: + 211 .cfi_def_cfa_offset 36 + 212 .cfi_offset 14, -4 + 213 .cfi_offset 11, -8 + 214 .cfi_offset 10, -12 + 215 .cfi_offset 9, -16 + 216 .cfi_offset 8, -20 + 217 .cfi_offset 7, -24 + 218 .cfi_offset 6, -28 + 219 .cfi_offset 5, -32 + 220 .cfi_offset 4, -36 + 221 .loc 1 73 0 + 222 0004 244B ldr r3, .L31 + 223 0006 DFF8A0B0 ldr fp, .L31+16 + 224 000a DB69 ldr r3, [r3, #28] + 225 000c 234E ldr r6, .L31+4 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 5 + + + 226 000e 244A ldr r2, .L31+8 + 227 .loc 1 78 0 + 228 0010 00EB8007 add r7, r0, r0, lsl #2 + 229 0014 234C ldr r4, .L31+12 + 230 .loc 1 65 0 + 231 0016 83B0 sub sp, sp, #12 + 232 .LCFI4: + 233 .cfi_def_cfa_offset 48 + 234 .loc 1 73 0 + 235 0018 9A61 str r2, [r3, #24] + 236 001a 0509 lsrs r5, r0, #4 + 237 001c 00F1FF39 add r9, r0, #-1 + 238 0020 00F10108 add r8, r0, #1 + 239 .loc 1 78 0 + 240 0024 0BEBC707 add r7, fp, r7, lsl #3 + 241 .loc 1 113 0 + 242 0028 B246 mov sl, r6 + 243 .LVL17: + 244 .L29: + 245 .loc 1 78 0 + 246 002a 3846 mov r0, r7 + 247 .LVL18: + 248 002c 01A9 add r1, sp, #4 + 249 002e 4FF0FF32 mov r2, #-1 + 250 0032 FFF7FEFF bl chMBFetch + 251 .LVL19: + 252 .loc 1 93 0 + 253 0036 2DB1 cbz r5, .L20 + 254 0038 2B46 mov r3, r5 + 255 .LVL20: + 256 .L21: + 257 .loc 1 94 0 + 258 003a 2268 ldr r2, [r4, #0] + 259 003c 0132 adds r2, r2, #1 + 260 .loc 1 93 0 + 261 003e 013B subs r3, r3, #1 + 262 .loc 1 94 0 + 263 0040 2260 str r2, [r4, #0] + 264 .loc 1 93 0 + 265 0042 FAD1 bne .L21 + 266 .L20: + 267 .loc 1 99 0 + 268 0044 0199 ldr r1, [sp, #4] + 269 .loc 1 100 0 + 270 0046 0029 cmp r1, #0 + 271 0048 14BF ite ne + 272 004a 4346 movne r3, r8 + 273 004c 4B46 moveq r3, r9 + 274 .LVL21: + 275 .loc 1 104 0 + 276 004e 032B cmp r3, #3 + 277 0050 11D9 bls .L30 + 278 .loc 1 113 0 + 279 0052 3368 ldr r3, [r6, #0] + 280 .LVL22: + 281 0054 0133 adds r3, r3, #1 + 282 0056 B3F5FA7F cmp r3, #500 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 6 + + + 283 005a 3360 str r3, [r6, #0] + 284 005c E5D3 bcc .L29 + 285 .loc 1 114 0 + 286 005e 0022 movs r2, #0 + 287 .loc 1 115 0 + 288 0060 4FF48063 mov r3, #1024 + 289 .loc 1 114 0 + 290 0064 CAF80020 str r2, [sl, #0] + 291 .loc 1 115 0 + 292 0068 C4F20203 movt r3, 16386 + 293 006c 5A69 ldr r2, [r3, #20] + 294 006e 82F04002 eor r2, r2, #64 + 295 0072 5A61 str r2, [r3, #20] + 296 0074 D9E7 b .L29 + 297 .LVL23: + 298 .L30: + 299 .loc 1 107 0 + 300 0076 03EB8303 add r3, r3, r3, lsl #2 + 301 .LVL24: + 302 007a 0BEBC300 add r0, fp, r3, lsl #3 + 303 007e 0022 movs r2, #0 + 304 0080 FFF7FEFF bl chMBPost + 305 0084 0190 str r0, [sp, #4] + 306 .loc 1 108 0 + 307 0086 0028 cmp r0, #0 + 308 0088 CFD0 beq .L29 + 309 .loc 1 109 0 + 310 008a 40F20002 movw r2, #:lower16:.LANCHOR1 + 311 008e 0123 movs r3, #1 + 312 0090 C0F20002 movt r2, #:upper16:.LANCHOR1 + 313 0094 1360 str r3, [r2, #0] + 314 0096 C8E7 b .L29 + 315 .L32: + 316 .align 2 + 317 .L31: + 318 0098 00000000 .word rlist + 319 009c 00000000 .word .LANCHOR3 + 320 00a0 04000000 .word .LC1 + 321 00a4 00000000 .word .LANCHOR2 + 322 00a8 00000000 .word .LANCHOR0 + 323 .cfi_endproc + 324 .LFE62: + 325 .size WorkerThread, .-WorkerThread + 326 00ac AFF30080 .section .text.printn,"ax",%progbits + 327 .align 2 + 328 .p2align 4,,15 + 329 .thumb + 330 .thumb_func + 331 .type printn, %function + 332 printn: + 333 .LFB67: + 334 .loc 1 185 0 + 335 .cfi_startproc + 336 @ args = 0, pretend = 0, frame = 16 + 337 @ frame_needed = 0, uses_anonymous_args = 0 + 338 .LVL25: + 339 0000 70B5 push {r4, r5, r6, lr} + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 7 + + + 340 .LCFI5: + 341 .cfi_def_cfa_offset 16 + 342 .cfi_offset 14, -4 + 343 .cfi_offset 6, -8 + 344 .cfi_offset 5, -12 + 345 .cfi_offset 4, -16 + 346 0002 84B0 sub sp, sp, #16 + 347 .LCFI6: + 348 .cfi_def_cfa_offset 32 + 349 .loc 1 188 0 + 350 0004 0028 cmp r0, #0 + 351 0006 24D0 beq .L39 + 352 .loc 1 193 0 + 353 0008 4CF6CD42 movw r2, #52429 + 354 .LBB40: + 355 .LBB41: + 356 .loc 1 191 0 + 357 000c 6D46 mov r5, sp + 358 .LBE41: + 359 .LBE40: + 360 .loc 1 188 0 + 361 000e 6C46 mov r4, sp + 362 .loc 1 193 0 + 363 0010 CCF6CC42 movt r2, 52428 + 364 .LVL26: + 365 .L36: + 366 0014 A2FB0013 umull r1, r3, r2, r0 + 367 0018 DB08 lsrs r3, r3, #3 + 368 001a 03EB8301 add r1, r3, r3, lsl #2 + 369 001e A0EB4101 sub r1, r0, r1, lsl #1 + 370 0022 3031 adds r1, r1, #48 + 371 0024 C9B2 uxtb r1, r1 + 372 .loc 1 192 0 + 373 0026 1846 mov r0, r3 + 374 .loc 1 193 0 + 375 0028 04F8011B strb r1, [r4], #1 + 376 .LVL27: + 377 .loc 1 192 0 + 378 002c 002B cmp r3, #0 + 379 002e F1D1 bne .L36 + 380 .loc 1 194 0 + 381 0030 AC42 cmp r4, r5 + 382 0032 0CD9 bls .L33 + 383 0034 0B4E ldr r6, .L41 + 384 .loc 1 185 0 + 385 0036 013C subs r4, r4, #1 + 386 .LVL28: + 387 0038 01E0 b .L37 + 388 .LVL29: + 389 .L40: + 390 .loc 1 194 0 + 391 003a 14F8011D ldrb r1, [r4, #-1]! @ zero_extendqisi2 + 392 .L37: + 393 .loc 1 195 0 + 394 003e 3368 ldr r3, [r6, #0] + 395 0040 0848 ldr r0, .L41 + 396 0042 1B69 ldr r3, [r3, #16] + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 8 + + + 397 0044 4FF0FF32 mov r2, #-1 + 398 0048 9847 blx r3 + 399 .loc 1 194 0 + 400 004a AC42 cmp r4, r5 + 401 004c F5D1 bne .L40 + 402 .L33: + 403 .loc 1 197 0 + 404 004e 04B0 add sp, sp, #16 + 405 0050 70BD pop {r4, r5, r6, pc} + 406 .LVL30: + 407 .L39: + 408 .LBB43: + 409 .LBB42: + 410 .loc 1 189 0 + 411 0052 0448 ldr r0, .L41 + 412 .LVL31: + 413 0054 3021 movs r1, #48 + 414 0056 0368 ldr r3, [r0, #0] + 415 0058 4FF0FF32 mov r2, #-1 + 416 005c 1B69 ldr r3, [r3, #16] + 417 005e 9847 blx r3 + 418 0060 F5E7 b .L33 + 419 .L42: + 420 0062 00BF .align 2 + 421 .L41: + 422 0064 00000000 .word SD1 + 423 .LBE42: + 424 .LBE43: + 425 .cfi_endproc + 426 .LFE67: + 427 .size printn, .-printn + 428 0068 AFF30080 .section .text.startup.main,"ax",%progbits + 428 AFF30080 + 429 .align 2 + 430 .p2align 4,,15 + 431 .global main + 432 .thumb + 433 .thumb_func + 434 .type main, %function + 435 main: + 436 .LFB68: + 437 .loc 1 202 0 + 438 .cfi_startproc + 439 @ args = 0, pretend = 0, frame = 8 + 440 @ frame_needed = 0, uses_anonymous_args = 0 + 441 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, sl, lr} + 442 .LCFI7: + 443 .cfi_def_cfa_offset 32 + 444 .cfi_offset 14, -4 + 445 .cfi_offset 10, -8 + 446 .cfi_offset 9, -12 + 447 .cfi_offset 8, -16 + 448 .cfi_offset 7, -20 + 449 .cfi_offset 6, -24 + 450 .cfi_offset 5, -28 + 451 .cfi_offset 4, -32 + 452 0004 84B0 sub sp, sp, #16 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 9 + + + 453 .LCFI8: + 454 .cfi_def_cfa_offset 48 + 455 .loc 1 213 0 + 456 0006 FFF7FEFF bl halInit + 457 .loc 1 214 0 + 458 000a FFF7FEFF bl chSysInit + 459 .loc 1 219 0 + 460 000e 9048 ldr r0, .L84 + 461 0010 0021 movs r1, #0 + 462 0012 FFF7FEFF bl sdStart + 463 .loc 1 220 0 + 464 0016 0020 movs r0, #0 + 465 0018 C4F20200 movt r0, 16386 + 466 001c 4FF40071 mov r1, #512 + 467 0020 40F28232 movw r2, #898 + 468 0024 FFF7FEFF bl _pal_lld_setgroupmode + 469 .loc 1 221 0 + 470 0028 0020 movs r0, #0 + 471 002a 40F28232 movw r2, #898 + 472 002e C4F20200 movt r0, 16386 + 473 0032 4FF48061 mov r1, #1024 + 474 0036 FFF7FEFF bl _pal_lld_setgroupmode + 475 .loc 1 222 0 + 476 003a 8648 ldr r0, .L84+4 + 477 003c 8649 ldr r1, .L84+8 + 478 003e FFF7FEFF bl gptStart + 479 .loc 1 223 0 + 480 0042 8648 ldr r0, .L84+12 + 481 0044 8649 ldr r1, .L84+16 + 482 0046 FFF7FEFF bl gptStart + 483 .LVL32: + 484 .loc 1 229 0 + 485 004a 864E ldr r6, .L84+20 + 486 .loc 1 230 0 + 487 004c 864D ldr r5, .L84+24 + 488 004e 874F ldr r7, .L84+28 + 489 .loc 1 228 0 + 490 0050 0024 movs r4, #0 + 491 .LVL33: + 492 .L44: + 493 .loc 1 229 0 discriminator 2 + 494 0052 04EB8400 add r0, r4, r4, lsl #2 + 495 0056 3146 mov r1, r6 + 496 0058 0422 movs r2, #4 + 497 005a 07EBC000 add r0, r7, r0, lsl #3 + 498 005e FFF7FEFF bl chMBInit + 499 .loc 1 230 0 discriminator 2 + 500 0062 0094 str r4, [sp, #0] + 501 0064 2846 mov r0, r5 + 502 0066 2C22 movs r2, #44 + 503 0068 4FF49071 mov r1, #288 + 504 006c 804B ldr r3, .L84+32 + 505 .loc 1 228 0 discriminator 2 + 506 006e 0134 adds r4, r4, #1 + 507 .loc 1 230 0 discriminator 2 + 508 0070 FFF7FEFF bl chThdCreateStatic + 509 .LVL34: + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 10 + + + 510 .loc 1 228 0 discriminator 2 + 511 0074 1036 adds r6, r6, #16 + 512 0076 042C cmp r4, #4 + 513 0078 05F59075 add r5, r5, #288 + 514 007c E9D1 bne .L44 + 515 .loc 1 237 0 + 516 007e 7D48 ldr r0, .L84+36 + 517 0080 FFF7FEFF bl println + 518 .loc 1 238 0 + 519 0084 7C48 ldr r0, .L84+40 + 520 0086 FFF7FEFF bl println + 521 .loc 1 239 0 + 522 008a 7C4C ldr r4, .L84+44 + 523 .LVL35: + 524 008c 7C48 ldr r0, .L84+48 + 525 008e 704D ldr r5, .L84 + 526 0090 FFF7FEFF bl println + 527 .LVL36: + 528 .loc 1 172 0 + 529 0094 2A21 movs r1, #42 + 530 .LVL37: + 531 .L45: + 532 .LBB44: + 533 .LBB45: + 534 .loc 1 173 0 + 535 0096 2B68 ldr r3, [r5, #0] + 536 0098 6D48 ldr r0, .L84 + 537 009a 1B69 ldr r3, [r3, #16] + 538 009c 4FF0FF32 mov r2, #-1 + 539 00a0 9847 blx r3 + 540 .loc 1 172 0 + 541 00a2 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 542 00a6 0029 cmp r1, #0 + 543 00a8 F5D1 bne .L45 + 544 .LBE45: + 545 .LBE44: + 546 .loc 1 241 0 + 547 00aa 7648 ldr r0, .L84+52 + 548 00ac 764C ldr r4, .L84+56 + 549 00ae FFF7FEFF bl println + 550 .LVL38: + 551 .loc 1 172 0 + 552 00b2 2A21 movs r1, #42 + 553 .LVL39: + 554 .L46: + 555 .LBB46: + 556 .LBB47: + 557 .loc 1 173 0 + 558 00b4 2B68 ldr r3, [r5, #0] + 559 00b6 6648 ldr r0, .L84 + 560 00b8 1B69 ldr r3, [r3, #16] + 561 00ba 4FF0FF32 mov r2, #-1 + 562 00be 9847 blx r3 + 563 .loc 1 172 0 + 564 00c0 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 565 00c4 0029 cmp r1, #0 + 566 00c6 F5D1 bne .L46 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 11 + + + 567 .LBE47: + 568 .LBE46: + 569 .loc 1 244 0 + 570 00c8 7048 ldr r0, .L84+60 + 571 00ca 714C ldr r4, .L84+64 + 572 00cc FFF7FEFF bl println + 573 .LVL40: + 574 .loc 1 172 0 + 575 00d0 2A21 movs r1, #42 + 576 .LVL41: + 577 .L47: + 578 .LBB48: + 579 .LBB49: + 580 .loc 1 173 0 + 581 00d2 2B68 ldr r3, [r5, #0] + 582 00d4 5E48 ldr r0, .L84 + 583 00d6 1B69 ldr r3, [r3, #16] + 584 00d8 4FF0FF32 mov r2, #-1 + 585 00dc 9847 blx r3 + 586 .loc 1 172 0 + 587 00de 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 588 00e2 0029 cmp r1, #0 + 589 00e4 F5D1 bne .L47 + 590 .LBE49: + 591 .LBE48: + 592 .loc 1 247 0 + 593 00e6 6B48 ldr r0, .L84+68 + 594 00e8 6B4C ldr r4, .L84+72 + 595 00ea FFF7FEFF bl println + 596 .LVL42: + 597 .loc 1 172 0 + 598 00ee 2A21 movs r1, #42 + 599 .LVL43: + 600 .L48: + 601 .LBB50: + 602 .LBB51: + 603 .loc 1 173 0 + 604 00f0 2B68 ldr r3, [r5, #0] + 605 00f2 5748 ldr r0, .L84 + 606 00f4 1B69 ldr r3, [r3, #16] + 607 00f6 4FF0FF32 mov r2, #-1 + 608 00fa 9847 blx r3 + 609 .loc 1 172 0 + 610 00fc 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 611 0100 0029 cmp r1, #0 + 612 0102 F5D1 bne .L48 + 613 .LBE51: + 614 .LBE50: + 615 .loc 1 250 0 + 616 0104 6548 ldr r0, .L84+76 + 617 0106 664C ldr r4, .L84+80 + 618 0108 FFF7FEFF bl println + 619 .LVL44: + 620 .loc 1 172 0 + 621 010c 2A21 movs r1, #42 + 622 .LVL45: + 623 .L49: + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 12 + + + 624 .LBB52: + 625 .LBB53: + 626 .loc 1 173 0 + 627 010e 2B68 ldr r3, [r5, #0] + 628 0110 4F48 ldr r0, .L84 + 629 0112 1B69 ldr r3, [r3, #16] + 630 0114 4FF0FF32 mov r2, #-1 + 631 0118 9847 blx r3 + 632 .loc 1 172 0 + 633 011a 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 634 011e 0029 cmp r1, #0 + 635 0120 F5D1 bne .L49 + 636 .LBE53: + 637 .LBE52: + 638 .loc 1 254 0 + 639 0122 6048 ldr r0, .L84+84 + 640 0124 604C ldr r4, .L84+88 + 641 0126 FFF7FEFF bl println + 642 .LVL46: + 643 .loc 1 172 0 + 644 012a 2A21 movs r1, #42 + 645 .LVL47: + 646 .L50: + 647 .LBB54: + 648 .LBB55: + 649 .loc 1 173 0 + 650 012c 2B68 ldr r3, [r5, #0] + 651 012e 4848 ldr r0, .L84 + 652 0130 1B69 ldr r3, [r3, #16] + 653 0132 4FF0FF32 mov r2, #-1 + 654 0136 9847 blx r3 + 655 .loc 1 172 0 + 656 0138 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 657 013c 0029 cmp r1, #0 + 658 013e F5D1 bne .L50 + 659 .LBE55: + 660 .LBE54: + 661 .loc 1 258 0 + 662 0140 5A48 ldr r0, .L84+92 + 663 0142 FFF7FEFF bl println + 664 .loc 1 260 0 + 665 0146 5A4C ldr r4, .L84+96 + 666 0148 4D48 ldr r0, .L84+48 + 667 014a FFF7FEFF bl println + 668 .LVL48: + 669 .loc 1 172 0 + 670 014e 2A21 movs r1, #42 + 671 .LVL49: + 672 .L51: + 673 .LBB56: + 674 .LBB57: + 675 .loc 1 173 0 + 676 0150 2B68 ldr r3, [r5, #0] + 677 0152 3F48 ldr r0, .L84 + 678 0154 1B69 ldr r3, [r3, #16] + 679 0156 4FF0FF32 mov r2, #-1 + 680 015a 9847 blx r3 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 13 + + + 681 .loc 1 172 0 + 682 015c 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 683 0160 0029 cmp r1, #0 + 684 0162 F5D1 bne .L51 + 685 .LBE57: + 686 .LBE56: + 687 .loc 1 262 0 + 688 0164 4FF49040 mov r0, #18432 + 689 0168 C0F2E810 movt r0, 488 + 690 016c FFF7FEFF bl printn + 691 .loc 1 263 0 + 692 0170 504C ldr r4, .L84+100 + 693 0172 4048 ldr r0, .L84+36 + 694 0174 FFF7FEFF bl println + 695 .LVL50: + 696 .loc 1 172 0 + 697 0178 2A21 movs r1, #42 + 698 .LVL51: + 699 .L52: + 700 .LBB58: + 701 .LBB59: + 702 .loc 1 173 0 + 703 017a 2B68 ldr r3, [r5, #0] + 704 017c 3448 ldr r0, .L84 + 705 017e 1B69 ldr r3, [r3, #16] + 706 0180 4FF0FF32 mov r2, #-1 + 707 0184 9847 blx r3 + 708 .loc 1 172 0 + 709 0186 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 710 018a 0029 cmp r1, #0 + 711 018c F5D1 bne .L52 + 712 .LBE59: + 713 .LBE58: + 714 .loc 1 265 0 + 715 018e 6420 movs r0, #100 + 716 0190 FFF7FEFF bl printn + 717 .loc 1 266 0 + 718 0194 484C ldr r4, .L84+104 + 719 0196 3748 ldr r0, .L84+36 + 720 0198 FFF7FEFF bl println + 721 .LVL52: + 722 .loc 1 172 0 + 723 019c 2A21 movs r1, #42 + 724 .LVL53: + 725 .L53: + 726 .LBB60: + 727 .LBB61: + 728 .loc 1 173 0 + 729 019e 2B68 ldr r3, [r5, #0] + 730 01a0 2B48 ldr r0, .L84 + 731 01a2 1B69 ldr r3, [r3, #16] + 732 01a4 4FF0FF32 mov r2, #-1 + 733 01a8 9847 blx r3 + 734 .loc 1 172 0 + 735 01aa 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 736 01ae 0029 cmp r1, #0 + 737 01b0 F5D1 bne .L53 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 14 + + + 738 .LBE61: + 739 .LBE60: + 740 .loc 1 268 0 + 741 01b2 0846 mov r0, r1 + 742 01b4 FFF7FEFF bl printn + 743 .loc 1 269 0 + 744 01b8 404C ldr r4, .L84+108 + 745 01ba 2E48 ldr r0, .L84+36 + 746 01bc FFF7FEFF bl println + 747 .LVL54: + 748 .loc 1 172 0 + 749 01c0 2A21 movs r1, #42 + 750 .LVL55: + 751 .L54: + 752 .LBB62: + 753 .LBB63: + 754 .loc 1 173 0 + 755 01c2 2B68 ldr r3, [r5, #0] + 756 01c4 2248 ldr r0, .L84 + 757 01c6 1B69 ldr r3, [r3, #16] + 758 01c8 4FF0FF32 mov r2, #-1 + 759 01cc 9847 blx r3 + 760 .loc 1 172 0 + 761 01ce 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 762 01d2 0029 cmp r1, #0 + 763 01d4 F5D1 bne .L54 + 764 .LBE63: + 765 .LBE62: + 766 .loc 1 271 0 + 767 01d6 0420 movs r0, #4 + 768 01d8 FFF7FEFF bl printn + 769 .loc 1 272 0 + 770 01dc 2548 ldr r0, .L84+36 + 771 01de FFF7FEFF bl println + 772 .LVL56: + 773 01e2 374C ldr r4, .L84+112 + 774 .loc 1 172 0 + 775 01e4 2A26 movs r6, #42 + 776 .LVL57: + 777 .L55: + 778 .LBB64: + 779 .LBB65: + 780 .loc 1 173 0 + 781 01e6 2B68 ldr r3, [r5, #0] + 782 01e8 3146 mov r1, r6 + 783 01ea 1B69 ldr r3, [r3, #16] + 784 01ec 1848 ldr r0, .L84 + 785 01ee 4FF0FF32 mov r2, #-1 + 786 01f2 9847 blx r3 + 787 .loc 1 172 0 + 788 01f4 14F8016F ldrb r6, [r4, #1]! @ zero_extendqisi2 + 789 01f8 002E cmp r6, #0 + 790 01fa F4D1 bne .L55 + 791 .LBE65: + 792 .LBE64: + 793 .loc 1 274 0 + 794 01fc 0420 movs r0, #4 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 15 + + + 795 01fe FFF7FEFF bl printn + 796 .loc 1 275 0 + 797 0202 1C48 ldr r0, .L84+36 + 798 0204 FFF7FEFF bl println + 799 .loc 1 277 0 + 800 0208 1A48 ldr r0, .L84+36 + 801 020a FFF7FEFF bl println + 802 .LVL58: + 803 .loc 1 285 0 + 804 020e 4CF6CD48 movw r8, #52429 + 805 0212 2C4F ldr r7, .L84+116 + 806 .loc 1 278 0 + 807 0214 B246 mov sl, r6 + 808 .loc 1 279 0 + 809 0216 4FF00109 mov r9, #1 + 810 .loc 1 285 0 + 811 021a CCF6CC48 movt r8, 52428 + 812 .LVL59: + 813 .L56: + 814 .loc 1 279 0 + 815 021e 2A4C ldr r4, .L84+120 + 816 .loc 1 172 0 + 817 0220 4921 movs r1, #73 + 818 .LVL60: + 819 .L57: + 820 .LBB66: + 821 .LBB67: + 822 .loc 1 173 0 + 823 0222 2B68 ldr r3, [r5, #0] + 824 0224 0A48 ldr r0, .L84 + 825 0226 1B69 ldr r3, [r3, #16] + 826 0228 4FF0FF32 mov r2, #-1 + 827 022c 9847 blx r3 + 828 .loc 1 172 0 + 829 022e 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 830 0232 0029 cmp r1, #0 + 831 0234 F5D1 bne .L57 + 832 .LBE67: + 833 .LBE66: + 834 .loc 1 281 0 + 835 0236 4846 mov r0, r9 + 836 0238 0391 str r1, [sp, #12] + 837 023a FFF7FEFF bl printn + 838 .loc 1 282 0 + 839 023e 0D48 ldr r0, .L84+36 + 840 0240 FFF7FEFF bl println + 841 .loc 1 284 0 + 842 0244 0399 ldr r1, [sp, #12] + 843 .loc 1 285 0 + 844 0246 4FF4FA66 mov r6, #2000 + 845 .loc 1 284 0 + 846 024a 0C46 mov r4, r1 + 847 .loc 1 283 0 + 848 024c 3960 str r1, [r7, #0] + 849 .LVL61: + 850 024e 48E0 b .L60 + 851 .L85: + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 16 + + + 852 .align 2 + 853 .L84: + 854 0250 00000000 .word SD1 + 855 0254 00000000 .word GPTD2 + 856 0258 00000000 .word .LANCHOR4 + 857 025c 00000000 .word GPTD3 + 858 0260 00000000 .word .LANCHOR5 + 859 0264 00000000 .word .LANCHOR6 + 860 0268 00000000 .word .LANCHOR7 + 861 026c 00000000 .word .LANCHOR0 + 862 0270 00000000 .word WorkerThread + 863 0274 0C000000 .word .LC2 + 864 0278 10000000 .word .LC3 + 865 027c 40000000 .word .LC5 + 866 0280 3C000000 .word .LC4 + 867 0284 54000000 .word .LC6 + 868 0288 64000000 .word .LC7 + 869 028c 78000000 .word .LC8 + 870 0290 80000000 .word .LC9 + 871 0294 94000000 .word .LC10 + 872 0298 9C000000 .word .LC11 + 873 029c B0000000 .word .LC12 + 874 02a0 BC000000 .word .LC13 + 875 02a4 D0000000 .word .LC14 + 876 02a8 F8000000 .word .LC15 + 877 02ac 0C010000 .word .LC16 + 878 02b0 20010000 .word .LC17 + 879 02b4 34010000 .word .LC18 + 880 02b8 48010000 .word .LC19 + 881 02bc 5C010000 .word .LC20 + 882 02c0 70010000 .word .LC21 + 883 02c4 00000000 .word .LANCHOR1 + 884 02c8 98010000 .word .LC24 + 885 .LVL62: + 886 .L83: + 887 .LBB68: + 888 .LBB69: + 889 .loc 1 173 0 + 890 02cc 2B68 ldr r3, [r5, #0] + 891 02ce 2E21 movs r1, #46 + 892 02d0 1B69 ldr r3, [r3, #16] + 893 02d2 9847 blx r3 + 894 .LVL63: + 895 .LBE69: + 896 .LBE68: + 897 .loc 1 285 0 + 898 02d4 A8FB0623 umull r2, r3, r8, r6 + 899 02d8 A6EBD306 sub r6, r6, r3, lsr #3 + 900 02dc B6B2 uxth r6, r6 + 901 .LVL64: + 902 02de 132E cmp r6, #19 + 903 02e0 27D9 bls .L82 + 904 .LVL65: + 905 .L60: + 906 .loc 1 286 0 + 907 02e2 711E subs r1, r6, #1 + 908 02e4 89B2 uxth r1, r1 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 17 + + + 909 02e6 3748 ldr r0, .L86 + 910 02e8 FFF7FEFF bl gptStartContinuous + 911 .loc 1 287 0 + 912 02ec 711C adds r1, r6, #1 + 913 02ee 89B2 uxth r1, r1 + 914 02f0 3548 ldr r0, .L86+4 + 915 02f2 FFF7FEFF bl gptStartContinuous + 916 .loc 1 288 0 + 917 02f6 4FF47A70 mov r0, #1000 + 918 02fa FFF7FEFF bl chThdSleep + 919 .loc 1 289 0 + 920 02fe 3148 ldr r0, .L86 + 921 0300 FFF7FEFF bl gptStopTimer + 922 .loc 1 290 0 + 923 0304 3048 ldr r0, .L86+4 + 924 0306 FFF7FEFF bl gptStopTimer + 925 .loc 1 291 0 + 926 030a 3B68 ldr r3, [r7, #0] + 927 .LBB70: + 928 .LBB71: + 929 .loc 1 173 0 + 930 030c 2F48 ldr r0, .L86+8 + 931 030e 2321 movs r1, #35 + 932 0310 4FF0FF32 mov r2, #-1 + 933 .LBE71: + 934 .LBE70: + 935 .loc 1 291 0 + 936 0314 002B cmp r3, #0 + 937 0316 D9D0 beq .L83 + 938 .LVL66: + 939 .LBB74: + 940 .LBB72: + 941 .loc 1 173 0 + 942 0318 2B68 ldr r3, [r5, #0] + 943 .LBE72: + 944 .LBE74: + 945 .loc 1 295 0 + 946 031a 002C cmp r4, #0 + 947 031c 08BF it eq + 948 031e 3446 moveq r4, r6 + 949 .LBB75: + 950 .LBB73: + 951 .loc 1 173 0 + 952 0320 1B69 ldr r3, [r3, #16] + 953 0322 9847 blx r3 + 954 .LVL67: + 955 .LBE73: + 956 .LBE75: + 957 .loc 1 285 0 + 958 0324 A8FB0623 umull r2, r3, r8, r6 + 959 0328 A6EBD306 sub r6, r6, r3, lsr #3 + 960 032c B6B2 uxth r6, r6 + 961 .LVL68: + 962 032e 132E cmp r6, #19 + 963 0330 D7D8 bhi .L60 + 964 .LVL69: + 965 .L82: + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 18 + + + 966 .loc 1 301 0 + 967 0332 1420 movs r0, #20 + 968 0334 FFF7FEFF bl chThdSleep + 969 .loc 1 302 0 + 970 0338 254E ldr r6, .L86+12 + 971 033a 2648 ldr r0, .L86+16 + 972 033c FFF7FEFF bl println + 973 .LVL70: + 974 .loc 1 172 0 + 975 0340 5321 movs r1, #83 + 976 .LVL71: + 977 .L61: + 978 .LBB76: + 979 .LBB77: + 980 .loc 1 173 0 + 981 0342 2B68 ldr r3, [r5, #0] + 982 0344 2148 ldr r0, .L86+8 + 983 0346 1B69 ldr r3, [r3, #16] + 984 0348 4FF0FF32 mov r2, #-1 + 985 034c 9847 blx r3 + 986 .loc 1 172 0 + 987 034e 16F8011F ldrb r1, [r6, #1]! @ zero_extendqisi2 + 988 0352 0029 cmp r1, #0 + 989 0354 F5D1 bne .L61 + 990 .LBE77: + 991 .LBE76: + 992 .loc 1 304 0 + 993 0356 2046 mov r0, r4 + 994 0358 FFF7FEFF bl printn + 995 .loc 1 305 0 + 996 035c 1E48 ldr r0, .L86+20 + 997 035e FFF7FEFF bl println + 998 .loc 1 279 0 + 999 0362 09F10109 add r9, r9, #1 + 1000 .loc 1 306 0 + 1001 0366 1B48 ldr r0, .L86+16 + 1002 0368 5445 cmp r4, sl + 1003 036a 28BF it cs + 1004 036c A246 movcs sl, r4 + 1005 036e FFF7FEFF bl println + 1006 .loc 1 279 0 + 1007 0372 B9F1650F cmp r9, #101 + 1008 .loc 1 306 0 + 1009 0376 1FFA8AFA uxth sl, sl + 1010 .LVL72: + 1011 .loc 1 279 0 + 1012 037a 7FF450AF bne .L56 + 1013 .loc 1 310 0 + 1014 037e 1148 ldr r0, .L86 + 1015 0380 FFF7FEFF bl gptStopTimer + 1016 .loc 1 311 0 + 1017 0384 154C ldr r4, .L86+24 + 1018 0386 1048 ldr r0, .L86+4 + 1019 0388 FFF7FEFF bl gptStopTimer + 1020 .LVL73: + 1021 .loc 1 172 0 + 1022 038c 5721 movs r1, #87 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 19 + + + 1023 .LVL74: + 1024 .L63: + 1025 .LBB78: + 1026 .LBB79: + 1027 .loc 1 173 0 + 1028 038e 2B68 ldr r3, [r5, #0] + 1029 0390 0E48 ldr r0, .L86+8 + 1030 0392 1B69 ldr r3, [r3, #16] + 1031 0394 4FF0FF32 mov r2, #-1 + 1032 0398 9847 blx r3 + 1033 .loc 1 172 0 + 1034 039a 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 + 1035 039e 0029 cmp r1, #0 + 1036 03a0 F5D1 bne .L63 + 1037 .LBE79: + 1038 .LBE78: + 1039 .loc 1 314 0 + 1040 03a2 5046 mov r0, sl + 1041 03a4 FFF7FEFF bl printn + 1042 .loc 1 315 0 + 1043 03a8 0B48 ldr r0, .L86+20 + 1044 03aa FFF7FEFF bl println + 1045 .loc 1 316 0 + 1046 03ae 0948 ldr r0, .L86+16 + 1047 03b0 FFF7FEFF bl println + 1048 .loc 1 317 0 + 1049 03b4 0A48 ldr r0, .L86+28 + 1050 03b6 FFF7FEFF bl println + 1051 .L64: + 1052 .loc 1 323 0 discriminator 1 + 1053 03ba 41F28830 movw r0, #5000 + 1054 03be FFF7FEFF bl chThdSleep + 1055 03c2 FAE7 b .L64 + 1056 .L87: + 1057 .align 2 + 1058 .L86: + 1059 03c4 00000000 .word GPTD2 + 1060 03c8 00000000 .word GPTD3 + 1061 03cc 00000000 .word SD1 + 1062 03d0 84010000 .word .LC22 + 1063 03d4 0C000000 .word .LC2 + 1064 03d8 94010000 .word .LC23 + 1065 03dc A4010000 .word .LC25 + 1066 03e0 B4010000 .word .LC26 + 1067 .cfi_endproc + 1068 .LFE68: + 1069 .size main, .-main + 1070 03e4 AFF30080 .section .rodata.gpt2cfg,"a",%progbits + 1070 AFF30080 + 1070 AFF30080 + 1071 .align 2 + 1072 .set .LANCHOR4,. + 0 + 1073 .type gpt2cfg, %object + 1074 .size gpt2cfg, 8 + 1075 gpt2cfg: + 1076 0000 40420F00 .word 1000000 + 1077 0004 00000000 .word gpt2cb + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 20 + + + 1078 .section .bss.waWorkerThread,"aw",%nobits + 1079 .align 3 + 1080 .set .LANCHOR7,. + 0 + 1081 .type waWorkerThread, %object + 1082 .size waWorkerThread, 1152 + 1083 waWorkerThread: + 1084 0000 00000000 .space 1152 + 1084 00000000 + 1084 00000000 + 1084 00000000 + 1084 00000000 + 1085 .section .bss.saturated,"aw",%nobits + 1086 .align 2 + 1087 .set .LANCHOR1,. + 0 + 1088 .type saturated, %object + 1089 .size saturated, 4 + 1090 saturated: + 1091 0000 00000000 .space 4 + 1092 .section .rodata.gpt3cfg,"a",%progbits + 1093 .align 2 + 1094 .set .LANCHOR5,. + 0 + 1095 .type gpt3cfg, %object + 1096 .size gpt3cfg, 8 + 1097 gpt3cfg: + 1098 0000 40420F00 .word 1000000 + 1099 0004 00000000 .word gpt3cb + 1100 .section .rodata.str1.4,"aMS",%progbits,1 + 1101 .align 2 + 1102 .LC0: + 1103 0000 0D0A00 .ascii "\015\012\000" + 1104 0003 00 .space 1 + 1105 .LC1: + 1106 0004 776F726B .ascii "worker\000" + 1106 657200 + 1107 000b 00 .space 1 + 1108 .LC2: + 1109 000c 00 .ascii "\000" + 1110 000d 000000 .space 3 + 1111 .LC3: + 1112 0010 2A2A2A20 .ascii "*** ChibiOS/RT IRQ-STORM long duration test\000" + 1112 43686962 + 1112 694F532F + 1112 52542049 + 1112 52512D53 + 1113 .LC4: + 1114 003c 2A2A2A00 .ascii "***\000" + 1115 .LC5: + 1116 0040 2A2A2A20 .ascii "*** Kernel: \000" + 1116 4B65726E + 1116 656C3A20 + 1116 20202020 + 1116 202000 + 1117 0053 00 .space 1 + 1118 .LC6: + 1119 0054 322E332E .ascii "2.3.3unstable\000" + 1119 33756E73 + 1119 7461626C + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 21 + + + 1119 6500 + 1120 0062 0000 .space 2 + 1121 .LC7: + 1122 0064 2A2A2A20 .ascii "*** GCC Version: \000" + 1122 47434320 + 1122 56657273 + 1122 696F6E3A + 1122 202000 + 1123 0077 00 .space 1 + 1124 .LC8: + 1125 0078 342E362E .ascii "4.6.0\000" + 1125 3000 + 1126 007e 0000 .space 2 + 1127 .LC9: + 1128 0080 2A2A2A20 .ascii "*** Architecture: \000" + 1128 41726368 + 1128 69746563 + 1128 74757265 + 1128 3A2000 + 1129 0093 00 .space 1 + 1130 .LC10: + 1131 0094 41524D76 .ascii "ARMv7-M\000" + 1131 372D4D00 + 1132 .LC11: + 1133 009c 2A2A2A20 .ascii "*** Core Variant: \000" + 1133 436F7265 + 1133 20566172 + 1133 69616E74 + 1133 3A2000 + 1134 00af 00 .space 1 + 1135 .LC12: + 1136 00b0 436F7274 .ascii "Cortex-M3\000" + 1136 65782D4D + 1136 3300 + 1137 00ba 0000 .space 2 + 1138 .LC13: + 1139 00bc 2A2A2A20 .ascii "*** Platform: \000" + 1139 506C6174 + 1139 666F726D + 1139 3A202020 + 1139 202000 + 1140 00cf 00 .space 1 + 1141 .LC14: + 1142 00d0 53544D33 .ascii "STM32L Ultra Low Power Medium Density\000" + 1142 324C2055 + 1142 6C747261 + 1142 204C6F77 + 1142 20506F77 + 1143 00f6 0000 .space 2 + 1144 .LC15: + 1145 00f8 2A2A2A20 .ascii "*** Test Board: \000" + 1145 54657374 + 1145 20426F61 + 1145 72643A20 + 1145 202000 + 1146 010b 00 .space 1 + 1147 .LC16: + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 22 + + + 1148 010c 53542053 .ascii "ST STM32L-Discovery\000" + 1148 544D3332 + 1148 4C2D4469 + 1148 73636F76 + 1148 65727900 + 1149 .LC17: + 1150 0120 2A2A2A20 .ascii "*** System Clock: \000" + 1150 53797374 + 1150 656D2043 + 1150 6C6F636B + 1150 3A2000 + 1151 0133 00 .space 1 + 1152 .LC18: + 1153 0134 2A2A2A20 .ascii "*** Iterations: \000" + 1153 49746572 + 1153 6174696F + 1153 6E733A20 + 1153 202000 + 1154 0147 00 .space 1 + 1155 .LC19: + 1156 0148 2A2A2A20 .ascii "*** Randomize: \000" + 1156 52616E64 + 1156 6F6D697A + 1156 653A2020 + 1156 202000 + 1157 015b 00 .space 1 + 1158 .LC20: + 1159 015c 2A2A2A20 .ascii "*** Threads: \000" + 1159 54687265 + 1159 6164733A + 1159 20202020 + 1159 202000 + 1160 016f 00 .space 1 + 1161 .LC21: + 1162 0170 2A2A2A20 .ascii "*** Mailbox size: \000" + 1162 4D61696C + 1162 626F7820 + 1162 73697A65 + 1162 3A2000 + 1163 0183 00 .space 1 + 1164 .LC22: + 1165 0184 53617475 .ascii "Saturated at \000" + 1165 72617465 + 1165 64206174 + 1165 2000 + 1166 0192 0000 .space 2 + 1167 .LC23: + 1168 0194 20755300 .ascii " uS\000" + 1169 .LC24: + 1170 0198 49746572 .ascii "Iteration \000" + 1170 6174696F + 1170 6E2000 + 1171 01a3 00 .space 1 + 1172 .LC25: + 1173 01a4 576F7273 .ascii "Worst case at \000" + 1173 74206361 + 1173 73652061 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 23 + + + 1173 742000 + 1174 01b3 00 .space 1 + 1175 .LC26: + 1176 01b4 54657374 .ascii "Test Complete\000" + 1176 20436F6D + 1176 706C6574 + 1176 6500 + 1177 01c2 0000 .section .bss.mb,"aw",%nobits + 1178 .align 2 + 1179 .set .LANCHOR0,. + 0 + 1180 .type mb, %object + 1181 .size mb, 160 + 1182 mb: + 1183 0000 00000000 .space 160 + 1183 00000000 + 1183 00000000 + 1183 00000000 + 1183 00000000 + 1184 .section .bss.b,"aw",%nobits + 1185 .align 2 + 1186 .set .LANCHOR6,. + 0 + 1187 .type b, %object + 1188 .size b, 64 + 1189 b: + 1190 0000 00000000 .space 64 + 1190 00000000 + 1190 00000000 + 1190 00000000 + 1190 00000000 + 1191 .section .bss.x.3441,"aw",%nobits + 1192 .align 2 + 1193 .set .LANCHOR2,. + 0 + 1194 .type x.3441, %object + 1195 .size x.3441, 4 + 1196 x.3441: + 1197 0000 00000000 .space 4 + 1198 .section .bss.cnt.3442,"aw",%nobits + 1199 .align 2 + 1200 .set .LANCHOR3,. + 0 + 1201 .type cnt.3442, %object + 1202 .size cnt.3442, 4 + 1203 cnt.3442: + 1204 0000 00000000 .space 4 + 1205 .text + 1206 .Letext0: + 1207 .file 2 "c:\\programmi\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.6.0/include/stddef.h" + 1208 .file 3 "c:/programmi/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" + 1209 .file 4 "../../../os/ports/GCC/ARMCMx/chtypes.h" + 1210 .file 5 "../../../os/kernel/include/chlists.h" + 1211 .file 6 "../../../os/kernel/include/chthreads.h" + 1212 .file 7 "../../../os/ports/GCC/ARMCMx/chcore_v7m.h" + 1213 .file 8 "../../../os/ports/GCC/ARMCMx/chcore.h" + 1214 .file 9 "../../../os/kernel/include/chschd.h" + 1215 .file 10 "../../../os/kernel/include/chsem.h" + 1216 .file 11 "../../../os/kernel/include/chmtx.h" + 1217 .file 12 "../../../os/kernel/include/chevents.h" + 1218 .file 13 "../../../os/kernel/include/chmboxes.h" + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 24 + + + 1219 .file 14 "../../../os/kernel/include/chqueues.h" + 1220 .file 15 "../../../os/kernel/include/chioch.h" + 1221 .file 16 "../../../os/hal/platforms/STM32L1xx/stm32l1xx.h" + 1222 .file 17 "../../../os/hal/platforms/STM32/GPIOv2/pal_lld.h" + 1223 .file 18 "../../../os/hal/include/gpt.h" + 1224 .file 19 "../../../os/hal/platforms/STM32/gpt_lld.h" + 1225 .file 20 "../../../os/hal/include/serial.h" + 1226 .file 21 "../../../os/ports/common/ARMCMx/CMSIS/include/core_cm3.h" + 1227 .file 22 "../../../os/hal/platforms/STM32/serial_lld.h" + 1228 .section .debug_info,"",%progbits + 1229 .Ldebug_info0: + 1230 0000 1F130000 .4byte 0x131f + 1231 0004 0200 .2byte 0x2 + 1232 0006 00000000 .4byte .Ldebug_abbrev0 + 1233 000a 04 .byte 0x4 + 1234 000b 01 .uleb128 0x1 + 1235 000c 15000000 .4byte .LASF191 + 1236 0010 01 .byte 0x1 + 1237 0011 ED030000 .4byte .LASF192 + 1238 0015 80040000 .4byte .LASF193 + 1239 0019 00000000 .4byte 0 + 1240 001d 00000000 .4byte 0 + 1241 0021 50000000 .4byte .Ldebug_ranges0+0x50 + 1242 0025 00000000 .4byte .Ldebug_line0 + 1243 0029 02 .uleb128 0x2 + 1244 002a 51020000 .4byte .LASF10 + 1245 002e 02 .byte 0x2 + 1246 002f D4 .byte 0xd4 + 1247 0030 34000000 .4byte 0x34 + 1248 0034 03 .uleb128 0x3 + 1249 0035 04 .byte 0x4 + 1250 0036 07 .byte 0x7 + 1251 0037 88020000 .4byte .LASF0 + 1252 003b 03 .uleb128 0x3 + 1253 003c 01 .byte 0x1 + 1254 003d 06 .byte 0x6 + 1255 003e 07010000 .4byte .LASF1 + 1256 0042 03 .uleb128 0x3 + 1257 0043 01 .byte 0x1 + 1258 0044 08 .byte 0x8 + 1259 0045 CF040000 .4byte .LASF2 + 1260 0049 03 .uleb128 0x3 + 1261 004a 02 .byte 0x2 + 1262 004b 05 .byte 0x5 + 1263 004c 0F050000 .4byte .LASF3 + 1264 0050 03 .uleb128 0x3 + 1265 0051 02 .byte 0x2 + 1266 0052 07 .byte 0x7 + 1267 0053 12020000 .4byte .LASF4 + 1268 0057 04 .uleb128 0x4 + 1269 0058 04 .byte 0x4 + 1270 0059 05 .byte 0x5 + 1271 005a 696E7400 .ascii "int\000" + 1272 005e 03 .uleb128 0x3 + 1273 005f 08 .byte 0x8 + 1274 0060 05 .byte 0x5 + 1275 0061 F9000000 .4byte .LASF5 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 25 + + + 1276 0065 03 .uleb128 0x3 + 1277 0066 08 .byte 0x8 + 1278 0067 07 .byte 0x7 + 1279 0068 86000000 .4byte .LASF6 + 1280 006c 03 .uleb128 0x3 + 1281 006d 04 .byte 0x4 + 1282 006e 05 .byte 0x5 + 1283 006f A4010000 .4byte .LASF7 + 1284 0073 05 .uleb128 0x5 + 1285 0074 04 .byte 0x4 + 1286 0075 03 .uleb128 0x3 + 1287 0076 04 .byte 0x4 + 1288 0077 07 .byte 0x7 + 1289 0078 B1050000 .4byte .LASF8 + 1290 007c 06 .uleb128 0x6 + 1291 007d 04 .byte 0x4 + 1292 007e 82000000 .4byte 0x82 + 1293 0082 03 .uleb128 0x3 + 1294 0083 01 .byte 0x1 + 1295 0084 08 .byte 0x8 + 1296 0085 D2050000 .4byte .LASF9 + 1297 0089 06 .uleb128 0x6 + 1298 008a 04 .byte 0x4 + 1299 008b 8F000000 .4byte 0x8f + 1300 008f 07 .uleb128 0x7 + 1301 0090 82000000 .4byte 0x82 + 1302 0094 02 .uleb128 0x2 + 1303 0095 A6060000 .4byte .LASF11 + 1304 0099 03 .byte 0x3 + 1305 009a 2A .byte 0x2a + 1306 009b 42000000 .4byte 0x42 + 1307 009f 02 .uleb128 0x2 + 1308 00a0 95020000 .4byte .LASF12 + 1309 00a4 03 .byte 0x3 + 1310 00a5 36 .byte 0x36 + 1311 00a6 50000000 .4byte 0x50 + 1312 00aa 02 .uleb128 0x2 + 1313 00ab C7040000 .4byte .LASF13 + 1314 00af 03 .byte 0x3 + 1315 00b0 4F .byte 0x4f + 1316 00b1 6C000000 .4byte 0x6c + 1317 00b5 02 .uleb128 0x2 + 1318 00b6 75050000 .4byte .LASF14 + 1319 00ba 03 .byte 0x3 + 1320 00bb 50 .byte 0x50 + 1321 00bc 75000000 .4byte 0x75 + 1322 00c0 02 .uleb128 0x2 + 1323 00c1 0C000000 .4byte .LASF15 + 1324 00c5 03 .byte 0x3 + 1325 00c6 78 .byte 0x78 + 1326 00c7 65000000 .4byte 0x65 + 1327 00cb 02 .uleb128 0x2 + 1328 00cc 78000000 .4byte .LASF16 + 1329 00d0 03 .byte 0x3 + 1330 00d1 A6 .byte 0xa6 + 1331 00d2 34000000 .4byte 0x34 + 1332 00d6 02 .uleb128 0x2 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 26 + + + 1333 00d7 1D010000 .4byte .LASF17 + 1334 00db 04 .byte 0x4 + 1335 00dc 27 .byte 0x27 + 1336 00dd AA000000 .4byte 0xaa + 1337 00e1 02 .uleb128 0x2 + 1338 00e2 C9060000 .4byte .LASF18 + 1339 00e6 04 .byte 0x4 + 1340 00e7 28 .byte 0x28 + 1341 00e8 94000000 .4byte 0x94 + 1342 00ec 02 .uleb128 0x2 + 1343 00ed BE010000 .4byte .LASF19 + 1344 00f1 04 .byte 0x4 + 1345 00f2 29 .byte 0x29 + 1346 00f3 94000000 .4byte 0x94 + 1347 00f7 02 .uleb128 0x2 + 1348 00f8 1B040000 .4byte .LASF20 + 1349 00fc 04 .byte 0x4 + 1350 00fd 2A .byte 0x2a + 1351 00fe 94000000 .4byte 0x94 + 1352 0102 02 .uleb128 0x2 + 1353 0103 70040000 .4byte .LASF21 + 1354 0107 04 .byte 0x4 + 1355 0108 2B .byte 0x2b + 1356 0109 B5000000 .4byte 0xb5 + 1357 010d 02 .uleb128 0x2 + 1358 010e 0C030000 .4byte .LASF22 + 1359 0112 04 .byte 0x4 + 1360 0113 2C .byte 0x2c + 1361 0114 AA000000 .4byte 0xaa + 1362 0118 02 .uleb128 0x2 + 1363 0119 4A030000 .4byte .LASF23 + 1364 011d 04 .byte 0x4 + 1365 011e 2E .byte 0x2e + 1366 011f B5000000 .4byte 0xb5 + 1367 0123 02 .uleb128 0x2 + 1368 0124 16060000 .4byte .LASF24 + 1369 0128 04 .byte 0x4 + 1370 0129 2F .byte 0x2f + 1371 012a B5000000 .4byte 0xb5 + 1372 012e 02 .uleb128 0x2 + 1373 012f AC030000 .4byte .LASF25 + 1374 0133 04 .byte 0x4 + 1375 0134 30 .byte 0x30 + 1376 0135 AA000000 .4byte 0xaa + 1377 0139 02 .uleb128 0x2 + 1378 013a 46050000 .4byte .LASF26 + 1379 013e 05 .byte 0x5 + 1380 013f 23 .byte 0x23 + 1381 0140 44010000 .4byte 0x144 + 1382 0144 08 .uleb128 0x8 + 1383 0145 46050000 .4byte .LASF26 + 1384 0149 48 .byte 0x48 + 1385 014a 06 .byte 0x6 + 1386 014b 4D .byte 0x4d + 1387 014c 5B020000 .4byte 0x25b + 1388 0150 09 .uleb128 0x9 + 1389 0151 27050000 .4byte .LASF27 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 27 + + + 1390 0155 06 .byte 0x6 + 1391 0156 4E .byte 0x4e + 1392 0157 80020000 .4byte 0x280 + 1393 015b 02 .byte 0x2 + 1394 015c 23 .byte 0x23 + 1395 015d 00 .uleb128 0 + 1396 015e 09 .uleb128 0x9 + 1397 015f 55040000 .4byte .LASF28 + 1398 0163 06 .byte 0x6 + 1399 0164 50 .byte 0x50 + 1400 0165 80020000 .4byte 0x280 + 1401 0169 02 .byte 0x2 + 1402 016a 23 .byte 0x23 + 1403 016b 04 .uleb128 0x4 + 1404 016c 09 .uleb128 0x9 + 1405 016d E0000000 .4byte .LASF29 + 1406 0171 06 .byte 0x6 + 1407 0172 52 .byte 0x52 + 1408 0173 02010000 .4byte 0x102 + 1409 0177 02 .byte 0x2 + 1410 0178 23 .byte 0x23 + 1411 0179 08 .uleb128 0x8 + 1412 017a 09 .uleb128 0x9 + 1413 017b 02070000 .4byte .LASF30 + 1414 017f 06 .byte 0x6 + 1415 0180 53 .byte 0x53 + 1416 0181 52030000 .4byte 0x352 + 1417 0185 02 .byte 0x2 + 1418 0186 23 .byte 0x23 + 1419 0187 0C .uleb128 0xc + 1420 0188 09 .uleb128 0x9 + 1421 0189 E6010000 .4byte .LASF31 + 1422 018d 06 .byte 0x6 + 1423 018e 55 .byte 0x55 + 1424 018f 80020000 .4byte 0x280 + 1425 0193 02 .byte 0x2 + 1426 0194 23 .byte 0x23 + 1427 0195 10 .uleb128 0x10 + 1428 0196 09 .uleb128 0x9 + 1429 0197 C2030000 .4byte .LASF32 + 1430 019b 06 .byte 0x6 + 1431 019c 56 .byte 0x56 + 1432 019d 80020000 .4byte 0x280 + 1433 01a1 02 .byte 0x2 + 1434 01a2 23 .byte 0x23 + 1435 01a3 14 .uleb128 0x14 + 1436 01a4 09 .uleb128 0x9 + 1437 01a5 2B060000 .4byte .LASF33 + 1438 01a9 06 .byte 0x6 + 1439 01aa 5D .byte 0x5d + 1440 01ab 89000000 .4byte 0x89 + 1441 01af 02 .byte 0x2 + 1442 01b0 23 .byte 0x23 + 1443 01b1 18 .uleb128 0x18 + 1444 01b2 09 .uleb128 0x9 + 1445 01b3 FD040000 .4byte .LASF34 + 1446 01b7 06 .byte 0x6 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 28 + + + 1447 01b8 68 .byte 0x68 + 1448 01b9 EC000000 .4byte 0xec + 1449 01bd 02 .byte 0x2 + 1450 01be 23 .byte 0x23 + 1451 01bf 1C .uleb128 0x1c + 1452 01c0 09 .uleb128 0x9 + 1453 01c1 2E050000 .4byte .LASF35 + 1454 01c5 06 .byte 0x6 + 1455 01c6 6C .byte 0x6c + 1456 01c7 E1000000 .4byte 0xe1 + 1457 01cb 02 .byte 0x2 + 1458 01cc 23 .byte 0x23 + 1459 01cd 1D .uleb128 0x1d + 1460 01ce 09 .uleb128 0x9 + 1461 01cf C7010000 .4byte .LASF36 + 1462 01d3 06 .byte 0x6 + 1463 01d4 71 .byte 0x71 + 1464 01d5 F7000000 .4byte 0xf7 + 1465 01d9 02 .byte 0x2 + 1466 01da 23 .byte 0x23 + 1467 01db 1E .uleb128 0x1e + 1468 01dc 09 .uleb128 0x9 + 1469 01dd DF010000 .4byte .LASF37 + 1470 01e1 06 .byte 0x6 + 1471 01e2 78 .byte 0x78 + 1472 01e3 73030000 .4byte 0x373 + 1473 01e7 02 .byte 0x2 + 1474 01e8 23 .byte 0x23 + 1475 01e9 20 .uleb128 0x20 + 1476 01ea 0A .uleb128 0xa + 1477 01eb 705F7500 .ascii "p_u\000" + 1478 01ef 06 .byte 0x6 + 1479 01f0 9D .byte 0x9d + 1480 01f1 46050000 .4byte 0x546 + 1481 01f5 02 .byte 0x2 + 1482 01f6 23 .byte 0x23 + 1483 01f7 24 .uleb128 0x24 + 1484 01f8 09 .uleb128 0x9 + 1485 01f9 08070000 .4byte .LASF38 + 1486 01fd 06 .byte 0x6 + 1487 01fe A2 .byte 0xa2 + 1488 01ff A8020000 .4byte 0x2a8 + 1489 0203 02 .byte 0x2 + 1490 0204 23 .byte 0x23 + 1491 0205 28 .uleb128 0x28 + 1492 0206 09 .uleb128 0x9 + 1493 0207 B5020000 .4byte .LASF39 + 1494 020b 06 .byte 0x6 + 1495 020c A8 .byte 0xa8 + 1496 020d 86020000 .4byte 0x286 + 1497 0211 02 .byte 0x2 + 1498 0212 23 .byte 0x23 + 1499 0213 2C .uleb128 0x2c + 1500 0214 09 .uleb128 0x9 + 1501 0215 E3050000 .4byte .LASF40 + 1502 0219 06 .byte 0x6 + 1503 021a AC .byte 0xac + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 29 + + + 1504 021b 0D010000 .4byte 0x10d + 1505 021f 02 .byte 0x2 + 1506 0220 23 .byte 0x23 + 1507 0221 34 .uleb128 0x34 + 1508 0222 09 .uleb128 0x9 + 1509 0223 4D050000 .4byte .LASF41 + 1510 0227 06 .byte 0x6 + 1511 0228 B2 .byte 0xb2 + 1512 0229 18010000 .4byte 0x118 + 1513 022d 02 .byte 0x2 + 1514 022e 23 .byte 0x23 + 1515 022f 38 .uleb128 0x38 + 1516 0230 09 .uleb128 0x9 + 1517 0231 05050000 .4byte .LASF42 + 1518 0235 06 .byte 0x6 + 1519 0236 B9 .byte 0xb9 + 1520 0237 7B050000 .4byte 0x57b + 1521 023b 02 .byte 0x2 + 1522 023c 23 .byte 0x23 + 1523 023d 3C .uleb128 0x3c + 1524 023e 09 .uleb128 0x9 + 1525 023f 20060000 .4byte .LASF43 + 1526 0243 06 .byte 0x6 + 1527 0244 BD .byte 0xbd + 1528 0245 02010000 .4byte 0x102 + 1529 0249 02 .byte 0x2 + 1530 024a 23 .byte 0x23 + 1531 024b 40 .uleb128 0x40 + 1532 024c 09 .uleb128 0x9 + 1533 024d 04030000 .4byte .LASF44 + 1534 0251 06 .byte 0x6 + 1535 0252 C3 .byte 0xc3 + 1536 0253 73000000 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.uleb128 0x11 + 4112 01b0 01 .uleb128 0x1 + 4113 01b1 12 .uleb128 0x12 + 4114 01b2 01 .uleb128 0x1 + 4115 01b3 00 .byte 0 + 4116 01b4 00 .byte 0 + 4117 01b5 24 .uleb128 0x24 + 4118 01b6 2E .uleb128 0x2e + 4119 01b7 01 .byte 0x1 + 4120 01b8 03 .uleb128 0x3 + 4121 01b9 0E .uleb128 0xe + 4122 01ba 3A .uleb128 0x3a + 4123 01bb 0B .uleb128 0xb + 4124 01bc 3B .uleb128 0x3b + 4125 01bd 0B .uleb128 0xb + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 75 + + + 4126 01be 27 .uleb128 0x27 + 4127 01bf 0C .uleb128 0xc + 4128 01c0 49 .uleb128 0x49 + 4129 01c1 13 .uleb128 0x13 + 4130 01c2 11 .uleb128 0x11 + 4131 01c3 01 .uleb128 0x1 + 4132 01c4 12 .uleb128 0x12 + 4133 01c5 01 .uleb128 0x1 + 4134 01c6 40 .uleb128 0x40 + 4135 01c7 06 .uleb128 0x6 + 4136 01c8 01 .uleb128 0x1 + 4137 01c9 13 .uleb128 0x13 + 4138 01ca 00 .byte 0 + 4139 01cb 00 .byte 0 + 4140 01cc 25 .uleb128 0x25 + 4141 01cd 34 .uleb128 0x34 + 4142 01ce 00 .byte 0 + 4143 01cf 03 .uleb128 0x3 + 4144 01d0 0E .uleb128 0xe + 4145 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0 + 4182 01f6 31 .uleb128 0x31 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 76 + + + 4183 01f7 13 .uleb128 0x13 + 4184 01f8 02 .uleb128 0x2 + 4185 01f9 0A .uleb128 0xa + 4186 01fa 00 .byte 0 + 4187 01fb 00 .byte 0 + 4188 01fc 29 .uleb128 0x29 + 4189 01fd 34 .uleb128 0x34 + 4190 01fe 00 .byte 0 + 4191 01ff 31 .uleb128 0x31 + 4192 0200 13 .uleb128 0x13 + 4193 0201 02 .uleb128 0x2 + 4194 0202 06 .uleb128 0x6 + 4195 0203 00 .byte 0 + 4196 0204 00 .byte 0 + 4197 0205 2A .uleb128 0x2a + 4198 0206 1D .uleb128 0x1d + 4199 0207 01 .byte 0x1 + 4200 0208 31 .uleb128 0x31 + 4201 0209 13 .uleb128 0x13 + 4202 020a 52 .uleb128 0x52 + 4203 020b 01 .uleb128 0x1 + 4204 020c 55 .uleb128 0x55 + 4205 020d 06 .uleb128 0x6 + 4206 020e 58 .uleb128 0x58 + 4207 020f 0B .uleb128 0xb + 4208 0210 59 .uleb128 0x59 + 4209 0211 0B .uleb128 0xb + 4210 0212 00 .byte 0 + 4211 0213 00 .byte 0 + 4212 0214 2B .uleb128 0x2b + 4213 0215 0B .uleb128 0xb + 4214 0216 01 .byte 0x1 + 4215 0217 55 .uleb128 0x55 + 4216 0218 06 .uleb128 0x6 + 4217 0219 00 .byte 0 + 4218 021a 00 .byte 0 + 4219 021b 2C .uleb128 0x2c + 4220 021c 34 .uleb128 0x34 + 4221 021d 00 .byte 0 + 4222 021e 31 .uleb128 0x31 + 4223 021f 13 .uleb128 0x13 + 4224 0220 00 .byte 0 + 4225 0221 00 .byte 0 + 4226 0222 2D .uleb128 0x2d + 4227 0223 05 .uleb128 0x5 + 4228 0224 00 .byte 0 + 4229 0225 31 .uleb128 0x31 + 4230 0226 13 .uleb128 0x13 + 4231 0227 00 .byte 0 + 4232 0228 00 .byte 0 + 4233 0229 2E .uleb128 0x2e + 4234 022a 2E .uleb128 0x2e + 4235 022b 01 .byte 0x1 + 4236 022c 3F .uleb128 0x3f + 4237 022d 0C .uleb128 0xc + 4238 022e 03 .uleb128 0x3 + 4239 022f 0E .uleb128 0xe + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 77 + + + 4240 0230 3A .uleb128 0x3a + 4241 0231 0B .uleb128 0xb + 4242 0232 3B .uleb128 0x3b + 4243 0233 0B .uleb128 0xb + 4244 0234 27 .uleb128 0x27 + 4245 0235 0C .uleb128 0xc + 4246 0236 49 .uleb128 0x49 + 4247 0237 13 .uleb128 0x13 + 4248 0238 11 .uleb128 0x11 + 4249 0239 01 .uleb128 0x1 + 4250 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0xb + 4320 0280 59 .uleb128 0x59 + 4321 0281 05 .uleb128 0x5 + 4322 0282 00 .byte 0 + 4323 0283 00 .byte 0 + 4324 0284 33 .uleb128 0x33 + 4325 0285 34 .uleb128 0x34 + 4326 0286 00 .byte 0 + 4327 0287 03 .uleb128 0x3 + 4328 0288 0E .uleb128 0xe + 4329 0289 3A .uleb128 0x3a + 4330 028a 0B .uleb128 0xb + 4331 028b 3B .uleb128 0x3b + 4332 028c 0B .uleb128 0xb + 4333 028d 49 .uleb128 0x49 + 4334 028e 13 .uleb128 0x13 + 4335 028f 3F .uleb128 0x3f + 4336 0290 0C .uleb128 0xc + 4337 0291 3C .uleb128 0x3c + 4338 0292 0C .uleb128 0xc + 4339 0293 00 .byte 0 + 4340 0294 00 .byte 0 + 4341 0295 34 .uleb128 0x34 + 4342 0296 34 .uleb128 0x34 + 4343 0297 00 .byte 0 + 4344 0298 03 .uleb128 0x3 + 4345 0299 0E .uleb128 0xe + 4346 029a 3A .uleb128 0x3a + 4347 029b 0B .uleb128 0xb + 4348 029c 3B .uleb128 0x3b + 4349 029d 05 .uleb128 0x5 + 4350 029e 49 .uleb128 0x49 + 4351 029f 13 .uleb128 0x13 + 4352 02a0 3F .uleb128 0x3f + 4353 02a1 0C .uleb128 0xc + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 79 + + + 4354 02a2 3C .uleb128 0x3c + 4355 02a3 0C .uleb128 0xc + 4356 02a4 00 .byte 0 + 4357 02a5 00 .byte 0 + 4358 02a6 35 .uleb128 0x35 + 4359 02a7 34 .uleb128 0x34 + 4360 02a8 00 .byte 0 + 4361 02a9 03 .uleb128 0x3 + 4362 02aa 08 .uleb128 0x8 + 4363 02ab 3A .uleb128 0x3a + 4364 02ac 0B .uleb128 0xb + 4365 02ad 3B .uleb128 0x3b + 4366 02ae 0B .uleb128 0xb + 4367 02af 49 .uleb128 0x49 + 4368 02b0 13 .uleb128 0x13 + 4369 02b1 3F .uleb128 0x3f + 4370 02b2 0C .uleb128 0xc + 4371 02b3 3C .uleb128 0x3c + 4372 02b4 0C .uleb128 0xc + 4373 02b5 00 .byte 0 + 4374 02b6 00 .byte 0 + 4375 02b7 36 .uleb128 0x36 + 4376 02b8 34 .uleb128 0x34 + 4377 02b9 00 .byte 0 + 4378 02ba 03 .uleb128 0x3 + 4379 02bb 0E .uleb128 0xe + 4380 02bc 3A .uleb128 0x3a + 4381 02bd 0B .uleb128 0xb + 4382 02be 3B .uleb128 0x3b + 4383 02bf 0B .uleb128 0xb + 4384 02c0 49 .uleb128 0x49 + 4385 02c1 13 .uleb128 0x13 + 4386 02c2 02 .uleb128 0x2 + 4387 02c3 0A .uleb128 0xa + 4388 02c4 00 .byte 0 + 4389 02c5 00 .byte 0 + 4390 02c6 00 .byte 0 + 4391 .section .debug_loc,"",%progbits + 4392 .Ldebug_loc0: + 4393 .LLST0: + 4394 0000 00000000 .4byte .LFB66 + 4395 0004 02000000 .4byte .LCFI0 + 4396 0008 0200 .2byte 0x2 + 4397 000a 7D .byte 0x7d + 4398 000b 00 .sleb128 0 + 4399 000c 02000000 .4byte .LCFI0 + 4400 0010 38000000 .4byte .LFE66 + 4401 0014 0200 .2byte 0x2 + 4402 0016 7D .byte 0x7d + 4403 0017 10 .sleb128 16 + 4404 0018 00000000 .4byte 0 + 4405 001c 00000000 .4byte 0 + 4406 .LLST1: + 4407 0020 00000000 .4byte .LVL0 + 4408 0024 0A000000 .4byte .LVL1 + 4409 0028 0100 .2byte 0x1 + 4410 002a 50 .byte 0x50 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 80 + + + 4411 002b 00000000 .4byte 0 + 4412 002f 00000000 .4byte 0 + 4413 .LLST2: + 4414 0033 00000000 .4byte .LFB64 + 4415 0037 02000000 .4byte .LCFI1 + 4416 003b 0200 .2byte 0x2 + 4417 003d 7D .byte 0x7d + 4418 003e 00 .sleb128 0 + 4419 003f 02000000 .4byte .LCFI1 + 4420 0043 28000000 .4byte .LFE64 + 4421 0047 0200 .2byte 0x2 + 4422 0049 7D .byte 0x7d + 4423 004a 08 .sleb128 8 + 4424 004b 00000000 .4byte 0 + 4425 004f 00000000 .4byte 0 + 4426 .LLST3: + 4427 0053 00000000 .4byte .LVL2 + 4428 0057 0A000000 .4byte .LVL5 + 4429 005b 0100 .2byte 0x1 + 4430 005d 50 .byte 0x50 + 4431 005e 00000000 .4byte 0 + 4432 0062 00000000 .4byte 0 + 4433 .LLST4: + 4434 0066 08000000 .4byte .LVL4 + 4435 006a 0F000000 .4byte .LVL6-1 + 4436 006e 0100 .2byte 0x1 + 4437 0070 53 .byte 0x53 + 4438 0071 00000000 .4byte 0 + 4439 0075 00000000 .4byte 0 + 4440 .LLST5: + 4441 0079 1E000000 .4byte .LVL8 + 4442 007d 28000000 .4byte .LFE64 + 4443 0081 0100 .2byte 0x1 + 4444 0083 53 .byte 0x53 + 4445 0084 00000000 .4byte 0 + 4446 0088 00000000 .4byte 0 + 4447 .LLST6: + 4448 008c 00000000 .4byte .LFB63 + 4449 0090 02000000 .4byte .LCFI2 + 4450 0094 0200 .2byte 0x2 + 4451 0096 7D .byte 0x7d + 4452 0097 00 .sleb128 0 + 4453 0098 02000000 .4byte .LCFI2 + 4454 009c 28000000 .4byte .LFE63 + 4455 00a0 0200 .2byte 0x2 + 4456 00a2 7D .byte 0x7d + 4457 00a3 08 .sleb128 8 + 4458 00a4 00000000 .4byte 0 + 4459 00a8 00000000 .4byte 0 + 4460 .LLST7: + 4461 00ac 00000000 .4byte .LVL9 + 4462 00b0 0A000000 .4byte .LVL12 + 4463 00b4 0100 .2byte 0x1 + 4464 00b6 50 .byte 0x50 + 4465 00b7 00000000 .4byte 0 + 4466 00bb 00000000 .4byte 0 + 4467 .LLST8: + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 81 + + + 4468 00bf 08000000 .4byte .LVL11 + 4469 00c3 0F000000 .4byte .LVL13-1 + 4470 00c7 0100 .2byte 0x1 + 4471 00c9 53 .byte 0x53 + 4472 00ca 00000000 .4byte 0 + 4473 00ce 00000000 .4byte 0 + 4474 .LLST9: + 4475 00d2 1E000000 .4byte .LVL15 + 4476 00d6 28000000 .4byte .LFE63 + 4477 00da 0100 .2byte 0x1 + 4478 00dc 53 .byte 0x53 + 4479 00dd 00000000 .4byte 0 + 4480 00e1 00000000 .4byte 0 + 4481 .LLST10: + 4482 00e5 00000000 .4byte .LFB62 + 4483 00e9 04000000 .4byte .LCFI3 + 4484 00ed 0200 .2byte 0x2 + 4485 00ef 7D .byte 0x7d + 4486 00f0 00 .sleb128 0 + 4487 00f1 04000000 .4byte .LCFI3 + 4488 00f5 18000000 .4byte .LCFI4 + 4489 00f9 0200 .2byte 0x2 + 4490 00fb 7D .byte 0x7d + 4491 00fc 24 .sleb128 36 + 4492 00fd 18000000 .4byte .LCFI4 + 4493 0101 AC000000 .4byte .LFE62 + 4494 0105 0200 .2byte 0x2 + 4495 0107 7D .byte 0x7d + 4496 0108 30 .sleb128 48 + 4497 0109 00000000 .4byte 0 + 4498 010d 00000000 .4byte 0 + 4499 .LLST11: + 4500 0111 00000000 .4byte .LVL16 + 4501 0115 2A000000 .4byte .LVL17 + 4502 0119 0100 .2byte 0x1 + 4503 011b 50 .byte 0x50 + 4504 011c 2A000000 .4byte .LVL17 + 4505 0120 AC000000 .4byte .LFE62 + 4506 0124 0300 .2byte 0x3 + 4507 0126 79 .byte 0x79 + 4508 0127 01 .sleb128 1 + 4509 0128 9F .byte 0x9f + 4510 0129 00000000 .4byte 0 + 4511 012d 00000000 .4byte 0 + 4512 .LLST13: + 4513 0131 4E000000 .4byte .LVL21 + 4514 0135 54000000 .4byte .LVL22 + 4515 0139 0100 .2byte 0x1 + 4516 013b 53 .byte 0x53 + 4517 013c 76000000 .4byte .LVL23 + 4518 0140 7A000000 .4byte .LVL24 + 4519 0144 0100 .2byte 0x1 + 4520 0146 53 .byte 0x53 + 4521 0147 00000000 .4byte 0 + 4522 014b 00000000 .4byte 0 + 4523 .LLST14: + 4524 014f 36000000 .4byte .LVL19 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 82 + + + 4525 0153 3A000000 .4byte .LVL20 + 4526 0157 0300 .2byte 0x3 + 4527 0159 75 .byte 0x75 + 4528 015a 7F .sleb128 -1 + 4529 015b 9F .byte 0x9f + 4530 015c 00000000 .4byte 0 + 4531 0160 00000000 .4byte 0 + 4532 .LLST15: + 4533 0164 2A000000 .4byte .LVL17 + 4534 0168 2C000000 .4byte .LVL18 + 4535 016c 0100 .2byte 0x1 + 4536 016e 50 .byte 0x50 + 4537 016f 2C000000 .4byte .LVL18 + 4538 0173 AC000000 .4byte .LFE62 + 4539 0177 0200 .2byte 0x2 + 4540 0179 91 .byte 0x91 + 4541 017a 54 .sleb128 -44 + 4542 017b 00000000 .4byte 0 + 4543 017f 00000000 .4byte 0 + 4544 .LLST16: + 4545 0183 00000000 .4byte .LFB67 + 4546 0187 02000000 .4byte .LCFI5 + 4547 018b 0200 .2byte 0x2 + 4548 018d 7D .byte 0x7d + 4549 018e 00 .sleb128 0 + 4550 018f 02000000 .4byte .LCFI5 + 4551 0193 04000000 .4byte .LCFI6 + 4552 0197 0200 .2byte 0x2 + 4553 0199 7D .byte 0x7d + 4554 019a 10 .sleb128 16 + 4555 019b 04000000 .4byte .LCFI6 + 4556 019f 68000000 .4byte .LFE67 + 4557 01a3 0200 .2byte 0x2 + 4558 01a5 7D .byte 0x7d + 4559 01a6 20 .sleb128 32 + 4560 01a7 00000000 .4byte 0 + 4561 01ab 00000000 .4byte 0 + 4562 .LLST17: + 4563 01af 00000000 .4byte .LVL25 + 4564 01b3 14000000 .4byte .LVL26 + 4565 01b7 0100 .2byte 0x1 + 4566 01b9 50 .byte 0x50 + 4567 01ba 2C000000 .4byte .LVL27 + 4568 01be 3A000000 .4byte .LVL29 + 4569 01c2 0100 .2byte 0x1 + 4570 01c4 53 .byte 0x53 + 4571 01c5 52000000 .4byte .LVL30 + 4572 01c9 54000000 .4byte .LVL31 + 4573 01cd 0100 .2byte 0x1 + 4574 01cf 50 .byte 0x50 + 4575 01d0 00000000 .4byte 0 + 4576 01d4 00000000 .4byte 0 + 4577 .LLST18: + 4578 01d8 2C000000 .4byte .LVL27 + 4579 01dc 38000000 .4byte .LVL28 + 4580 01e0 0100 .2byte 0x1 + 4581 01e2 54 .byte 0x54 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 83 + + + 4582 01e3 38000000 .4byte .LVL28 + 4583 01e7 3A000000 .4byte .LVL29 + 4584 01eb 0300 .2byte 0x3 + 4585 01ed 74 .byte 0x74 + 4586 01ee 01 .sleb128 1 + 4587 01ef 9F .byte 0x9f + 4588 01f0 00000000 .4byte 0 + 4589 01f4 00000000 .4byte 0 + 4590 .LLST19: + 4591 01f8 00000000 .4byte .LFB68 + 4592 01fc 04000000 .4byte .LCFI7 + 4593 0200 0200 .2byte 0x2 + 4594 0202 7D .byte 0x7d + 4595 0203 00 .sleb128 0 + 4596 0204 04000000 .4byte .LCFI7 + 4597 0208 06000000 .4byte .LCFI8 + 4598 020c 0200 .2byte 0x2 + 4599 020e 7D .byte 0x7d + 4600 020f 20 .sleb128 32 + 4601 0210 06000000 .4byte .LCFI8 + 4602 0214 E4030000 .4byte .LFE68 + 4603 0218 0200 .2byte 0x2 + 4604 021a 7D .byte 0x7d + 4605 021b 30 .sleb128 48 + 4606 021c 00000000 .4byte 0 + 4607 0220 00000000 .4byte 0 + 4608 .LLST20: + 4609 0224 4A000000 .4byte .LVL32 + 4610 0228 52000000 .4byte .LVL33 + 4611 022c 0200 .2byte 0x2 + 4612 022e 30 .byte 0x30 + 4613 022f 9F .byte 0x9f + 4614 0230 74000000 .4byte .LVL34 + 4615 0234 8C000000 .4byte .LVL35 + 4616 0238 0100 .2byte 0x1 + 4617 023a 54 .byte 0x54 + 4618 023b 0E020000 .4byte .LVL58 + 4619 023f 1E020000 .4byte .LVL59 + 4620 0243 0200 .2byte 0x2 + 4621 0245 31 .byte 0x31 + 4622 0246 9F .byte 0x9f + 4623 0247 7A030000 .4byte .LVL72 + 4624 024b E4030000 .4byte .LFE68 + 4625 024f 0100 .2byte 0x1 + 4626 0251 59 .byte 0x59 + 4627 0252 00000000 .4byte 0 + 4628 0256 00000000 .4byte 0 + 4629 .LLST21: + 4630 025a 4E020000 .4byte .LVL61 + 4631 025e CC020000 .4byte .LVL62 + 4632 0262 0400 .2byte 0x4 + 4633 0264 0A .byte 0xa + 4634 0265 D007 .2byte 0x7d0 + 4635 0267 9F .byte 0x9f + 4636 0268 DE020000 .4byte .LVL64 + 4637 026c E2020000 .4byte .LVL65 + 4638 0270 0100 .2byte 0x1 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 84 + + + 4639 0272 56 .byte 0x56 + 4640 0273 2E030000 .4byte .LVL68 + 4641 0277 32030000 .4byte .LVL69 + 4642 027b 0100 .2byte 0x1 + 4643 027d 56 .byte 0x56 + 4644 027e 00000000 .4byte 0 + 4645 0282 00000000 .4byte 0 + 4646 .LLST22: + 4647 0286 4E020000 .4byte .LVL61 + 4648 028a CC020000 .4byte .LVL62 + 4649 028e 0200 .2byte 0x2 + 4650 0290 30 .byte 0x30 + 4651 0291 9F .byte 0x9f + 4652 0292 D4020000 .4byte .LVL63 + 4653 0296 E2020000 .4byte .LVL65 + 4654 029a 0100 .2byte 0x1 + 4655 029c 54 .byte 0x54 + 4656 029d 24030000 .4byte .LVL67 + 4657 02a1 32030000 .4byte .LVL69 + 4658 02a5 0100 .2byte 0x1 + 4659 02a7 54 .byte 0x54 + 4660 02a8 00000000 .4byte 0 + 4661 02ac 00000000 .4byte 0 + 4662 .LLST23: + 4663 02b0 0E020000 .4byte .LVL58 + 4664 02b4 1E020000 .4byte .LVL59 + 4665 02b8 0200 .2byte 0x2 + 4666 02ba 30 .byte 0x30 + 4667 02bb 9F .byte 0x9f + 4668 02bc 7A030000 .4byte .LVL72 + 4669 02c0 E4030000 .4byte .LFE68 + 4670 02c4 0100 .2byte 0x1 + 4671 02c6 5A .byte 0x5a + 4672 02c7 00000000 .4byte 0 + 4673 02cb 00000000 .4byte 0 + 4674 .LLST24: + 4675 02cf 94000000 .4byte .LVL36 + 4676 02d3 96000000 .4byte .LVL37 + 4677 02d7 0600 .2byte 0x6 + 4678 02d9 03 .byte 0x3 + 4679 02da 40000000 .4byte .LC5 + 4680 02de 9F .byte 0x9f + 4681 02df 00000000 .4byte 0 + 4682 02e3 00000000 .4byte 0 + 4683 .LLST25: + 4684 02e7 B2000000 .4byte .LVL38 + 4685 02eb B4000000 .4byte .LVL39 + 4686 02ef 0600 .2byte 0x6 + 4687 02f1 03 .byte 0x3 + 4688 02f2 64000000 .4byte .LC7 + 4689 02f6 9F .byte 0x9f + 4690 02f7 00000000 .4byte 0 + 4691 02fb 00000000 .4byte 0 + 4692 .LLST26: + 4693 02ff D0000000 .4byte .LVL40 + 4694 0303 D2000000 .4byte .LVL41 + 4695 0307 0600 .2byte 0x6 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 85 + + + 4696 0309 03 .byte 0x3 + 4697 030a 80000000 .4byte .LC9 + 4698 030e 9F .byte 0x9f + 4699 030f 00000000 .4byte 0 + 4700 0313 00000000 .4byte 0 + 4701 .LLST27: + 4702 0317 EE000000 .4byte .LVL42 + 4703 031b F0000000 .4byte .LVL43 + 4704 031f 0600 .2byte 0x6 + 4705 0321 03 .byte 0x3 + 4706 0322 9C000000 .4byte .LC11 + 4707 0326 9F .byte 0x9f + 4708 0327 00000000 .4byte 0 + 4709 032b 00000000 .4byte 0 + 4710 .LLST28: + 4711 032f 0C010000 .4byte .LVL44 + 4712 0333 0E010000 .4byte .LVL45 + 4713 0337 0600 .2byte 0x6 + 4714 0339 03 .byte 0x3 + 4715 033a BC000000 .4byte .LC13 + 4716 033e 9F .byte 0x9f + 4717 033f 00000000 .4byte 0 + 4718 0343 00000000 .4byte 0 + 4719 .LLST29: + 4720 0347 2A010000 .4byte .LVL46 + 4721 034b 2C010000 .4byte .LVL47 + 4722 034f 0600 .2byte 0x6 + 4723 0351 03 .byte 0x3 + 4724 0352 F8000000 .4byte .LC15 + 4725 0356 9F .byte 0x9f + 4726 0357 00000000 .4byte 0 + 4727 035b 00000000 .4byte 0 + 4728 .LLST30: + 4729 035f 4E010000 .4byte .LVL48 + 4730 0363 50010000 .4byte .LVL49 + 4731 0367 0600 .2byte 0x6 + 4732 0369 03 .byte 0x3 + 4733 036a 20010000 .4byte .LC17 + 4734 036e 9F .byte 0x9f + 4735 036f 00000000 .4byte 0 + 4736 0373 00000000 .4byte 0 + 4737 .LLST31: + 4738 0377 78010000 .4byte .LVL50 + 4739 037b 7A010000 .4byte .LVL51 + 4740 037f 0600 .2byte 0x6 + 4741 0381 03 .byte 0x3 + 4742 0382 34010000 .4byte .LC18 + 4743 0386 9F .byte 0x9f + 4744 0387 00000000 .4byte 0 + 4745 038b 00000000 .4byte 0 + 4746 .LLST32: + 4747 038f 9C010000 .4byte .LVL52 + 4748 0393 9E010000 .4byte .LVL53 + 4749 0397 0600 .2byte 0x6 + 4750 0399 03 .byte 0x3 + 4751 039a 48010000 .4byte .LC19 + 4752 039e 9F .byte 0x9f + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 86 + + + 4753 039f 00000000 .4byte 0 + 4754 03a3 00000000 .4byte 0 + 4755 .LLST33: + 4756 03a7 C0010000 .4byte .LVL54 + 4757 03ab C2010000 .4byte .LVL55 + 4758 03af 0600 .2byte 0x6 + 4759 03b1 03 .byte 0x3 + 4760 03b2 5C010000 .4byte .LC20 + 4761 03b6 9F .byte 0x9f + 4762 03b7 00000000 .4byte 0 + 4763 03bb 00000000 .4byte 0 + 4764 .LLST34: + 4765 03bf E2010000 .4byte .LVL56 + 4766 03c3 E6010000 .4byte .LVL57 + 4767 03c7 0600 .2byte 0x6 + 4768 03c9 03 .byte 0x3 + 4769 03ca 70010000 .4byte .LC21 + 4770 03ce 9F .byte 0x9f + 4771 03cf 00000000 .4byte 0 + 4772 03d3 00000000 .4byte 0 + 4773 .LLST35: + 4774 03d7 1E020000 .4byte .LVL59 + 4775 03db 22020000 .4byte .LVL60 + 4776 03df 0600 .2byte 0x6 + 4777 03e1 03 .byte 0x3 + 4778 03e2 98010000 .4byte .LC24 + 4779 03e6 9F .byte 0x9f + 4780 03e7 00000000 .4byte 0 + 4781 03eb 00000000 .4byte 0 + 4782 .LLST38: + 4783 03ef 40030000 .4byte .LVL70 + 4784 03f3 42030000 .4byte .LVL71 + 4785 03f7 0600 .2byte 0x6 + 4786 03f9 03 .byte 0x3 + 4787 03fa 84010000 .4byte .LC22 + 4788 03fe 9F .byte 0x9f + 4789 03ff 00000000 .4byte 0 + 4790 0403 00000000 .4byte 0 + 4791 .LLST39: + 4792 0407 8C030000 .4byte .LVL73 + 4793 040b 8E030000 .4byte .LVL74 + 4794 040f 0600 .2byte 0x6 + 4795 0411 03 .byte 0x3 + 4796 0412 A4010000 .4byte .LC25 + 4797 0416 9F .byte 0x9f + 4798 0417 00000000 .4byte 0 + 4799 041b 00000000 .4byte 0 + 4800 .section .debug_aranges,"",%progbits + 4801 0000 44000000 .4byte 0x44 + 4802 0004 0200 .2byte 0x2 + 4803 0006 00000000 .4byte .Ldebug_info0 + 4804 000a 04 .byte 0x4 + 4805 000b 00 .byte 0 + 4806 000c 0000 .2byte 0 + 4807 000e 0000 .2byte 0 + 4808 0010 00000000 .4byte .LFB66 + 4809 0014 38000000 .4byte .LFE66-.LFB66 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 87 + + + 4810 0018 00000000 .4byte .LFB64 + 4811 001c 28000000 .4byte .LFE64-.LFB64 + 4812 0020 00000000 .4byte .LFB63 + 4813 0024 28000000 .4byte .LFE63-.LFB63 + 4814 0028 00000000 .4byte .LFB62 + 4815 002c AC000000 .4byte .LFE62-.LFB62 + 4816 0030 00000000 .4byte .LFB67 + 4817 0034 68000000 .4byte .LFE67-.LFB67 + 4818 0038 00000000 .4byte .LFB68 + 4819 003c E4030000 .4byte .LFE68-.LFB68 + 4820 0040 00000000 .4byte 0 + 4821 0044 00000000 .4byte 0 + 4822 .section .debug_ranges,"",%progbits + 4823 .Ldebug_ranges0: + 4824 0000 0C000000 .4byte .LBB40 + 4825 0004 0E000000 .4byte .LBE40 + 4826 0008 52000000 .4byte .LBB43 + 4827 000c 68000000 .4byte .LBE43 + 4828 0010 00000000 .4byte 0 + 4829 0014 00000000 .4byte 0 + 4830 0018 0C000000 .4byte .LBB41 + 4831 001c 0E000000 .4byte .LBE41 + 4832 0020 52000000 .4byte .LBB42 + 4833 0024 68000000 .4byte .LBE42 + 4834 0028 00000000 .4byte 0 + 4835 002c 00000000 .4byte 0 + 4836 0030 0C030000 .4byte .LBB70 + 4837 0034 14030000 .4byte .LBE70 + 4838 0038 18030000 .4byte .LBB74 + 4839 003c 1A030000 .4byte .LBE74 + 4840 0040 20030000 .4byte .LBB75 + 4841 0044 24030000 .4byte .LBE75 + 4842 0048 00000000 .4byte 0 + 4843 004c 00000000 .4byte 0 + 4844 0050 00000000 .4byte .LFB66 + 4845 0054 38000000 .4byte .LFE66 + 4846 0058 00000000 .4byte .LFB64 + 4847 005c 28000000 .4byte .LFE64 + 4848 0060 00000000 .4byte .LFB63 + 4849 0064 28000000 .4byte .LFE63 + 4850 0068 00000000 .4byte .LFB62 + 4851 006c AC000000 .4byte .LFE62 + 4852 0070 00000000 .4byte .LFB67 + 4853 0074 68000000 .4byte .LFE67 + 4854 0078 00000000 .4byte .LFB68 + 4855 007c E4030000 .4byte .LFE68 + 4856 0080 00000000 .4byte 0 + 4857 0084 00000000 .4byte 0 + 4858 .section .debug_line,"",%progbits + 4859 .Ldebug_line0: + 4860 0000 55040000 .section .debug_str,"MS",%progbits,1 + 4860 02009402 + 4860 00000201 + 4860 FB0E0D00 + 4860 01010101 + 4861 .LASF99: + 4862 0000 44494552 .ascii "DIER\000" + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 88 + + + 4862 00 + 4863 .LASF79: + 4864 0005 7264796D .ascii "rdymsg\000" + 4864 736700 + 4865 .LASF15: + 4866 000c 75696E74 .ascii "uint64_t\000" + 4866 36345F74 + 4866 00 + 4867 .LASF191: + 4868 0015 474E5520 .ascii "GNU C 4.6.0\000" + 4868 4320342E + 4868 362E3000 + 4869 .LASF93: + 4870 0021 4F757470 .ascii "OutputQueue\000" + 4870 75745175 + 4870 65756500 + 4871 .LASF130: + 4872 002d 4F545950 .ascii "OTYPER\000" + 4872 455200 + 4873 .LASF143: + 4874 0034 4750545F .ascii "GPT_ONESHOT\000" + 4874 4F4E4553 + 4874 484F5400 + 4875 .LASF76: + 4876 0040 6D625F66 .ascii "mb_fullsem\000" + 4876 756C6C73 + 4876 656D00 + 4877 .LASF138: + 4878 004b 696F706F .ascii "ioportmask_t\000" + 4878 72746D61 + 4878 736B5F74 + 4878 00 + 4879 .LASF126: + 4880 0058 54494D5F .ascii "TIM_TypeDef\000" + 4880 54797065 + 4880 44656600 + 4881 .LASF87: + 4882 0064 715F746F .ascii "q_top\000" + 4882 7000 + 4883 .LASF78: + 4884 006a 4D61696C .ascii "Mailbox\000" + 4884 626F7800 + 4885 .LASF129: + 4886 0072 4D4F4445 .ascii "MODER\000" + 4886 5200 + 4887 .LASF16: + 4888 0078 75696E74 .ascii "uint_fast16_t\000" + 4888 5F666173 + 4888 7431365F + 4888 7400 + 4889 .LASF6: + 4890 0086 6C6F6E67 .ascii "long long unsigned int\000" + 4890 206C6F6E + 4890 6720756E + 4890 7369676E + 4890 65642069 + 4891 .LASF132: + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 89 + + + 4892 009d 50555044 .ascii "PUPDR\000" + 4892 5200 + 4893 .LASF80: + 4894 00a3 65786974 .ascii "exitcode\000" + 4894 636F6465 + 4894 00 + 4895 .LASF174: + 4896 00ac 7072696E .ascii "print\000" + 4896 7400 + 4897 .LASF187: + 4898 00b2 73617475 .ascii "saturated\000" + 4898 72617465 + 4898 6400 + 4899 .LASF173: + 4900 00bc 7072696E .ascii "printn\000" + 4900 746E00 + 4901 .LASF185: + 4902 00c3 47505444 .ascii "GPTD2\000" + 4902 3200 + 4903 .LASF186: + 4904 00c9 47505444 .ascii "GPTD3\000" + 4904 3300 + 4905 .LASF152: + 4906 00cf 66726571 .ascii "frequency\000" + 4906 75656E63 + 4906 7900 + 4907 .LASF178: + 4908 00d9 67707432 .ascii "gpt2cb\000" + 4908 636200 + 4909 .LASF29: + 4910 00e0 705F7072 .ascii "p_prio\000" + 4910 696F00 + 4911 .LASF171: + 4912 00e7 72656164 .ascii "readt\000" + 4912 7400 + 4913 .LASF103: + 4914 00ed 43434D52 .ascii "CCMR1\000" + 4914 3100 + 4915 .LASF105: + 4916 00f3 43434D52 .ascii "CCMR2\000" + 4916 3200 + 4917 .LASF5: + 4918 00f9 6C6F6E67 .ascii "long long int\000" + 4918 206C6F6E + 4918 6720696E + 4918 7400 + 4919 .LASF1: + 4920 0107 7369676E .ascii "signed char\000" + 4920 65642063 + 4920 68617200 + 4921 .LASF133: + 4922 0113 42535252 .ascii "BSRR\000" + 4922 00 + 4923 .LASF127: + 4924 0118 47545052 .ascii "GTPR\000" + 4924 00 + 4925 .LASF17: + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 90 + + + 4926 011d 626F6F6C .ascii "bool_t\000" + 4926 5F7400 + 4927 .LASF63: + 4928 0124 6D5F7175 .ascii "m_queue\000" + 4928 65756500 + 4929 .LASF142: + 4930 012c 4750545F .ascii "GPT_CONTINUOUS\000" + 4930 434F4E54 + 4930 494E554F + 4930 555300 + 4931 .LASF110: + 4932 013b 52455345 .ascii "RESERVED10\000" + 4932 52564544 + 4932 313000 + 4933 .LASF111: + 4934 0146 52455345 .ascii "RESERVED11\000" + 4934 52564544 + 4934 313100 + 4935 .LASF112: + 4936 0151 52455345 .ascii "RESERVED12\000" + 4936 52564544 + 4936 313200 + 4937 .LASF114: + 4938 015c 52455345 .ascii "RESERVED13\000" + 4938 52564544 + 4938 313300 + 4939 .LASF116: + 4940 0167 52455345 .ascii "RESERVED14\000" + 4940 52564544 + 4940 313400 + 4941 .LASF118: + 4942 0172 52455345 .ascii "RESERVED15\000" + 4942 52564544 + 4942 313500 + 4943 .LASF120: + 4944 017d 52455345 .ascii "RESERVED16\000" + 4944 52564544 + 4944 313600 + 4945 .LASF121: + 4946 0188 52455345 .ascii "RESERVED17\000" + 4946 52564544 + 4946 313700 + 4947 .LASF122: + 4948 0193 52455345 .ascii "RESERVED18\000" + 4948 52564544 + 4948 313800 + 4949 .LASF146: + 4950 019e 73746174 .ascii "state\000" + 4950 6500 + 4951 .LASF7: + 4952 01a4 6C6F6E67 .ascii "long int\000" + 4952 20696E74 + 4952 00 + 4953 .LASF151: + 4954 01ad 67707463 .ascii "gptcnt_t\000" + 4954 6E745F74 + 4954 00 + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 91 + + + 4955 .LASF190: + 4956 01b6 67707433 .ascii "gpt3cfg\000" + 4956 63666700 + 4957 .LASF19: + 4958 01be 74737461 .ascii "tstate_t\000" + 4958 74655F74 + 4958 00 + 4959 .LASF36: + 4960 01c7 705F7265 .ascii "p_refs\000" + 4960 667300 + 4961 .LASF86: + 4962 01ce 715F6275 .ascii "q_buffer\000" + 4962 66666572 + 4962 00 + 4963 .LASF88: + 4964 01d7 715F7772 .ascii "q_wrptr\000" + 4964 70747200 + 4965 .LASF37: + 4966 01df 705F7469 .ascii "p_time\000" + 4966 6D6500 + 4967 .LASF31: + 4968 01e6 705F6E65 .ascii "p_newer\000" + 4968 77657200 + 4969 .LASF168: + 4970 01ee 70757477 .ascii "putwouldblock\000" + 4970 6F756C64 + 4970 626C6F63 + 4970 6B00 + 4971 .LASF60: + 4972 01fc 735F7175 .ascii "s_queue\000" + 4972 65756500 + 4973 .LASF149: + 4974 0204 67707463 .ascii "gptcallback_t\000" + 4974 616C6C62 + 4974 61636B5F + 4974 7400 + 4975 .LASF4: + 4976 0212 73686F72 .ascii "short unsigned int\000" + 4976 7420756E + 4976 7369676E + 4976 65642069 + 4976 6E7400 + 4977 .LASF180: + 4978 0225 696E7465 .ascii "interval\000" + 4978 7276616C + 4978 00 + 4979 .LASF131: + 4980 022e 4F535045 .ascii "OSPEEDR\000" + 4980 45445200 + 4981 .LASF54: + 4982 0236 725F6E65 .ascii "r_newer\000" + 4982 77657200 + 4983 .LASF145: + 4984 023e 47505444 .ascii "GPTDriver\000" + 4984 72697665 + 4984 7200 + 4985 .LASF47: + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 92 + + + 4986 0248 72656761 .ascii "regarm_t\000" + 4986 726D5F74 + 4986 00 + 4987 .LASF10: + 4988 0251 73697A65 .ascii "size_t\000" + 4988 5F7400 + 4989 .LASF125: + 4990 0258 52455345 .ascii "RESERVED20\000" + 4990 52564544 + 4990 323000 + 4991 .LASF189: + 4992 0263 67707432 .ascii "gpt2cfg\000" + 4992 63666700 + 4993 .LASF70: + 4994 026b 4576656E .ascii "EventSource\000" + 4994 74536F75 + 4994 72636500 + 4995 .LASF144: + 4996 0277 67707473 .ascii "gptstate_t\000" + 4996 74617465 + 4996 5F7400 + 4997 .LASF164: + 4998 0282 75736172 .ascii "usart\000" + 4998 7400 + 4999 .LASF0: + 5000 0288 756E7369 .ascii "unsigned int\000" + 5000 676E6564 + 5000 20696E74 + 5000 00 + 5001 .LASF12: + 5002 0295 75696E74 .ascii "uint16_t\000" + 5002 31365F74 + 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696E7463 .ascii "intctx\000" + 5207 747800 + 5208 .LASF157: + 5209 065e 53445F52 .ascii "SD_READY\000" + 5209 45414459 + 5209 00 + 5210 .LASF59: + 5211 0667 53656D61 .ascii "Semaphore\000" + 5211 70686F72 + 5211 6500 + 5212 .LASF113: + 5213 0671 43435231 .ascii "CCR1\000" + 5213 00 + 5214 .LASF115: + 5215 0676 43435232 .ascii "CCR2\000" + 5215 00 + 5216 .LASF117: + 5217 067b 43435233 .ascii "CCR3\000" + 5217 00 + 5218 .LASF119: + 5219 0680 43435234 .ascii "CCR4\000" + 5219 00 + 5220 .LASF71: + 5221 0685 65735F6E .ascii "es_next\000" + 5221 65787400 + 5222 .LASF58: + 5223 068d 52656164 .ascii "ReadyList\000" + 5223 794C6973 + 5223 7400 + 5224 .LASF90: + 5225 0697 715F6E6F .ascii "q_notify\000" + 5225 74696679 + 5225 00 + 5226 .LASF183: + 5227 06a0 726C6973 .ascii "rlist\000" + 5227 7400 + 5228 .LASF11: + 5229 06a6 75696E74 .ascii "uint8_t\000" + 5229 385F7400 + 5230 .LASF161: + 5231 06ae 666C6167 .ascii "flags\000" + 5231 7300 + 5232 .LASF66: + 5233 06b4 4576656E .ascii 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page 101 + + +DEFINED SYMBOLS + *ABS*:00000000 main.c +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:18 .text.println:00000000 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:23 .text.println:00000000 println +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:69 .text.println:00000030 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:75 .text.gpt3cb:00000000 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:80 .text.gpt3cb:00000000 gpt3cb +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:130 .text.gpt3cb:00000020 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:136 .text.gpt2cb:00000000 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:141 .text.gpt2cb:00000000 gpt2cb +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:191 .text.gpt2cb:00000020 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:197 .text.WorkerThread:00000000 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:202 .text.WorkerThread:00000000 WorkerThread +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1087 .bss.saturated:00000000 .LANCHOR1 +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:318 .text.WorkerThread:00000098 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:327 .text.printn:00000000 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:332 .text.printn:00000000 printn +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:422 .text.printn:00000064 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:429 .text.startup.main:00000000 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:435 .text.startup.main:00000000 main +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:854 .text.startup.main:00000250 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:890 .text.startup.main:000002cc $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1059 .text.startup.main:000003c4 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1071 .rodata.gpt2cfg:00000000 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1075 .rodata.gpt2cfg:00000000 gpt2cfg +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1079 .bss.waWorkerThread:00000000 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1083 .bss.waWorkerThread:00000000 waWorkerThread +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1086 .bss.saturated:00000000 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1090 .bss.saturated:00000000 saturated +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1093 .rodata.gpt3cfg:00000000 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1097 .rodata.gpt3cfg:00000000 gpt3cfg +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1101 .rodata.str1.4:00000000 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1178 .bss.mb:00000000 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1182 .bss.mb:00000000 mb +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1185 .bss.b:00000000 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1189 .bss.b:00000000 b +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1192 .bss.x.3441:00000000 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1196 .bss.x.3441:00000000 x.3441 +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1199 .bss.cnt.3442:00000000 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1203 .bss.cnt.3442:00000000 cnt.3442 + .debug_frame:00000010 $d +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:74 .text.println:00000038 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:135 .text.gpt3cb:00000028 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:196 .text.gpt2cb:00000028 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:326 .text.WorkerThread:000000ac $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:428 .text.printn:00000068 $t +C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1070 .text.startup.main:000003e4 $t + +UNDEFINED SYMBOLS +SD1 +chMBPostI +chMBFetch +chMBPost +rlist +halInit +chSysInit +sdStart + ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 102 + + +_pal_lld_setgroupmode +gptStart +chMBInit +chThdCreateStatic +GPTD2 +GPTD3 +gptStartContinuous +chThdSleep +gptStopTimer diff --git a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..5839ef86a --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h @@ -0,0 +1,185 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_1P8 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 6 +#define STM32_GPT_TIM3_IRQ_PRIORITY 10 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/IRQ_STORM/readme.txt b/testhal/STM32L1xx/IRQ_STORM/readme.txt new file mode 100644 index 000000000..f55cf8471 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx PWM-ICU drivers. + +** Board Setup ** + +- Remove the LCD module. +- Connect PA15 and PC6 together. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/PWM-ICU/Makefile b/testhal/STM32L1xx/PWM-ICU/Makefile index 10a6ed0e8..9209b441d 100644 --- a/testhal/STM32L1xx/PWM-ICU/Makefile +++ b/testhal/STM32L1xx/PWM-ICU/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C++ specific options here (added to USE_OPT). -- cgit v1.2.3 From c1a1893307e154fa295f2fbf1d873e0471c0fd81 Mon Sep 17 00:00:00 2001 From: barthess Date: Mon, 19 Sep 2011 11:47:12 +0000 Subject: small fix in RCC helper for RTC git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3347 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/stm32_rcc.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h index 7735b2034..7f215a720 100644 --- a/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -214,7 +214,8 @@ * * @api */ -#define rccEnableBKP(lp) rccEnableAPB1(RCC_APB1ENR_BKPEN, lp); +#define rccEnableBKP(lp) \ + rccEnableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp); /** * @brief Disables BKP interface clock. @@ -224,7 +225,8 @@ * * @api */ -#define rccDisableBKP(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp); +#define rccDisableBKP(lp) \ + rccDisableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp); /** * @brief Resets the Backup Domain. -- cgit v1.2.3 From 22d8fa4450d5563d3ff1134a9f007b73c977ff9a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Sep 2011 12:04:02 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3348 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/GPIOv2/pal_lld.h | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h index a73f80c7a..6c799c14c 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -135,7 +135,13 @@ typedef struct { volatile uint32_t PUPDR; volatile uint32_t IDR; volatile uint32_t ODR; - volatile uint32_t BSRR; + volatile union { + uint32_t W; + struct { + uint16_t set; + uint16_t clear; + } H; + } BSRR; volatile uint32_t LCKR; volatile uint32_t AFRL; volatile uint32_t AFRH; @@ -369,7 +375,7 @@ typedef GPIO_TypeDef * ioportid_t; * * @notapi */ -#define pal_lld_setport(port, bits) ((port)->BSRR = (uint32_t)(bits)) +#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits)) /** * @brief Clears a bits mask on a I/O port. @@ -386,7 +392,7 @@ typedef GPIO_TypeDef * ioportid_t; * * @notapi */ -#define pal_lld_clearport(port, bits) ((port)->BSRR = (uint32_t)(bits) << 16) +#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) /** * @brief Writes a group of bits. @@ -407,8 +413,8 @@ typedef GPIO_TypeDef * ioportid_t; * @notapi */ #define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \ - (((bits) & (mask)) << (offset))) + ((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) | \ + (((bits) & (mask)) << (offset))) /** * @brief Pads group mode setup. -- cgit v1.2.3 From 79f641c928cc438ab41df0eab6850355f07edd1d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Sep 2011 12:09:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3349 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/GPT/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testhal/STM32L1xx/GPT/main.c b/testhal/STM32L1xx/GPT/main.c index 49247bac6..4fadc4f9c 100644 --- a/testhal/STM32L1xx/GPT/main.c +++ b/testhal/STM32L1xx/GPT/main.c @@ -87,12 +87,12 @@ int main(void) { */ while (TRUE) { palSetPad(GPIOB, GPIOB_LED3); - gptStopTimer(&GPTD2); gptStartContinuous(&GPTD2, 5000); chThdSleepMilliseconds(5000); - palClearPad(GPIOB, GPIOB_LED3); gptStopTimer(&GPTD2); + palClearPad(GPIOB, GPIOB_LED3); gptStartContinuous(&GPTD2, 2500); chThdSleepMilliseconds(5000); + gptStopTimer(&GPTD2); } } -- cgit v1.2.3 From bae85ff69f0037ae22bb9bf1fada5762f7db4292 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Sep 2011 12:54:13 +0000 Subject: Fixed problem in gptPolledDelay(). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3350 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/src/gpt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os/hal/src/gpt.c b/os/hal/src/gpt.c index c677f5284..726936ca8 100644 --- a/os/hal/src/gpt.c +++ b/os/hal/src/gpt.c @@ -236,6 +236,7 @@ void gptPolledDelay(GPTDriver *gptp, gptcnt_t interval) { gptp->state = GPT_ONESHOT; gpt_lld_polled_delay(gptp, interval); + gptp->state = GPT_READY; } #endif /* HAL_USE_GPT */ -- cgit v1.2.3 From 9ced1d4e653d7721b256fbde40f9260446ea434b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Sep 2011 13:01:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3351 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/IRQ_STORM/main.lst | 6048 ---------------------------------- 1 file changed, 6048 deletions(-) delete mode 100644 testhal/STM32L1xx/IRQ_STORM/main.lst diff --git a/testhal/STM32L1xx/IRQ_STORM/main.lst b/testhal/STM32L1xx/IRQ_STORM/main.lst deleted file mode 100644 index 7b4c43cc3..000000000 --- a/testhal/STM32L1xx/IRQ_STORM/main.lst +++ /dev/null @@ -1,6048 +0,0 @@ -ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 2 - 11 .eabi_attribute 18, 4 - 12 .thumb - 13 .file "main.c" - 14 .text - 15 .Ltext0: - 16 .cfi_sections .debug_frame - 17 .section .text.println,"ax",%progbits - 18 .align 2 - 19 .p2align 4,,15 - 20 .thumb - 21 .thumb_func - 22 .type println, %function - 23 println: - 24 .LFB66: - 25 .file 1 "main.c" - 26 .loc 1 177 0 - 27 .cfi_startproc - 28 @ args = 0, pretend = 0, frame = 0 - 29 @ frame_needed = 0, uses_anonymous_args = 0 - 30 .LVL0: - 31 0000 38B5 push {r3, r4, r5, lr} - 32 .LCFI0: - 33 .cfi_def_cfa_offset 16 - 34 .cfi_offset 14, -4 - 35 .cfi_offset 5, -8 - 36 .cfi_offset 4, -12 - 37 .cfi_offset 3, -16 - 38 .loc 1 179 0 - 39 0002 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 40 0004 0A4D ldr r5, .L8 - 41 0006 0446 mov r4, r0 - 42 0008 49B1 cbz r1, .L2 - 43 .LVL1: - 44 .L3: - 45 .loc 1 180 0 - 46 000a 2B68 ldr r3, [r5, #0] - 47 000c 0848 ldr r0, .L8 - 48 000e 1B69 ldr r3, [r3, #16] - 49 0010 4FF0FF32 mov r2, #-1 - 50 0014 9847 blx r3 - 51 .loc 1 179 0 - 52 0016 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 53 001a 0029 cmp r1, #0 - 54 001c F5D1 bne .L3 - 55 .L2: - 56 .loc 1 182 0 - 57 001e 2B68 ldr r3, [r5, #0] - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 2 - - - 58 0020 0449 ldr r1, .L8+4 - 59 0022 9C69 ldr r4, [r3, #24] - 60 0024 0222 movs r2, #2 - 61 0026 4FF0FF33 mov r3, #-1 - 62 002a 0148 ldr r0, .L8 - 63 002c A047 blx r4 - 64 .loc 1 183 0 - 65 002e 38BD pop {r3, r4, r5, pc} - 66 .L9: - 67 .align 2 - 68 .L8: - 69 0030 00000000 .word SD1 - 70 0034 00000000 .word .LC0 - 71 .cfi_endproc - 72 .LFE66: - 73 .size println, .-println - 74 0038 AFF30080 .section .text.gpt3cb,"ax",%progbits - 74 AFF30080 - 75 .align 2 - 76 .p2align 4,,15 - 77 .thumb - 78 .thumb_func - 79 .type gpt3cb, %function - 80 gpt3cb: - 81 .LFB64: - 82 .loc 1 138 0 - 83 .cfi_startproc - 84 @ args = 0, pretend = 0, frame = 0 - 85 @ frame_needed = 0, uses_anonymous_args = 0 - 86 .LVL2: - 87 0000 08B5 push {r3, lr} - 88 .LCFI1: - 89 .cfi_def_cfa_offset 8 - 90 .cfi_offset 14, -4 - 91 .cfi_offset 3, -8 - 92 .LBB34: - 93 .loc 1 142 0 - 94 0002 2023 movs r3, #32 - 95 .LVL3: - 96 @ 142 "main.c" 1 - 97 0004 83F31188 msr BASEPRI, r3 - 98 @ 0 "" 2 - 99 .LVL4: - 100 .thumb - 101 .LBE34: - 102 .loc 1 143 0 - 103 0008 0548 ldr r0, .L12 - 104 .LVL5: - 105 000a 0021 movs r1, #0 - 106 000c FFF7FEFF bl chMBPostI - 107 .LVL6: - 108 .loc 1 144 0 - 109 0010 10B1 cbz r0, .L11 - 110 .loc 1 145 0 - 111 0012 044B ldr r3, .L12+4 - 112 0014 0122 movs r2, #1 - 113 0016 1A60 str r2, [r3, #0] - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 3 - - - 114 .L11: - 115 .LBB35: - 116 .loc 1 146 0 - 117 0018 0023 movs r3, #0 - 118 .LVL7: - 119 @ 146 "main.c" 1 - 120 001a 83F31188 msr BASEPRI, r3 - 121 @ 0 "" 2 - 122 .LVL8: - 123 .thumb - 124 .LBE35: - 125 .loc 1 147 0 - 126 001e 08BD pop {r3, pc} - 127 .L13: - 128 .align 2 - 129 .L12: - 130 0020 78000000 .word .LANCHOR0+120 - 131 0024 00000000 .word .LANCHOR1 - 132 .cfi_endproc - 133 .LFE64: - 134 .size gpt3cb, .-gpt3cb - 135 0028 AFF30080 .section .text.gpt2cb,"ax",%progbits - 135 AFF30080 - 136 .align 2 - 137 .p2align 4,,15 - 138 .thumb - 139 .thumb_func - 140 .type gpt2cb, %function - 141 gpt2cb: - 142 .LFB63: - 143 .loc 1 124 0 - 144 .cfi_startproc - 145 @ args = 0, pretend = 0, frame = 0 - 146 @ frame_needed = 0, uses_anonymous_args = 0 - 147 .LVL9: - 148 0000 08B5 push {r3, lr} - 149 .LCFI2: - 150 .cfi_def_cfa_offset 8 - 151 .cfi_offset 14, -4 - 152 .cfi_offset 3, -8 - 153 .LBB36: - 154 .loc 1 128 0 - 155 0002 2023 movs r3, #32 - 156 .LVL10: - 157 @ 128 "main.c" 1 - 158 0004 83F31188 msr BASEPRI, r3 - 159 @ 0 "" 2 - 160 .LVL11: - 161 .thumb - 162 .LBE36: - 163 .loc 1 129 0 - 164 0008 0548 ldr r0, .L16 - 165 .LVL12: - 166 000a 0121 movs r1, #1 - 167 000c FFF7FEFF bl chMBPostI - 168 .LVL13: - 169 .loc 1 130 0 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 4 - - - 170 0010 10B1 cbz r0, .L15 - 171 .loc 1 131 0 - 172 0012 044B ldr r3, .L16+4 - 173 0014 0122 movs r2, #1 - 174 0016 1A60 str r2, [r3, #0] - 175 .L15: - 176 .LBB37: - 177 .loc 1 132 0 - 178 0018 0023 movs r3, #0 - 179 .LVL14: - 180 @ 132 "main.c" 1 - 181 001a 83F31188 msr BASEPRI, r3 - 182 @ 0 "" 2 - 183 .LVL15: - 184 .thumb - 185 .LBE37: - 186 .loc 1 133 0 - 187 001e 08BD pop {r3, pc} - 188 .L17: - 189 .align 2 - 190 .L16: - 191 0020 00000000 .word .LANCHOR0 - 192 0024 00000000 .word .LANCHOR1 - 193 .cfi_endproc - 194 .LFE63: - 195 .size gpt2cb, .-gpt2cb - 196 0028 AFF30080 .section .text.WorkerThread,"ax",%progbits - 196 AFF30080 - 197 .align 2 - 198 .p2align 4,,15 - 199 .thumb - 200 .thumb_func - 201 .type WorkerThread, %function - 202 WorkerThread: - 203 .LFB62: - 204 .loc 1 65 0 - 205 .cfi_startproc - 206 @ args = 0, pretend = 0, frame = 8 - 207 @ frame_needed = 0, uses_anonymous_args = 0 - 208 .LVL16: - 209 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 210 .LCFI3: - 211 .cfi_def_cfa_offset 36 - 212 .cfi_offset 14, -4 - 213 .cfi_offset 11, -8 - 214 .cfi_offset 10, -12 - 215 .cfi_offset 9, -16 - 216 .cfi_offset 8, -20 - 217 .cfi_offset 7, -24 - 218 .cfi_offset 6, -28 - 219 .cfi_offset 5, -32 - 220 .cfi_offset 4, -36 - 221 .loc 1 73 0 - 222 0004 244B ldr r3, .L31 - 223 0006 DFF8A0B0 ldr fp, .L31+16 - 224 000a DB69 ldr r3, [r3, #28] - 225 000c 234E ldr r6, .L31+4 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 5 - - - 226 000e 244A ldr r2, .L31+8 - 227 .loc 1 78 0 - 228 0010 00EB8007 add r7, r0, r0, lsl #2 - 229 0014 234C ldr r4, .L31+12 - 230 .loc 1 65 0 - 231 0016 83B0 sub sp, sp, #12 - 232 .LCFI4: - 233 .cfi_def_cfa_offset 48 - 234 .loc 1 73 0 - 235 0018 9A61 str r2, [r3, #24] - 236 001a 0509 lsrs r5, r0, #4 - 237 001c 00F1FF39 add r9, r0, #-1 - 238 0020 00F10108 add r8, r0, #1 - 239 .loc 1 78 0 - 240 0024 0BEBC707 add r7, fp, r7, lsl #3 - 241 .loc 1 113 0 - 242 0028 B246 mov sl, r6 - 243 .LVL17: - 244 .L29: - 245 .loc 1 78 0 - 246 002a 3846 mov r0, r7 - 247 .LVL18: - 248 002c 01A9 add r1, sp, #4 - 249 002e 4FF0FF32 mov r2, #-1 - 250 0032 FFF7FEFF bl chMBFetch - 251 .LVL19: - 252 .loc 1 93 0 - 253 0036 2DB1 cbz r5, .L20 - 254 0038 2B46 mov r3, r5 - 255 .LVL20: - 256 .L21: - 257 .loc 1 94 0 - 258 003a 2268 ldr r2, [r4, #0] - 259 003c 0132 adds r2, r2, #1 - 260 .loc 1 93 0 - 261 003e 013B subs r3, r3, #1 - 262 .loc 1 94 0 - 263 0040 2260 str r2, [r4, #0] - 264 .loc 1 93 0 - 265 0042 FAD1 bne .L21 - 266 .L20: - 267 .loc 1 99 0 - 268 0044 0199 ldr r1, [sp, #4] - 269 .loc 1 100 0 - 270 0046 0029 cmp r1, #0 - 271 0048 14BF ite ne - 272 004a 4346 movne r3, r8 - 273 004c 4B46 moveq r3, r9 - 274 .LVL21: - 275 .loc 1 104 0 - 276 004e 032B cmp r3, #3 - 277 0050 11D9 bls .L30 - 278 .loc 1 113 0 - 279 0052 3368 ldr r3, [r6, #0] - 280 .LVL22: - 281 0054 0133 adds r3, r3, #1 - 282 0056 B3F5FA7F cmp r3, #500 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 6 - - - 283 005a 3360 str r3, [r6, #0] - 284 005c E5D3 bcc .L29 - 285 .loc 1 114 0 - 286 005e 0022 movs r2, #0 - 287 .loc 1 115 0 - 288 0060 4FF48063 mov r3, #1024 - 289 .loc 1 114 0 - 290 0064 CAF80020 str r2, [sl, #0] - 291 .loc 1 115 0 - 292 0068 C4F20203 movt r3, 16386 - 293 006c 5A69 ldr r2, [r3, #20] - 294 006e 82F04002 eor r2, r2, #64 - 295 0072 5A61 str r2, [r3, #20] - 296 0074 D9E7 b .L29 - 297 .LVL23: - 298 .L30: - 299 .loc 1 107 0 - 300 0076 03EB8303 add r3, r3, r3, lsl #2 - 301 .LVL24: - 302 007a 0BEBC300 add r0, fp, r3, lsl #3 - 303 007e 0022 movs r2, #0 - 304 0080 FFF7FEFF bl chMBPost - 305 0084 0190 str r0, [sp, #4] - 306 .loc 1 108 0 - 307 0086 0028 cmp r0, #0 - 308 0088 CFD0 beq .L29 - 309 .loc 1 109 0 - 310 008a 40F20002 movw r2, #:lower16:.LANCHOR1 - 311 008e 0123 movs r3, #1 - 312 0090 C0F20002 movt r2, #:upper16:.LANCHOR1 - 313 0094 1360 str r3, [r2, #0] - 314 0096 C8E7 b .L29 - 315 .L32: - 316 .align 2 - 317 .L31: - 318 0098 00000000 .word rlist - 319 009c 00000000 .word .LANCHOR3 - 320 00a0 04000000 .word .LC1 - 321 00a4 00000000 .word .LANCHOR2 - 322 00a8 00000000 .word .LANCHOR0 - 323 .cfi_endproc - 324 .LFE62: - 325 .size WorkerThread, .-WorkerThread - 326 00ac AFF30080 .section .text.printn,"ax",%progbits - 327 .align 2 - 328 .p2align 4,,15 - 329 .thumb - 330 .thumb_func - 331 .type printn, %function - 332 printn: - 333 .LFB67: - 334 .loc 1 185 0 - 335 .cfi_startproc - 336 @ args = 0, pretend = 0, frame = 16 - 337 @ frame_needed = 0, uses_anonymous_args = 0 - 338 .LVL25: - 339 0000 70B5 push {r4, r5, r6, lr} - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 7 - - - 340 .LCFI5: - 341 .cfi_def_cfa_offset 16 - 342 .cfi_offset 14, -4 - 343 .cfi_offset 6, -8 - 344 .cfi_offset 5, -12 - 345 .cfi_offset 4, -16 - 346 0002 84B0 sub sp, sp, #16 - 347 .LCFI6: - 348 .cfi_def_cfa_offset 32 - 349 .loc 1 188 0 - 350 0004 0028 cmp r0, #0 - 351 0006 24D0 beq .L39 - 352 .loc 1 193 0 - 353 0008 4CF6CD42 movw r2, #52429 - 354 .LBB40: - 355 .LBB41: - 356 .loc 1 191 0 - 357 000c 6D46 mov r5, sp - 358 .LBE41: - 359 .LBE40: - 360 .loc 1 188 0 - 361 000e 6C46 mov r4, sp - 362 .loc 1 193 0 - 363 0010 CCF6CC42 movt r2, 52428 - 364 .LVL26: - 365 .L36: - 366 0014 A2FB0013 umull r1, r3, r2, r0 - 367 0018 DB08 lsrs r3, r3, #3 - 368 001a 03EB8301 add r1, r3, r3, lsl #2 - 369 001e A0EB4101 sub r1, r0, r1, lsl #1 - 370 0022 3031 adds r1, r1, #48 - 371 0024 C9B2 uxtb r1, r1 - 372 .loc 1 192 0 - 373 0026 1846 mov r0, r3 - 374 .loc 1 193 0 - 375 0028 04F8011B strb r1, [r4], #1 - 376 .LVL27: - 377 .loc 1 192 0 - 378 002c 002B cmp r3, #0 - 379 002e F1D1 bne .L36 - 380 .loc 1 194 0 - 381 0030 AC42 cmp r4, r5 - 382 0032 0CD9 bls .L33 - 383 0034 0B4E ldr r6, .L41 - 384 .loc 1 185 0 - 385 0036 013C subs r4, r4, #1 - 386 .LVL28: - 387 0038 01E0 b .L37 - 388 .LVL29: - 389 .L40: - 390 .loc 1 194 0 - 391 003a 14F8011D ldrb r1, [r4, #-1]! @ zero_extendqisi2 - 392 .L37: - 393 .loc 1 195 0 - 394 003e 3368 ldr r3, [r6, #0] - 395 0040 0848 ldr r0, .L41 - 396 0042 1B69 ldr r3, [r3, #16] - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 8 - - - 397 0044 4FF0FF32 mov r2, #-1 - 398 0048 9847 blx r3 - 399 .loc 1 194 0 - 400 004a AC42 cmp r4, r5 - 401 004c F5D1 bne .L40 - 402 .L33: - 403 .loc 1 197 0 - 404 004e 04B0 add sp, sp, #16 - 405 0050 70BD pop {r4, r5, r6, pc} - 406 .LVL30: - 407 .L39: - 408 .LBB43: - 409 .LBB42: - 410 .loc 1 189 0 - 411 0052 0448 ldr r0, .L41 - 412 .LVL31: - 413 0054 3021 movs r1, #48 - 414 0056 0368 ldr r3, [r0, #0] - 415 0058 4FF0FF32 mov r2, #-1 - 416 005c 1B69 ldr r3, [r3, #16] - 417 005e 9847 blx r3 - 418 0060 F5E7 b .L33 - 419 .L42: - 420 0062 00BF .align 2 - 421 .L41: - 422 0064 00000000 .word SD1 - 423 .LBE42: - 424 .LBE43: - 425 .cfi_endproc - 426 .LFE67: - 427 .size printn, .-printn - 428 0068 AFF30080 .section .text.startup.main,"ax",%progbits - 428 AFF30080 - 429 .align 2 - 430 .p2align 4,,15 - 431 .global main - 432 .thumb - 433 .thumb_func - 434 .type main, %function - 435 main: - 436 .LFB68: - 437 .loc 1 202 0 - 438 .cfi_startproc - 439 @ args = 0, pretend = 0, frame = 8 - 440 @ frame_needed = 0, uses_anonymous_args = 0 - 441 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, sl, lr} - 442 .LCFI7: - 443 .cfi_def_cfa_offset 32 - 444 .cfi_offset 14, -4 - 445 .cfi_offset 10, -8 - 446 .cfi_offset 9, -12 - 447 .cfi_offset 8, -16 - 448 .cfi_offset 7, -20 - 449 .cfi_offset 6, -24 - 450 .cfi_offset 5, -28 - 451 .cfi_offset 4, -32 - 452 0004 84B0 sub sp, sp, #16 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 9 - - - 453 .LCFI8: - 454 .cfi_def_cfa_offset 48 - 455 .loc 1 213 0 - 456 0006 FFF7FEFF bl halInit - 457 .loc 1 214 0 - 458 000a FFF7FEFF bl chSysInit - 459 .loc 1 219 0 - 460 000e 9048 ldr r0, .L84 - 461 0010 0021 movs r1, #0 - 462 0012 FFF7FEFF bl sdStart - 463 .loc 1 220 0 - 464 0016 0020 movs r0, #0 - 465 0018 C4F20200 movt r0, 16386 - 466 001c 4FF40071 mov r1, #512 - 467 0020 40F28232 movw r2, #898 - 468 0024 FFF7FEFF bl _pal_lld_setgroupmode - 469 .loc 1 221 0 - 470 0028 0020 movs r0, #0 - 471 002a 40F28232 movw r2, #898 - 472 002e C4F20200 movt r0, 16386 - 473 0032 4FF48061 mov r1, #1024 - 474 0036 FFF7FEFF bl _pal_lld_setgroupmode - 475 .loc 1 222 0 - 476 003a 8648 ldr r0, .L84+4 - 477 003c 8649 ldr r1, .L84+8 - 478 003e FFF7FEFF bl gptStart - 479 .loc 1 223 0 - 480 0042 8648 ldr r0, .L84+12 - 481 0044 8649 ldr r1, .L84+16 - 482 0046 FFF7FEFF bl gptStart - 483 .LVL32: - 484 .loc 1 229 0 - 485 004a 864E ldr r6, .L84+20 - 486 .loc 1 230 0 - 487 004c 864D ldr r5, .L84+24 - 488 004e 874F ldr r7, .L84+28 - 489 .loc 1 228 0 - 490 0050 0024 movs r4, #0 - 491 .LVL33: - 492 .L44: - 493 .loc 1 229 0 discriminator 2 - 494 0052 04EB8400 add r0, r4, r4, lsl #2 - 495 0056 3146 mov r1, r6 - 496 0058 0422 movs r2, #4 - 497 005a 07EBC000 add r0, r7, r0, lsl #3 - 498 005e FFF7FEFF bl chMBInit - 499 .loc 1 230 0 discriminator 2 - 500 0062 0094 str r4, [sp, #0] - 501 0064 2846 mov r0, r5 - 502 0066 2C22 movs r2, #44 - 503 0068 4FF49071 mov r1, #288 - 504 006c 804B ldr r3, .L84+32 - 505 .loc 1 228 0 discriminator 2 - 506 006e 0134 adds r4, r4, #1 - 507 .loc 1 230 0 discriminator 2 - 508 0070 FFF7FEFF bl chThdCreateStatic - 509 .LVL34: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 10 - - - 510 .loc 1 228 0 discriminator 2 - 511 0074 1036 adds r6, r6, #16 - 512 0076 042C cmp r4, #4 - 513 0078 05F59075 add r5, r5, #288 - 514 007c E9D1 bne .L44 - 515 .loc 1 237 0 - 516 007e 7D48 ldr r0, .L84+36 - 517 0080 FFF7FEFF bl println - 518 .loc 1 238 0 - 519 0084 7C48 ldr r0, .L84+40 - 520 0086 FFF7FEFF bl println - 521 .loc 1 239 0 - 522 008a 7C4C ldr r4, .L84+44 - 523 .LVL35: - 524 008c 7C48 ldr r0, .L84+48 - 525 008e 704D ldr r5, .L84 - 526 0090 FFF7FEFF bl println - 527 .LVL36: - 528 .loc 1 172 0 - 529 0094 2A21 movs r1, #42 - 530 .LVL37: - 531 .L45: - 532 .LBB44: - 533 .LBB45: - 534 .loc 1 173 0 - 535 0096 2B68 ldr r3, [r5, #0] - 536 0098 6D48 ldr r0, .L84 - 537 009a 1B69 ldr r3, [r3, #16] - 538 009c 4FF0FF32 mov r2, #-1 - 539 00a0 9847 blx r3 - 540 .loc 1 172 0 - 541 00a2 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 542 00a6 0029 cmp r1, #0 - 543 00a8 F5D1 bne .L45 - 544 .LBE45: - 545 .LBE44: - 546 .loc 1 241 0 - 547 00aa 7648 ldr r0, .L84+52 - 548 00ac 764C ldr r4, .L84+56 - 549 00ae FFF7FEFF bl println - 550 .LVL38: - 551 .loc 1 172 0 - 552 00b2 2A21 movs r1, #42 - 553 .LVL39: - 554 .L46: - 555 .LBB46: - 556 .LBB47: - 557 .loc 1 173 0 - 558 00b4 2B68 ldr r3, [r5, #0] - 559 00b6 6648 ldr r0, .L84 - 560 00b8 1B69 ldr r3, [r3, #16] - 561 00ba 4FF0FF32 mov r2, #-1 - 562 00be 9847 blx r3 - 563 .loc 1 172 0 - 564 00c0 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 565 00c4 0029 cmp r1, #0 - 566 00c6 F5D1 bne .L46 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 11 - - - 567 .LBE47: - 568 .LBE46: - 569 .loc 1 244 0 - 570 00c8 7048 ldr r0, .L84+60 - 571 00ca 714C ldr r4, .L84+64 - 572 00cc FFF7FEFF bl println - 573 .LVL40: - 574 .loc 1 172 0 - 575 00d0 2A21 movs r1, #42 - 576 .LVL41: - 577 .L47: - 578 .LBB48: - 579 .LBB49: - 580 .loc 1 173 0 - 581 00d2 2B68 ldr r3, [r5, #0] - 582 00d4 5E48 ldr r0, .L84 - 583 00d6 1B69 ldr r3, [r3, #16] - 584 00d8 4FF0FF32 mov r2, #-1 - 585 00dc 9847 blx r3 - 586 .loc 1 172 0 - 587 00de 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 588 00e2 0029 cmp r1, #0 - 589 00e4 F5D1 bne .L47 - 590 .LBE49: - 591 .LBE48: - 592 .loc 1 247 0 - 593 00e6 6B48 ldr r0, .L84+68 - 594 00e8 6B4C ldr r4, .L84+72 - 595 00ea FFF7FEFF bl println - 596 .LVL42: - 597 .loc 1 172 0 - 598 00ee 2A21 movs r1, #42 - 599 .LVL43: - 600 .L48: - 601 .LBB50: - 602 .LBB51: - 603 .loc 1 173 0 - 604 00f0 2B68 ldr r3, [r5, #0] - 605 00f2 5748 ldr r0, .L84 - 606 00f4 1B69 ldr r3, [r3, #16] - 607 00f6 4FF0FF32 mov r2, #-1 - 608 00fa 9847 blx r3 - 609 .loc 1 172 0 - 610 00fc 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 611 0100 0029 cmp r1, #0 - 612 0102 F5D1 bne .L48 - 613 .LBE51: - 614 .LBE50: - 615 .loc 1 250 0 - 616 0104 6548 ldr r0, .L84+76 - 617 0106 664C ldr r4, .L84+80 - 618 0108 FFF7FEFF bl println - 619 .LVL44: - 620 .loc 1 172 0 - 621 010c 2A21 movs r1, #42 - 622 .LVL45: - 623 .L49: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 12 - - - 624 .LBB52: - 625 .LBB53: - 626 .loc 1 173 0 - 627 010e 2B68 ldr r3, [r5, #0] - 628 0110 4F48 ldr r0, .L84 - 629 0112 1B69 ldr r3, [r3, #16] - 630 0114 4FF0FF32 mov r2, #-1 - 631 0118 9847 blx r3 - 632 .loc 1 172 0 - 633 011a 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 634 011e 0029 cmp r1, #0 - 635 0120 F5D1 bne .L49 - 636 .LBE53: - 637 .LBE52: - 638 .loc 1 254 0 - 639 0122 6048 ldr r0, .L84+84 - 640 0124 604C ldr r4, .L84+88 - 641 0126 FFF7FEFF bl println - 642 .LVL46: - 643 .loc 1 172 0 - 644 012a 2A21 movs r1, #42 - 645 .LVL47: - 646 .L50: - 647 .LBB54: - 648 .LBB55: - 649 .loc 1 173 0 - 650 012c 2B68 ldr r3, [r5, #0] - 651 012e 4848 ldr r0, .L84 - 652 0130 1B69 ldr r3, [r3, #16] - 653 0132 4FF0FF32 mov r2, #-1 - 654 0136 9847 blx r3 - 655 .loc 1 172 0 - 656 0138 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 657 013c 0029 cmp r1, #0 - 658 013e F5D1 bne .L50 - 659 .LBE55: - 660 .LBE54: - 661 .loc 1 258 0 - 662 0140 5A48 ldr r0, .L84+92 - 663 0142 FFF7FEFF bl println - 664 .loc 1 260 0 - 665 0146 5A4C ldr r4, .L84+96 - 666 0148 4D48 ldr r0, .L84+48 - 667 014a FFF7FEFF bl println - 668 .LVL48: - 669 .loc 1 172 0 - 670 014e 2A21 movs r1, #42 - 671 .LVL49: - 672 .L51: - 673 .LBB56: - 674 .LBB57: - 675 .loc 1 173 0 - 676 0150 2B68 ldr r3, [r5, #0] - 677 0152 3F48 ldr r0, .L84 - 678 0154 1B69 ldr r3, [r3, #16] - 679 0156 4FF0FF32 mov r2, #-1 - 680 015a 9847 blx r3 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 13 - - - 681 .loc 1 172 0 - 682 015c 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 683 0160 0029 cmp r1, #0 - 684 0162 F5D1 bne .L51 - 685 .LBE57: - 686 .LBE56: - 687 .loc 1 262 0 - 688 0164 4FF49040 mov r0, #18432 - 689 0168 C0F2E810 movt r0, 488 - 690 016c FFF7FEFF bl printn - 691 .loc 1 263 0 - 692 0170 504C ldr r4, .L84+100 - 693 0172 4048 ldr r0, .L84+36 - 694 0174 FFF7FEFF bl println - 695 .LVL50: - 696 .loc 1 172 0 - 697 0178 2A21 movs r1, #42 - 698 .LVL51: - 699 .L52: - 700 .LBB58: - 701 .LBB59: - 702 .loc 1 173 0 - 703 017a 2B68 ldr r3, [r5, #0] - 704 017c 3448 ldr r0, .L84 - 705 017e 1B69 ldr r3, [r3, #16] - 706 0180 4FF0FF32 mov r2, #-1 - 707 0184 9847 blx r3 - 708 .loc 1 172 0 - 709 0186 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 710 018a 0029 cmp r1, #0 - 711 018c F5D1 bne .L52 - 712 .LBE59: - 713 .LBE58: - 714 .loc 1 265 0 - 715 018e 6420 movs r0, #100 - 716 0190 FFF7FEFF bl printn - 717 .loc 1 266 0 - 718 0194 484C ldr r4, .L84+104 - 719 0196 3748 ldr r0, .L84+36 - 720 0198 FFF7FEFF bl println - 721 .LVL52: - 722 .loc 1 172 0 - 723 019c 2A21 movs r1, #42 - 724 .LVL53: - 725 .L53: - 726 .LBB60: - 727 .LBB61: - 728 .loc 1 173 0 - 729 019e 2B68 ldr r3, [r5, #0] - 730 01a0 2B48 ldr r0, .L84 - 731 01a2 1B69 ldr r3, [r3, #16] - 732 01a4 4FF0FF32 mov r2, #-1 - 733 01a8 9847 blx r3 - 734 .loc 1 172 0 - 735 01aa 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 736 01ae 0029 cmp r1, #0 - 737 01b0 F5D1 bne .L53 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 14 - - - 738 .LBE61: - 739 .LBE60: - 740 .loc 1 268 0 - 741 01b2 0846 mov r0, r1 - 742 01b4 FFF7FEFF bl printn - 743 .loc 1 269 0 - 744 01b8 404C ldr r4, .L84+108 - 745 01ba 2E48 ldr r0, .L84+36 - 746 01bc FFF7FEFF bl println - 747 .LVL54: - 748 .loc 1 172 0 - 749 01c0 2A21 movs r1, #42 - 750 .LVL55: - 751 .L54: - 752 .LBB62: - 753 .LBB63: - 754 .loc 1 173 0 - 755 01c2 2B68 ldr r3, [r5, #0] - 756 01c4 2248 ldr r0, .L84 - 757 01c6 1B69 ldr r3, [r3, #16] - 758 01c8 4FF0FF32 mov r2, #-1 - 759 01cc 9847 blx r3 - 760 .loc 1 172 0 - 761 01ce 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 762 01d2 0029 cmp r1, #0 - 763 01d4 F5D1 bne .L54 - 764 .LBE63: - 765 .LBE62: - 766 .loc 1 271 0 - 767 01d6 0420 movs r0, #4 - 768 01d8 FFF7FEFF bl printn - 769 .loc 1 272 0 - 770 01dc 2548 ldr r0, .L84+36 - 771 01de FFF7FEFF bl println - 772 .LVL56: - 773 01e2 374C ldr r4, .L84+112 - 774 .loc 1 172 0 - 775 01e4 2A26 movs r6, #42 - 776 .LVL57: - 777 .L55: - 778 .LBB64: - 779 .LBB65: - 780 .loc 1 173 0 - 781 01e6 2B68 ldr r3, [r5, #0] - 782 01e8 3146 mov r1, r6 - 783 01ea 1B69 ldr r3, [r3, #16] - 784 01ec 1848 ldr r0, .L84 - 785 01ee 4FF0FF32 mov r2, #-1 - 786 01f2 9847 blx r3 - 787 .loc 1 172 0 - 788 01f4 14F8016F ldrb r6, [r4, #1]! @ zero_extendqisi2 - 789 01f8 002E cmp r6, #0 - 790 01fa F4D1 bne .L55 - 791 .LBE65: - 792 .LBE64: - 793 .loc 1 274 0 - 794 01fc 0420 movs r0, #4 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 15 - - - 795 01fe FFF7FEFF bl printn - 796 .loc 1 275 0 - 797 0202 1C48 ldr r0, .L84+36 - 798 0204 FFF7FEFF bl println - 799 .loc 1 277 0 - 800 0208 1A48 ldr r0, .L84+36 - 801 020a FFF7FEFF bl println - 802 .LVL58: - 803 .loc 1 285 0 - 804 020e 4CF6CD48 movw r8, #52429 - 805 0212 2C4F ldr r7, .L84+116 - 806 .loc 1 278 0 - 807 0214 B246 mov sl, r6 - 808 .loc 1 279 0 - 809 0216 4FF00109 mov r9, #1 - 810 .loc 1 285 0 - 811 021a CCF6CC48 movt r8, 52428 - 812 .LVL59: - 813 .L56: - 814 .loc 1 279 0 - 815 021e 2A4C ldr r4, .L84+120 - 816 .loc 1 172 0 - 817 0220 4921 movs r1, #73 - 818 .LVL60: - 819 .L57: - 820 .LBB66: - 821 .LBB67: - 822 .loc 1 173 0 - 823 0222 2B68 ldr r3, [r5, #0] - 824 0224 0A48 ldr r0, .L84 - 825 0226 1B69 ldr r3, [r3, #16] - 826 0228 4FF0FF32 mov r2, #-1 - 827 022c 9847 blx r3 - 828 .loc 1 172 0 - 829 022e 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 830 0232 0029 cmp r1, #0 - 831 0234 F5D1 bne .L57 - 832 .LBE67: - 833 .LBE66: - 834 .loc 1 281 0 - 835 0236 4846 mov r0, r9 - 836 0238 0391 str r1, [sp, #12] - 837 023a FFF7FEFF bl printn - 838 .loc 1 282 0 - 839 023e 0D48 ldr r0, .L84+36 - 840 0240 FFF7FEFF bl println - 841 .loc 1 284 0 - 842 0244 0399 ldr r1, [sp, #12] - 843 .loc 1 285 0 - 844 0246 4FF4FA66 mov r6, #2000 - 845 .loc 1 284 0 - 846 024a 0C46 mov r4, r1 - 847 .loc 1 283 0 - 848 024c 3960 str r1, [r7, #0] - 849 .LVL61: - 850 024e 48E0 b .L60 - 851 .L85: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 16 - - - 852 .align 2 - 853 .L84: - 854 0250 00000000 .word SD1 - 855 0254 00000000 .word GPTD2 - 856 0258 00000000 .word .LANCHOR4 - 857 025c 00000000 .word GPTD3 - 858 0260 00000000 .word .LANCHOR5 - 859 0264 00000000 .word .LANCHOR6 - 860 0268 00000000 .word .LANCHOR7 - 861 026c 00000000 .word .LANCHOR0 - 862 0270 00000000 .word WorkerThread - 863 0274 0C000000 .word .LC2 - 864 0278 10000000 .word .LC3 - 865 027c 40000000 .word .LC5 - 866 0280 3C000000 .word .LC4 - 867 0284 54000000 .word .LC6 - 868 0288 64000000 .word .LC7 - 869 028c 78000000 .word .LC8 - 870 0290 80000000 .word .LC9 - 871 0294 94000000 .word .LC10 - 872 0298 9C000000 .word .LC11 - 873 029c B0000000 .word .LC12 - 874 02a0 BC000000 .word .LC13 - 875 02a4 D0000000 .word .LC14 - 876 02a8 F8000000 .word .LC15 - 877 02ac 0C010000 .word .LC16 - 878 02b0 20010000 .word .LC17 - 879 02b4 34010000 .word .LC18 - 880 02b8 48010000 .word .LC19 - 881 02bc 5C010000 .word .LC20 - 882 02c0 70010000 .word .LC21 - 883 02c4 00000000 .word .LANCHOR1 - 884 02c8 98010000 .word .LC24 - 885 .LVL62: - 886 .L83: - 887 .LBB68: - 888 .LBB69: - 889 .loc 1 173 0 - 890 02cc 2B68 ldr r3, [r5, #0] - 891 02ce 2E21 movs r1, #46 - 892 02d0 1B69 ldr r3, [r3, #16] - 893 02d2 9847 blx r3 - 894 .LVL63: - 895 .LBE69: - 896 .LBE68: - 897 .loc 1 285 0 - 898 02d4 A8FB0623 umull r2, r3, r8, r6 - 899 02d8 A6EBD306 sub r6, r6, r3, lsr #3 - 900 02dc B6B2 uxth r6, r6 - 901 .LVL64: - 902 02de 132E cmp r6, #19 - 903 02e0 27D9 bls .L82 - 904 .LVL65: - 905 .L60: - 906 .loc 1 286 0 - 907 02e2 711E subs r1, r6, #1 - 908 02e4 89B2 uxth r1, r1 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 17 - - - 909 02e6 3748 ldr r0, .L86 - 910 02e8 FFF7FEFF bl gptStartContinuous - 911 .loc 1 287 0 - 912 02ec 711C adds r1, r6, #1 - 913 02ee 89B2 uxth r1, r1 - 914 02f0 3548 ldr r0, .L86+4 - 915 02f2 FFF7FEFF bl gptStartContinuous - 916 .loc 1 288 0 - 917 02f6 4FF47A70 mov r0, #1000 - 918 02fa FFF7FEFF bl chThdSleep - 919 .loc 1 289 0 - 920 02fe 3148 ldr r0, .L86 - 921 0300 FFF7FEFF bl gptStopTimer - 922 .loc 1 290 0 - 923 0304 3048 ldr r0, .L86+4 - 924 0306 FFF7FEFF bl gptStopTimer - 925 .loc 1 291 0 - 926 030a 3B68 ldr r3, [r7, #0] - 927 .LBB70: - 928 .LBB71: - 929 .loc 1 173 0 - 930 030c 2F48 ldr r0, .L86+8 - 931 030e 2321 movs r1, #35 - 932 0310 4FF0FF32 mov r2, #-1 - 933 .LBE71: - 934 .LBE70: - 935 .loc 1 291 0 - 936 0314 002B cmp r3, #0 - 937 0316 D9D0 beq .L83 - 938 .LVL66: - 939 .LBB74: - 940 .LBB72: - 941 .loc 1 173 0 - 942 0318 2B68 ldr r3, [r5, #0] - 943 .LBE72: - 944 .LBE74: - 945 .loc 1 295 0 - 946 031a 002C cmp r4, #0 - 947 031c 08BF it eq - 948 031e 3446 moveq r4, r6 - 949 .LBB75: - 950 .LBB73: - 951 .loc 1 173 0 - 952 0320 1B69 ldr r3, [r3, #16] - 953 0322 9847 blx r3 - 954 .LVL67: - 955 .LBE73: - 956 .LBE75: - 957 .loc 1 285 0 - 958 0324 A8FB0623 umull r2, r3, r8, r6 - 959 0328 A6EBD306 sub r6, r6, r3, lsr #3 - 960 032c B6B2 uxth r6, r6 - 961 .LVL68: - 962 032e 132E cmp r6, #19 - 963 0330 D7D8 bhi .L60 - 964 .LVL69: - 965 .L82: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 18 - - - 966 .loc 1 301 0 - 967 0332 1420 movs r0, #20 - 968 0334 FFF7FEFF bl chThdSleep - 969 .loc 1 302 0 - 970 0338 254E ldr r6, .L86+12 - 971 033a 2648 ldr r0, .L86+16 - 972 033c FFF7FEFF bl println - 973 .LVL70: - 974 .loc 1 172 0 - 975 0340 5321 movs r1, #83 - 976 .LVL71: - 977 .L61: - 978 .LBB76: - 979 .LBB77: - 980 .loc 1 173 0 - 981 0342 2B68 ldr r3, [r5, #0] - 982 0344 2148 ldr r0, .L86+8 - 983 0346 1B69 ldr r3, [r3, #16] - 984 0348 4FF0FF32 mov r2, #-1 - 985 034c 9847 blx r3 - 986 .loc 1 172 0 - 987 034e 16F8011F ldrb r1, [r6, #1]! @ zero_extendqisi2 - 988 0352 0029 cmp r1, #0 - 989 0354 F5D1 bne .L61 - 990 .LBE77: - 991 .LBE76: - 992 .loc 1 304 0 - 993 0356 2046 mov r0, r4 - 994 0358 FFF7FEFF bl printn - 995 .loc 1 305 0 - 996 035c 1E48 ldr r0, .L86+20 - 997 035e FFF7FEFF bl println - 998 .loc 1 279 0 - 999 0362 09F10109 add r9, r9, #1 - 1000 .loc 1 306 0 - 1001 0366 1B48 ldr r0, .L86+16 - 1002 0368 5445 cmp r4, sl - 1003 036a 28BF it cs - 1004 036c A246 movcs sl, r4 - 1005 036e FFF7FEFF bl println - 1006 .loc 1 279 0 - 1007 0372 B9F1650F cmp r9, #101 - 1008 .loc 1 306 0 - 1009 0376 1FFA8AFA uxth sl, sl - 1010 .LVL72: - 1011 .loc 1 279 0 - 1012 037a 7FF450AF bne .L56 - 1013 .loc 1 310 0 - 1014 037e 1148 ldr r0, .L86 - 1015 0380 FFF7FEFF bl gptStopTimer - 1016 .loc 1 311 0 - 1017 0384 154C ldr r4, .L86+24 - 1018 0386 1048 ldr r0, .L86+4 - 1019 0388 FFF7FEFF bl gptStopTimer - 1020 .LVL73: - 1021 .loc 1 172 0 - 1022 038c 5721 movs r1, #87 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 19 - - - 1023 .LVL74: - 1024 .L63: - 1025 .LBB78: - 1026 .LBB79: - 1027 .loc 1 173 0 - 1028 038e 2B68 ldr r3, [r5, #0] - 1029 0390 0E48 ldr r0, .L86+8 - 1030 0392 1B69 ldr r3, [r3, #16] - 1031 0394 4FF0FF32 mov r2, #-1 - 1032 0398 9847 blx r3 - 1033 .loc 1 172 0 - 1034 039a 14F8011F ldrb r1, [r4, #1]! @ zero_extendqisi2 - 1035 039e 0029 cmp r1, #0 - 1036 03a0 F5D1 bne .L63 - 1037 .LBE79: - 1038 .LBE78: - 1039 .loc 1 314 0 - 1040 03a2 5046 mov r0, sl - 1041 03a4 FFF7FEFF bl printn - 1042 .loc 1 315 0 - 1043 03a8 0B48 ldr r0, .L86+20 - 1044 03aa FFF7FEFF bl println - 1045 .loc 1 316 0 - 1046 03ae 0948 ldr r0, .L86+16 - 1047 03b0 FFF7FEFF bl println - 1048 .loc 1 317 0 - 1049 03b4 0A48 ldr r0, .L86+28 - 1050 03b6 FFF7FEFF bl println - 1051 .L64: - 1052 .loc 1 323 0 discriminator 1 - 1053 03ba 41F28830 movw r0, #5000 - 1054 03be FFF7FEFF bl chThdSleep - 1055 03c2 FAE7 b .L64 - 1056 .L87: - 1057 .align 2 - 1058 .L86: - 1059 03c4 00000000 .word GPTD2 - 1060 03c8 00000000 .word GPTD3 - 1061 03cc 00000000 .word SD1 - 1062 03d0 84010000 .word .LC22 - 1063 03d4 0C000000 .word .LC2 - 1064 03d8 94010000 .word .LC23 - 1065 03dc A4010000 .word .LC25 - 1066 03e0 B4010000 .word .LC26 - 1067 .cfi_endproc - 1068 .LFE68: - 1069 .size main, .-main - 1070 03e4 AFF30080 .section .rodata.gpt2cfg,"a",%progbits - 1070 AFF30080 - 1070 AFF30080 - 1071 .align 2 - 1072 .set .LANCHOR4,. + 0 - 1073 .type gpt2cfg, %object - 1074 .size gpt2cfg, 8 - 1075 gpt2cfg: - 1076 0000 40420F00 .word 1000000 - 1077 0004 00000000 .word gpt2cb - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 20 - - - 1078 .section .bss.waWorkerThread,"aw",%nobits - 1079 .align 3 - 1080 .set .LANCHOR7,. + 0 - 1081 .type waWorkerThread, %object - 1082 .size waWorkerThread, 1152 - 1083 waWorkerThread: - 1084 0000 00000000 .space 1152 - 1084 00000000 - 1084 00000000 - 1084 00000000 - 1084 00000000 - 1085 .section .bss.saturated,"aw",%nobits - 1086 .align 2 - 1087 .set .LANCHOR1,. + 0 - 1088 .type saturated, %object - 1089 .size saturated, 4 - 1090 saturated: - 1091 0000 00000000 .space 4 - 1092 .section .rodata.gpt3cfg,"a",%progbits - 1093 .align 2 - 1094 .set .LANCHOR5,. + 0 - 1095 .type gpt3cfg, %object - 1096 .size gpt3cfg, 8 - 1097 gpt3cfg: - 1098 0000 40420F00 .word 1000000 - 1099 0004 00000000 .word gpt3cb - 1100 .section .rodata.str1.4,"aMS",%progbits,1 - 1101 .align 2 - 1102 .LC0: - 1103 0000 0D0A00 .ascii "\015\012\000" - 1104 0003 00 .space 1 - 1105 .LC1: - 1106 0004 776F726B .ascii "worker\000" - 1106 657200 - 1107 000b 00 .space 1 - 1108 .LC2: - 1109 000c 00 .ascii "\000" - 1110 000d 000000 .space 3 - 1111 .LC3: - 1112 0010 2A2A2A20 .ascii "*** ChibiOS/RT IRQ-STORM long duration test\000" - 1112 43686962 - 1112 694F532F - 1112 52542049 - 1112 52512D53 - 1113 .LC4: - 1114 003c 2A2A2A00 .ascii "***\000" - 1115 .LC5: - 1116 0040 2A2A2A20 .ascii "*** Kernel: \000" - 1116 4B65726E - 1116 656C3A20 - 1116 20202020 - 1116 202000 - 1117 0053 00 .space 1 - 1118 .LC6: - 1119 0054 322E332E .ascii "2.3.3unstable\000" - 1119 33756E73 - 1119 7461626C - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 21 - - - 1119 6500 - 1120 0062 0000 .space 2 - 1121 .LC7: - 1122 0064 2A2A2A20 .ascii "*** GCC Version: \000" - 1122 47434320 - 1122 56657273 - 1122 696F6E3A - 1122 202000 - 1123 0077 00 .space 1 - 1124 .LC8: - 1125 0078 342E362E .ascii "4.6.0\000" - 1125 3000 - 1126 007e 0000 .space 2 - 1127 .LC9: - 1128 0080 2A2A2A20 .ascii "*** Architecture: \000" - 1128 41726368 - 1128 69746563 - 1128 74757265 - 1128 3A2000 - 1129 0093 00 .space 1 - 1130 .LC10: - 1131 0094 41524D76 .ascii "ARMv7-M\000" - 1131 372D4D00 - 1132 .LC11: - 1133 009c 2A2A2A20 .ascii "*** Core Variant: \000" - 1133 436F7265 - 1133 20566172 - 1133 69616E74 - 1133 3A2000 - 1134 00af 00 .space 1 - 1135 .LC12: - 1136 00b0 436F7274 .ascii "Cortex-M3\000" - 1136 65782D4D - 1136 3300 - 1137 00ba 0000 .space 2 - 1138 .LC13: - 1139 00bc 2A2A2A20 .ascii "*** Platform: \000" - 1139 506C6174 - 1139 666F726D - 1139 3A202020 - 1139 202000 - 1140 00cf 00 .space 1 - 1141 .LC14: - 1142 00d0 53544D33 .ascii "STM32L Ultra Low Power Medium Density\000" - 1142 324C2055 - 1142 6C747261 - 1142 204C6F77 - 1142 20506F77 - 1143 00f6 0000 .space 2 - 1144 .LC15: - 1145 00f8 2A2A2A20 .ascii "*** Test Board: \000" - 1145 54657374 - 1145 20426F61 - 1145 72643A20 - 1145 202000 - 1146 010b 00 .space 1 - 1147 .LC16: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 22 - - - 1148 010c 53542053 .ascii "ST STM32L-Discovery\000" - 1148 544D3332 - 1148 4C2D4469 - 1148 73636F76 - 1148 65727900 - 1149 .LC17: - 1150 0120 2A2A2A20 .ascii "*** System Clock: \000" - 1150 53797374 - 1150 656D2043 - 1150 6C6F636B - 1150 3A2000 - 1151 0133 00 .space 1 - 1152 .LC18: - 1153 0134 2A2A2A20 .ascii "*** Iterations: \000" - 1153 49746572 - 1153 6174696F - 1153 6E733A20 - 1153 202000 - 1154 0147 00 .space 1 - 1155 .LC19: - 1156 0148 2A2A2A20 .ascii "*** Randomize: \000" - 1156 52616E64 - 1156 6F6D697A - 1156 653A2020 - 1156 202000 - 1157 015b 00 .space 1 - 1158 .LC20: - 1159 015c 2A2A2A20 .ascii "*** Threads: \000" - 1159 54687265 - 1159 6164733A - 1159 20202020 - 1159 202000 - 1160 016f 00 .space 1 - 1161 .LC21: - 1162 0170 2A2A2A20 .ascii "*** Mailbox size: \000" - 1162 4D61696C - 1162 626F7820 - 1162 73697A65 - 1162 3A2000 - 1163 0183 00 .space 1 - 1164 .LC22: - 1165 0184 53617475 .ascii "Saturated at \000" - 1165 72617465 - 1165 64206174 - 1165 2000 - 1166 0192 0000 .space 2 - 1167 .LC23: - 1168 0194 20755300 .ascii " uS\000" - 1169 .LC24: - 1170 0198 49746572 .ascii "Iteration \000" - 1170 6174696F - 1170 6E2000 - 1171 01a3 00 .space 1 - 1172 .LC25: - 1173 01a4 576F7273 .ascii "Worst case at \000" - 1173 74206361 - 1173 73652061 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 23 - - - 1173 742000 - 1174 01b3 00 .space 1 - 1175 .LC26: - 1176 01b4 54657374 .ascii "Test Complete\000" - 1176 20436F6D - 1176 706C6574 - 1176 6500 - 1177 01c2 0000 .section .bss.mb,"aw",%nobits - 1178 .align 2 - 1179 .set .LANCHOR0,. + 0 - 1180 .type mb, %object - 1181 .size mb, 160 - 1182 mb: - 1183 0000 00000000 .space 160 - 1183 00000000 - 1183 00000000 - 1183 00000000 - 1183 00000000 - 1184 .section .bss.b,"aw",%nobits - 1185 .align 2 - 1186 .set .LANCHOR6,. + 0 - 1187 .type b, %object - 1188 .size b, 64 - 1189 b: - 1190 0000 00000000 .space 64 - 1190 00000000 - 1190 00000000 - 1190 00000000 - 1190 00000000 - 1191 .section .bss.x.3441,"aw",%nobits - 1192 .align 2 - 1193 .set .LANCHOR2,. + 0 - 1194 .type x.3441, %object - 1195 .size x.3441, 4 - 1196 x.3441: - 1197 0000 00000000 .space 4 - 1198 .section .bss.cnt.3442,"aw",%nobits - 1199 .align 2 - 1200 .set .LANCHOR3,. + 0 - 1201 .type cnt.3442, %object - 1202 .size cnt.3442, 4 - 1203 cnt.3442: - 1204 0000 00000000 .space 4 - 1205 .text - 1206 .Letext0: - 1207 .file 2 "c:\\programmi\\yagarto\\bin\\../lib/gcc/arm-none-eabi/4.6.0/include/stddef.h" - 1208 .file 3 "c:/programmi/yagarto/lib/gcc/../../arm-none-eabi/sys-include/stdint.h" - 1209 .file 4 "../../../os/ports/GCC/ARMCMx/chtypes.h" - 1210 .file 5 "../../../os/kernel/include/chlists.h" - 1211 .file 6 "../../../os/kernel/include/chthreads.h" - 1212 .file 7 "../../../os/ports/GCC/ARMCMx/chcore_v7m.h" - 1213 .file 8 "../../../os/ports/GCC/ARMCMx/chcore.h" - 1214 .file 9 "../../../os/kernel/include/chschd.h" - 1215 .file 10 "../../../os/kernel/include/chsem.h" - 1216 .file 11 "../../../os/kernel/include/chmtx.h" - 1217 .file 12 "../../../os/kernel/include/chevents.h" - 1218 .file 13 "../../../os/kernel/include/chmboxes.h" - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 24 - - - 1219 .file 14 "../../../os/kernel/include/chqueues.h" - 1220 .file 15 "../../../os/kernel/include/chioch.h" - 1221 .file 16 "../../../os/hal/platforms/STM32L1xx/stm32l1xx.h" - 1222 .file 17 "../../../os/hal/platforms/STM32/GPIOv2/pal_lld.h" - 1223 .file 18 "../../../os/hal/include/gpt.h" - 1224 .file 19 "../../../os/hal/platforms/STM32/gpt_lld.h" - 1225 .file 20 "../../../os/hal/include/serial.h" - 1226 .file 21 "../../../os/ports/common/ARMCMx/CMSIS/include/core_cm3.h" - 1227 .file 22 "../../../os/hal/platforms/STM32/serial_lld.h" - 1228 .section .debug_info,"",%progbits - 1229 .Ldebug_info0: - 1230 0000 1F130000 .4byte 0x131f - 1231 0004 0200 .2byte 0x2 - 1232 0006 00000000 .4byte .Ldebug_abbrev0 - 1233 000a 04 .byte 0x4 - 1234 000b 01 .uleb128 0x1 - 1235 000c 15000000 .4byte .LASF191 - 1236 0010 01 .byte 0x1 - 1237 0011 ED030000 .4byte .LASF192 - 1238 0015 80040000 .4byte .LASF193 - 1239 0019 00000000 .4byte 0 - 1240 001d 00000000 .4byte 0 - 1241 0021 50000000 .4byte .Ldebug_ranges0+0x50 - 1242 0025 00000000 .4byte .Ldebug_line0 - 1243 0029 02 .uleb128 0x2 - 1244 002a 51020000 .4byte .LASF10 - 1245 002e 02 .byte 0x2 - 1246 002f D4 .byte 0xd4 - 1247 0030 34000000 .4byte 0x34 - 1248 0034 03 .uleb128 0x3 - 1249 0035 04 .byte 0x4 - 1250 0036 07 .byte 0x7 - 1251 0037 88020000 .4byte .LASF0 - 1252 003b 03 .uleb128 0x3 - 1253 003c 01 .byte 0x1 - 1254 003d 06 .byte 0x6 - 1255 003e 07010000 .4byte .LASF1 - 1256 0042 03 .uleb128 0x3 - 1257 0043 01 .byte 0x1 - 1258 0044 08 .byte 0x8 - 1259 0045 CF040000 .4byte .LASF2 - 1260 0049 03 .uleb128 0x3 - 1261 004a 02 .byte 0x2 - 1262 004b 05 .byte 0x5 - 1263 004c 0F050000 .4byte .LASF3 - 1264 0050 03 .uleb128 0x3 - 1265 0051 02 .byte 0x2 - 1266 0052 07 .byte 0x7 - 1267 0053 12020000 .4byte .LASF4 - 1268 0057 04 .uleb128 0x4 - 1269 0058 04 .byte 0x4 - 1270 0059 05 .byte 0x5 - 1271 005a 696E7400 .ascii "int\000" - 1272 005e 03 .uleb128 0x3 - 1273 005f 08 .byte 0x8 - 1274 0060 05 .byte 0x5 - 1275 0061 F9000000 .4byte .LASF5 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 25 - - - 1276 0065 03 .uleb128 0x3 - 1277 0066 08 .byte 0x8 - 1278 0067 07 .byte 0x7 - 1279 0068 86000000 .4byte .LASF6 - 1280 006c 03 .uleb128 0x3 - 1281 006d 04 .byte 0x4 - 1282 006e 05 .byte 0x5 - 1283 006f A4010000 .4byte .LASF7 - 1284 0073 05 .uleb128 0x5 - 1285 0074 04 .byte 0x4 - 1286 0075 03 .uleb128 0x3 - 1287 0076 04 .byte 0x4 - 1288 0077 07 .byte 0x7 - 1289 0078 B1050000 .4byte .LASF8 - 1290 007c 06 .uleb128 0x6 - 1291 007d 04 .byte 0x4 - 1292 007e 82000000 .4byte 0x82 - 1293 0082 03 .uleb128 0x3 - 1294 0083 01 .byte 0x1 - 1295 0084 08 .byte 0x8 - 1296 0085 D2050000 .4byte .LASF9 - 1297 0089 06 .uleb128 0x6 - 1298 008a 04 .byte 0x4 - 1299 008b 8F000000 .4byte 0x8f - 1300 008f 07 .uleb128 0x7 - 1301 0090 82000000 .4byte 0x82 - 1302 0094 02 .uleb128 0x2 - 1303 0095 A6060000 .4byte .LASF11 - 1304 0099 03 .byte 0x3 - 1305 009a 2A .byte 0x2a - 1306 009b 42000000 .4byte 0x42 - 1307 009f 02 .uleb128 0x2 - 1308 00a0 95020000 .4byte .LASF12 - 1309 00a4 03 .byte 0x3 - 1310 00a5 36 .byte 0x36 - 1311 00a6 50000000 .4byte 0x50 - 1312 00aa 02 .uleb128 0x2 - 1313 00ab C7040000 .4byte .LASF13 - 1314 00af 03 .byte 0x3 - 1315 00b0 4F .byte 0x4f - 1316 00b1 6C000000 .4byte 0x6c - 1317 00b5 02 .uleb128 0x2 - 1318 00b6 75050000 .4byte .LASF14 - 1319 00ba 03 .byte 0x3 - 1320 00bb 50 .byte 0x50 - 1321 00bc 75000000 .4byte 0x75 - 1322 00c0 02 .uleb128 0x2 - 1323 00c1 0C000000 .4byte .LASF15 - 1324 00c5 03 .byte 0x3 - 1325 00c6 78 .byte 0x78 - 1326 00c7 65000000 .4byte 0x65 - 1327 00cb 02 .uleb128 0x2 - 1328 00cc 78000000 .4byte .LASF16 - 1329 00d0 03 .byte 0x3 - 1330 00d1 A6 .byte 0xa6 - 1331 00d2 34000000 .4byte 0x34 - 1332 00d6 02 .uleb128 0x2 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 26 - - - 1333 00d7 1D010000 .4byte .LASF17 - 1334 00db 04 .byte 0x4 - 1335 00dc 27 .byte 0x27 - 1336 00dd AA000000 .4byte 0xaa - 1337 00e1 02 .uleb128 0x2 - 1338 00e2 C9060000 .4byte .LASF18 - 1339 00e6 04 .byte 0x4 - 1340 00e7 28 .byte 0x28 - 1341 00e8 94000000 .4byte 0x94 - 1342 00ec 02 .uleb128 0x2 - 1343 00ed BE010000 .4byte .LASF19 - 1344 00f1 04 .byte 0x4 - 1345 00f2 29 .byte 0x29 - 1346 00f3 94000000 .4byte 0x94 - 1347 00f7 02 .uleb128 0x2 - 1348 00f8 1B040000 .4byte .LASF20 - 1349 00fc 04 .byte 0x4 - 1350 00fd 2A .byte 0x2a - 1351 00fe 94000000 .4byte 0x94 - 1352 0102 02 .uleb128 0x2 - 1353 0103 70040000 .4byte .LASF21 - 1354 0107 04 .byte 0x4 - 1355 0108 2B .byte 0x2b - 1356 0109 B5000000 .4byte 0xb5 - 1357 010d 02 .uleb128 0x2 - 1358 010e 0C030000 .4byte .LASF22 - 1359 0112 04 .byte 0x4 - 1360 0113 2C .byte 0x2c - 1361 0114 AA000000 .4byte 0xaa - 1362 0118 02 .uleb128 0x2 - 1363 0119 4A030000 .4byte .LASF23 - 1364 011d 04 .byte 0x4 - 1365 011e 2E .byte 0x2e - 1366 011f B5000000 .4byte 0xb5 - 1367 0123 02 .uleb128 0x2 - 1368 0124 16060000 .4byte .LASF24 - 1369 0128 04 .byte 0x4 - 1370 0129 2F .byte 0x2f - 1371 012a B5000000 .4byte 0xb5 - 1372 012e 02 .uleb128 0x2 - 1373 012f AC030000 .4byte .LASF25 - 1374 0133 04 .byte 0x4 - 1375 0134 30 .byte 0x30 - 1376 0135 AA000000 .4byte 0xaa - 1377 0139 02 .uleb128 0x2 - 1378 013a 46050000 .4byte .LASF26 - 1379 013e 05 .byte 0x5 - 1380 013f 23 .byte 0x23 - 1381 0140 44010000 .4byte 0x144 - 1382 0144 08 .uleb128 0x8 - 1383 0145 46050000 .4byte .LASF26 - 1384 0149 48 .byte 0x48 - 1385 014a 06 .byte 0x6 - 1386 014b 4D .byte 0x4d - 1387 014c 5B020000 .4byte 0x25b - 1388 0150 09 .uleb128 0x9 - 1389 0151 27050000 .4byte .LASF27 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 27 - - - 1390 0155 06 .byte 0x6 - 1391 0156 4E .byte 0x4e - 1392 0157 80020000 .4byte 0x280 - 1393 015b 02 .byte 0x2 - 1394 015c 23 .byte 0x23 - 1395 015d 00 .uleb128 0 - 1396 015e 09 .uleb128 0x9 - 1397 015f 55040000 .4byte .LASF28 - 1398 0163 06 .byte 0x6 - 1399 0164 50 .byte 0x50 - 1400 0165 80020000 .4byte 0x280 - 1401 0169 02 .byte 0x2 - 1402 016a 23 .byte 0x23 - 1403 016b 04 .uleb128 0x4 - 1404 016c 09 .uleb128 0x9 - 1405 016d E0000000 .4byte .LASF29 - 1406 0171 06 .byte 0x6 - 1407 0172 52 .byte 0x52 - 1408 0173 02010000 .4byte 0x102 - 1409 0177 02 .byte 0x2 - 1410 0178 23 .byte 0x23 - 1411 0179 08 .uleb128 0x8 - 1412 017a 09 .uleb128 0x9 - 1413 017b 02070000 .4byte .LASF30 - 1414 017f 06 .byte 0x6 - 1415 0180 53 .byte 0x53 - 1416 0181 52030000 .4byte 0x352 - 1417 0185 02 .byte 0x2 - 1418 0186 23 .byte 0x23 - 1419 0187 0C .uleb128 0xc - 1420 0188 09 .uleb128 0x9 - 1421 0189 E6010000 .4byte .LASF31 - 1422 018d 06 .byte 0x6 - 1423 018e 55 .byte 0x55 - 1424 018f 80020000 .4byte 0x280 - 1425 0193 02 .byte 0x2 - 1426 0194 23 .byte 0x23 - 1427 0195 10 .uleb128 0x10 - 1428 0196 09 .uleb128 0x9 - 1429 0197 C2030000 .4byte .LASF32 - 1430 019b 06 .byte 0x6 - 1431 019c 56 .byte 0x56 - 1432 019d 80020000 .4byte 0x280 - 1433 01a1 02 .byte 0x2 - 1434 01a2 23 .byte 0x23 - 1435 01a3 14 .uleb128 0x14 - 1436 01a4 09 .uleb128 0x9 - 1437 01a5 2B060000 .4byte .LASF33 - 1438 01a9 06 .byte 0x6 - 1439 01aa 5D .byte 0x5d - 1440 01ab 89000000 .4byte 0x89 - 1441 01af 02 .byte 0x2 - 1442 01b0 23 .byte 0x23 - 1443 01b1 18 .uleb128 0x18 - 1444 01b2 09 .uleb128 0x9 - 1445 01b3 FD040000 .4byte .LASF34 - 1446 01b7 06 .byte 0x6 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 28 - - - 1447 01b8 68 .byte 0x68 - 1448 01b9 EC000000 .4byte 0xec - 1449 01bd 02 .byte 0x2 - 1450 01be 23 .byte 0x23 - 1451 01bf 1C .uleb128 0x1c - 1452 01c0 09 .uleb128 0x9 - 1453 01c1 2E050000 .4byte .LASF35 - 1454 01c5 06 .byte 0x6 - 1455 01c6 6C .byte 0x6c - 1456 01c7 E1000000 .4byte 0xe1 - 1457 01cb 02 .byte 0x2 - 1458 01cc 23 .byte 0x23 - 1459 01cd 1D .uleb128 0x1d - 1460 01ce 09 .uleb128 0x9 - 1461 01cf C7010000 .4byte .LASF36 - 1462 01d3 06 .byte 0x6 - 1463 01d4 71 .byte 0x71 - 1464 01d5 F7000000 .4byte 0xf7 - 1465 01d9 02 .byte 0x2 - 1466 01da 23 .byte 0x23 - 1467 01db 1E .uleb128 0x1e - 1468 01dc 09 .uleb128 0x9 - 1469 01dd DF010000 .4byte .LASF37 - 1470 01e1 06 .byte 0x6 - 1471 01e2 78 .byte 0x78 - 1472 01e3 73030000 .4byte 0x373 - 1473 01e7 02 .byte 0x2 - 1474 01e8 23 .byte 0x23 - 1475 01e9 20 .uleb128 0x20 - 1476 01ea 0A .uleb128 0xa - 1477 01eb 705F7500 .ascii "p_u\000" - 1478 01ef 06 .byte 0x6 - 1479 01f0 9D .byte 0x9d - 1480 01f1 46050000 .4byte 0x546 - 1481 01f5 02 .byte 0x2 - 1482 01f6 23 .byte 0x23 - 1483 01f7 24 .uleb128 0x24 - 1484 01f8 09 .uleb128 0x9 - 1485 01f9 08070000 .4byte .LASF38 - 1486 01fd 06 .byte 0x6 - 1487 01fe A2 .byte 0xa2 - 1488 01ff A8020000 .4byte 0x2a8 - 1489 0203 02 .byte 0x2 - 1490 0204 23 .byte 0x23 - 1491 0205 28 .uleb128 0x28 - 1492 0206 09 .uleb128 0x9 - 1493 0207 B5020000 .4byte .LASF39 - 1494 020b 06 .byte 0x6 - 1495 020c A8 .byte 0xa8 - 1496 020d 86020000 .4byte 0x286 - 1497 0211 02 .byte 0x2 - 1498 0212 23 .byte 0x23 - 1499 0213 2C .uleb128 0x2c - 1500 0214 09 .uleb128 0x9 - 1501 0215 E3050000 .4byte .LASF40 - 1502 0219 06 .byte 0x6 - 1503 021a AC .byte 0xac - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 29 - - - 1504 021b 0D010000 .4byte 0x10d - 1505 021f 02 .byte 0x2 - 1506 0220 23 .byte 0x23 - 1507 0221 34 .uleb128 0x34 - 1508 0222 09 .uleb128 0x9 - 1509 0223 4D050000 .4byte .LASF41 - 1510 0227 06 .byte 0x6 - 1511 0228 B2 .byte 0xb2 - 1512 0229 18010000 .4byte 0x118 - 1513 022d 02 .byte 0x2 - 1514 022e 23 .byte 0x23 - 1515 022f 38 .uleb128 0x38 - 1516 0230 09 .uleb128 0x9 - 1517 0231 05050000 .4byte .LASF42 - 1518 0235 06 .byte 0x6 - 1519 0236 B9 .byte 0xb9 - 1520 0237 7B050000 .4byte 0x57b - 1521 023b 02 .byte 0x2 - 1522 023c 23 .byte 0x23 - 1523 023d 3C .uleb128 0x3c - 1524 023e 09 .uleb128 0x9 - 1525 023f 20060000 .4byte .LASF43 - 1526 0243 06 .byte 0x6 - 1527 0244 BD .byte 0xbd - 1528 0245 02010000 .4byte 0x102 - 1529 0249 02 .byte 0x2 - 1530 024a 23 .byte 0x23 - 1531 024b 40 .uleb128 0x40 - 1532 024c 09 .uleb128 0x9 - 1533 024d 04030000 .4byte .LASF44 - 1534 0251 06 .byte 0x6 - 1535 0252 C3 .byte 0xc3 - 1536 0253 73000000 .4byte 0x73 - 1537 0257 02 .byte 0x2 - 1538 0258 23 .byte 0x23 - 1539 0259 44 .uleb128 0x44 - 1540 025a 00 .byte 0 - 1541 025b 0B .uleb128 0xb - 1542 025c 08 .byte 0x8 - 1543 025d 05 .byte 0x5 - 1544 025e 5A .byte 0x5a - 1545 025f 80020000 .4byte 0x280 - 1546 0263 09 .uleb128 0x9 - 1547 0264 27050000 .4byte .LASF27 - 1548 0268 05 .byte 0x5 - 1549 0269 5B .byte 0x5b - 1550 026a 80020000 .4byte 0x280 - 1551 026e 02 .byte 0x2 - 1552 026f 23 .byte 0x23 - 1553 0270 00 .uleb128 0 - 1554 0271 09 .uleb128 0x9 - 1555 0272 55040000 .4byte .LASF28 - 1556 0276 05 .byte 0x5 - 1557 0277 5D .byte 0x5d - 1558 0278 80020000 .4byte 0x280 - 1559 027c 02 .byte 0x2 - 1560 027d 23 .byte 0x23 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 30 - - - 1561 027e 04 .uleb128 0x4 - 1562 027f 00 .byte 0 - 1563 0280 06 .uleb128 0x6 - 1564 0281 04 .byte 0x4 - 1565 0282 39010000 .4byte 0x139 - 1566 0286 02 .uleb128 0x2 - 1567 0287 D0030000 .4byte .LASF45 - 1568 028b 05 .byte 0x5 - 1569 028c 5F .byte 0x5f - 1570 028d 5B020000 .4byte 0x25b - 1571 0291 0B .uleb128 0xb - 1572 0292 04 .byte 0x4 - 1573 0293 05 .byte 0x5 - 1574 0294 64 .byte 0x64 - 1575 0295 A8020000 .4byte 0x2a8 - 1576 0299 09 .uleb128 0x9 - 1577 029a 27050000 .4byte .LASF27 - 1578 029e 05 .byte 0x5 - 1579 029f 66 .byte 0x66 - 1580 02a0 80020000 .4byte 0x280 - 1581 02a4 02 .byte 0x2 - 1582 02a5 23 .byte 0x23 - 1583 02a6 00 .uleb128 0 - 1584 02a7 00 .byte 0 - 1585 02a8 02 .uleb128 0x2 - 1586 02a9 3E030000 .4byte .LASF46 - 1587 02ad 05 .byte 0x5 - 1588 02ae 69 .byte 0x69 - 1589 02af 91020000 .4byte 0x291 - 1590 02b3 02 .uleb128 0x2 - 1591 02b4 48020000 .4byte .LASF47 - 1592 02b8 07 .byte 0x7 - 1593 02b9 88 .byte 0x88 - 1594 02ba 73000000 .4byte 0x73 - 1595 02be 08 .uleb128 0x8 - 1596 02bf 57060000 .4byte .LASF48 - 1597 02c3 24 .byte 0x24 - 1598 02c4 07 .byte 0x7 - 1599 02c5 96 .byte 0x96 - 1600 02c6 42030000 .4byte 0x342 - 1601 02ca 0A .uleb128 0xa - 1602 02cb 723400 .ascii "r4\000" - 1603 02ce 07 .byte 0x7 - 1604 02cf 97 .byte 0x97 - 1605 02d0 B3020000 .4byte 0x2b3 - 1606 02d4 02 .byte 0x2 - 1607 02d5 23 .byte 0x23 - 1608 02d6 00 .uleb128 0 - 1609 02d7 0A .uleb128 0xa - 1610 02d8 723500 .ascii "r5\000" - 1611 02db 07 .byte 0x7 - 1612 02dc 98 .byte 0x98 - 1613 02dd B3020000 .4byte 0x2b3 - 1614 02e1 02 .byte 0x2 - 1615 02e2 23 .byte 0x23 - 1616 02e3 04 .uleb128 0x4 - 1617 02e4 0A .uleb128 0xa - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 31 - - - 1618 02e5 723600 .ascii "r6\000" - 1619 02e8 07 .byte 0x7 - 1620 02e9 99 .byte 0x99 - 1621 02ea B3020000 .4byte 0x2b3 - 1622 02ee 02 .byte 0x2 - 1623 02ef 23 .byte 0x23 - 1624 02f0 08 .uleb128 0x8 - 1625 02f1 0A .uleb128 0xa - 1626 02f2 723700 .ascii "r7\000" - 1627 02f5 07 .byte 0x7 - 1628 02f6 9A .byte 0x9a - 1629 02f7 B3020000 .4byte 0x2b3 - 1630 02fb 02 .byte 0x2 - 1631 02fc 23 .byte 0x23 - 1632 02fd 0C .uleb128 0xc - 1633 02fe 0A .uleb128 0xa - 1634 02ff 723800 .ascii "r8\000" - 1635 0302 07 .byte 0x7 - 1636 0303 9B .byte 0x9b - 1637 0304 B3020000 .4byte 0x2b3 - 1638 0308 02 .byte 0x2 - 1639 0309 23 .byte 0x23 - 1640 030a 10 .uleb128 0x10 - 1641 030b 0A .uleb128 0xa - 1642 030c 723900 .ascii "r9\000" - 1643 030f 07 .byte 0x7 - 1644 0310 9C .byte 0x9c - 1645 0311 B3020000 .4byte 0x2b3 - 1646 0315 02 .byte 0x2 - 1647 0316 23 .byte 0x23 - 1648 0317 14 .uleb128 0x14 - 1649 0318 0A .uleb128 0xa - 1650 0319 72313000 .ascii "r10\000" - 1651 031d 07 .byte 0x7 - 1652 031e 9D .byte 0x9d - 1653 031f B3020000 .4byte 0x2b3 - 1654 0323 02 .byte 0x2 - 1655 0324 23 .byte 0x23 - 1656 0325 18 .uleb128 0x18 - 1657 0326 0A .uleb128 0xa - 1658 0327 72313100 .ascii "r11\000" - 1659 032b 07 .byte 0x7 - 1660 032c 9E .byte 0x9e - 1661 032d B3020000 .4byte 0x2b3 - 1662 0331 02 .byte 0x2 - 1663 0332 23 .byte 0x23 - 1664 0333 1C .uleb128 0x1c - 1665 0334 0A .uleb128 0xa - 1666 0335 6C7200 .ascii "lr\000" - 1667 0338 07 .byte 0x7 - 1668 0339 9F .byte 0x9f - 1669 033a B3020000 .4byte 0x2b3 - 1670 033e 02 .byte 0x2 - 1671 033f 23 .byte 0x23 - 1672 0340 20 .uleb128 0x20 - 1673 0341 00 .byte 0 - 1674 0342 0C .uleb128 0xc - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 32 - - - 1675 0343 B5000000 .4byte 0xb5 - 1676 0347 02 .uleb128 0x2 - 1677 0348 78030000 .4byte .LASF49 - 1678 034c 08 .byte 0x8 - 1679 034d C7 .byte 0xc7 - 1680 034e C0000000 .4byte 0xc0 - 1681 0352 08 .uleb128 0x8 - 1682 0353 45060000 .4byte .LASF50 - 1683 0357 04 .byte 0x4 - 1684 0358 08 .byte 0x8 - 1685 0359 E9 .byte 0xe9 - 1686 035a 6D030000 .4byte 0x36d - 1687 035e 0A .uleb128 0xa - 1688 035f 72313300 .ascii "r13\000" - 1689 0363 08 .byte 0x8 - 1690 0364 EA .byte 0xea - 1691 0365 6D030000 .4byte 0x36d - 1692 0369 02 .byte 0x2 - 1693 036a 23 .byte 0x23 - 1694 036b 00 .uleb128 0 - 1695 036c 00 .byte 0 - 1696 036d 06 .uleb128 0x6 - 1697 036e 04 .byte 0x4 - 1698 036f BE020000 .4byte 0x2be - 1699 0373 0C .uleb128 0xc - 1700 0374 23010000 .4byte 0x123 - 1701 0378 0B .uleb128 0xb - 1702 0379 20 .byte 0x20 - 1703 037a 09 .byte 0x9 - 1704 037b 57 .byte 0x57 - 1705 037c E3030000 .4byte 0x3e3 - 1706 0380 09 .uleb128 0x9 - 1707 0381 88050000 .4byte .LASF51 - 1708 0385 09 .byte 0x9 - 1709 0386 58 .byte 0x58 - 1710 0387 86020000 .4byte 0x286 - 1711 038b 02 .byte 0x2 - 1712 038c 23 .byte 0x23 - 1713 038d 00 .uleb128 0 - 1714 038e 09 .uleb128 0x9 - 1715 038f 19050000 .4byte .LASF52 - 1716 0393 09 .byte 0x9 - 1717 0394 59 .byte 0x59 - 1718 0395 02010000 .4byte 0x102 - 1719 0399 02 .byte 0x2 - 1720 039a 23 .byte 0x23 - 1721 039b 08 .uleb128 0x8 - 1722 039c 09 .uleb128 0x9 - 1723 039d CA030000 .4byte .LASF53 - 1724 03a1 09 .byte 0x9 - 1725 03a2 5B .byte 0x5b - 1726 03a3 52030000 .4byte 0x352 - 1727 03a7 02 .byte 0x2 - 1728 03a8 23 .byte 0x23 - 1729 03a9 0C .uleb128 0xc - 1730 03aa 09 .uleb128 0x9 - 1731 03ab 36020000 .4byte .LASF54 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 33 - - - 1732 03af 09 .byte 0x9 - 1733 03b0 5E .byte 0x5e - 1734 03b1 80020000 .4byte 0x280 - 1735 03b5 02 .byte 0x2 - 1736 03b6 23 .byte 0x23 - 1737 03b7 10 .uleb128 0x10 - 1738 03b8 09 .uleb128 0x9 - 1739 03b9 F4030000 .4byte .LASF55 - 1740 03bd 09 .byte 0x9 - 1741 03be 5F .byte 0x5f - 1742 03bf 80020000 .4byte 0x280 - 1743 03c3 02 .byte 0x2 - 1744 03c4 23 .byte 0x23 - 1745 03c5 14 .uleb128 0x14 - 1746 03c6 09 .uleb128 0x9 - 1747 03c7 BD040000 .4byte .LASF56 - 1748 03cb 09 .byte 0x9 - 1749 03cc 63 .byte 0x63 - 1750 03cd 2E010000 .4byte 0x12e - 1751 03d1 02 .byte 0x2 - 1752 03d2 23 .byte 0x23 - 1753 03d3 18 .uleb128 0x18 - 1754 03d4 09 .uleb128 0x9 - 1755 03d5 C3050000 .4byte .LASF57 - 1756 03d9 09 .byte 0x9 - 1757 03da 65 .byte 0x65 - 1758 03db 80020000 .4byte 0x280 - 1759 03df 02 .byte 0x2 - 1760 03e0 23 .byte 0x23 - 1761 03e1 1C .uleb128 0x1c - 1762 03e2 00 .byte 0 - 1763 03e3 02 .uleb128 0x2 - 1764 03e4 8D060000 .4byte .LASF58 - 1765 03e8 09 .byte 0x9 - 1766 03e9 67 .byte 0x67 - 1767 03ea 78030000 .4byte 0x378 - 1768 03ee 08 .uleb128 0x8 - 1769 03ef 67060000 .4byte .LASF59 - 1770 03f3 0C .byte 0xc - 1771 03f4 0A .byte 0xa - 1772 03f5 25 .byte 0x25 - 1773 03f6 17040000 .4byte 0x417 - 1774 03fa 09 .uleb128 0x9 - 1775 03fb FC010000 .4byte .LASF60 - 1776 03ff 0A .byte 0xa - 1777 0400 26 .byte 0x26 - 1778 0401 86020000 .4byte 0x286 - 1779 0405 02 .byte 0x2 - 1780 0406 23 .byte 0x23 - 1781 0407 00 .uleb128 0 - 1782 0408 09 .uleb128 0x9 - 1783 0409 E3020000 .4byte .LASF61 - 1784 040d 0A .byte 0xa - 1785 040e 28 .byte 0x28 - 1786 040f 2E010000 .4byte 0x12e - 1787 0413 02 .byte 0x2 - 1788 0414 23 .byte 0x23 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 34 - - - 1789 0415 08 .uleb128 0x8 - 1790 0416 00 .byte 0 - 1791 0417 02 .uleb128 0x2 - 1792 0418 67060000 .4byte .LASF59 - 1793 041c 0A .byte 0xa - 1794 041d 29 .byte 0x29 - 1795 041e EE030000 .4byte 0x3ee - 1796 0422 08 .uleb128 0x8 - 1797 0423 9C030000 .4byte .LASF62 - 1798 0427 10 .byte 0x10 - 1799 0428 0B .byte 0xb - 1800 0429 25 .byte 0x25 - 1801 042a 59040000 .4byte 0x459 - 1802 042e 09 .uleb128 0x9 - 1803 042f 24010000 .4byte .LASF63 - 1804 0433 0B .byte 0xb - 1805 0434 26 .byte 0x26 - 1806 0435 86020000 .4byte 0x286 - 1807 0439 02 .byte 0x2 - 1808 043a 23 .byte 0x23 - 1809 043b 00 .uleb128 0 - 1810 043c 09 .uleb128 0x9 - 1811 043d FA060000 .4byte .LASF64 - 1812 0441 0B .byte 0xb - 1813 0442 28 .byte 0x28 - 1814 0443 80020000 .4byte 0x280 - 1815 0447 02 .byte 0x2 - 1816 0448 23 .byte 0x23 - 1817 0449 08 .uleb128 0x8 - 1818 044a 09 .uleb128 0x9 - 1819 044b 0F060000 .4byte .LASF65 - 1820 044f 0B .byte 0xb - 1821 0450 2A .byte 0x2a - 1822 0451 59040000 .4byte 0x459 - 1823 0455 02 .byte 0x2 - 1824 0456 23 .byte 0x23 - 1825 0457 0C .uleb128 0xc - 1826 0458 00 .byte 0 - 1827 0459 06 .uleb128 0x6 - 1828 045a 04 .byte 0x4 - 1829 045b 22040000 .4byte 0x422 - 1830 045f 02 .uleb128 0x2 - 1831 0460 9C030000 .4byte .LASF62 - 1832 0464 0B .byte 0xb - 1833 0465 2C .byte 0x2c - 1834 0466 22040000 .4byte 0x422 - 1835 046a 02 .uleb128 0x2 - 1836 046b B4060000 .4byte .LASF66 - 1837 046f 0C .byte 0xc - 1838 0470 22 .byte 0x22 - 1839 0471 75040000 .4byte 0x475 - 1840 0475 08 .uleb128 0x8 - 1841 0476 B4060000 .4byte .LASF66 - 1842 047a 0C .byte 0xc - 1843 047b 0C .byte 0xc - 1844 047c 27 .byte 0x27 - 1845 047d AC040000 .4byte 0x4ac - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 35 - - - 1846 0481 09 .uleb128 0x9 - 1847 0482 36050000 .4byte .LASF67 - 1848 0486 0C .byte 0xc - 1849 0487 28 .byte 0x28 - 1850 0488 AC040000 .4byte 0x4ac - 1851 048c 02 .byte 0x2 - 1852 048d 23 .byte 0x23 - 1853 048e 00 .uleb128 0 - 1854 048f 09 .uleb128 0x9 - 1855 0490 E4040000 .4byte .LASF68 - 1856 0494 0C .byte 0xc - 1857 0495 2B .byte 0x2b - 1858 0496 80020000 .4byte 0x280 - 1859 049a 02 .byte 0x2 - 1860 049b 23 .byte 0x23 - 1861 049c 04 .uleb128 0x4 - 1862 049d 09 .uleb128 0x9 - 1863 049e B2030000 .4byte .LASF69 - 1864 04a2 0C .byte 0xc - 1865 04a3 2D .byte 0x2d - 1866 04a4 18010000 .4byte 0x118 - 1867 04a8 02 .byte 0x2 - 1868 04a9 23 .byte 0x23 - 1869 04aa 08 .uleb128 0x8 - 1870 04ab 00 .byte 0 - 1871 04ac 06 .uleb128 0x6 - 1872 04ad 04 .byte 0x4 - 1873 04ae 6A040000 .4byte 0x46a - 1874 04b2 08 .uleb128 0x8 - 1875 04b3 6B020000 .4byte .LASF70 - 1876 04b7 04 .byte 0x4 - 1877 04b8 0C .byte 0xc - 1878 04b9 35 .byte 0x35 - 1879 04ba CD040000 .4byte 0x4cd - 1880 04be 09 .uleb128 0x9 - 1881 04bf 85060000 .4byte .LASF71 - 1882 04c3 0C .byte 0xc - 1883 04c4 36 .byte 0x36 - 1884 04c5 AC040000 .4byte 0x4ac - 1885 04c9 02 .byte 0x2 - 1886 04ca 23 .byte 0x23 - 1887 04cb 00 .uleb128 0 - 1888 04cc 00 .byte 0 - 1889 04cd 02 .uleb128 0x2 - 1890 04ce 6B020000 .4byte .LASF70 - 1891 04d2 0C .byte 0xc - 1892 04d3 39 .byte 0x39 - 1893 04d4 B2040000 .4byte 0x4b2 - 1894 04d8 0B .uleb128 0xb - 1895 04d9 28 .byte 0x28 - 1896 04da 0D .byte 0xd - 1897 04db 2C .byte 0x2c - 1898 04dc 35050000 .4byte 0x535 - 1899 04e0 09 .uleb128 0x9 - 1900 04e1 DD030000 .4byte .LASF72 - 1901 04e5 0D .byte 0xd - 1902 04e6 2D .byte 0x2d - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 36 - - - 1903 04e7 35050000 .4byte 0x535 - 1904 04eb 02 .byte 0x2 - 1905 04ec 23 .byte 0x23 - 1906 04ed 00 .uleb128 0 - 1907 04ee 09 .uleb128 0x9 - 1908 04ef DD040000 .4byte .LASF73 - 1909 04f3 0D .byte 0xd - 1910 04f4 2F .byte 0x2f - 1911 04f5 35050000 .4byte 0x535 - 1912 04f9 02 .byte 0x2 - 1913 04fa 23 .byte 0x23 - 1914 04fb 04 .uleb128 0x4 - 1915 04fc 09 .uleb128 0x9 - 1916 04fd F1060000 .4byte .LASF74 - 1917 0501 0D .byte 0xd - 1918 0502 31 .byte 0x31 - 1919 0503 35050000 .4byte 0x535 - 1920 0507 02 .byte 0x2 - 1921 0508 23 .byte 0x23 - 1922 0509 08 .uleb128 0x8 - 1923 050a 09 .uleb128 0x9 - 1924 050b 93030000 .4byte .LASF75 - 1925 050f 0D .byte 0xd - 1926 0510 32 .byte 0x32 - 1927 0511 35050000 .4byte 0x535 - 1928 0515 02 .byte 0x2 - 1929 0516 23 .byte 0x23 - 1930 0517 0C .uleb128 0xc - 1931 0518 09 .uleb128 0x9 - 1932 0519 40000000 .4byte .LASF76 - 1933 051d 0D .byte 0xd - 1934 051e 33 .byte 0x33 - 1935 051f 17040000 .4byte 0x417 - 1936 0523 02 .byte 0x2 - 1937 0524 23 .byte 0x23 - 1938 0525 10 .uleb128 0x10 - 1939 0526 09 .uleb128 0x9 - 1940 0527 CD020000 .4byte .LASF77 - 1941 052b 0D .byte 0xd - 1942 052c 35 .byte 0x35 - 1943 052d 17040000 .4byte 0x417 - 1944 0531 02 .byte 0x2 - 1945 0532 23 .byte 0x23 - 1946 0533 1C .uleb128 0x1c - 1947 0534 00 .byte 0 - 1948 0535 06 .uleb128 0x6 - 1949 0536 04 .byte 0x4 - 1950 0537 0D010000 .4byte 0x10d - 1951 053b 02 .uleb128 0x2 - 1952 053c 6A000000 .4byte .LASF78 - 1953 0540 0D .byte 0xd - 1954 0541 37 .byte 0x37 - 1955 0542 D8040000 .4byte 0x4d8 - 1956 0546 0D .uleb128 0xd - 1957 0547 04 .byte 0x4 - 1958 0548 06 .byte 0x6 - 1959 0549 7F .byte 0x7f - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 37 - - - 1960 054a 7B050000 .4byte 0x57b - 1961 054e 0E .uleb128 0xe - 1962 054f 05000000 .4byte .LASF79 - 1963 0553 06 .byte 0x6 - 1964 0554 86 .byte 0x86 - 1965 0555 0D010000 .4byte 0x10d - 1966 0559 0E .uleb128 0xe - 1967 055a A3000000 .4byte .LASF80 - 1968 055e 06 .byte 0x6 - 1969 055f 8D .byte 0x8d - 1970 0560 0D010000 .4byte 0x10d - 1971 0564 0E .uleb128 0xe - 1972 0565 C2060000 .4byte .LASF81 - 1973 0569 06 .byte 0x6 - 1974 056a 94 .byte 0x94 - 1975 056b 73000000 .4byte 0x73 - 1976 056f 0E .uleb128 0xe - 1977 0570 20050000 .4byte .LASF82 - 1978 0574 06 .byte 0x6 - 1979 0575 9B .byte 0x9b - 1980 0576 18010000 .4byte 0x118 - 1981 057a 00 .byte 0 - 1982 057b 06 .uleb128 0x6 - 1983 057c 04 .byte 0x4 - 1984 057d 5F040000 .4byte 0x45f - 1985 0581 02 .uleb128 0x2 - 1986 0582 6B030000 .4byte .LASF83 - 1987 0586 0E .byte 0xe - 1988 0587 30 .byte 0x30 - 1989 0588 8C050000 .4byte 0x58c - 1990 058c 08 .uleb128 0x8 - 1991 058d 6B030000 .4byte .LASF83 - 1992 0591 20 .byte 0x20 - 1993 0592 0E .byte 0xe - 1994 0593 3E .byte 0x3e - 1995 0594 FB050000 .4byte 0x5fb - 1996 0598 09 .uleb128 0x9 - 1997 0599 11040000 .4byte .LASF84 - 1998 059d 0E .byte 0xe - 1999 059e 3F .byte 0x3f - 2000 059f 86020000 .4byte 0x286 - 2001 05a3 02 .byte 0x2 - 2002 05a4 23 .byte 0x23 - 2003 05a5 00 .uleb128 0 - 2004 05a6 09 .uleb128 0x9 - 2005 05a7 89030000 .4byte .LASF85 - 2006 05ab 0E .byte 0xe - 2007 05ac 40 .byte 0x40 - 2008 05ad 29000000 .4byte 0x29 - 2009 05b1 02 .byte 0x2 - 2010 05b2 23 .byte 0x23 - 2011 05b3 08 .uleb128 0x8 - 2012 05b4 09 .uleb128 0x9 - 2013 05b5 CE010000 .4byte .LASF86 - 2014 05b9 0E .byte 0xe - 2015 05ba 41 .byte 0x41 - 2016 05bb 1E060000 .4byte 0x61e - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 38 - - - 2017 05bf 02 .byte 0x2 - 2018 05c0 23 .byte 0x23 - 2019 05c1 0C .uleb128 0xc - 2020 05c2 09 .uleb128 0x9 - 2021 05c3 64000000 .4byte .LASF87 - 2022 05c7 0E .byte 0xe - 2023 05c8 42 .byte 0x42 - 2024 05c9 1E060000 .4byte 0x61e - 2025 05cd 02 .byte 0x2 - 2026 05ce 23 .byte 0x23 - 2027 05cf 10 .uleb128 0x10 - 2028 05d0 09 .uleb128 0x9 - 2029 05d1 D7010000 .4byte .LASF88 - 2030 05d5 0E .byte 0xe - 2031 05d6 44 .byte 0x44 - 2032 05d7 1E060000 .4byte 0x61e - 2033 05db 02 .byte 0x2 - 2034 05dc 23 .byte 0x23 - 2035 05dd 14 .uleb128 0x14 - 2036 05de 09 .uleb128 0x9 - 2037 05df 78040000 .4byte .LASF89 - 2038 05e3 0E .byte 0xe - 2039 05e4 45 .byte 0x45 - 2040 05e5 1E060000 .4byte 0x61e - 2041 05e9 02 .byte 0x2 - 2042 05ea 23 .byte 0x23 - 2043 05eb 18 .uleb128 0x18 - 2044 05ec 09 .uleb128 0x9 - 2045 05ed 97060000 .4byte .LASF90 - 2046 05f1 0E .byte 0xe - 2047 05f2 46 .byte 0x46 - 2048 05f3 FB050000 .4byte 0x5fb - 2049 05f7 02 .byte 0x2 - 2050 05f8 23 .byte 0x23 - 2051 05f9 1C .uleb128 0x1c - 2052 05fa 00 .byte 0 - 2053 05fb 02 .uleb128 0x2 - 2054 05fc 61030000 .4byte .LASF91 - 2055 0600 0E .byte 0xe - 2056 0601 33 .byte 0x33 - 2057 0602 06060000 .4byte 0x606 - 2058 0606 06 .uleb128 0x6 - 2059 0607 04 .byte 0x4 - 2060 0608 0C060000 .4byte 0x60c - 2061 060c 0F .uleb128 0xf - 2062 060d 01 .byte 0x1 - 2063 060e 18060000 .4byte 0x618 - 2064 0612 10 .uleb128 0x10 - 2065 0613 18060000 .4byte 0x618 - 2066 0617 00 .byte 0 - 2067 0618 06 .uleb128 0x6 - 2068 0619 04 .byte 0x4 - 2069 061a 81050000 .4byte 0x581 - 2070 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.4byte 0x63a - 2102 0665 11 .uleb128 0x11 - 2103 0666 01 .byte 0x1 - 2104 0667 29000000 .4byte 0x29 - 2105 066b 7F060000 .4byte 0x67f - 2106 066f 10 .uleb128 0x10 - 2107 0670 73000000 .4byte 0x73 - 2108 0674 10 .uleb128 0x10 - 2109 0675 1E060000 .4byte 0x61e - 2110 0679 10 .uleb128 0x10 - 2111 067a 29000000 .4byte 0x29 - 2112 067e 00 .byte 0 - 2113 067f 06 .uleb128 0x6 - 2114 0680 04 .byte 0x4 - 2115 0681 65060000 .4byte 0x665 - 2116 0685 11 .uleb128 0x11 - 2117 0686 01 .byte 0x1 - 2118 0687 D6000000 .4byte 0xd6 - 2119 068b 95060000 .4byte 0x695 - 2120 068f 10 .uleb128 0x10 - 2121 0690 73000000 .4byte 0x73 - 2122 0694 00 .byte 0 - 2123 0695 06 .uleb128 0x6 - 2124 0696 04 .byte 0x4 - 2125 0697 85060000 .4byte 0x685 - 2126 069b 11 .uleb128 0x11 - 2127 069c 01 .byte 0x1 - 2128 069d 0D010000 .4byte 0x10d - 2129 06a1 B5060000 .4byte 0x6b5 - 2130 06a5 10 .uleb128 0x10 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 40 - - - 2131 06a6 73000000 .4byte 0x73 - 2132 06aa 10 .uleb128 0x10 - 2133 06ab 94000000 .4byte 0x94 - 2134 06af 10 .uleb128 0x10 - 2135 06b0 23010000 .4byte 0x123 - 2136 06b4 00 .byte 0 - 2137 06b5 06 .uleb128 0x6 - 2138 06b6 04 .byte 0x4 - 2139 06b7 9B060000 .4byte 0x69b - 2140 06bb 11 .uleb128 0x11 - 2141 06bc 01 .byte 0x1 - 2142 06bd 0D010000 .4byte 0x10d - 2143 06c1 D0060000 .4byte 0x6d0 - 2144 06c5 10 .uleb128 0x10 - 2145 06c6 73000000 .4byte 0x73 - 2146 06ca 10 .uleb128 0x10 - 2147 06cb 23010000 .4byte 0x123 - 2148 06cf 00 .byte 0 - 2149 06d0 06 .uleb128 0x6 - 2150 06d1 04 .byte 0x4 - 2151 06d2 BB060000 .4byte 0x6bb - 2152 06d6 11 .uleb128 0x11 - 2153 06d7 01 .byte 0x1 - 2154 06d8 29000000 .4byte 0x29 - 2155 06dc F5060000 .4byte 0x6f5 - 2156 06e0 10 .uleb128 0x10 - 2157 06e1 73000000 .4byte 0x73 - 2158 06e5 10 .uleb128 0x10 - 2159 06e6 54060000 .4byte 0x654 - 2160 06ea 10 .uleb128 0x10 - 2161 06eb 29000000 .4byte 0x29 - 2162 06ef 10 .uleb128 0x10 - 2163 06f0 23010000 .4byte 0x123 - 2164 06f4 00 .byte 0 - 2165 06f5 06 .uleb128 0x6 - 2166 06f6 04 .byte 0x4 - 2167 06f7 D6060000 .4byte 0x6d6 - 2168 06fb 11 .uleb128 0x11 - 2169 06fc 01 .byte 0x1 - 2170 06fd 29000000 .4byte 0x29 - 2171 0701 1A070000 .4byte 0x71a - 2172 0705 10 .uleb128 0x10 - 2173 0706 73000000 .4byte 0x73 - 2174 070a 10 .uleb128 0x10 - 2175 070b 1E060000 .4byte 0x61e - 2176 070f 10 .uleb128 0x10 - 2177 0710 29000000 .4byte 0x29 - 2178 0714 10 .uleb128 0x10 - 2179 0715 23010000 .4byte 0x123 - 2180 0719 00 .byte 0 - 2181 071a 06 .uleb128 0x6 - 2182 071b 04 .byte 0x4 - 2183 071c FB060000 .4byte 0x6fb - 2184 0720 12 .uleb128 0x12 - 2185 0721 4D060000 .4byte .LASF94 - 2186 0725 0F .byte 0xf - 2187 0726 0401 .2byte 0x104 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 41 - - - 2188 0728 CB000000 .4byte 0xcb - 2189 072c 11 .uleb128 0x11 - 2190 072d 01 .byte 0x1 - 2191 072e 20070000 .4byte 0x720 - 2192 0732 3C070000 .4byte 0x73c - 2193 0736 10 .uleb128 0x10 - 2194 0737 73000000 .4byte 0x73 - 2195 073b 00 .byte 0 - 2196 073c 06 .uleb128 0x6 - 2197 073d 04 .byte 0x4 - 2198 073e 2C070000 .4byte 0x72c - 2199 0742 0C .uleb128 0xc - 2200 0743 9F000000 .4byte 0x9f - 2201 0747 13 .uleb128 0x13 - 2202 0748 54 .byte 0x54 - 2203 0749 10 .byte 0x10 - 2204 074a 6902 .2byte 0x269 - 2205 074c A7090000 .4byte 0x9a7 - 2206 0750 14 .uleb128 0x14 - 2207 0751 43523100 .ascii "CR1\000" - 2208 0755 10 .byte 0x10 - 2209 0756 6B02 .2byte 0x26b - 2210 0758 42070000 .4byte 0x742 - 2211 075c 02 .byte 0x2 - 2212 075d 23 .byte 0x23 - 2213 075e 00 .uleb128 0 - 2214 075f 15 .uleb128 0x15 - 2215 0760 23040000 .4byte .LASF95 - 2216 0764 10 .byte 0x10 - 2217 0765 6C02 .2byte 0x26c - 2218 0767 9F000000 .4byte 0x9f - 2219 076b 02 .byte 0x2 - 2220 076c 23 .byte 0x23 - 2221 076d 02 .uleb128 0x2 - 2222 076e 14 .uleb128 0x14 - 2223 076f 43523200 .ascii "CR2\000" - 2224 0773 10 .byte 0x10 - 2225 0774 6D02 .2byte 0x26d - 2226 0776 42070000 .4byte 0x742 - 2227 077a 02 .byte 0x2 - 2228 077b 23 .byte 0x23 - 2229 077c 04 .uleb128 0x4 - 2230 077d 15 .uleb128 0x15 - 2231 077e 2D040000 .4byte .LASF96 - 2232 0782 10 .byte 0x10 - 2233 0783 6E02 .2byte 0x26e - 2234 0785 9F000000 .4byte 0x9f - 2235 0789 02 .byte 0x2 - 2236 078a 23 .byte 0x23 - 2237 078b 06 .uleb128 0x6 - 2238 078c 15 .uleb128 0x15 - 2239 078d D7050000 .4byte .LASF97 - 2240 0791 10 .byte 0x10 - 2241 0792 6F02 .2byte 0x26f - 2242 0794 42070000 .4byte 0x742 - 2243 0798 02 .byte 0x2 - 2244 0799 23 .byte 0x23 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 42 - - - 2245 079a 08 .uleb128 0x8 - 2246 079b 15 .uleb128 0x15 - 2247 079c 37040000 .4byte .LASF98 - 2248 07a0 10 .byte 0x10 - 2249 07a1 7002 .2byte 0x270 - 2250 07a3 9F000000 .4byte 0x9f - 2251 07a7 02 .byte 0x2 - 2252 07a8 23 .byte 0x23 - 2253 07a9 0A .uleb128 0xa - 2254 07aa 15 .uleb128 0x15 - 2255 07ab 00000000 .4byte .LASF99 - 2256 07af 10 .byte 0x10 - 2257 07b0 7102 .2byte 0x271 - 2258 07b2 42070000 .4byte 0x742 - 2259 07b6 02 .byte 0x2 - 2260 07b7 23 .byte 0x23 - 2261 07b8 0C .uleb128 0xc - 2262 07b9 15 .uleb128 0x15 - 2263 07ba 41040000 .4byte .LASF100 - 2264 07be 10 .byte 0x10 - 2265 07bf 7202 .2byte 0x272 - 2266 07c1 9F000000 .4byte 0x9f - 2267 07c5 02 .byte 0x2 - 2268 07c6 23 .byte 0x23 - 2269 07c7 0E .uleb128 0xe - 2270 07c8 14 .uleb128 0x14 - 2271 07c9 535200 .ascii "SR\000" - 2272 07cc 10 .byte 0x10 - 2273 07cd 7302 .2byte 0x273 - 2274 07cf 42070000 .4byte 0x742 - 2275 07d3 02 .byte 0x2 - 2276 07d4 23 .byte 0x23 - 2277 07d5 10 .uleb128 0x10 - 2278 07d6 15 .uleb128 0x15 - 2279 07d7 4B040000 .4byte .LASF101 - 2280 07db 10 .byte 0x10 - 2281 07dc 7402 .2byte 0x274 - 2282 07de 9F000000 .4byte 0x9f - 2283 07e2 02 .byte 0x2 - 2284 07e3 23 .byte 0x23 - 2285 07e4 12 .uleb128 0x12 - 2286 07e5 14 .uleb128 0x14 - 2287 07e6 45475200 .ascii "EGR\000" - 2288 07ea 10 .byte 0x10 - 2289 07eb 7502 .2byte 0x275 - 2290 07ed 42070000 .4byte 0x742 - 2291 07f1 02 .byte 0x2 - 2292 07f2 23 .byte 0x23 - 2293 07f3 14 .uleb128 0x14 - 2294 07f4 15 .uleb128 0x15 - 2295 07f5 62050000 .4byte .LASF102 - 2296 07f9 10 .byte 0x10 - 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0x2 - 2722 0b0f 23 .byte 0x23 - 2723 0b10 1C .uleb128 0x1c - 2724 0b11 09 .uleb128 0x9 - 2725 0b12 0C040000 .4byte .LASF135 - 2726 0b16 11 .byte 0x11 - 2727 0b17 8C .byte 0x8c - 2728 0b18 42030000 .4byte 0x342 - 2729 0b1c 02 .byte 0x2 - 2730 0b1d 23 .byte 0x23 - 2731 0b1e 20 .uleb128 0x20 - 2732 0b1f 09 .uleb128 0x9 - 2733 0b20 07040000 .4byte .LASF136 - 2734 0b24 11 .byte 0x11 - 2735 0b25 8D .byte 0x8d - 2736 0b26 42030000 .4byte 0x342 - 2737 0b2a 02 .byte 0x2 - 2738 0b2b 23 .byte 0x23 - 2739 0b2c 24 .uleb128 0x24 - 2740 0b2d 00 .byte 0 - 2741 0b2e 02 .uleb128 0x2 - 2742 0b2f C0020000 .4byte .LASF137 - 2743 0b33 11 .byte 0x11 - 2744 0b34 8E .byte 0x8e - 2745 0b35 990A0000 .4byte 0xa99 - 2746 0b39 02 .uleb128 0x2 - 2747 0b3a 4B000000 .4byte .LASF138 - 2748 0b3e 11 .byte 0x11 - 2749 0b3f D8 .byte 0xd8 - 2750 0b40 B5000000 .4byte 0xb5 - 2751 0b44 16 .uleb128 0x16 - 2752 0b45 01 .byte 0x1 - 2753 0b46 12 .byte 0x12 - 2754 0b47 35 .byte 0x35 - 2755 0b48 6B0B0000 .4byte 0xb6b - 2756 0b4c 17 .uleb128 0x17 - 2757 0b4d E9020000 .4byte .LASF139 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 51 - - - 2758 0b51 00 .sleb128 0 - 2759 0b52 17 .uleb128 0x17 - 2760 0b53 6C050000 .4byte .LASF140 - 2761 0b57 01 .sleb128 1 - 2762 0b58 17 .uleb128 0x17 - 2763 0b59 A2030000 .4byte .LASF141 - 2764 0b5d 02 .sleb128 2 - 2765 0b5e 17 .uleb128 0x17 - 2766 0b5f 2C010000 .4byte .LASF142 - 2767 0b63 03 .sleb128 3 - 2768 0b64 17 .uleb128 0x17 - 2769 0b65 34000000 .4byte .LASF143 - 2770 0b69 04 .sleb128 4 - 2771 0b6a 00 .byte 0 - 2772 0b6b 02 .uleb128 0x2 - 2773 0b6c 77020000 .4byte .LASF144 - 2774 0b70 12 .byte 0x12 - 2775 0b71 3B .byte 0x3b - 2776 0b72 440B0000 .4byte 0xb44 - 2777 0b76 02 .uleb128 0x2 - 2778 0b77 3E020000 .4byte .LASF145 - 2779 0b7b 12 .byte 0x12 - 2780 0b7c 40 .byte 0x40 - 2781 0b7d 810B0000 .4byte 0xb81 - 2782 0b81 08 .uleb128 0x8 - 2783 0b82 3E020000 .4byte .LASF145 - 2784 0b86 10 .byte 0x10 - 2785 0b87 13 .byte 0x13 - 2786 0b88 D0 .byte 0xd0 - 2787 0b89 C60B0000 .4byte 0xbc6 - 2788 0b8d 09 .uleb128 0x9 - 2789 0b8e 9E010000 .4byte .LASF146 - 2790 0b92 13 .byte 0x13 - 2791 0b93 D4 .byte 0xd4 - 2792 0b94 6B0B0000 .4byte 0xb6b - 2793 0b98 02 .byte 0x2 - 2794 0b99 23 .byte 0x23 - 2795 0b9a 00 .uleb128 0 - 2796 0b9b 09 .uleb128 0x9 - 2797 0b9c DC050000 .4byte .LASF147 - 2798 0ba0 13 .byte 0x13 - 2799 0ba1 D8 .byte 0xd8 - 2800 0ba2 2F0C0000 .4byte 0xc2f - 2801 0ba6 02 .byte 0x2 - 2802 0ba7 23 .byte 0x23 - 2803 0ba8 04 .uleb128 0x4 - 2804 0ba9 09 .uleb128 0x9 - 2805 0baa D8060000 .4byte .LASF148 - 2806 0bae 13 .byte 0x13 - 2807 0baf E0 .byte 0xe0 - 2808 0bb0 B5000000 .4byte 0xb5 - 2809 0bb4 02 .byte 0x2 - 2810 0bb5 23 .byte 0x23 - 2811 0bb6 08 .uleb128 0x8 - 2812 0bb7 0A .uleb128 0xa - 2813 0bb8 74696D00 .ascii "tim\000" - 2814 0bbc 13 .byte 0x13 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 52 - - - 2815 0bbd E4 .byte 0xe4 - 2816 0bbe 3A0C0000 .4byte 0xc3a - 2817 0bc2 02 .byte 0x2 - 2818 0bc3 23 .byte 0x23 - 2819 0bc4 0C .uleb128 0xc - 2820 0bc5 00 .byte 0 - 2821 0bc6 02 .uleb128 0x2 - 2822 0bc7 04020000 .4byte .LASF149 - 2823 0bcb 12 .byte 0x12 - 2824 0bcc 47 .byte 0x47 - 2825 0bcd D10B0000 .4byte 0xbd1 - 2826 0bd1 06 .uleb128 0x6 - 2827 0bd2 04 .byte 0x4 - 2828 0bd3 D70B0000 .4byte 0xbd7 - 2829 0bd7 0F .uleb128 0xf - 2830 0bd8 01 .byte 0x1 - 2831 0bd9 E30B0000 .4byte 0xbe3 - 2832 0bdd 10 .uleb128 0x10 - 2833 0bde E30B0000 .4byte 0xbe3 - 2834 0be2 00 .byte 0 - 2835 0be3 06 .uleb128 0x6 - 2836 0be4 04 .byte 0x4 - 2837 0be5 760B0000 .4byte 0xb76 - 2838 0be9 02 .uleb128 0x2 - 2839 0bea FA020000 .4byte .LASF150 - 2840 0bee 13 .byte 0x13 - 2841 0bef B3 .byte 0xb3 - 2842 0bf0 B5000000 .4byte 0xb5 - 2843 0bf4 02 .uleb128 0x2 - 2844 0bf5 AD010000 .4byte .LASF151 - 2845 0bf9 13 .byte 0x13 - 2846 0bfa B8 .byte 0xb8 - 2847 0bfb 9F000000 .4byte 0x9f - 2848 0bff 0B .uleb128 0xb - 2849 0c00 08 .byte 0x8 - 2850 0c01 13 .byte 0x13 - 2851 0c02 BE .byte 0xbe - 2852 0c03 240C0000 .4byte 0xc24 - 2853 0c07 09 .uleb128 0x9 - 2854 0c08 CF000000 .4byte .LASF152 - 2855 0c0c 13 .byte 0x13 - 2856 0c0d C4 .byte 0xc4 - 2857 0c0e E90B0000 .4byte 0xbe9 - 2858 0c12 02 .byte 0x2 - 2859 0c13 23 .byte 0x23 - 2860 0c14 00 .uleb128 0 - 2861 0c15 09 .uleb128 0x9 - 2862 0c16 19030000 .4byte .LASF153 - 2863 0c1a 13 .byte 0x13 - 2864 0c1b C9 .byte 0xc9 - 2865 0c1c C60B0000 .4byte 0xbc6 - 2866 0c20 02 .byte 0x2 - 2867 0c21 23 .byte 0x23 - 2868 0c22 04 .uleb128 0x4 - 2869 0c23 00 .byte 0 - 2870 0c24 02 .uleb128 0x2 - 2871 0c25 32060000 .4byte .LASF154 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 53 - - - 2872 0c29 13 .byte 0x13 - 2873 0c2a CB .byte 0xcb - 2874 0c2b FF0B0000 .4byte 0xbff - 2875 0c2f 06 .uleb128 0x6 - 2876 0c30 04 .byte 0x4 - 2877 0c31 350C0000 .4byte 0xc35 - 2878 0c35 07 .uleb128 0x7 - 2879 0c36 240C0000 .4byte 0xc24 - 2880 0c3a 06 .uleb128 0x6 - 2881 0c3b 04 .byte 0x4 - 2882 0c3c A7090000 .4byte 0x9a7 - 2883 0c40 16 .uleb128 0x16 - 2884 0c41 01 .byte 0x1 - 2885 0c42 14 .byte 0x14 - 2886 0c43 5D .byte 0x5d - 2887 0c44 5B0C0000 .4byte 0xc5b - 2888 0c48 17 .uleb128 0x17 - 2889 0c49 58050000 .4byte .LASF155 - 2890 0c4d 00 .sleb128 0 - 2891 0c4e 17 .uleb128 0x17 - 2892 0c4f 3E050000 .4byte .LASF156 - 2893 0c53 01 .sleb128 1 - 2894 0c54 17 .uleb128 0x17 - 2895 0c55 5E060000 .4byte .LASF157 - 2896 0c59 02 .sleb128 2 - 2897 0c5a 00 .byte 0 - 2898 0c5b 02 .uleb128 0x2 - 2899 0c5c 90050000 .4byte .LASF158 - 2900 0c60 14 .byte 0x14 - 2901 0c61 61 .byte 0x61 - 2902 0c62 400C0000 .4byte 0xc40 - 2903 0c66 02 .uleb128 0x2 - 2904 0c67 A4050000 .4byte .LASF159 - 2905 0c6b 14 .byte 0x14 - 2906 0c6c 66 .byte 0x66 - 2907 0c6d 710C0000 .4byte 0xc71 - 2908 0c71 08 .uleb128 0x8 - 2909 0c72 A4050000 .4byte .LASF159 - 2910 0c76 74 .byte 0x74 - 2911 0c77 14 .byte 0x14 - 2912 0c78 80 .byte 0x80 - 2913 0c79 FA0C0000 .4byte 0xcfa - 2914 0c7d 0A .uleb128 0xa - 2915 0c7e 766D7400 .ascii "vmt\000" - 2916 0c82 14 .byte 0x14 - 2917 0c83 82 .byte 0x82 - 2918 0c84 850D0000 .4byte 0xd85 - 2919 0c88 02 .byte 0x2 - 2920 0c89 23 .byte 0x23 - 2921 0c8a 00 .uleb128 0 - 2922 0c8b 09 .uleb128 0x9 - 2923 0c8c F4020000 .4byte .LASF160 - 2924 0c90 14 .byte 0x14 - 2925 0c91 83 .byte 0x83 - 2926 0c92 CD040000 .4byte 0x4cd - 2927 0c96 02 .byte 0x2 - 2928 0c97 23 .byte 0x23 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 54 - - - 2929 0c98 04 .uleb128 0x4 - 2930 0c99 09 .uleb128 0x9 - 2931 0c9a AE060000 .4byte .LASF161 - 2932 0c9e 14 .byte 0x14 - 2933 0c9f 83 .byte 0x83 - 2934 0ca0 20070000 .4byte 0x720 - 2935 0ca4 02 .byte 0x2 - 2936 0ca5 23 .byte 0x23 - 2937 0ca6 08 .uleb128 0x8 - 2938 0ca7 09 .uleb128 0x9 - 2939 0ca8 9E010000 .4byte .LASF146 - 2940 0cac 14 .byte 0x14 - 2941 0cad 83 .byte 0x83 - 2942 0cae 5B0C0000 .4byte 0xc5b - 2943 0cb2 02 .byte 0x2 - 2944 0cb3 23 .byte 0x23 - 2945 0cb4 0C .uleb128 0xc - 2946 0cb5 09 .uleb128 0x9 - 2947 0cb6 AE020000 .4byte .LASF162 - 2948 0cba 14 .byte 0x14 - 2949 0cbb 83 .byte 0x83 - 2950 0cbc 24060000 .4byte 0x624 - 2951 0cc0 02 .byte 0x2 - 2952 0cc1 23 .byte 0x23 - 2953 0cc2 10 .uleb128 0x10 - 2954 0cc3 09 .uleb128 0x9 - 2955 0cc4 12030000 .4byte .LASF163 - 2956 0cc8 14 .byte 0x14 - 2957 0cc9 83 .byte 0x83 - 2958 0cca 2F060000 .4byte 0x62f - 2959 0cce 02 .byte 0x2 - 2960 0ccf 23 .byte 0x23 - 2961 0cd0 30 .uleb128 0x30 - 2962 0cd1 0A .uleb128 0xa - 2963 0cd2 696200 .ascii "ib\000" - 2964 0cd5 14 .byte 0x14 - 2965 0cd6 83 .byte 0x83 - 2966 0cd7 900D0000 .4byte 0xd90 - 2967 0cdb 02 .byte 0x2 - 2968 0cdc 23 .byte 0x23 - 2969 0cdd 50 .uleb128 0x50 - 2970 0cde 0A .uleb128 0xa - 2971 0cdf 6F6200 .ascii "ob\000" - 2972 0ce2 14 .byte 0x14 - 2973 0ce3 83 .byte 0x83 - 2974 0ce4 900D0000 .4byte 0xd90 - 2975 0ce8 02 .byte 0x2 - 2976 0ce9 23 .byte 0x23 - 2977 0cea 60 .uleb128 0x60 - 2978 0ceb 09 .uleb128 0x9 - 2979 0cec 82020000 .4byte .LASF164 - 2980 0cf0 14 .byte 0x14 - 2981 0cf1 83 .byte 0x83 - 2982 0cf2 A00D0000 .4byte 0xda0 - 2983 0cf6 02 .byte 0x2 - 2984 0cf7 23 .byte 0x23 - 2985 0cf8 70 .uleb128 0x70 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 55 - - - 2986 0cf9 00 .byte 0 - 2987 0cfa 08 .uleb128 0x8 - 2988 0cfb 9E020000 .4byte .LASF165 - 2989 0cff 24 .byte 0x24 - 2990 0d00 14 .byte 0x14 - 2991 0d01 75 .byte 0x75 - 2992 0d02 850D0000 .4byte 0xd85 - 2993 0d06 09 .uleb128 0x9 - 2994 0d07 83030000 .4byte .LASF166 - 2995 0d0b 14 .byte 0x14 - 2996 0d0c 76 .byte 0x76 - 2997 0d0d 5F060000 .4byte 0x65f - 2998 0d11 02 .byte 0x2 - 2999 0d12 23 .byte 0x23 - 3000 0d13 00 .uleb128 0 - 3001 0d14 09 .uleb128 0x9 - 3002 0d15 CD050000 .4byte .LASF167 - 3003 0d19 14 .byte 0x14 - 3004 0d1a 76 .byte 0x76 - 3005 0d1b 7F060000 .4byte 0x67f - 3006 0d1f 02 .byte 0x2 - 3007 0d20 23 .byte 0x23 - 3008 0d21 04 .uleb128 0x4 - 3009 0d22 09 .uleb128 0x9 - 3010 0d23 EE010000 .4byte .LASF168 - 3011 0d27 14 .byte 0x14 - 3012 0d28 76 .byte 0x76 - 3013 0d29 95060000 .4byte 0x695 - 3014 0d2d 02 .byte 0x2 - 3015 0d2e 23 .byte 0x23 - 3016 0d2f 08 .uleb128 0x8 - 3017 0d30 09 .uleb128 0x9 - 3018 0d31 DE060000 .4byte .LASF169 - 3019 0d35 14 .byte 0x14 - 3020 0d36 76 .byte 0x76 - 3021 0d37 95060000 .4byte 0x695 - 3022 0d3b 02 .byte 0x2 - 3023 0d3c 23 .byte 0x23 - 3024 0d3d 0C .uleb128 0xc - 3025 0d3e 0A .uleb128 0xa - 3026 0d3f 70757400 .ascii "put\000" - 3027 0d43 14 .byte 0x14 - 3028 0d44 76 .byte 0x76 - 3029 0d45 B5060000 .4byte 0x6b5 - 3030 0d49 02 .byte 0x2 - 3031 0d4a 23 .byte 0x23 - 3032 0d4b 10 .uleb128 0x10 - 3033 0d4c 0A .uleb128 0xa - 3034 0d4d 67657400 .ascii "get\000" - 3035 0d51 14 .byte 0x14 - 3036 0d52 76 .byte 0x76 - 3037 0d53 D0060000 .4byte 0x6d0 - 3038 0d57 02 .byte 0x2 - 3039 0d58 23 .byte 0x23 - 3040 0d59 14 .uleb128 0x14 - 3041 0d5a 09 .uleb128 0x9 - 3042 0d5b 30030000 .4byte .LASF170 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 56 - - - 3043 0d5f 14 .byte 0x14 - 3044 0d60 76 .byte 0x76 - 3045 0d61 F5060000 .4byte 0x6f5 - 3046 0d65 02 .byte 0x2 - 3047 0d66 23 .byte 0x23 - 3048 0d67 18 .uleb128 0x18 - 3049 0d68 09 .uleb128 0x9 - 3050 0d69 E7000000 .4byte .LASF171 - 3051 0d6d 14 .byte 0x14 - 3052 0d6e 76 .byte 0x76 - 3053 0d6f 1A070000 .4byte 0x71a - 3054 0d73 02 .byte 0x2 - 3055 0d74 23 .byte 0x23 - 3056 0d75 1C .uleb128 0x1c - 3057 0d76 09 .uleb128 0x9 - 3058 0d77 3C060000 .4byte .LASF172 - 3059 0d7b 14 .byte 0x14 - 3060 0d7c 76 .byte 0x76 - 3061 0d7d 3C070000 .4byte 0x73c - 3062 0d81 02 .byte 0x2 - 3063 0d82 23 .byte 0x23 - 3064 0d83 20 .uleb128 0x20 - 3065 0d84 00 .byte 0 - 3066 0d85 06 .uleb128 0x6 - 3067 0d86 04 .byte 0x4 - 3068 0d87 8B0D0000 .4byte 0xd8b - 3069 0d8b 07 .uleb128 0x7 - 3070 0d8c FA0C0000 .4byte 0xcfa - 3071 0d90 18 .uleb128 0x18 - 3072 0d91 94000000 .4byte 0x94 - 3073 0d95 A00D0000 .4byte 0xda0 - 3074 0d99 19 .uleb128 0x19 - 3075 0d9a 34000000 .4byte 0x34 - 3076 0d9e 0F .byte 0xf - 3077 0d9f 00 .byte 0 - 3078 0da0 06 .uleb128 0x6 - 3079 0da1 04 .byte 0x4 - 3080 0da2 8D0A0000 .4byte 0xa8d - 3081 0da6 1A .uleb128 0x1a - 3082 0da7 BC000000 .4byte .LASF173 - 3083 0dab 01 .byte 0x1 - 3084 0dac B9 .byte 0xb9 - 3085 0dad 01 .byte 0x1 - 3086 0dae 01 .byte 0x1 - 3087 0daf D10D0000 .4byte 0xdd1 - 3088 0db3 1B .uleb128 0x1b - 3089 0db4 6E00 .ascii "n\000" - 3090 0db6 01 .byte 0x1 - 3091 0db7 B9 .byte 0xb9 - 3092 0db8 B5000000 .4byte 0xb5 - 3093 0dbc 1C .uleb128 0x1c - 3094 0dbd 62756600 .ascii "buf\000" - 3095 0dc1 01 .byte 0x1 - 3096 0dc2 BA .byte 0xba - 3097 0dc3 D10D0000 .4byte 0xdd1 - 3098 0dc7 1C .uleb128 0x1c - 3099 0dc8 7000 .ascii "p\000" - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 57 - - - 3100 0dca 01 .byte 0x1 - 3101 0dcb BA .byte 0xba - 3102 0dcc 7C000000 .4byte 0x7c - 3103 0dd0 00 .byte 0 - 3104 0dd1 18 .uleb128 0x18 - 3105 0dd2 82000000 .4byte 0x82 - 3106 0dd6 E10D0000 .4byte 0xde1 - 3107 0dda 19 .uleb128 0x19 - 3108 0ddb 34000000 .4byte 0x34 - 3109 0ddf 0F .byte 0xf - 3110 0de0 00 .byte 0 - 3111 0de1 1A .uleb128 0x1a - 3112 0de2 AC000000 .4byte .LASF174 - 3113 0de6 01 .byte 0x1 - 3114 0de7 AA .byte 0xaa - 3115 0de8 01 .byte 0x1 - 3116 0de9 01 .byte 0x1 - 3117 0dea F80D0000 .4byte 0xdf8 - 3118 0dee 1B .uleb128 0x1b - 3119 0def 7000 .ascii "p\000" - 3120 0df1 01 .byte 0x1 - 3121 0df2 AA .byte 0xaa - 3122 0df3 7C000000 .4byte 0x7c - 3123 0df7 00 .byte 0 - 3124 0df8 1D .uleb128 0x1d - 3125 0df9 BA030000 .4byte .LASF175 - 3126 0dfd 01 .byte 0x1 - 3127 0dfe B1 .byte 0xb1 - 3128 0dff 01 .byte 0x1 - 3129 0e00 00000000 .4byte .LFB66 - 3130 0e04 38000000 .4byte .LFE66 - 3131 0e08 00000000 .4byte .LLST0 - 3132 0e0c 1E0E0000 .4byte 0xe1e - 3133 0e10 1E .uleb128 0x1e - 3134 0e11 7000 .ascii "p\000" - 3135 0e13 01 .byte 0x1 - 3136 0e14 B1 .byte 0xb1 - 3137 0e15 7C000000 .4byte 0x7c - 3138 0e19 20000000 .4byte .LLST1 - 3139 0e1d 00 .byte 0 - 3140 0e1e 1D .uleb128 0x1d - 3141 0e1f D1060000 .4byte .LASF176 - 3142 0e23 01 .byte 0x1 - 3143 0e24 8A .byte 0x8a - 3144 0e25 01 .byte 0x1 - 3145 0e26 00000000 .4byte .LFB64 - 3146 0e2a 28000000 .4byte .LFE64 - 3147 0e2e 33000000 .4byte .LLST2 - 3148 0e32 890E0000 .4byte 0xe89 - 3149 0e36 1F .uleb128 0x1f - 3150 0e37 DE020000 .4byte .LASF177 - 3151 0e3b 01 .byte 0x1 - 3152 0e3c 8A .byte 0x8a - 3153 0e3d E30B0000 .4byte 0xbe3 - 3154 0e41 53000000 .4byte .LLST3 - 3155 0e45 20 .uleb128 0x20 - 3156 0e46 6D736700 .ascii "msg\000" - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 58 - - - 3157 0e4a 01 .byte 0x1 - 3158 0e4b 8B .byte 0x8b - 3159 0e4c 0D010000 .4byte 0x10d - 3160 0e50 01 .byte 0x1 - 3161 0e51 50 .byte 0x50 - 3162 0e52 21 .uleb128 0x21 - 3163 0e53 02000000 .4byte .LBB34 - 3164 0e57 08000000 .4byte .LBE34 - 3165 0e5b 6F0E0000 .4byte 0xe6f - 3166 0e5f 22 .uleb128 0x22 - 3167 0e60 746D7000 .ascii "tmp\000" - 3168 0e64 01 .byte 0x1 - 3169 0e65 8E .byte 0x8e - 3170 0e66 B5000000 .4byte 0xb5 - 3171 0e6a 66000000 .4byte .LLST4 - 3172 0e6e 00 .byte 0 - 3173 0e6f 23 .uleb128 0x23 - 3174 0e70 18000000 .4byte .LBB35 - 3175 0e74 1E000000 .4byte .LBE35 - 3176 0e78 22 .uleb128 0x22 - 3177 0e79 746D7000 .ascii "tmp\000" - 3178 0e7d 01 .byte 0x1 - 3179 0e7e 92 .byte 0x92 - 3180 0e7f B5000000 .4byte 0xb5 - 3181 0e83 79000000 .4byte .LLST5 - 3182 0e87 00 .byte 0 - 3183 0e88 00 .byte 0 - 3184 0e89 1D .uleb128 0x1d - 3185 0e8a D9000000 .4byte .LASF178 - 3186 0e8e 01 .byte 0x1 - 3187 0e8f 7C .byte 0x7c - 3188 0e90 01 .byte 0x1 - 3189 0e91 00000000 .4byte .LFB63 - 3190 0e95 28000000 .4byte .LFE63 - 3191 0e99 8C000000 .4byte .LLST6 - 3192 0e9d F40E0000 .4byte 0xef4 - 3193 0ea1 1F .uleb128 0x1f - 3194 0ea2 DE020000 .4byte .LASF177 - 3195 0ea6 01 .byte 0x1 - 3196 0ea7 7C .byte 0x7c - 3197 0ea8 E30B0000 .4byte 0xbe3 - 3198 0eac AC000000 .4byte .LLST7 - 3199 0eb0 20 .uleb128 0x20 - 3200 0eb1 6D736700 .ascii "msg\000" - 3201 0eb5 01 .byte 0x1 - 3202 0eb6 7D .byte 0x7d - 3203 0eb7 0D010000 .4byte 0x10d - 3204 0ebb 01 .byte 0x1 - 3205 0ebc 50 .byte 0x50 - 3206 0ebd 21 .uleb128 0x21 - 3207 0ebe 02000000 .4byte .LBB36 - 3208 0ec2 08000000 .4byte .LBE36 - 3209 0ec6 DA0E0000 .4byte 0xeda - 3210 0eca 22 .uleb128 0x22 - 3211 0ecb 746D7000 .ascii "tmp\000" - 3212 0ecf 01 .byte 0x1 - 3213 0ed0 80 .byte 0x80 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 59 - - - 3214 0ed1 B5000000 .4byte 0xb5 - 3215 0ed5 BF000000 .4byte .LLST8 - 3216 0ed9 00 .byte 0 - 3217 0eda 23 .uleb128 0x23 - 3218 0edb 18000000 .4byte .LBB37 - 3219 0edf 1E000000 .4byte .LBE37 - 3220 0ee3 22 .uleb128 0x22 - 3221 0ee4 746D7000 .ascii "tmp\000" - 3222 0ee8 01 .byte 0x1 - 3223 0ee9 84 .byte 0x84 - 3224 0eea B5000000 .4byte 0xb5 - 3225 0eee D2000000 .4byte .LLST9 - 3226 0ef2 00 .byte 0 - 3227 0ef3 00 .byte 0 - 3228 0ef4 24 .uleb128 0x24 - 3229 0ef5 EE050000 .4byte .LASF194 - 3230 0ef9 01 .byte 0x1 - 3231 0efa 41 .byte 0x41 - 3232 0efb 01 .byte 0x1 - 3233 0efc 0D010000 .4byte 0x10d - 3234 0f00 00000000 .4byte .LFB62 - 3235 0f04 AC000000 .4byte .LFE62 - 3236 0f08 E5000000 .4byte .LLST10 - 3237 0f0c 790F0000 .4byte 0xf79 - 3238 0f10 1E .uleb128 0x1e - 3239 0f11 61726700 .ascii "arg\000" - 3240 0f15 01 .byte 0x1 - 3241 0f16 41 .byte 0x41 - 3242 0f17 73000000 .4byte 0x73 - 3243 0f1b 11010000 .4byte .LLST11 - 3244 0f1f 20 .uleb128 0x20 - 3245 0f20 7800 .ascii "x\000" - 3246 0f22 01 .byte 0x1 - 3247 0f23 42 .byte 0x42 - 3248 0f24 790F0000 .4byte 0xf79 - 3249 0f28 05 .byte 0x5 - 3250 0f29 03 .byte 0x3 - 3251 0f2a 00000000 .4byte x.3441 - 3252 0f2e 20 .uleb128 0x20 - 3253 0f2f 636E7400 .ascii "cnt\000" - 3254 0f33 01 .byte 0x1 - 3255 0f34 43 .byte 0x43 - 3256 0f35 34000000 .4byte 0x34 - 3257 0f39 05 .byte 0x5 - 3258 0f3a 03 .byte 0x3 - 3259 0f3b 00000000 .4byte cnt.3442 - 3260 0f3f 22 .uleb128 0x22 - 3261 0f40 6D6500 .ascii "me\000" - 3262 0f43 01 .byte 0x1 - 3263 0f44 44 .byte 0x44 - 3264 0f45 34000000 .4byte 0x34 - 3265 0f49 11010000 .4byte .LLST11 - 3266 0f4d 25 .uleb128 0x25 - 3267 0f4e 37030000 .4byte .LASF179 - 3268 0f52 01 .byte 0x1 - 3269 0f53 45 .byte 0x45 - 3270 0f54 34000000 .4byte 0x34 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 60 - - - 3271 0f58 31010000 .4byte .LLST13 - 3272 0f5c 22 .uleb128 0x22 - 3273 0f5d 7200 .ascii "r\000" - 3274 0f5f 01 .byte 0x1 - 3275 0f60 46 .byte 0x46 - 3276 0f61 34000000 .4byte 0x34 - 3277 0f65 4F010000 .4byte .LLST14 - 3278 0f69 22 .uleb128 0x22 - 3279 0f6a 6D736700 .ascii "msg\000" - 3280 0f6e 01 .byte 0x1 - 3281 0f6f 47 .byte 0x47 - 3282 0f70 0D010000 .4byte 0x10d - 3283 0f74 64010000 .4byte .LLST15 - 3284 0f78 00 .byte 0 - 3285 0f79 0C .uleb128 0xc - 3286 0f7a 34000000 .4byte 0x34 - 3287 0f7e 26 .uleb128 0x26 - 3288 0f7f A60D0000 .4byte 0xda6 - 3289 0f83 00000000 .4byte .LFB67 - 3290 0f87 68000000 .4byte .LFE67 - 3291 0f8b 83010000 .4byte .LLST16 - 3292 0f8f D30F0000 .4byte 0xfd3 - 3293 0f93 27 .uleb128 0x27 - 3294 0f94 B30D0000 .4byte 0xdb3 - 3295 0f98 AF010000 .4byte .LLST17 - 3296 0f9c 28 .uleb128 0x28 - 3297 0f9d BC0D0000 .4byte 0xdbc - 3298 0fa1 02 .byte 0x2 - 3299 0fa2 91 .byte 0x91 - 3300 0fa3 60 .sleb128 -32 - 3301 0fa4 29 .uleb128 0x29 - 3302 0fa5 C70D0000 .4byte 0xdc7 - 3303 0fa9 D8010000 .4byte .LLST18 - 3304 0fad 2A .uleb128 0x2a - 3305 0fae A60D0000 .4byte 0xda6 - 3306 0fb2 0C000000 .4byte .LBB40 - 3307 0fb6 00000000 .4byte .Ldebug_ranges0+0 - 3308 0fba 01 .byte 0x1 - 3309 0fbb B9 .byte 0xb9 - 3310 0fbc 2B .uleb128 0x2b - 3311 0fbd 18000000 .4byte .Ldebug_ranges0+0x18 - 3312 0fc1 2C .uleb128 0x2c - 3313 0fc2 BC0D0000 .4byte 0xdbc - 3314 0fc6 2C .uleb128 0x2c - 3315 0fc7 C70D0000 .4byte 0xdc7 - 3316 0fcb 2D .uleb128 0x2d - 3317 0fcc B30D0000 .4byte 0xdb3 - 3318 0fd0 00 .byte 0 - 3319 0fd1 00 .byte 0 - 3320 0fd2 00 .byte 0 - 3321 0fd3 2E .uleb128 0x2e - 3322 0fd4 01 .byte 0x1 - 3323 0fd5 EC060000 .4byte .LASF195 - 3324 0fd9 01 .byte 0x1 - 3325 0fda CA .byte 0xca - 3326 0fdb 01 .byte 0x1 - 3327 0fdc 57000000 .4byte 0x57 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 61 - - - 3328 0fe0 00000000 .4byte .LFB68 - 3329 0fe4 E4030000 .4byte .LFE68 - 3330 0fe8 F8010000 .4byte .LLST19 - 3331 0fec FA110000 .4byte 0x11fa - 3332 0ff0 22 .uleb128 0x22 - 3333 0ff1 6900 .ascii "i\000" - 3334 0ff3 01 .byte 0x1 - 3335 0ff4 CB .byte 0xcb - 3336 0ff5 34000000 .4byte 0x34 - 3337 0ff9 24020000 .4byte .LLST20 - 3338 0ffd 25 .uleb128 0x25 - 3339 0ffe 25020000 .4byte .LASF180 - 3340 1002 01 .byte 0x1 - 3341 1003 CC .byte 0xcc - 3342 1004 F40B0000 .4byte 0xbf4 - 3343 1008 5A020000 .4byte .LLST21 - 3344 100c 25 .uleb128 0x25 - 3345 100d B3040000 .4byte .LASF181 - 3346 1011 01 .byte 0x1 - 3347 1012 CC .byte 0xcc - 3348 1013 F40B0000 .4byte 0xbf4 - 3349 1017 86020000 .4byte .LLST22 - 3350 101b 25 .uleb128 0x25 - 3351 101c E7030000 .4byte .LASF182 - 3352 1020 01 .byte 0x1 - 3353 1021 CC .byte 0xcc - 3354 1022 F40B0000 .4byte 0xbf4 - 3355 1026 B0020000 .4byte .LLST23 - 3356 102a 2F .uleb128 0x2f - 3357 102b E10D0000 .4byte 0xde1 - 3358 102f 96000000 .4byte .LBB44 - 3359 1033 AA000000 .4byte .LBE44 - 3360 1037 01 .byte 0x1 - 3361 1038 F0 .byte 0xf0 - 3362 1039 47100000 .4byte 0x1047 - 3363 103d 27 .uleb128 0x27 - 3364 103e EE0D0000 .4byte 0xdee - 3365 1042 CF020000 .4byte .LLST24 - 3366 1046 00 .byte 0 - 3367 1047 2F .uleb128 0x2f - 3368 1048 E10D0000 .4byte 0xde1 - 3369 104c B4000000 .4byte .LBB46 - 3370 1050 C8000000 .4byte .LBE46 - 3371 1054 01 .byte 0x1 - 3372 1055 F3 .byte 0xf3 - 3373 1056 64100000 .4byte 0x1064 - 3374 105a 27 .uleb128 0x27 - 3375 105b EE0D0000 .4byte 0xdee - 3376 105f E7020000 .4byte .LLST25 - 3377 1063 00 .byte 0 - 3378 1064 2F .uleb128 0x2f - 3379 1065 E10D0000 .4byte 0xde1 - 3380 1069 D2000000 .4byte .LBB48 - 3381 106d E6000000 .4byte .LBE48 - 3382 1071 01 .byte 0x1 - 3383 1072 F6 .byte 0xf6 - 3384 1073 81100000 .4byte 0x1081 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 62 - - - 3385 1077 27 .uleb128 0x27 - 3386 1078 EE0D0000 .4byte 0xdee - 3387 107c FF020000 .4byte .LLST26 - 3388 1080 00 .byte 0 - 3389 1081 2F .uleb128 0x2f - 3390 1082 E10D0000 .4byte 0xde1 - 3391 1086 F0000000 .4byte .LBB50 - 3392 108a 04010000 .4byte .LBE50 - 3393 108e 01 .byte 0x1 - 3394 108f F9 .byte 0xf9 - 3395 1090 9E100000 .4byte 0x109e - 3396 1094 27 .uleb128 0x27 - 3397 1095 EE0D0000 .4byte 0xdee - 3398 1099 17030000 .4byte .LLST27 - 3399 109d 00 .byte 0 - 3400 109e 2F .uleb128 0x2f - 3401 109f E10D0000 .4byte 0xde1 - 3402 10a3 0E010000 .4byte .LBB52 - 3403 10a7 22010000 .4byte .LBE52 - 3404 10ab 01 .byte 0x1 - 3405 10ac FD .byte 0xfd - 3406 10ad BB100000 .4byte 0x10bb - 3407 10b1 27 .uleb128 0x27 - 3408 10b2 EE0D0000 .4byte 0xdee - 3409 10b6 2F030000 .4byte .LLST28 - 3410 10ba 00 .byte 0 - 3411 10bb 30 .uleb128 0x30 - 3412 10bc E10D0000 .4byte 0xde1 - 3413 10c0 2C010000 .4byte .LBB54 - 3414 10c4 40010000 .4byte .LBE54 - 3415 10c8 01 .byte 0x1 - 3416 10c9 0101 .2byte 0x101 - 3417 10cb D9100000 .4byte 0x10d9 - 3418 10cf 27 .uleb128 0x27 - 3419 10d0 EE0D0000 .4byte 0xdee - 3420 10d4 47030000 .4byte .LLST29 - 3421 10d8 00 .byte 0 - 3422 10d9 30 .uleb128 0x30 - 3423 10da E10D0000 .4byte 0xde1 - 3424 10de 50010000 .4byte .LBB56 - 3425 10e2 64010000 .4byte .LBE56 - 3426 10e6 01 .byte 0x1 - 3427 10e7 0501 .2byte 0x105 - 3428 10e9 F7100000 .4byte 0x10f7 - 3429 10ed 27 .uleb128 0x27 - 3430 10ee EE0D0000 .4byte 0xdee - 3431 10f2 5F030000 .4byte .LLST30 - 3432 10f6 00 .byte 0 - 3433 10f7 30 .uleb128 0x30 - 3434 10f8 E10D0000 .4byte 0xde1 - 3435 10fc 7A010000 .4byte .LBB58 - 3436 1100 8E010000 .4byte .LBE58 - 3437 1104 01 .byte 0x1 - 3438 1105 0801 .2byte 0x108 - 3439 1107 15110000 .4byte 0x1115 - 3440 110b 27 .uleb128 0x27 - 3441 110c EE0D0000 .4byte 0xdee - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 63 - - - 3442 1110 77030000 .4byte .LLST31 - 3443 1114 00 .byte 0 - 3444 1115 30 .uleb128 0x30 - 3445 1116 E10D0000 .4byte 0xde1 - 3446 111a 9E010000 .4byte .LBB60 - 3447 111e B2010000 .4byte .LBE60 - 3448 1122 01 .byte 0x1 - 3449 1123 0B01 .2byte 0x10b - 3450 1125 33110000 .4byte 0x1133 - 3451 1129 27 .uleb128 0x27 - 3452 112a EE0D0000 .4byte 0xdee - 3453 112e 8F030000 .4byte .LLST32 - 3454 1132 00 .byte 0 - 3455 1133 30 .uleb128 0x30 - 3456 1134 E10D0000 .4byte 0xde1 - 3457 1138 C2010000 .4byte .LBB62 - 3458 113c D6010000 .4byte .LBE62 - 3459 1140 01 .byte 0x1 - 3460 1141 0E01 .2byte 0x10e - 3461 1143 51110000 .4byte 0x1151 - 3462 1147 27 .uleb128 0x27 - 3463 1148 EE0D0000 .4byte 0xdee - 3464 114c A7030000 .4byte .LLST33 - 3465 1150 00 .byte 0 - 3466 1151 30 .uleb128 0x30 - 3467 1152 E10D0000 .4byte 0xde1 - 3468 1156 E6010000 .4byte .LBB64 - 3469 115a FC010000 .4byte .LBE64 - 3470 115e 01 .byte 0x1 - 3471 115f 1101 .2byte 0x111 - 3472 1161 6F110000 .4byte 0x116f - 3473 1165 27 .uleb128 0x27 - 3474 1166 EE0D0000 .4byte 0xdee - 3475 116a BF030000 .4byte .LLST34 - 3476 116e 00 .byte 0 - 3477 116f 30 .uleb128 0x30 - 3478 1170 E10D0000 .4byte 0xde1 - 3479 1174 22020000 .4byte .LBB66 - 3480 1178 36020000 .4byte .LBE66 - 3481 117c 01 .byte 0x1 - 3482 117d 1801 .2byte 0x118 - 3483 117f 8D110000 .4byte 0x118d - 3484 1183 27 .uleb128 0x27 - 3485 1184 EE0D0000 .4byte 0xdee - 3486 1188 D7030000 .4byte .LLST35 - 3487 118c 00 .byte 0 - 3488 118d 30 .uleb128 0x30 - 3489 118e E10D0000 .4byte 0xde1 - 3490 1192 CC020000 .4byte .LBB68 - 3491 1196 D4020000 .4byte .LBE68 - 3492 119a 01 .byte 0x1 - 3493 119b 2401 .2byte 0x124 - 3494 119d A7110000 .4byte 0x11a7 - 3495 11a1 2D .uleb128 0x2d - 3496 11a2 EE0D0000 .4byte 0xdee - 3497 11a6 00 .byte 0 - 3498 11a7 31 .uleb128 0x31 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 64 - - - 3499 11a8 E10D0000 .4byte 0xde1 - 3500 11ac 0C030000 .4byte .LBB70 - 3501 11b0 30000000 .4byte .Ldebug_ranges0+0x30 - 3502 11b4 01 .byte 0x1 - 3503 11b5 2601 .2byte 0x126 - 3504 11b7 C1110000 .4byte 0x11c1 - 3505 11bb 2D .uleb128 0x2d - 3506 11bc EE0D0000 .4byte 0xdee - 3507 11c0 00 .byte 0 - 3508 11c1 30 .uleb128 0x30 - 3509 11c2 E10D0000 .4byte 0xde1 - 3510 11c6 42030000 .4byte .LBB76 - 3511 11ca 56030000 .4byte .LBE76 - 3512 11ce 01 .byte 0x1 - 3513 11cf 2F01 .2byte 0x12f - 3514 11d1 DF110000 .4byte 0x11df - 3515 11d5 27 .uleb128 0x27 - 3516 11d6 EE0D0000 .4byte 0xdee - 3517 11da EF030000 .4byte .LLST38 - 3518 11de 00 .byte 0 - 3519 11df 32 .uleb128 0x32 - 3520 11e0 E10D0000 .4byte 0xde1 - 3521 11e4 8E030000 .4byte .LBB78 - 3522 11e8 A2030000 .4byte .LBE78 - 3523 11ec 01 .byte 0x1 - 3524 11ed 3901 .2byte 0x139 - 3525 11ef 27 .uleb128 0x27 - 3526 11f0 EE0D0000 .4byte 0xdee - 3527 11f4 07040000 .4byte .LLST39 - 3528 11f8 00 .byte 0 - 3529 11f9 00 .byte 0 - 3530 11fa 33 .uleb128 0x33 - 3531 11fb A0060000 .4byte .LASF183 - 3532 11ff 09 .byte 0x9 - 3533 1200 6B .byte 0x6b - 3534 1201 E3030000 .4byte 0x3e3 - 3535 1205 01 .byte 0x1 - 3536 1206 01 .byte 0x1 - 3537 1207 34 .uleb128 0x34 - 3538 1208 F0040000 .4byte .LASF184 - 3539 120c 15 .byte 0x15 - 3540 120d 8C04 .2byte 0x48c - 3541 120f 15120000 .4byte 0x1215 - 3542 1213 01 .byte 0x1 - 3543 1214 01 .byte 0x1 - 3544 1215 0C .uleb128 0xc - 3545 1216 AA000000 .4byte 0xaa - 3546 121a 33 .uleb128 0x33 - 3547 121b C3000000 .4byte .LASF185 - 3548 121f 13 .byte 0x13 - 3549 1220 F4 .byte 0xf4 - 3550 1221 760B0000 .4byte 0xb76 - 3551 1225 01 .byte 0x1 - 3552 1226 01 .byte 0x1 - 3553 1227 33 .uleb128 0x33 - 3554 1228 C9000000 .4byte .LASF186 - 3555 122c 13 .byte 0x13 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 65 - - - 3556 122d F8 .byte 0xf8 - 3557 122e 760B0000 .4byte 0xb76 - 3558 1232 01 .byte 0x1 - 3559 1233 01 .byte 0x1 - 3560 1234 35 .uleb128 0x35 - 3561 1235 53443100 .ascii "SD1\000" - 3562 1239 16 .byte 0x16 - 3563 123a DB .byte 0xdb - 3564 123b 660C0000 .4byte 0xc66 - 3565 123f 01 .byte 0x1 - 3566 1240 01 .byte 0x1 - 3567 1241 36 .uleb128 0x36 - 3568 1242 B2000000 .4byte .LASF187 - 3569 1246 01 .byte 0x1 - 3570 1247 35 .byte 0x35 - 3571 1248 D6000000 .4byte 0xd6 - 3572 124c 05 .byte 0x5 - 3573 124d 03 .byte 0x3 - 3574 124e 00000000 .4byte saturated - 3575 1252 18 .uleb128 0x18 - 3576 1253 3B050000 .4byte 0x53b - 3577 1257 62120000 .4byte 0x1262 - 3578 125b 19 .uleb128 0x19 - 3579 125c 34000000 .4byte 0x34 - 3580 1260 03 .byte 0x3 - 3581 1261 00 .byte 0 - 3582 1262 20 .uleb128 0x20 - 3583 1263 6D6200 .ascii "mb\000" - 3584 1266 01 .byte 0x1 - 3585 1267 3A .byte 0x3a - 3586 1268 52120000 .4byte 0x1252 - 3587 126c 05 .byte 0x5 - 3588 126d 03 .byte 0x3 - 3589 126e 00000000 .4byte mb - 3590 1272 18 .uleb128 0x18 - 3591 1273 0D010000 .4byte 0x10d - 3592 1277 88120000 .4byte 0x1288 - 3593 127b 19 .uleb128 0x19 - 3594 127c 34000000 .4byte 0x34 - 3595 1280 03 .byte 0x3 - 3596 1281 19 .uleb128 0x19 - 3597 1282 34000000 .4byte 0x34 - 3598 1286 03 .byte 0x3 - 3599 1287 00 .byte 0 - 3600 1288 20 .uleb128 0x20 - 3601 1289 6200 .ascii "b\000" - 3602 128b 01 .byte 0x1 - 3603 128c 3B .byte 0x3b - 3604 128d 72120000 .4byte 0x1272 - 3605 1291 05 .byte 0x5 - 3606 1292 03 .byte 0x3 - 3607 1293 00000000 .4byte b - 3608 1297 18 .uleb128 0x18 - 3609 1298 47030000 .4byte 0x347 - 3610 129c AD120000 .4byte 0x12ad - 3611 12a0 19 .uleb128 0x19 - 3612 12a1 34000000 .4byte 0x34 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 66 - - - 3613 12a5 03 .byte 0x3 - 3614 12a6 19 .uleb128 0x19 - 3615 12a7 34000000 .4byte 0x34 - 3616 12ab 23 .byte 0x23 - 3617 12ac 00 .byte 0 - 3618 12ad 36 .uleb128 0x36 - 3619 12ae FB050000 .4byte .LASF188 - 3620 12b2 01 .byte 0x1 - 3621 12b3 40 .byte 0x40 - 3622 12b4 97120000 .4byte 0x1297 - 3623 12b8 05 .byte 0x5 - 3624 12b9 03 .byte 0x3 - 3625 12ba 00000000 .4byte waWorkerThread - 3626 12be 36 .uleb128 0x36 - 3627 12bf 63020000 .4byte .LASF189 - 3628 12c3 01 .byte 0x1 - 3629 12c4 98 .byte 0x98 - 3630 12c5 350C0000 .4byte 0xc35 - 3631 12c9 05 .byte 0x5 - 3632 12ca 03 .byte 0x3 - 3633 12cb 00000000 .4byte gpt2cfg - 3634 12cf 36 .uleb128 0x36 - 3635 12d0 B6010000 .4byte .LASF190 - 3636 12d4 01 .byte 0x1 - 3637 12d5 A0 .byte 0xa0 - 3638 12d6 350C0000 .4byte 0xc35 - 3639 12da 05 .byte 0x5 - 3640 12db 03 .byte 0x3 - 3641 12dc 00000000 .4byte gpt3cfg - 3642 12e0 33 .uleb128 0x33 - 3643 12e1 A0060000 .4byte .LASF183 - 3644 12e5 09 .byte 0x9 - 3645 12e6 6B .byte 0x6b - 3646 12e7 E3030000 .4byte 0x3e3 - 3647 12eb 01 .byte 0x1 - 3648 12ec 01 .byte 0x1 - 3649 12ed 34 .uleb128 0x34 - 3650 12ee F0040000 .4byte .LASF184 - 3651 12f2 15 .byte 0x15 - 3652 12f3 8C04 .2byte 0x48c - 3653 12f5 15120000 .4byte 0x1215 - 3654 12f9 01 .byte 0x1 - 3655 12fa 01 .byte 0x1 - 3656 12fb 33 .uleb128 0x33 - 3657 12fc C3000000 .4byte .LASF185 - 3658 1300 13 .byte 0x13 - 3659 1301 F4 .byte 0xf4 - 3660 1302 760B0000 .4byte 0xb76 - 3661 1306 01 .byte 0x1 - 3662 1307 01 .byte 0x1 - 3663 1308 33 .uleb128 0x33 - 3664 1309 C9000000 .4byte .LASF186 - 3665 130d 13 .byte 0x13 - 3666 130e F8 .byte 0xf8 - 3667 130f 760B0000 .4byte 0xb76 - 3668 1313 01 .byte 0x1 - 3669 1314 01 .byte 0x1 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 67 - - - 3670 1315 35 .uleb128 0x35 - 3671 1316 53443100 .ascii "SD1\000" - 3672 131a 16 .byte 0x16 - 3673 131b DB .byte 0xdb - 3674 131c 660C0000 .4byte 0xc66 - 3675 1320 01 .byte 0x1 - 3676 1321 01 .byte 0x1 - 3677 1322 00 .byte 0 - 3678 .section .debug_abbrev,"",%progbits - 3679 .Ldebug_abbrev0: - 3680 0000 01 .uleb128 0x1 - 3681 0001 11 .uleb128 0x11 - 3682 0002 01 .byte 0x1 - 3683 0003 25 .uleb128 0x25 - 3684 0004 0E .uleb128 0xe - 3685 0005 13 .uleb128 0x13 - 3686 0006 0B .uleb128 0xb - 3687 0007 03 .uleb128 0x3 - 3688 0008 0E .uleb128 0xe - 3689 0009 1B .uleb128 0x1b - 3690 000a 0E .uleb128 0xe - 3691 000b 11 .uleb128 0x11 - 3692 000c 01 .uleb128 0x1 - 3693 000d 52 .uleb128 0x52 - 3694 000e 01 .uleb128 0x1 - 3695 000f 55 .uleb128 0x55 - 3696 0010 06 .uleb128 0x6 - 3697 0011 10 .uleb128 0x10 - 3698 0012 06 .uleb128 0x6 - 3699 0013 00 .byte 0 - 3700 0014 00 .byte 0 - 3701 0015 02 .uleb128 0x2 - 3702 0016 16 .uleb128 0x16 - 3703 0017 00 .byte 0 - 3704 0018 03 .uleb128 0x3 - 3705 0019 0E .uleb128 0xe - 3706 001a 3A .uleb128 0x3a - 3707 001b 0B .uleb128 0xb - 3708 001c 3B .uleb128 0x3b - 3709 001d 0B .uleb128 0xb - 3710 001e 49 .uleb128 0x49 - 3711 001f 13 .uleb128 0x13 - 3712 0020 00 .byte 0 - 3713 0021 00 .byte 0 - 3714 0022 03 .uleb128 0x3 - 3715 0023 24 .uleb128 0x24 - 3716 0024 00 .byte 0 - 3717 0025 0B .uleb128 0xb - 3718 0026 0B .uleb128 0xb - 3719 0027 3E .uleb128 0x3e - 3720 0028 0B .uleb128 0xb - 3721 0029 03 .uleb128 0x3 - 3722 002a 0E .uleb128 0xe - 3723 002b 00 .byte 0 - 3724 002c 00 .byte 0 - 3725 002d 04 .uleb128 0x4 - 3726 002e 24 .uleb128 0x24 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 68 - - - 3727 002f 00 .byte 0 - 3728 0030 0B .uleb128 0xb - 3729 0031 0B .uleb128 0xb - 3730 0032 3E .uleb128 0x3e - 3731 0033 0B .uleb128 0xb - 3732 0034 03 .uleb128 0x3 - 3733 0035 08 .uleb128 0x8 - 3734 0036 00 .byte 0 - 3735 0037 00 .byte 0 - 3736 0038 05 .uleb128 0x5 - 3737 0039 0F .uleb128 0xf - 3738 003a 00 .byte 0 - 3739 003b 0B .uleb128 0xb - 3740 003c 0B .uleb128 0xb - 3741 003d 00 .byte 0 - 3742 003e 00 .byte 0 - 3743 003f 06 .uleb128 0x6 - 3744 0040 0F .uleb128 0xf - 3745 0041 00 .byte 0 - 3746 0042 0B .uleb128 0xb - 3747 0043 0B .uleb128 0xb - 3748 0044 49 .uleb128 0x49 - 3749 0045 13 .uleb128 0x13 - 3750 0046 00 .byte 0 - 3751 0047 00 .byte 0 - 3752 0048 07 .uleb128 0x7 - 3753 0049 26 .uleb128 0x26 - 3754 004a 00 .byte 0 - 3755 004b 49 .uleb128 0x49 - 3756 004c 13 .uleb128 0x13 - 3757 004d 00 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00 .byte 0 - 3933 00fd 16 .uleb128 0x16 - 3934 00fe 04 .uleb128 0x4 - 3935 00ff 01 .byte 0x1 - 3936 0100 0B .uleb128 0xb - 3937 0101 0B .uleb128 0xb - 3938 0102 3A .uleb128 0x3a - 3939 0103 0B .uleb128 0xb - 3940 0104 3B .uleb128 0x3b - 3941 0105 0B .uleb128 0xb - 3942 0106 01 .uleb128 0x1 - 3943 0107 13 .uleb128 0x13 - 3944 0108 00 .byte 0 - 3945 0109 00 .byte 0 - 3946 010a 17 .uleb128 0x17 - 3947 010b 28 .uleb128 0x28 - 3948 010c 00 .byte 0 - 3949 010d 03 .uleb128 0x3 - 3950 010e 0E .uleb128 0xe - 3951 010f 1C .uleb128 0x1c - 3952 0110 0D .uleb128 0xd - 3953 0111 00 .byte 0 - 3954 0112 00 .byte 0 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 72 - - - 3955 0113 18 .uleb128 0x18 - 3956 0114 01 .uleb128 0x1 - 3957 0115 01 .byte 0x1 - 3958 0116 49 .uleb128 0x49 - 3959 0117 13 .uleb128 0x13 - 3960 0118 01 .uleb128 0x1 - 3961 0119 13 .uleb128 0x13 - 3962 011a 00 .byte 0 - 3963 011b 00 .byte 0 - 3964 011c 19 .uleb128 0x19 - 3965 011d 21 .uleb128 0x21 - 3966 011e 00 .byte 0 - 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0187 08 .uleb128 0x8 - 4072 0188 3A .uleb128 0x3a - 4073 0189 0B .uleb128 0xb - 4074 018a 3B .uleb128 0x3b - 4075 018b 0B .uleb128 0xb - 4076 018c 49 .uleb128 0x49 - 4077 018d 13 .uleb128 0x13 - 4078 018e 02 .uleb128 0x2 - 4079 018f 0A .uleb128 0xa - 4080 0190 00 .byte 0 - 4081 0191 00 .byte 0 - 4082 0192 21 .uleb128 0x21 - 4083 0193 0B .uleb128 0xb - 4084 0194 01 .byte 0x1 - 4085 0195 11 .uleb128 0x11 - 4086 0196 01 .uleb128 0x1 - 4087 0197 12 .uleb128 0x12 - 4088 0198 01 .uleb128 0x1 - 4089 0199 01 .uleb128 0x1 - 4090 019a 13 .uleb128 0x13 - 4091 019b 00 .byte 0 - 4092 019c 00 .byte 0 - 4093 019d 22 .uleb128 0x22 - 4094 019e 34 .uleb128 0x34 - 4095 019f 00 .byte 0 - 4096 01a0 03 .uleb128 0x3 - 4097 01a1 08 .uleb128 0x8 - 4098 01a2 3A .uleb128 0x3a - 4099 01a3 0B .uleb128 0xb - 4100 01a4 3B .uleb128 0x3b - 4101 01a5 0B .uleb128 0xb - 4102 01a6 49 .uleb128 0x49 - 4103 01a7 13 .uleb128 0x13 - 4104 01a8 02 .uleb128 0x2 - 4105 01a9 06 .uleb128 0x6 - 4106 01aa 00 .byte 0 - 4107 01ab 00 .byte 0 - 4108 01ac 23 .uleb128 0x23 - 4109 01ad 0B .uleb128 0xb - 4110 01ae 01 .byte 0x1 - 4111 01af 11 .uleb128 0x11 - 4112 01b0 01 .uleb128 0x1 - 4113 01b1 12 .uleb128 0x12 - 4114 01b2 01 .uleb128 0x1 - 4115 01b3 00 .byte 0 - 4116 01b4 00 .byte 0 - 4117 01b5 24 .uleb128 0x24 - 4118 01b6 2E .uleb128 0x2e - 4119 01b7 01 .byte 0x1 - 4120 01b8 03 .uleb128 0x3 - 4121 01b9 0E .uleb128 0xe - 4122 01ba 3A .uleb128 0x3a - 4123 01bb 0B .uleb128 0xb - 4124 01bc 3B .uleb128 0x3b - 4125 01bd 0B .uleb128 0xb - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 75 - - - 4126 01be 27 .uleb128 0x27 - 4127 01bf 0C .uleb128 0xc - 4128 01c0 49 .uleb128 0x49 - 4129 01c1 13 .uleb128 0x13 - 4130 01c2 11 .uleb128 0x11 - 4131 01c3 01 .uleb128 0x1 - 4132 01c4 12 .uleb128 0x12 - 4133 01c5 01 .uleb128 0x1 - 4134 01c6 40 .uleb128 0x40 - 4135 01c7 06 .uleb128 0x6 - 4136 01c8 01 .uleb128 0x1 - 4137 01c9 13 .uleb128 0x13 - 4138 01ca 00 .byte 0 - 4139 01cb 00 .byte 0 - 4140 01cc 25 .uleb128 0x25 - 4141 01cd 34 .uleb128 0x34 - 4142 01ce 00 .byte 0 - 4143 01cf 03 .uleb128 0x3 - 4144 01d0 0E .uleb128 0xe - 4145 01d1 3A .uleb128 0x3a - 4146 01d2 0B .uleb128 0xb - 4147 01d3 3B .uleb128 0x3b - 4148 01d4 0B .uleb128 0xb - 4149 01d5 49 .uleb128 0x49 - 4150 01d6 13 .uleb128 0x13 - 4151 01d7 02 .uleb128 0x2 - 4152 01d8 06 .uleb128 0x6 - 4153 01d9 00 .byte 0 - 4154 01da 00 .byte 0 - 4155 01db 26 .uleb128 0x26 - 4156 01dc 2E .uleb128 0x2e - 4157 01dd 01 .byte 0x1 - 4158 01de 31 .uleb128 0x31 - 4159 01df 13 .uleb128 0x13 - 4160 01e0 11 .uleb128 0x11 - 4161 01e1 01 .uleb128 0x1 - 4162 01e2 12 .uleb128 0x12 - 4163 01e3 01 .uleb128 0x1 - 4164 01e4 40 .uleb128 0x40 - 4165 01e5 06 .uleb128 0x6 - 4166 01e6 01 .uleb128 0x1 - 4167 01e7 13 .uleb128 0x13 - 4168 01e8 00 .byte 0 - 4169 01e9 00 .byte 0 - 4170 01ea 27 .uleb128 0x27 - 4171 01eb 05 .uleb128 0x5 - 4172 01ec 00 .byte 0 - 4173 01ed 31 .uleb128 0x31 - 4174 01ee 13 .uleb128 0x13 - 4175 01ef 02 .uleb128 0x2 - 4176 01f0 06 .uleb128 0x6 - 4177 01f1 00 .byte 0 - 4178 01f2 00 .byte 0 - 4179 01f3 28 .uleb128 0x28 - 4180 01f4 34 .uleb128 0x34 - 4181 01f5 00 .byte 0 - 4182 01f6 31 .uleb128 0x31 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 76 - - - 4183 01f7 13 .uleb128 0x13 - 4184 01f8 02 .uleb128 0x2 - 4185 01f9 0A .uleb128 0xa - 4186 01fa 00 .byte 0 - 4187 01fb 00 .byte 0 - 4188 01fc 29 .uleb128 0x29 - 4189 01fd 34 .uleb128 0x34 - 4190 01fe 00 .byte 0 - 4191 01ff 31 .uleb128 0x31 - 4192 0200 13 .uleb128 0x13 - 4193 0201 02 .uleb128 0x2 - 4194 0202 06 .uleb128 0x6 - 4195 0203 00 .byte 0 - 4196 0204 00 .byte 0 - 4197 0205 2A .uleb128 0x2a - 4198 0206 1D .uleb128 0x1d - 4199 0207 01 .byte 0x1 - 4200 0208 31 .uleb128 0x31 - 4201 0209 13 .uleb128 0x13 - 4202 020a 52 .uleb128 0x52 - 4203 020b 01 .uleb128 0x1 - 4204 020c 55 .uleb128 0x55 - 4205 020d 06 .uleb128 0x6 - 4206 020e 58 .uleb128 0x58 - 4207 020f 0B .uleb128 0xb - 4208 0210 59 .uleb128 0x59 - 4209 0211 0B .uleb128 0xb - 4210 0212 00 .byte 0 - 4211 0213 00 .byte 0 - 4212 0214 2B .uleb128 0x2b - 4213 0215 0B .uleb128 0xb - 4214 0216 01 .byte 0x1 - 4215 0217 55 .uleb128 0x55 - 4216 0218 06 .uleb128 0x6 - 4217 0219 00 .byte 0 - 4218 021a 00 .byte 0 - 4219 021b 2C .uleb128 0x2c - 4220 021c 34 .uleb128 0x34 - 4221 021d 00 .byte 0 - 4222 021e 31 .uleb128 0x31 - 4223 021f 13 .uleb128 0x13 - 4224 0220 00 .byte 0 - 4225 0221 00 .byte 0 - 4226 0222 2D .uleb128 0x2d - 4227 0223 05 .uleb128 0x5 - 4228 0224 00 .byte 0 - 4229 0225 31 .uleb128 0x31 - 4230 0226 13 .uleb128 0x13 - 4231 0227 00 .byte 0 - 4232 0228 00 .byte 0 - 4233 0229 2E .uleb128 0x2e - 4234 022a 2E .uleb128 0x2e - 4235 022b 01 .byte 0x1 - 4236 022c 3F .uleb128 0x3f - 4237 022d 0C .uleb128 0xc - 4238 022e 03 .uleb128 0x3 - 4239 022f 0E .uleb128 0xe - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 77 - - - 4240 0230 3A .uleb128 0x3a - 4241 0231 0B .uleb128 0xb - 4242 0232 3B .uleb128 0x3b - 4243 0233 0B .uleb128 0xb - 4244 0234 27 .uleb128 0x27 - 4245 0235 0C .uleb128 0xc - 4246 0236 49 .uleb128 0x49 - 4247 0237 13 .uleb128 0x13 - 4248 0238 11 .uleb128 0x11 - 4249 0239 01 .uleb128 0x1 - 4250 023a 12 .uleb128 0x12 - 4251 023b 01 .uleb128 0x1 - 4252 023c 40 .uleb128 0x40 - 4253 023d 06 .uleb128 0x6 - 4254 023e 01 .uleb128 0x1 - 4255 023f 13 .uleb128 0x13 - 4256 0240 00 .byte 0 - 4257 0241 00 .byte 0 - 4258 0242 2F .uleb128 0x2f - 4259 0243 1D .uleb128 0x1d - 4260 0244 01 .byte 0x1 - 4261 0245 31 .uleb128 0x31 - 4262 0246 13 .uleb128 0x13 - 4263 0247 11 .uleb128 0x11 - 4264 0248 01 .uleb128 0x1 - 4265 0249 12 .uleb128 0x12 - 4266 024a 01 .uleb128 0x1 - 4267 024b 58 .uleb128 0x58 - 4268 024c 0B .uleb128 0xb - 4269 024d 59 .uleb128 0x59 - 4270 024e 0B .uleb128 0xb - 4271 024f 01 .uleb128 0x1 - 4272 0250 13 .uleb128 0x13 - 4273 0251 00 .byte 0 - 4274 0252 00 .byte 0 - 4275 0253 30 .uleb128 0x30 - 4276 0254 1D .uleb128 0x1d - 4277 0255 01 .byte 0x1 - 4278 0256 31 .uleb128 0x31 - 4279 0257 13 .uleb128 0x13 - 4280 0258 11 .uleb128 0x11 - 4281 0259 01 .uleb128 0x1 - 4282 025a 12 .uleb128 0x12 - 4283 025b 01 .uleb128 0x1 - 4284 025c 58 .uleb128 0x58 - 4285 025d 0B .uleb128 0xb - 4286 025e 59 .uleb128 0x59 - 4287 025f 05 .uleb128 0x5 - 4288 0260 01 .uleb128 0x1 - 4289 0261 13 .uleb128 0x13 - 4290 0262 00 .byte 0 - 4291 0263 00 .byte 0 - 4292 0264 31 .uleb128 0x31 - 4293 0265 1D .uleb128 0x1d - 4294 0266 01 .byte 0x1 - 4295 0267 31 .uleb128 0x31 - 4296 0268 13 .uleb128 0x13 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 78 - - - 4297 0269 52 .uleb128 0x52 - 4298 026a 01 .uleb128 0x1 - 4299 026b 55 .uleb128 0x55 - 4300 026c 06 .uleb128 0x6 - 4301 026d 58 .uleb128 0x58 - 4302 026e 0B .uleb128 0xb - 4303 026f 59 .uleb128 0x59 - 4304 0270 05 .uleb128 0x5 - 4305 0271 01 .uleb128 0x1 - 4306 0272 13 .uleb128 0x13 - 4307 0273 00 .byte 0 - 4308 0274 00 .byte 0 - 4309 0275 32 .uleb128 0x32 - 4310 0276 1D .uleb128 0x1d - 4311 0277 01 .byte 0x1 - 4312 0278 31 .uleb128 0x31 - 4313 0279 13 .uleb128 0x13 - 4314 027a 11 .uleb128 0x11 - 4315 027b 01 .uleb128 0x1 - 4316 027c 12 .uleb128 0x12 - 4317 027d 01 .uleb128 0x1 - 4318 027e 58 .uleb128 0x58 - 4319 027f 0B .uleb128 0xb - 4320 0280 59 .uleb128 0x59 - 4321 0281 05 .uleb128 0x5 - 4322 0282 00 .byte 0 - 4323 0283 00 .byte 0 - 4324 0284 33 .uleb128 0x33 - 4325 0285 34 .uleb128 0x34 - 4326 0286 00 .byte 0 - 4327 0287 03 .uleb128 0x3 - 4328 0288 0E .uleb128 0xe - 4329 0289 3A .uleb128 0x3a - 4330 028a 0B .uleb128 0xb - 4331 028b 3B .uleb128 0x3b - 4332 028c 0B .uleb128 0xb - 4333 028d 49 .uleb128 0x49 - 4334 028e 13 .uleb128 0x13 - 4335 028f 3F .uleb128 0x3f - 4336 0290 0C .uleb128 0xc - 4337 0291 3C .uleb128 0x3c - 4338 0292 0C .uleb128 0xc - 4339 0293 00 .byte 0 - 4340 0294 00 .byte 0 - 4341 0295 34 .uleb128 0x34 - 4342 0296 34 .uleb128 0x34 - 4343 0297 00 .byte 0 - 4344 0298 03 .uleb128 0x3 - 4345 0299 0E .uleb128 0xe - 4346 029a 3A .uleb128 0x3a - 4347 029b 0B .uleb128 0xb - 4348 029c 3B .uleb128 0x3b - 4349 029d 05 .uleb128 0x5 - 4350 029e 49 .uleb128 0x49 - 4351 029f 13 .uleb128 0x13 - 4352 02a0 3F .uleb128 0x3f - 4353 02a1 0C .uleb128 0xc - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 79 - - - 4354 02a2 3C .uleb128 0x3c - 4355 02a3 0C .uleb128 0xc - 4356 02a4 00 .byte 0 - 4357 02a5 00 .byte 0 - 4358 02a6 35 .uleb128 0x35 - 4359 02a7 34 .uleb128 0x34 - 4360 02a8 00 .byte 0 - 4361 02a9 03 .uleb128 0x3 - 4362 02aa 08 .uleb128 0x8 - 4363 02ab 3A .uleb128 0x3a - 4364 02ac 0B .uleb128 0xb - 4365 02ad 3B .uleb128 0x3b - 4366 02ae 0B .uleb128 0xb - 4367 02af 49 .uleb128 0x49 - 4368 02b0 13 .uleb128 0x13 - 4369 02b1 3F .uleb128 0x3f - 4370 02b2 0C .uleb128 0xc - 4371 02b3 3C .uleb128 0x3c - 4372 02b4 0C .uleb128 0xc - 4373 02b5 00 .byte 0 - 4374 02b6 00 .byte 0 - 4375 02b7 36 .uleb128 0x36 - 4376 02b8 34 .uleb128 0x34 - 4377 02b9 00 .byte 0 - 4378 02ba 03 .uleb128 0x3 - 4379 02bb 0E .uleb128 0xe - 4380 02bc 3A .uleb128 0x3a - 4381 02bd 0B .uleb128 0xb - 4382 02be 3B .uleb128 0x3b - 4383 02bf 0B .uleb128 0xb - 4384 02c0 49 .uleb128 0x49 - 4385 02c1 13 .uleb128 0x13 - 4386 02c2 02 .uleb128 0x2 - 4387 02c3 0A .uleb128 0xa - 4388 02c4 00 .byte 0 - 4389 02c5 00 .byte 0 - 4390 02c6 00 .byte 0 - 4391 .section .debug_loc,"",%progbits - 4392 .Ldebug_loc0: - 4393 .LLST0: - 4394 0000 00000000 .4byte .LFB66 - 4395 0004 02000000 .4byte .LCFI0 - 4396 0008 0200 .2byte 0x2 - 4397 000a 7D .byte 0x7d - 4398 000b 00 .sleb128 0 - 4399 000c 02000000 .4byte .LCFI0 - 4400 0010 38000000 .4byte .LFE66 - 4401 0014 0200 .2byte 0x2 - 4402 0016 7D .byte 0x7d - 4403 0017 10 .sleb128 16 - 4404 0018 00000000 .4byte 0 - 4405 001c 00000000 .4byte 0 - 4406 .LLST1: - 4407 0020 00000000 .4byte .LVL0 - 4408 0024 0A000000 .4byte .LVL1 - 4409 0028 0100 .2byte 0x1 - 4410 002a 50 .byte 0x50 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 80 - - - 4411 002b 00000000 .4byte 0 - 4412 002f 00000000 .4byte 0 - 4413 .LLST2: - 4414 0033 00000000 .4byte .LFB64 - 4415 0037 02000000 .4byte .LCFI1 - 4416 003b 0200 .2byte 0x2 - 4417 003d 7D .byte 0x7d - 4418 003e 00 .sleb128 0 - 4419 003f 02000000 .4byte .LCFI1 - 4420 0043 28000000 .4byte .LFE64 - 4421 0047 0200 .2byte 0x2 - 4422 0049 7D .byte 0x7d - 4423 004a 08 .sleb128 8 - 4424 004b 00000000 .4byte 0 - 4425 004f 00000000 .4byte 0 - 4426 .LLST3: - 4427 0053 00000000 .4byte .LVL2 - 4428 0057 0A000000 .4byte .LVL5 - 4429 005b 0100 .2byte 0x1 - 4430 005d 50 .byte 0x50 - 4431 005e 00000000 .4byte 0 - 4432 0062 00000000 .4byte 0 - 4433 .LLST4: - 4434 0066 08000000 .4byte .LVL4 - 4435 006a 0F000000 .4byte .LVL6-1 - 4436 006e 0100 .2byte 0x1 - 4437 0070 53 .byte 0x53 - 4438 0071 00000000 .4byte 0 - 4439 0075 00000000 .4byte 0 - 4440 .LLST5: - 4441 0079 1E000000 .4byte .LVL8 - 4442 007d 28000000 .4byte .LFE64 - 4443 0081 0100 .2byte 0x1 - 4444 0083 53 .byte 0x53 - 4445 0084 00000000 .4byte 0 - 4446 0088 00000000 .4byte 0 - 4447 .LLST6: - 4448 008c 00000000 .4byte .LFB63 - 4449 0090 02000000 .4byte .LCFI2 - 4450 0094 0200 .2byte 0x2 - 4451 0096 7D .byte 0x7d - 4452 0097 00 .sleb128 0 - 4453 0098 02000000 .4byte .LCFI2 - 4454 009c 28000000 .4byte .LFE63 - 4455 00a0 0200 .2byte 0x2 - 4456 00a2 7D .byte 0x7d - 4457 00a3 08 .sleb128 8 - 4458 00a4 00000000 .4byte 0 - 4459 00a8 00000000 .4byte 0 - 4460 .LLST7: - 4461 00ac 00000000 .4byte .LVL9 - 4462 00b0 0A000000 .4byte .LVL12 - 4463 00b4 0100 .2byte 0x1 - 4464 00b6 50 .byte 0x50 - 4465 00b7 00000000 .4byte 0 - 4466 00bb 00000000 .4byte 0 - 4467 .LLST8: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 81 - - - 4468 00bf 08000000 .4byte .LVL11 - 4469 00c3 0F000000 .4byte .LVL13-1 - 4470 00c7 0100 .2byte 0x1 - 4471 00c9 53 .byte 0x53 - 4472 00ca 00000000 .4byte 0 - 4473 00ce 00000000 .4byte 0 - 4474 .LLST9: - 4475 00d2 1E000000 .4byte .LVL15 - 4476 00d6 28000000 .4byte .LFE63 - 4477 00da 0100 .2byte 0x1 - 4478 00dc 53 .byte 0x53 - 4479 00dd 00000000 .4byte 0 - 4480 00e1 00000000 .4byte 0 - 4481 .LLST10: - 4482 00e5 00000000 .4byte .LFB62 - 4483 00e9 04000000 .4byte .LCFI3 - 4484 00ed 0200 .2byte 0x2 - 4485 00ef 7D .byte 0x7d - 4486 00f0 00 .sleb128 0 - 4487 00f1 04000000 .4byte .LCFI3 - 4488 00f5 18000000 .4byte .LCFI4 - 4489 00f9 0200 .2byte 0x2 - 4490 00fb 7D .byte 0x7d - 4491 00fc 24 .sleb128 36 - 4492 00fd 18000000 .4byte .LCFI4 - 4493 0101 AC000000 .4byte .LFE62 - 4494 0105 0200 .2byte 0x2 - 4495 0107 7D .byte 0x7d - 4496 0108 30 .sleb128 48 - 4497 0109 00000000 .4byte 0 - 4498 010d 00000000 .4byte 0 - 4499 .LLST11: - 4500 0111 00000000 .4byte .LVL16 - 4501 0115 2A000000 .4byte .LVL17 - 4502 0119 0100 .2byte 0x1 - 4503 011b 50 .byte 0x50 - 4504 011c 2A000000 .4byte .LVL17 - 4505 0120 AC000000 .4byte .LFE62 - 4506 0124 0300 .2byte 0x3 - 4507 0126 79 .byte 0x79 - 4508 0127 01 .sleb128 1 - 4509 0128 9F .byte 0x9f - 4510 0129 00000000 .4byte 0 - 4511 012d 00000000 .4byte 0 - 4512 .LLST13: - 4513 0131 4E000000 .4byte .LVL21 - 4514 0135 54000000 .4byte .LVL22 - 4515 0139 0100 .2byte 0x1 - 4516 013b 53 .byte 0x53 - 4517 013c 76000000 .4byte .LVL23 - 4518 0140 7A000000 .4byte .LVL24 - 4519 0144 0100 .2byte 0x1 - 4520 0146 53 .byte 0x53 - 4521 0147 00000000 .4byte 0 - 4522 014b 00000000 .4byte 0 - 4523 .LLST14: - 4524 014f 36000000 .4byte .LVL19 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 82 - - - 4525 0153 3A000000 .4byte .LVL20 - 4526 0157 0300 .2byte 0x3 - 4527 0159 75 .byte 0x75 - 4528 015a 7F .sleb128 -1 - 4529 015b 9F .byte 0x9f - 4530 015c 00000000 .4byte 0 - 4531 0160 00000000 .4byte 0 - 4532 .LLST15: - 4533 0164 2A000000 .4byte .LVL17 - 4534 0168 2C000000 .4byte .LVL18 - 4535 016c 0100 .2byte 0x1 - 4536 016e 50 .byte 0x50 - 4537 016f 2C000000 .4byte .LVL18 - 4538 0173 AC000000 .4byte .LFE62 - 4539 0177 0200 .2byte 0x2 - 4540 0179 91 .byte 0x91 - 4541 017a 54 .sleb128 -44 - 4542 017b 00000000 .4byte 0 - 4543 017f 00000000 .4byte 0 - 4544 .LLST16: - 4545 0183 00000000 .4byte .LFB67 - 4546 0187 02000000 .4byte .LCFI5 - 4547 018b 0200 .2byte 0x2 - 4548 018d 7D .byte 0x7d - 4549 018e 00 .sleb128 0 - 4550 018f 02000000 .4byte .LCFI5 - 4551 0193 04000000 .4byte .LCFI6 - 4552 0197 0200 .2byte 0x2 - 4553 0199 7D .byte 0x7d - 4554 019a 10 .sleb128 16 - 4555 019b 04000000 .4byte .LCFI6 - 4556 019f 68000000 .4byte .LFE67 - 4557 01a3 0200 .2byte 0x2 - 4558 01a5 7D .byte 0x7d - 4559 01a6 20 .sleb128 32 - 4560 01a7 00000000 .4byte 0 - 4561 01ab 00000000 .4byte 0 - 4562 .LLST17: - 4563 01af 00000000 .4byte .LVL25 - 4564 01b3 14000000 .4byte .LVL26 - 4565 01b7 0100 .2byte 0x1 - 4566 01b9 50 .byte 0x50 - 4567 01ba 2C000000 .4byte .LVL27 - 4568 01be 3A000000 .4byte .LVL29 - 4569 01c2 0100 .2byte 0x1 - 4570 01c4 53 .byte 0x53 - 4571 01c5 52000000 .4byte .LVL30 - 4572 01c9 54000000 .4byte .LVL31 - 4573 01cd 0100 .2byte 0x1 - 4574 01cf 50 .byte 0x50 - 4575 01d0 00000000 .4byte 0 - 4576 01d4 00000000 .4byte 0 - 4577 .LLST18: - 4578 01d8 2C000000 .4byte .LVL27 - 4579 01dc 38000000 .4byte .LVL28 - 4580 01e0 0100 .2byte 0x1 - 4581 01e2 54 .byte 0x54 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 83 - - - 4582 01e3 38000000 .4byte .LVL28 - 4583 01e7 3A000000 .4byte .LVL29 - 4584 01eb 0300 .2byte 0x3 - 4585 01ed 74 .byte 0x74 - 4586 01ee 01 .sleb128 1 - 4587 01ef 9F .byte 0x9f - 4588 01f0 00000000 .4byte 0 - 4589 01f4 00000000 .4byte 0 - 4590 .LLST19: - 4591 01f8 00000000 .4byte .LFB68 - 4592 01fc 04000000 .4byte .LCFI7 - 4593 0200 0200 .2byte 0x2 - 4594 0202 7D .byte 0x7d - 4595 0203 00 .sleb128 0 - 4596 0204 04000000 .4byte .LCFI7 - 4597 0208 06000000 .4byte .LCFI8 - 4598 020c 0200 .2byte 0x2 - 4599 020e 7D .byte 0x7d - 4600 020f 20 .sleb128 32 - 4601 0210 06000000 .4byte .LCFI8 - 4602 0214 E4030000 .4byte .LFE68 - 4603 0218 0200 .2byte 0x2 - 4604 021a 7D .byte 0x7d - 4605 021b 30 .sleb128 48 - 4606 021c 00000000 .4byte 0 - 4607 0220 00000000 .4byte 0 - 4608 .LLST20: - 4609 0224 4A000000 .4byte .LVL32 - 4610 0228 52000000 .4byte .LVL33 - 4611 022c 0200 .2byte 0x2 - 4612 022e 30 .byte 0x30 - 4613 022f 9F .byte 0x9f - 4614 0230 74000000 .4byte .LVL34 - 4615 0234 8C000000 .4byte .LVL35 - 4616 0238 0100 .2byte 0x1 - 4617 023a 54 .byte 0x54 - 4618 023b 0E020000 .4byte .LVL58 - 4619 023f 1E020000 .4byte .LVL59 - 4620 0243 0200 .2byte 0x2 - 4621 0245 31 .byte 0x31 - 4622 0246 9F .byte 0x9f - 4623 0247 7A030000 .4byte .LVL72 - 4624 024b E4030000 .4byte .LFE68 - 4625 024f 0100 .2byte 0x1 - 4626 0251 59 .byte 0x59 - 4627 0252 00000000 .4byte 0 - 4628 0256 00000000 .4byte 0 - 4629 .LLST21: - 4630 025a 4E020000 .4byte .LVL61 - 4631 025e CC020000 .4byte .LVL62 - 4632 0262 0400 .2byte 0x4 - 4633 0264 0A .byte 0xa - 4634 0265 D007 .2byte 0x7d0 - 4635 0267 9F .byte 0x9f - 4636 0268 DE020000 .4byte .LVL64 - 4637 026c E2020000 .4byte .LVL65 - 4638 0270 0100 .2byte 0x1 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 84 - - - 4639 0272 56 .byte 0x56 - 4640 0273 2E030000 .4byte .LVL68 - 4641 0277 32030000 .4byte .LVL69 - 4642 027b 0100 .2byte 0x1 - 4643 027d 56 .byte 0x56 - 4644 027e 00000000 .4byte 0 - 4645 0282 00000000 .4byte 0 - 4646 .LLST22: - 4647 0286 4E020000 .4byte .LVL61 - 4648 028a CC020000 .4byte .LVL62 - 4649 028e 0200 .2byte 0x2 - 4650 0290 30 .byte 0x30 - 4651 0291 9F .byte 0x9f - 4652 0292 D4020000 .4byte .LVL63 - 4653 0296 E2020000 .4byte .LVL65 - 4654 029a 0100 .2byte 0x1 - 4655 029c 54 .byte 0x54 - 4656 029d 24030000 .4byte .LVL67 - 4657 02a1 32030000 .4byte .LVL69 - 4658 02a5 0100 .2byte 0x1 - 4659 02a7 54 .byte 0x54 - 4660 02a8 00000000 .4byte 0 - 4661 02ac 00000000 .4byte 0 - 4662 .LLST23: - 4663 02b0 0E020000 .4byte .LVL58 - 4664 02b4 1E020000 .4byte .LVL59 - 4665 02b8 0200 .2byte 0x2 - 4666 02ba 30 .byte 0x30 - 4667 02bb 9F .byte 0x9f - 4668 02bc 7A030000 .4byte .LVL72 - 4669 02c0 E4030000 .4byte .LFE68 - 4670 02c4 0100 .2byte 0x1 - 4671 02c6 5A .byte 0x5a - 4672 02c7 00000000 .4byte 0 - 4673 02cb 00000000 .4byte 0 - 4674 .LLST24: - 4675 02cf 94000000 .4byte .LVL36 - 4676 02d3 96000000 .4byte .LVL37 - 4677 02d7 0600 .2byte 0x6 - 4678 02d9 03 .byte 0x3 - 4679 02da 40000000 .4byte .LC5 - 4680 02de 9F .byte 0x9f - 4681 02df 00000000 .4byte 0 - 4682 02e3 00000000 .4byte 0 - 4683 .LLST25: - 4684 02e7 B2000000 .4byte .LVL38 - 4685 02eb B4000000 .4byte .LVL39 - 4686 02ef 0600 .2byte 0x6 - 4687 02f1 03 .byte 0x3 - 4688 02f2 64000000 .4byte .LC7 - 4689 02f6 9F .byte 0x9f - 4690 02f7 00000000 .4byte 0 - 4691 02fb 00000000 .4byte 0 - 4692 .LLST26: - 4693 02ff D0000000 .4byte .LVL40 - 4694 0303 D2000000 .4byte .LVL41 - 4695 0307 0600 .2byte 0x6 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 85 - - - 4696 0309 03 .byte 0x3 - 4697 030a 80000000 .4byte .LC9 - 4698 030e 9F .byte 0x9f - 4699 030f 00000000 .4byte 0 - 4700 0313 00000000 .4byte 0 - 4701 .LLST27: - 4702 0317 EE000000 .4byte .LVL42 - 4703 031b F0000000 .4byte .LVL43 - 4704 031f 0600 .2byte 0x6 - 4705 0321 03 .byte 0x3 - 4706 0322 9C000000 .4byte .LC11 - 4707 0326 9F .byte 0x9f - 4708 0327 00000000 .4byte 0 - 4709 032b 00000000 .4byte 0 - 4710 .LLST28: - 4711 032f 0C010000 .4byte .LVL44 - 4712 0333 0E010000 .4byte .LVL45 - 4713 0337 0600 .2byte 0x6 - 4714 0339 03 .byte 0x3 - 4715 033a BC000000 .4byte .LC13 - 4716 033e 9F .byte 0x9f - 4717 033f 00000000 .4byte 0 - 4718 0343 00000000 .4byte 0 - 4719 .LLST29: - 4720 0347 2A010000 .4byte .LVL46 - 4721 034b 2C010000 .4byte .LVL47 - 4722 034f 0600 .2byte 0x6 - 4723 0351 03 .byte 0x3 - 4724 0352 F8000000 .4byte .LC15 - 4725 0356 9F .byte 0x9f - 4726 0357 00000000 .4byte 0 - 4727 035b 00000000 .4byte 0 - 4728 .LLST30: - 4729 035f 4E010000 .4byte .LVL48 - 4730 0363 50010000 .4byte .LVL49 - 4731 0367 0600 .2byte 0x6 - 4732 0369 03 .byte 0x3 - 4733 036a 20010000 .4byte .LC17 - 4734 036e 9F .byte 0x9f - 4735 036f 00000000 .4byte 0 - 4736 0373 00000000 .4byte 0 - 4737 .LLST31: - 4738 0377 78010000 .4byte .LVL50 - 4739 037b 7A010000 .4byte .LVL51 - 4740 037f 0600 .2byte 0x6 - 4741 0381 03 .byte 0x3 - 4742 0382 34010000 .4byte .LC18 - 4743 0386 9F .byte 0x9f - 4744 0387 00000000 .4byte 0 - 4745 038b 00000000 .4byte 0 - 4746 .LLST32: - 4747 038f 9C010000 .4byte .LVL52 - 4748 0393 9E010000 .4byte .LVL53 - 4749 0397 0600 .2byte 0x6 - 4750 0399 03 .byte 0x3 - 4751 039a 48010000 .4byte .LC19 - 4752 039e 9F .byte 0x9f - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 86 - - - 4753 039f 00000000 .4byte 0 - 4754 03a3 00000000 .4byte 0 - 4755 .LLST33: - 4756 03a7 C0010000 .4byte .LVL54 - 4757 03ab C2010000 .4byte .LVL55 - 4758 03af 0600 .2byte 0x6 - 4759 03b1 03 .byte 0x3 - 4760 03b2 5C010000 .4byte .LC20 - 4761 03b6 9F .byte 0x9f - 4762 03b7 00000000 .4byte 0 - 4763 03bb 00000000 .4byte 0 - 4764 .LLST34: - 4765 03bf E2010000 .4byte .LVL56 - 4766 03c3 E6010000 .4byte .LVL57 - 4767 03c7 0600 .2byte 0x6 - 4768 03c9 03 .byte 0x3 - 4769 03ca 70010000 .4byte .LC21 - 4770 03ce 9F .byte 0x9f - 4771 03cf 00000000 .4byte 0 - 4772 03d3 00000000 .4byte 0 - 4773 .LLST35: - 4774 03d7 1E020000 .4byte .LVL59 - 4775 03db 22020000 .4byte .LVL60 - 4776 03df 0600 .2byte 0x6 - 4777 03e1 03 .byte 0x3 - 4778 03e2 98010000 .4byte .LC24 - 4779 03e6 9F .byte 0x9f - 4780 03e7 00000000 .4byte 0 - 4781 03eb 00000000 .4byte 0 - 4782 .LLST38: - 4783 03ef 40030000 .4byte .LVL70 - 4784 03f3 42030000 .4byte .LVL71 - 4785 03f7 0600 .2byte 0x6 - 4786 03f9 03 .byte 0x3 - 4787 03fa 84010000 .4byte .LC22 - 4788 03fe 9F .byte 0x9f - 4789 03ff 00000000 .4byte 0 - 4790 0403 00000000 .4byte 0 - 4791 .LLST39: - 4792 0407 8C030000 .4byte .LVL73 - 4793 040b 8E030000 .4byte .LVL74 - 4794 040f 0600 .2byte 0x6 - 4795 0411 03 .byte 0x3 - 4796 0412 A4010000 .4byte .LC25 - 4797 0416 9F .byte 0x9f - 4798 0417 00000000 .4byte 0 - 4799 041b 00000000 .4byte 0 - 4800 .section .debug_aranges,"",%progbits - 4801 0000 44000000 .4byte 0x44 - 4802 0004 0200 .2byte 0x2 - 4803 0006 00000000 .4byte .Ldebug_info0 - 4804 000a 04 .byte 0x4 - 4805 000b 00 .byte 0 - 4806 000c 0000 .2byte 0 - 4807 000e 0000 .2byte 0 - 4808 0010 00000000 .4byte .LFB66 - 4809 0014 38000000 .4byte .LFE66-.LFB66 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 87 - - - 4810 0018 00000000 .4byte .LFB64 - 4811 001c 28000000 .4byte .LFE64-.LFB64 - 4812 0020 00000000 .4byte .LFB63 - 4813 0024 28000000 .4byte .LFE63-.LFB63 - 4814 0028 00000000 .4byte .LFB62 - 4815 002c AC000000 .4byte .LFE62-.LFB62 - 4816 0030 00000000 .4byte .LFB67 - 4817 0034 68000000 .4byte .LFE67-.LFB67 - 4818 0038 00000000 .4byte .LFB68 - 4819 003c E4030000 .4byte .LFE68-.LFB68 - 4820 0040 00000000 .4byte 0 - 4821 0044 00000000 .4byte 0 - 4822 .section .debug_ranges,"",%progbits - 4823 .Ldebug_ranges0: - 4824 0000 0C000000 .4byte .LBB40 - 4825 0004 0E000000 .4byte .LBE40 - 4826 0008 52000000 .4byte .LBB43 - 4827 000c 68000000 .4byte .LBE43 - 4828 0010 00000000 .4byte 0 - 4829 0014 00000000 .4byte 0 - 4830 0018 0C000000 .4byte .LBB41 - 4831 001c 0E000000 .4byte .LBE41 - 4832 0020 52000000 .4byte .LBB42 - 4833 0024 68000000 .4byte .LBE42 - 4834 0028 00000000 .4byte 0 - 4835 002c 00000000 .4byte 0 - 4836 0030 0C030000 .4byte .LBB70 - 4837 0034 14030000 .4byte .LBE70 - 4838 0038 18030000 .4byte .LBB74 - 4839 003c 1A030000 .4byte .LBE74 - 4840 0040 20030000 .4byte .LBB75 - 4841 0044 24030000 .4byte .LBE75 - 4842 0048 00000000 .4byte 0 - 4843 004c 00000000 .4byte 0 - 4844 0050 00000000 .4byte .LFB66 - 4845 0054 38000000 .4byte .LFE66 - 4846 0058 00000000 .4byte .LFB64 - 4847 005c 28000000 .4byte .LFE64 - 4848 0060 00000000 .4byte .LFB63 - 4849 0064 28000000 .4byte .LFE63 - 4850 0068 00000000 .4byte .LFB62 - 4851 006c AC000000 .4byte .LFE62 - 4852 0070 00000000 .4byte .LFB67 - 4853 0074 68000000 .4byte .LFE67 - 4854 0078 00000000 .4byte .LFB68 - 4855 007c E4030000 .4byte .LFE68 - 4856 0080 00000000 .4byte 0 - 4857 0084 00000000 .4byte 0 - 4858 .section .debug_line,"",%progbits - 4859 .Ldebug_line0: - 4860 0000 55040000 .section .debug_str,"MS",%progbits,1 - 4860 02009402 - 4860 00000201 - 4860 FB0E0D00 - 4860 01010101 - 4861 .LASF99: - 4862 0000 44494552 .ascii "DIER\000" - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 88 - - - 4862 00 - 4863 .LASF79: - 4864 0005 7264796D .ascii "rdymsg\000" - 4864 736700 - 4865 .LASF15: - 4866 000c 75696E74 .ascii "uint64_t\000" - 4866 36345F74 - 4866 00 - 4867 .LASF191: - 4868 0015 474E5520 .ascii "GNU C 4.6.0\000" - 4868 4320342E - 4868 362E3000 - 4869 .LASF93: - 4870 0021 4F757470 .ascii "OutputQueue\000" - 4870 75745175 - 4870 65756500 - 4871 .LASF130: - 4872 002d 4F545950 .ascii "OTYPER\000" - 4872 455200 - 4873 .LASF143: - 4874 0034 4750545F .ascii "GPT_ONESHOT\000" - 4874 4F4E4553 - 4874 484F5400 - 4875 .LASF76: - 4876 0040 6D625F66 .ascii "mb_fullsem\000" - 4876 756C6C73 - 4876 656D00 - 4877 .LASF138: - 4878 004b 696F706F .ascii "ioportmask_t\000" - 4878 72746D61 - 4878 736B5F74 - 4878 00 - 4879 .LASF126: - 4880 0058 54494D5F .ascii "TIM_TypeDef\000" - 4880 54797065 - 4880 44656600 - 4881 .LASF87: - 4882 0064 715F746F .ascii "q_top\000" - 4882 7000 - 4883 .LASF78: - 4884 006a 4D61696C .ascii "Mailbox\000" - 4884 626F7800 - 4885 .LASF129: - 4886 0072 4D4F4445 .ascii "MODER\000" - 4886 5200 - 4887 .LASF16: - 4888 0078 75696E74 .ascii "uint_fast16_t\000" - 4888 5F666173 - 4888 7431365F - 4888 7400 - 4889 .LASF6: - 4890 0086 6C6F6E67 .ascii "long long unsigned int\000" - 4890 206C6F6E - 4890 6720756E - 4890 7369676E - 4890 65642069 - 4891 .LASF132: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 89 - - - 4892 009d 50555044 .ascii "PUPDR\000" - 4892 5200 - 4893 .LASF80: - 4894 00a3 65786974 .ascii "exitcode\000" - 4894 636F6465 - 4894 00 - 4895 .LASF174: - 4896 00ac 7072696E .ascii "print\000" - 4896 7400 - 4897 .LASF187: - 4898 00b2 73617475 .ascii "saturated\000" - 4898 72617465 - 4898 6400 - 4899 .LASF173: - 4900 00bc 7072696E .ascii "printn\000" - 4900 746E00 - 4901 .LASF185: - 4902 00c3 47505444 .ascii "GPTD2\000" - 4902 3200 - 4903 .LASF186: - 4904 00c9 47505444 .ascii "GPTD3\000" - 4904 3300 - 4905 .LASF152: - 4906 00cf 66726571 .ascii "frequency\000" - 4906 75656E63 - 4906 7900 - 4907 .LASF178: - 4908 00d9 67707432 .ascii "gpt2cb\000" - 4908 636200 - 4909 .LASF29: - 4910 00e0 705F7072 .ascii "p_prio\000" - 4910 696F00 - 4911 .LASF171: - 4912 00e7 72656164 .ascii "readt\000" - 4912 7400 - 4913 .LASF103: - 4914 00ed 43434D52 .ascii "CCMR1\000" - 4914 3100 - 4915 .LASF105: - 4916 00f3 43434D52 .ascii "CCMR2\000" - 4916 3200 - 4917 .LASF5: - 4918 00f9 6C6F6E67 .ascii "long long int\000" - 4918 206C6F6E - 4918 6720696E - 4918 7400 - 4919 .LASF1: - 4920 0107 7369676E .ascii "signed char\000" - 4920 65642063 - 4920 68617200 - 4921 .LASF133: - 4922 0113 42535252 .ascii "BSRR\000" - 4922 00 - 4923 .LASF127: - 4924 0118 47545052 .ascii "GTPR\000" - 4924 00 - 4925 .LASF17: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 90 - - - 4926 011d 626F6F6C .ascii "bool_t\000" - 4926 5F7400 - 4927 .LASF63: - 4928 0124 6D5F7175 .ascii "m_queue\000" - 4928 65756500 - 4929 .LASF142: - 4930 012c 4750545F .ascii "GPT_CONTINUOUS\000" - 4930 434F4E54 - 4930 494E554F - 4930 555300 - 4931 .LASF110: - 4932 013b 52455345 .ascii "RESERVED10\000" - 4932 52564544 - 4932 313000 - 4933 .LASF111: - 4934 0146 52455345 .ascii "RESERVED11\000" - 4934 52564544 - 4934 313100 - 4935 .LASF112: - 4936 0151 52455345 .ascii "RESERVED12\000" - 4936 52564544 - 4936 313200 - 4937 .LASF114: - 4938 015c 52455345 .ascii "RESERVED13\000" - 4938 52564544 - 4938 313300 - 4939 .LASF116: - 4940 0167 52455345 .ascii "RESERVED14\000" - 4940 52564544 - 4940 313400 - 4941 .LASF118: - 4942 0172 52455345 .ascii "RESERVED15\000" - 4942 52564544 - 4942 313500 - 4943 .LASF120: - 4944 017d 52455345 .ascii "RESERVED16\000" - 4944 52564544 - 4944 313600 - 4945 .LASF121: - 4946 0188 52455345 .ascii "RESERVED17\000" - 4946 52564544 - 4946 313700 - 4947 .LASF122: - 4948 0193 52455345 .ascii "RESERVED18\000" - 4948 52564544 - 4948 313800 - 4949 .LASF146: - 4950 019e 73746174 .ascii "state\000" - 4950 6500 - 4951 .LASF7: - 4952 01a4 6C6F6E67 .ascii "long int\000" - 4952 20696E74 - 4952 00 - 4953 .LASF151: - 4954 01ad 67707463 .ascii "gptcnt_t\000" - 4954 6E745F74 - 4954 00 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 91 - - - 4955 .LASF190: - 4956 01b6 67707433 .ascii "gpt3cfg\000" - 4956 63666700 - 4957 .LASF19: - 4958 01be 74737461 .ascii "tstate_t\000" - 4958 74655F74 - 4958 00 - 4959 .LASF36: - 4960 01c7 705F7265 .ascii "p_refs\000" - 4960 667300 - 4961 .LASF86: - 4962 01ce 715F6275 .ascii "q_buffer\000" - 4962 66666572 - 4962 00 - 4963 .LASF88: - 4964 01d7 715F7772 .ascii "q_wrptr\000" - 4964 70747200 - 4965 .LASF37: - 4966 01df 705F7469 .ascii "p_time\000" - 4966 6D6500 - 4967 .LASF31: - 4968 01e6 705F6E65 .ascii "p_newer\000" - 4968 77657200 - 4969 .LASF168: - 4970 01ee 70757477 .ascii "putwouldblock\000" - 4970 6F756C64 - 4970 626C6F63 - 4970 6B00 - 4971 .LASF60: - 4972 01fc 735F7175 .ascii "s_queue\000" - 4972 65756500 - 4973 .LASF149: - 4974 0204 67707463 .ascii "gptcallback_t\000" - 4974 616C6C62 - 4974 61636B5F - 4974 7400 - 4975 .LASF4: - 4976 0212 73686F72 .ascii "short unsigned int\000" - 4976 7420756E - 4976 7369676E - 4976 65642069 - 4976 6E7400 - 4977 .LASF180: - 4978 0225 696E7465 .ascii "interval\000" - 4978 7276616C - 4978 00 - 4979 .LASF131: - 4980 022e 4F535045 .ascii "OSPEEDR\000" - 4980 45445200 - 4981 .LASF54: - 4982 0236 725F6E65 .ascii "r_newer\000" - 4982 77657200 - 4983 .LASF145: - 4984 023e 47505444 .ascii "GPTDriver\000" - 4984 72697665 - 4984 7200 - 4985 .LASF47: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 92 - - - 4986 0248 72656761 .ascii "regarm_t\000" - 4986 726D5F74 - 4986 00 - 4987 .LASF10: - 4988 0251 73697A65 .ascii "size_t\000" - 4988 5F7400 - 4989 .LASF125: - 4990 0258 52455345 .ascii "RESERVED20\000" - 4990 52564544 - 4990 323000 - 4991 .LASF189: - 4992 0263 67707432 .ascii "gpt2cfg\000" - 4992 63666700 - 4993 .LASF70: - 4994 026b 4576656E .ascii "EventSource\000" - 4994 74536F75 - 4994 72636500 - 4995 .LASF144: - 4996 0277 67707473 .ascii "gptstate_t\000" - 4996 74617465 - 4996 5F7400 - 4997 .LASF164: - 4998 0282 75736172 .ascii "usart\000" - 4998 7400 - 4999 .LASF0: - 5000 0288 756E7369 .ascii "unsigned int\000" - 5000 676E6564 - 5000 20696E74 - 5000 00 - 5001 .LASF12: - 5002 0295 75696E74 .ascii "uint16_t\000" - 5002 31365F74 - 5002 00 - 5003 .LASF165: - 5004 029e 53657269 .ascii "SerialDriverVMT\000" - 5004 616C4472 - 5004 69766572 - 5004 564D5400 - 5005 .LASF162: - 5006 02ae 69717565 .ascii "iqueue\000" - 5006 756500 - 5007 .LASF39: - 5008 02b5 705F6D73 .ascii "p_msgqueue\000" - 5008 67717565 - 5008 756500 - 5009 .LASF137: - 5010 02c0 4750494F .ascii "GPIO_TypeDef\000" - 5010 5F547970 - 5010 65446566 - 5010 00 - 5011 .LASF77: - 5012 02cd 6D625F65 .ascii "mb_emptysem\000" - 5012 6D707479 - 5012 73656D00 - 5013 .LASF134: - 5014 02d9 4C434B52 .ascii "LCKR\000" - 5014 00 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 93 - - - 5015 .LASF177: - 5016 02de 67707470 .ascii "gptp\000" - 5016 00 - 5017 .LASF61: - 5018 02e3 735F636E .ascii "s_cnt\000" - 5018 7400 - 5019 .LASF139: - 5020 02e9 4750545F .ascii "GPT_UNINIT\000" - 5020 554E494E - 5020 495400 - 5021 .LASF160: - 5022 02f4 6576656E .ascii "event\000" - 5022 7400 - 5023 .LASF150: - 5024 02fa 67707466 .ascii "gptfreq_t\000" - 5024 7265715F - 5024 7400 - 5025 .LASF44: - 5026 0304 705F6D70 .ascii "p_mpool\000" - 5026 6F6F6C00 - 5027 .LASF22: - 5028 030c 6D73675F .ascii "msg_t\000" - 5028 7400 - 5029 .LASF163: - 5030 0312 6F717565 .ascii "oqueue\000" - 5030 756500 - 5031 .LASF153: - 5032 0319 63616C6C .ascii "callback\000" - 5032 6261636B - 5032 00 - 5033 .LASF128: - 5034 0322 55534152 .ascii "USART_TypeDef\000" - 5034 545F5479 - 5034 70654465 - 5034 6600 - 5035 .LASF170: - 5036 0330 77726974 .ascii "writet\000" - 5036 657400 - 5037 .LASF179: - 5038 0337 74617267 .ascii "target\000" - 5038 657400 - 5039 .LASF46: - 5040 033e 54687265 .ascii "ThreadsList\000" - 5040 6164734C - 5040 69737400 - 5041 .LASF23: - 5042 034a 6576656E .ascii "eventmask_t\000" - 5042 746D6173 - 5042 6B5F7400 - 5043 .LASF92: - 5044 0356 496E7075 .ascii "InputQueue\000" - 5044 74517565 - 5044 756500 - 5045 .LASF91: - 5046 0361 716E6F74 .ascii "qnotify_t\000" - 5046 6966795F - 5046 7400 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 94 - - - 5047 .LASF83: - 5048 036b 47656E65 .ascii "GenericQueue\000" - 5048 72696351 - 5048 75657565 - 5048 00 - 5049 .LASF49: - 5050 0378 73746B61 .ascii "stkalign_t\000" - 5050 6C69676E - 5050 5F7400 - 5051 .LASF166: - 5052 0383 77726974 .ascii "write\000" - 5052 6500 - 5053 .LASF85: - 5054 0389 715F636F .ascii "q_counter\000" - 5054 756E7465 - 5054 7200 - 5055 .LASF75: - 5056 0393 6D625F72 .ascii "mb_rdptr\000" - 5056 64707472 - 5056 00 - 5057 .LASF62: - 5058 039c 4D757465 .ascii "Mutex\000" - 5058 7800 - 5059 .LASF141: - 5060 03a2 4750545F .ascii "GPT_READY\000" - 5060 52454144 - 5060 5900 - 5061 .LASF25: - 5062 03ac 636E745F .ascii "cnt_t\000" - 5062 7400 - 5063 .LASF69: - 5064 03b2 656C5F6D .ascii "el_mask\000" - 5064 61736B00 - 5065 .LASF175: - 5066 03ba 7072696E .ascii "println\000" - 5066 746C6E00 - 5067 .LASF32: - 5068 03c2 705F6F6C .ascii "p_older\000" - 5068 64657200 - 5069 .LASF53: - 5070 03ca 725F6374 .ascii "r_ctx\000" - 5070 7800 - 5071 .LASF45: - 5072 03d0 54687265 .ascii "ThreadsQueue\000" - 5072 61647351 - 5072 75657565 - 5072 00 - 5073 .LASF72: - 5074 03dd 6D625F62 .ascii "mb_buffer\000" - 5074 75666665 - 5074 7200 - 5075 .LASF182: - 5076 03e7 776F7273 .ascii "worst\000" - 5076 7400 - 5077 .LASF192: - 5078 03ed 6D61696E .ascii "main.c\000" - 5078 2E6300 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 95 - - - 5079 .LASF55: - 5080 03f4 725F6F6C .ascii "r_older\000" - 5080 64657200 - 5081 .LASF124: - 5082 03fc 52455345 .ascii "RESERVED19\000" - 5082 52564544 - 5082 313900 - 5083 .LASF136: - 5084 0407 41465248 .ascii "AFRH\000" - 5084 00 - 5085 .LASF135: - 5086 040c 4146524C .ascii "AFRL\000" - 5086 00 - 5087 .LASF84: - 5088 0411 715F7761 .ascii "q_waiting\000" - 5088 6974696E - 5088 6700 - 5089 .LASF20: - 5090 041b 74726566 .ascii "trefs_t\000" - 5090 735F7400 - 5091 .LASF95: - 5092 0423 52455345 .ascii "RESERVED0\000" - 5092 52564544 - 5092 3000 - 5093 .LASF96: - 5094 042d 52455345 .ascii "RESERVED1\000" - 5094 52564544 - 5094 3100 - 5095 .LASF98: - 5096 0437 52455345 .ascii "RESERVED2\000" - 5096 52564544 - 5096 3200 - 5097 .LASF100: - 5098 0441 52455345 .ascii "RESERVED3\000" - 5098 52564544 - 5098 3300 - 5099 .LASF101: - 5100 044b 52455345 .ascii "RESERVED4\000" - 5100 52564544 - 5100 3400 - 5101 .LASF28: - 5102 0455 705F7072 .ascii "p_prev\000" - 5102 657600 - 5103 .LASF104: - 5104 045c 52455345 .ascii "RESERVED6\000" - 5104 52564544 - 5104 3600 - 5105 .LASF108: - 5106 0466 52455345 .ascii "RESERVED8\000" - 5106 52564544 - 5106 3800 - 5107 .LASF21: - 5108 0470 74707269 .ascii "tprio_t\000" - 5108 6F5F7400 - 5109 .LASF89: - 5110 0478 715F7264 .ascii "q_rdptr\000" - 5110 70747200 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 96 - - - 5111 .LASF193: - 5112 0480 443A5C50 .ascii "D:\\Progetti\\ChibiOS-RT\\testhal\\STM32L1xx\\IRQ_S" - 5112 726F6765 - 5112 7474695C - 5112 43686962 - 5112 694F532D - 5113 04ae 544F524D .ascii "TORM\000" - 5113 00 - 5114 .LASF181: - 5115 04b3 74687265 .ascii "threshold\000" - 5115 73686F6C - 5115 6400 - 5116 .LASF56: - 5117 04bd 725F7072 .ascii "r_preempt\000" - 5117 65656D70 - 5117 7400 - 5118 .LASF13: - 5119 04c7 696E7433 .ascii "int32_t\000" - 5119 325F7400 - 5120 .LASF2: - 5121 04cf 756E7369 .ascii "unsigned char\000" - 5121 676E6564 - 5121 20636861 - 5121 7200 - 5122 .LASF73: - 5123 04dd 6D625F74 .ascii "mb_top\000" - 5123 6F7000 - 5124 .LASF68: - 5125 04e4 656C5F6C .ascii "el_listener\000" - 5125 69737465 - 5125 6E657200 - 5126 .LASF184: - 5127 04f0 49544D5F .ascii "ITM_RxBuffer\000" - 5127 52784275 - 5127 66666572 - 5127 00 - 5128 .LASF34: - 5129 04fd 705F7374 .ascii "p_state\000" - 5129 61746500 - 5130 .LASF42: - 5131 0505 705F6D74 .ascii "p_mtxlist\000" - 5131 786C6973 - 5131 7400 - 5132 .LASF3: - 5133 050f 73686F72 .ascii "short int\000" - 5133 7420696E - 5133 7400 - 5134 .LASF52: - 5135 0519 725F7072 .ascii "r_prio\000" - 5135 696F00 - 5136 .LASF82: - 5137 0520 65776D61 .ascii "ewmask\000" - 5137 736B00 - 5138 .LASF27: - 5139 0527 705F6E65 .ascii "p_next\000" - 5139 787400 - 5140 .LASF35: - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 97 - - - 5141 052e 705F666C .ascii "p_flags\000" - 5141 61677300 - 5142 .LASF67: - 5143 0536 656C5F6E .ascii "el_next\000" - 5143 65787400 - 5144 .LASF156: - 5145 053e 53445F53 .ascii "SD_STOP\000" - 5145 544F5000 - 5146 .LASF26: - 5147 0546 54687265 .ascii "Thread\000" - 5147 616400 - 5148 .LASF41: - 5149 054d 705F6570 .ascii "p_epending\000" - 5149 656E6469 - 5149 6E6700 - 5150 .LASF155: - 5151 0558 53445F55 .ascii "SD_UNINIT\000" - 5151 4E494E49 - 5151 5400 - 5152 .LASF102: - 5153 0562 52455345 .ascii "RESERVED5\000" - 5153 52564544 - 5153 3500 - 5154 .LASF140: - 5155 056c 4750545F .ascii "GPT_STOP\000" - 5155 53544F50 - 5155 00 - 5156 .LASF14: - 5157 0575 75696E74 .ascii "uint32_t\000" - 5157 33325F74 - 5157 00 - 5158 .LASF106: - 5159 057e 52455345 .ascii "RESERVED7\000" - 5159 52564544 - 5159 3700 - 5160 .LASF51: - 5161 0588 725F7175 .ascii "r_queue\000" - 5161 65756500 - 5162 .LASF158: - 5163 0590 73647374 .ascii "sdstate_t\000" - 5163 6174655F - 5163 7400 - 5164 .LASF109: - 5165 059a 52455345 .ascii "RESERVED9\000" - 5165 52564544 - 5165 3900 - 5166 .LASF159: - 5167 05a4 53657269 .ascii "SerialDriver\000" - 5167 616C4472 - 5167 69766572 - 5167 00 - 5168 .LASF8: - 5169 05b1 6C6F6E67 .ascii "long unsigned int\000" - 5169 20756E73 - 5169 69676E65 - 5169 6420696E - 5169 7400 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 98 - - - 5170 .LASF57: - 5171 05c3 725F6375 .ascii "r_current\000" - 5171 7272656E - 5171 7400 - 5172 .LASF167: - 5173 05cd 72656164 .ascii "read\000" - 5173 00 - 5174 .LASF9: - 5175 05d2 63686172 .ascii "char\000" - 5175 00 - 5176 .LASF97: - 5177 05d7 534D4352 .ascii "SMCR\000" - 5177 00 - 5178 .LASF147: - 5179 05dc 636F6E66 .ascii "config\000" - 5179 696700 - 5180 .LASF40: - 5181 05e3 705F6D73 .ascii "p_msg\000" - 5181 6700 - 5182 .LASF123: - 5183 05e9 444D4152 .ascii "DMAR\000" - 5183 00 - 5184 .LASF194: - 5185 05ee 576F726B .ascii "WorkerThread\000" - 5185 65725468 - 5185 72656164 - 5185 00 - 5186 .LASF188: - 5187 05fb 7761576F .ascii "waWorkerThread\000" - 5187 726B6572 - 5187 54687265 - 5187 616400 - 5188 .LASF107: - 5189 060a 43434552 .ascii "CCER\000" - 5189 00 - 5190 .LASF65: - 5191 060f 6D5F6E65 .ascii "m_next\000" - 5191 787400 - 5192 .LASF24: - 5193 0616 73797374 .ascii "systime_t\000" - 5193 696D655F - 5193 7400 - 5194 .LASF43: - 5195 0620 705F7265 .ascii "p_realprio\000" - 5195 616C7072 - 5195 696F00 - 5196 .LASF33: - 5197 062b 705F6E61 .ascii "p_name\000" - 5197 6D6500 - 5198 .LASF154: - 5199 0632 47505443 .ascii "GPTConfig\000" - 5199 6F6E6669 - 5199 6700 - 5200 .LASF172: - 5201 063c 67657466 .ascii "getflags\000" - 5201 6C616773 - 5201 00 - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 99 - - - 5202 .LASF50: - 5203 0645 636F6E74 .ascii "context\000" - 5203 65787400 - 5204 .LASF94: - 5205 064d 696F666C .ascii "ioflags_t\000" - 5205 6167735F - 5205 7400 - 5206 .LASF48: - 5207 0657 696E7463 .ascii "intctx\000" - 5207 747800 - 5208 .LASF157: - 5209 065e 53445F52 .ascii "SD_READY\000" - 5209 45414459 - 5209 00 - 5210 .LASF59: - 5211 0667 53656D61 .ascii "Semaphore\000" - 5211 70686F72 - 5211 6500 - 5212 .LASF113: - 5213 0671 43435231 .ascii "CCR1\000" - 5213 00 - 5214 .LASF115: - 5215 0676 43435232 .ascii "CCR2\000" - 5215 00 - 5216 .LASF117: - 5217 067b 43435233 .ascii "CCR3\000" - 5217 00 - 5218 .LASF119: - 5219 0680 43435234 .ascii "CCR4\000" - 5219 00 - 5220 .LASF71: - 5221 0685 65735F6E .ascii "es_next\000" - 5221 65787400 - 5222 .LASF58: - 5223 068d 52656164 .ascii "ReadyList\000" - 5223 794C6973 - 5223 7400 - 5224 .LASF90: - 5225 0697 715F6E6F .ascii "q_notify\000" - 5225 74696679 - 5225 00 - 5226 .LASF183: - 5227 06a0 726C6973 .ascii "rlist\000" - 5227 7400 - 5228 .LASF11: - 5229 06a6 75696E74 .ascii "uint8_t\000" - 5229 385F7400 - 5230 .LASF161: - 5231 06ae 666C6167 .ascii "flags\000" - 5231 7300 - 5232 .LASF66: - 5233 06b4 4576656E .ascii "EventListener\000" - 5233 744C6973 - 5233 74656E65 - 5233 7200 - 5234 .LASF81: - 5235 06c2 77746F62 .ascii "wtobjp\000" - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 100 - - - 5235 6A7000 - 5236 .LASF18: - 5237 06c9 746D6F64 .ascii "tmode_t\000" - 5237 655F7400 - 5238 .LASF176: - 5239 06d1 67707433 .ascii "gpt3cb\000" - 5239 636200 - 5240 .LASF148: - 5241 06d8 636C6F63 .ascii "clock\000" - 5241 6B00 - 5242 .LASF169: - 5243 06de 67657477 .ascii "getwouldblock\000" - 5243 6F756C64 - 5243 626C6F63 - 5243 6B00 - 5244 .LASF195: - 5245 06ec 6D61696E .ascii "main\000" - 5245 00 - 5246 .LASF74: - 5247 06f1 6D625F77 .ascii "mb_wrptr\000" - 5247 72707472 - 5247 00 - 5248 .LASF64: - 5249 06fa 6D5F6F77 .ascii "m_owner\000" - 5249 6E657200 - 5250 .LASF30: - 5251 0702 705F6374 .ascii "p_ctx\000" - 5251 7800 - 5252 .LASF38: - 5253 0708 705F7761 .ascii "p_waiting\000" - 5253 6974696E - 5253 6700 - 5254 .ident "GCC: (GNU) 4.6.0" - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 101 - - -DEFINED SYMBOLS - *ABS*:00000000 main.c -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:18 .text.println:00000000 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:23 .text.println:00000000 println -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:69 .text.println:00000030 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:75 .text.gpt3cb:00000000 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:80 .text.gpt3cb:00000000 gpt3cb -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:130 .text.gpt3cb:00000020 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:136 .text.gpt2cb:00000000 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:141 .text.gpt2cb:00000000 gpt2cb -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:191 .text.gpt2cb:00000020 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:197 .text.WorkerThread:00000000 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:202 .text.WorkerThread:00000000 WorkerThread -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1087 .bss.saturated:00000000 .LANCHOR1 -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:318 .text.WorkerThread:00000098 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:327 .text.printn:00000000 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:332 .text.printn:00000000 printn -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:422 .text.printn:00000064 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:429 .text.startup.main:00000000 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:435 .text.startup.main:00000000 main -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:854 .text.startup.main:00000250 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:890 .text.startup.main:000002cc $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1059 .text.startup.main:000003c4 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1071 .rodata.gpt2cfg:00000000 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1075 .rodata.gpt2cfg:00000000 gpt2cfg -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1079 .bss.waWorkerThread:00000000 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1083 .bss.waWorkerThread:00000000 waWorkerThread -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1086 .bss.saturated:00000000 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1090 .bss.saturated:00000000 saturated -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1093 .rodata.gpt3cfg:00000000 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1097 .rodata.gpt3cfg:00000000 gpt3cfg -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1101 .rodata.str1.4:00000000 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1178 .bss.mb:00000000 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1182 .bss.mb:00000000 mb -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1185 .bss.b:00000000 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1189 .bss.b:00000000 b -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1192 .bss.x.3441:00000000 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1196 .bss.x.3441:00000000 x.3441 -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1199 .bss.cnt.3442:00000000 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1203 .bss.cnt.3442:00000000 cnt.3442 - .debug_frame:00000010 $d -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:74 .text.println:00000038 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:135 .text.gpt3cb:00000028 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:196 .text.gpt2cb:00000028 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:326 .text.WorkerThread:000000ac $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:428 .text.printn:00000068 $t -C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s:1070 .text.startup.main:000003e4 $t - -UNDEFINED SYMBOLS -SD1 -chMBPostI -chMBFetch -chMBPost -rlist -halInit -chSysInit -sdStart - ARM GAS C:\DOCUME~1\Giovanni\IMPOST~1\Temp\ccZ4NPZV.s page 102 - - -_pal_lld_setgroupmode -gptStart -chMBInit -chThdCreateStatic -GPTD2 -GPTD3 -gptStartContinuous -chThdSleep -gptStopTimer -- cgit v1.2.3 From 31a099cb104ea4d7d957bb65bbdc7e8edbdbe636 Mon Sep 17 00:00:00 2001 From: barthess Date: Mon, 19 Sep 2011 13:54:07 +0000 Subject: RTC. Driver improvements git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3352 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/dox/rtc.dox | 9 ++++++++ os/hal/platforms/STM32/rtc_lld.c | 41 ++++++++++++++++++++-------------- os/hal/platforms/STM32F1xx/stm32_rcc.h | 17 +++++++++----- 3 files changed, 45 insertions(+), 22 deletions(-) diff --git a/os/hal/dox/rtc.dox b/os/hal/dox/rtc.dox index 3572aca18..dc49c8bb0 100644 --- a/os/hal/dox/rtc.dox +++ b/os/hal/dox/rtc.dox @@ -30,5 +30,14 @@ * @pre In order to use the RTC driver the @p HAL_USE_RTC option * must be enabled in @p halconf.h. * + * @note STM32 Errata notes: + * Description + * When the LSIRDY flag is set, the clock may still be out of the + * specified frequency range (fLSI parameter, see LSI oscillator + * characteristics in the product datasheet). + * Workaround + * To have a fully stabilized clock in the specified range, a + * software temporization of 100 uS should be added. + * * @ingroup IO */ diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 62e114e66..875dc464c 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -112,29 +112,42 @@ CH_IRQ_HANDLER(RTC_IRQHandler) { * @notapi */ void rtc_lld_init(void){ - rccEnableBKP(FALSE); /* enable interface clocking */ - PWR->CR |= PWR_CR_DBP; /* enable access */ + rccEnableBKPInterface(FALSE); - if (!(RCC->BDCR & (RCC_BDCR_RTCEN | RCC_BDCR_LSEON))){ /* BKP domain was reseted */ - RCC->BDCR |= RTC_CLOCK_SOURCE; /* select clocking from LSE */ - RCC->BDCR |= RCC_BDCR_LSEON; /* switch LSE on */ - while(!(RCC->BDCR & RCC_BDCR_LSEON)) /* wait for stabilization */ + /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling + * clocking on APB1, because these values only update when APB1 functioning.*/ + RTC->CRL &= ~(RTC_CRL_RSF); + while (!(RTC->CRL & RTC_CRL_RSF)) + ; + + /* enable access to BKP registers */ + PWR->CR |= PWR_CR_DBP; + + if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ + RCC->BDCR |= RTC_CLOCK_SOURCE; + + /* for LSE source we must wait until source became stable */ + #if defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSE) + RCC->BDCR |= RCC_BDCR_LSEON; + while(!(RCC->BDCR & RCC_BDCR_LSERDY)) ; - RCC->BDCR |= RCC_BDCR_RTCEN; /* run clock */ + #endif + + RCC->BDCR |= RCC_BDCR_RTCEN; } #if defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSE) - uint32_t preload = STM32_LSECLK - 1UL; + uint32_t preload = STM32_LSECLK - 1; #elif defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSI) - uint32_t preload = STM32_LSICLK - 1UL; + uint32_t preload = STM32_LSICLK - 1; #elif defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_HSE) - uint32_t preload = (STM32_HSICLK / 128UL) - 1UL; + uint32_t preload = (STM32_HSICLK / 128) - 1; #else #error "RTC clock source not selected" #endif /* RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE */ /* Write preload register only if value changed */ - if (preload != (((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLH){ + if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLL)){ while(!(RTC->CRL & RTC_CRL_RTOFF)) ; @@ -147,12 +160,6 @@ void rtc_lld_init(void){ ; } - /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling - * clocking on APB1, because these values only update when APB1 functioning.*/ - RTC->CRL &= ~(RTC_CRL_RSF); - while (!(RTC->CRL & RTC_CRL_RSF)) - ; - /* disable all interrupts and clear all even flags just to be safe */ RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE); RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h index 7f215a720..9ca1140e9 100644 --- a/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -203,7 +203,7 @@ /** @} */ /** - * @brief Bakup domain interface specific RCC operations + * @brief Backup domain interface specific RCC operations * @{ */ /** @@ -214,7 +214,7 @@ * * @api */ -#define rccEnableBKP(lp) \ +#define rccEnableBKPInterface(lp) \ rccEnableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp); /** @@ -225,15 +225,22 @@ * * @api */ -#define rccDisableBKP(lp) \ +#define rccDisableBKPInterface(lp) \ rccDisableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp); /** - * @brief Resets the Backup Domain. + * @brief Resets the Backup Domain interface. * * @api */ -#define rccResetBKP(lp) rccResetAPB1(RCC_APB1ENR_BKPRST); +#define rccResetBKPInterface() rccResetAPB1(RCC_APB1ENR_BKPRST); + +/** + * @brief Resets the entire Backup Domain. + * + * @api + */ +#define rccResetBKP() (RCC->BDCR |= RCC_BDCR_BDRST); /** @} */ /** -- cgit v1.2.3 From f5c7e2f7cd4e43f272db4e9f053053eea9f92dde Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Sep 2011 14:01:42 +0000 Subject: Fixed an STM32 GPT driver problem. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3353 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/gpt_lld.c | 4 ++++ testhal/STM32L1xx/GPT/main.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32/gpt_lld.c b/os/hal/platforms/STM32/gpt_lld.c index 0fd5dde73..af8737f04 100644 --- a/os/hal/platforms/STM32/gpt_lld.c +++ b/os/hal/platforms/STM32/gpt_lld.c @@ -401,6 +401,10 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { gptp->tim->ARR = interval - 1; /* Time constant. */ gptp->tim->EGR = TIM_EGR_UG; /* Update event. */ + gptp->tim->CNT = 0; /* Reset counter. */ + /* NOTE: After generating the UG event it takes several clock cycles before + SR bit 0 goes to 1. This is because the clearing of CNT has been inserted + before the clearing of SR, to give it some time.*/ gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ gptp->tim->DIER = TIM_DIER_UIE; /* Update Event IRQ enabled. */ gptp->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN; diff --git a/testhal/STM32L1xx/GPT/main.c b/testhal/STM32L1xx/GPT/main.c index 4fadc4f9c..380d9650c 100644 --- a/testhal/STM32L1xx/GPT/main.c +++ b/testhal/STM32L1xx/GPT/main.c @@ -29,7 +29,7 @@ static void gpt2cb(GPTDriver *gptp) { (void)gptp; palSetPad(GPIOB, GPIOB_LED4); chSysLockFromIsr(); - gptStartOneShotI(&GPTD3, 200); /* 0.02 second pulse.*/ + gptStartOneShotI(&GPTD3, 1000); /* 0.02 second pulse.*/ chSysUnlockFromIsr(); } -- cgit v1.2.3 From 353ee572ad1d55e06648e5ff911f421b140baea7 Mon Sep 17 00:00:00 2001 From: barthess Date: Mon, 19 Sep 2011 15:02:02 +0000 Subject: RTC. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3354 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.c | 52 ++++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 875dc464c..941f2429f 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -112,6 +112,8 @@ CH_IRQ_HANDLER(RTC_IRQHandler) { * @notapi */ void rtc_lld_init(void){ + uint32_t preload = 0; + rccEnableBKPInterface(FALSE); /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling @@ -122,29 +124,39 @@ void rtc_lld_init(void){ /* enable access to BKP registers */ PWR->CR |= PWR_CR_DBP; - - if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ - RCC->BDCR |= RTC_CLOCK_SOURCE; - - /* for LSE source we must wait until source became stable */ - #if defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSE) - RCC->BDCR |= RCC_BDCR_LSEON; - while(!(RCC->BDCR & RCC_BDCR_LSERDY)) + /* select clock source */ + RCC->BDCR |= RTC_CLOCK_SOURCE; + + chDbgCheck(((RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE) &&\ + (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI) &&\ + (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE)), "No clock source selected"); + + if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE){ + if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ + RCC->BDCR |= RCC_BDCR_LSEON; + while(!(RCC->BDCR & RCC_BDCR_LSERDY)) + ; + RCC->BDCR |= RCC_BDCR_RTCEN; + } + preload = STM32_LSECLK - 1; + } + else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI){ + RCC->CSR |= RCC_CSR_LSION; + while(!(RCC->CSR & RCC_CSR_LSIRDY)) + ; + /* According to errata notes we must wait additional 100 uS for stabilization */ + uint32_t tmo = (STM32_SYSCLK / 1000000 ) * 100; + while(tmo--) ; - #endif - RCC->BDCR |= RCC_BDCR_RTCEN; + preload = STM32_LSICLK - 1; + } + else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE){ + preload = (STM32_HSICLK / 128) - 1; + } + else{ + chDbgPanic("Wrong"); } - - #if defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSE) - uint32_t preload = STM32_LSECLK - 1; - #elif defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_LSI) - uint32_t preload = STM32_LSICLK - 1; - #elif defined(RTC_CLOCK_SOURCE) == defined(RCC_BDCR_RTCSEL_HSE) - uint32_t preload = (STM32_HSICLK / 128) - 1; - #else - #error "RTC clock source not selected" - #endif /* RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE */ /* Write preload register only if value changed */ if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLL)){ -- cgit v1.2.3 From be4e2ca38d85319cfa5e0b3ea8849ee327e8c7a6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Sep 2011 19:27:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3355 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/GPT/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testhal/STM32F1xx/GPT/main.c b/testhal/STM32F1xx/GPT/main.c index e3e0797f8..01bd86452 100644 --- a/testhal/STM32F1xx/GPT/main.c +++ b/testhal/STM32F1xx/GPT/main.c @@ -86,12 +86,12 @@ int main(void) { * five seconds. */ while (TRUE) { - gptStopTimer(&GPTD1); gptStartContinuous(&GPTD1, 5000); chThdSleepMilliseconds(5000); gptStopTimer(&GPTD1); gptStartContinuous(&GPTD1, 2500); chThdSleepMilliseconds(5000); + gptStopTimer(&GPTD1); } return 0; } -- cgit v1.2.3 From da3d1eae7b4035fb916e14ba853a5cf2aa0f70cd Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 20 Sep 2011 07:02:14 +0000 Subject: RTC. Code reorganization to correspond ChibiOS rules. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3356 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.c | 43 ++++++++++++-------------- os/hal/platforms/STM32/rtc_lld.h | 8 ----- os/hal/platforms/STM32F1xx/hal_lld_f100.h | 7 +++++ os/hal/platforms/STM32F1xx/hal_lld_f103.h | 11 +++++++ os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 7 +++++ testhal/STM32F1xx/RTC/halconf.h | 7 ----- testhal/STM32F1xx/RTC/mcuconf.h | 1 + 7 files changed, 46 insertions(+), 38 deletions(-) diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 941f2429f..465f2f02e 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -115,23 +115,14 @@ void rtc_lld_init(void){ uint32_t preload = 0; rccEnableBKPInterface(FALSE); - - /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling - * clocking on APB1, because these values only update when APB1 functioning.*/ - RTC->CRL &= ~(RTC_CRL_RSF); - while (!(RTC->CRL & RTC_CRL_RSF)) - ; + //RCC->APB1ENR |= (RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN); /* enable access to BKP registers */ PWR->CR |= PWR_CR_DBP; /* select clock source */ - RCC->BDCR |= RTC_CLOCK_SOURCE; + RCC->BDCR |= STM32_RTC; - chDbgCheck(((RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE) &&\ - (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI) &&\ - (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE)), "No clock source selected"); - - if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE){ +#if STM32_RTC == STM32_RTC_LSE if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ RCC->BDCR |= RCC_BDCR_LSEON; while(!(RCC->BDCR & RCC_BDCR_LSERDY)) @@ -139,26 +130,32 @@ void rtc_lld_init(void){ RCC->BDCR |= RCC_BDCR_RTCEN; } preload = STM32_LSECLK - 1; - } - else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI){ + +#elif STM32_RTC == STM32_RTC_LSI RCC->CSR |= RCC_CSR_LSION; while(!(RCC->CSR & RCC_CSR_LSIRDY)) ; - /* According to errata notes we must wait additional 100 uS for stabilization */ + /* According to errata sheet we must wait additional 100 uS for stabilization */ uint32_t tmo = (STM32_SYSCLK / 1000000 ) * 100; while(tmo--) ; RCC->BDCR |= RCC_BDCR_RTCEN; preload = STM32_LSICLK - 1; - } - else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE){ + +#elif STM32_RTC == STM32_RTC_HSE preload = (STM32_HSICLK / 128) - 1; - } - else{ - chDbgPanic("Wrong"); - } - /* Write preload register only if value changed */ +#else +#error "RTC clock source not selected" +#endif + + /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling + * clocking on APB1, because these values only update when APB1 functioning.*/ + RTC->CRL &= ~(RTC_CRL_RSF); + while (!(RTC->CRL & RTC_CRL_RSF)) + ; + + /* Write preload register only if its value changed */ if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLL)){ while(!(RTC->CRL & RTC_CRL_RTOFF)) ; @@ -174,7 +171,7 @@ void rtc_lld_init(void){ /* disable all interrupts and clear all even flags just to be safe */ RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE); - RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); #if RTC_SUPPORTS_CALLBACKS RTCD.alarm_cb = NULL; diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h index c2c6f676b..7d7d703f0 100644 --- a/os/hal/platforms/STM32/rtc_lld.h +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -47,14 +47,6 @@ #define RTC_SUPPORTS_CALLBACKS TRUE #endif -/** - * @brief Clock source selecting. LSE by default. - */ -#if !defined(RTC_CLOCK_SOURCE) || defined(__DOXYGEN__) -#define RTC_CLOCK_SOURCE RCC_BDCR_RTCSEL_LSE -#endif - - /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index aad199528..60e42ece4 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -228,6 +228,13 @@ #define STM32_MCO STM32_MCO_NOCLOCK #endif +/** + * @brief Clock source selecting. LSI by default. + */ +#if !defined(STM32_RTC) || defined(__DOXYGEN__) +#define STM32_RTC STM32_RTC_LSI +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 4421663a0..f14ab5dc4 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -90,6 +90,11 @@ #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */ + /*===========================================================================*/ /* Platform specific friendly IRQ names. */ /*===========================================================================*/ @@ -251,6 +256,12 @@ #define STM32_MCO STM32_MCO_NOCLOCK #endif +/** + * @brief Clock source selecting. LSI by default. + */ +#if !defined(STM32_RTC) || defined(__DOXYGEN__) +#define STM32_RTC STM32_RTC_LSI +#endif /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 27a840ba8..52c124d2d 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -317,6 +317,13 @@ #define STM32_MCO STM32_MCO_NOCLOCK #endif +/** + * @brief Clock source selecting. LSI by default. + */ +#if !defined(STM32_RTC) || defined(__DOXYGEN__) +#define STM32_RTC STM32_RTC_LSI +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h index 93367c2d2..4dcef13da 100644 --- a/testhal/STM32F1xx/RTC/halconf.h +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -219,13 +219,6 @@ #define RTC_SUPPORTS_CALLBACKS TRUE #endif -/** - * @brief Clock source selecting. LSE by default. - */ -#if !defined(RTC_CLOCK_SOURCE) || defined(__DOXYGEN__) -#define RTC_CLOCK_SOURCE RCC_BDCR_RTCSEL_LSE -#endif - /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/RTC/mcuconf.h b/testhal/STM32F1xx/RTC/mcuconf.h index beefe5cba..2c5d4d8be 100644 --- a/testhal/STM32F1xx/RTC/mcuconf.h +++ b/testhal/STM32F1xx/RTC/mcuconf.h @@ -43,6 +43,7 @@ #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_MCO STM32_MCO_NOCLOCK +#define STM32_RTC STM32_RTC_LSE /* * ADC driver system settings. -- cgit v1.2.3 From 3035afea9de7fbf89c5c3852abeaf47780df4613 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 20 Sep 2011 07:18:29 +0000 Subject: RTC. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3357 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/hal_lld_f100.h | 5 +++++ os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 60e42ece4..5cabd9788 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -87,6 +87,11 @@ #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */ + /*===========================================================================*/ /* Platform specific friendly IRQ names. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 52c124d2d..caed49aca 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -92,6 +92,11 @@ #define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */ #define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */ +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */ + /* RCC_CFGR2 register bits definitions.*/ #define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */ #define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */ -- cgit v1.2.3 From ee0b40b93b5f797a830ebbd3cd735ca85ca15579 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 20 Sep 2011 07:25:39 +0000 Subject: EXT wakeup test updates. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3358 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/EXT_WAKEUP/halconf.h | 2 +- testhal/STM32F1xx/EXT_WAKEUP/main.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h index ca1d81b24..eb7142f50 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h @@ -289,7 +289,7 @@ * default configuration. */ #if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 38400 +#define SERIAL_DEFAULT_BITRATE 115200 #endif /** diff --git a/testhal/STM32F1xx/EXT_WAKEUP/main.c b/testhal/STM32F1xx/EXT_WAKEUP/main.c index f12a54207..3d6464ee7 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/main.c +++ b/testhal/STM32F1xx/EXT_WAKEUP/main.c @@ -102,7 +102,8 @@ static void cmd_sleep(BaseChannel *chp, int argc, char *argv[]){ extChannelEnable(&EXTD1, 10); chThdSleepMilliseconds(5); - PWR->CR |= (PWR_CR_CSBF | PWR_CR_CWUF); + PWR->CR |= (PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF); + PWR->CR &= ~PWR_CR_PDDS; // explicit clear PDDS, just to be safe SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; __WFI(); } -- cgit v1.2.3 From 0886cac0499a65b3fd1d410fd0f29b7cbcd4b1ba Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 20 Sep 2011 08:37:12 +0000 Subject: RTC. Removed errata note from rtc.dox because workaround realized in driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3359 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/dox/rtc.dox | 9 --------- 1 file changed, 9 deletions(-) diff --git a/os/hal/dox/rtc.dox b/os/hal/dox/rtc.dox index dc49c8bb0..b538f3a4a 100644 --- a/os/hal/dox/rtc.dox +++ b/os/hal/dox/rtc.dox @@ -29,15 +29,6 @@ * * @pre In order to use the RTC driver the @p HAL_USE_RTC option * must be enabled in @p halconf.h. - * - * @note STM32 Errata notes: - * Description - * When the LSIRDY flag is set, the clock may still be out of the - * specified frequency range (fLSI parameter, see LSI oscillator - * characteristics in the product datasheet). - * Workaround - * To have a fully stabilized clock in the specified range, a - * software temporization of 100 uS should be added. * * @ingroup IO */ -- cgit v1.2.3 From 5a3a608ad919591b88af842b0ce15f4e22790710 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 20 Sep 2011 16:00:30 +0000 Subject: Fixed bug 3411207 git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3360 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/kernel/src/chthreads.c | 1 + os/various/shell.c | 1 + 2 files changed, 2 insertions(+) diff --git a/os/kernel/src/chthreads.c b/os/kernel/src/chthreads.c index 46039561b..73236c850 100644 --- a/os/kernel/src/chthreads.c +++ b/os/kernel/src/chthreads.c @@ -353,6 +353,7 @@ void chThdExit(msg_t msg) { REG_REMOVE(tp); #endif chSchGoSleepS(THD_STATE_FINAL); + chSysUnlock(); } #if CH_USE_WAITEXIT || defined(__DOXYGEN__) diff --git a/os/various/shell.c b/os/various/shell.c index 1fe03fc1e..8a247b9f4 100644 --- a/os/various/shell.c +++ b/os/various/shell.c @@ -206,6 +206,7 @@ static msg_t shell_thread(void *p) { } chSysLock(); chEvtBroadcastI(&shell_terminated); + chSysUnlock(); return msg; } -- cgit v1.2.3 From bd339dfa99310b372fc2699b79c700bbec7a0543 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 20 Sep 2011 16:25:47 +0000 Subject: EXT wakeup test. Slow down serial baudrate. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3361 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/EXT_WAKEUP/Makefile | 2 +- testhal/STM32F1xx/EXT_WAKEUP/halconf.h | 2 +- testhal/STM32F1xx/EXT_WAKEUP/main.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/testhal/STM32F1xx/EXT_WAKEUP/Makefile b/testhal/STM32F1xx/EXT_WAKEUP/Makefile index 5f91baee0..96cfa2e2e 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/Makefile +++ b/testhal/STM32F1xx/EXT_WAKEUP/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C++ specific options here (added to USE_OPT). diff --git a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h index eb7142f50..ad81d2c24 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h @@ -289,7 +289,7 @@ * default configuration. */ #if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 +#define SERIAL_DEFAULT_BITRATE 57600 #endif /** diff --git a/testhal/STM32F1xx/EXT_WAKEUP/main.c b/testhal/STM32F1xx/EXT_WAKEUP/main.c index 3d6464ee7..522edde72 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/main.c +++ b/testhal/STM32F1xx/EXT_WAKEUP/main.c @@ -100,7 +100,6 @@ static void cmd_sleep(BaseChannel *chp, int argc, char *argv[]){ chThdSleepMilliseconds(200); // time to print out message in terminal extChannelEnable(&EXTD1, 10); - chThdSleepMilliseconds(5); PWR->CR |= (PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF); PWR->CR &= ~PWR_CR_PDDS; // explicit clear PDDS, just to be safe @@ -160,5 +159,6 @@ int main(void) { while (TRUE) { chThdSleepMilliseconds(100); palTogglePad(IOPORT3, GPIOC_LED); + chThdExit(0); } } -- cgit v1.2.3 From 5463b41d3a7a81da20c88631535c088decd61999 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Sep 2011 17:08:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3362 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/kernel/include/chthreads.h | 1 + os/kernel/src/chthreads.c | 24 +++++++++++++++++++++++- os/various/shell.c | 3 ++- readme.txt | 2 ++ 4 files changed, 28 insertions(+), 2 deletions(-) diff --git a/os/kernel/include/chthreads.h b/os/kernel/include/chthreads.h index bd3f21296..d99b2ee3b 100644 --- a/os/kernel/include/chthreads.h +++ b/os/kernel/include/chthreads.h @@ -345,6 +345,7 @@ extern "C" { void chThdSleepUntil(systime_t time); void chThdYield(void); void chThdExit(msg_t msg); + void chThdExitS(msg_t msg); #if CH_USE_WAITEXIT msg_t chThdWait(Thread *tp); #endif diff --git a/os/kernel/src/chthreads.c b/os/kernel/src/chthreads.c index 73236c850..b2231ef17 100644 --- a/os/kernel/src/chthreads.c +++ b/os/kernel/src/chthreads.c @@ -335,6 +335,27 @@ void chThdYield(void) { * @api */ void chThdExit(msg_t msg) { + + chSysLock(); + chThdExitS(msg); + /* The thread never returns here.*/ +} + +/** + * @brief Terminates the current thread. + * @details The thread goes in the @p THD_STATE_FINAL state holding the + * specified exit status code, other threads can retrieve the + * exit status code by invoking the function @p chThdWait(). + * @post Eventual code after this function will never be executed, + * this function never returns. The compiler has no way to + * know this so do not assume that the compiler would remove + * the dead code. + * + * @param[in] msg thread exit code + * + * @sclass + */ +void chThdExitS(msg_t msg) { Thread *tp = currp; chSysLock(); @@ -353,7 +374,8 @@ void chThdExit(msg_t msg) { REG_REMOVE(tp); #endif chSchGoSleepS(THD_STATE_FINAL); - chSysUnlock(); + /* The thread never returns here.*/ + chDbgAssert(FALSE, "chThdExitS(), #1", "zombies apocalypse"); } #if CH_USE_WAITEXIT || defined(__DOXYGEN__) diff --git a/os/various/shell.c b/os/various/shell.c index 8a247b9f4..b0f995757 100644 --- a/os/various/shell.c +++ b/os/various/shell.c @@ -204,9 +204,10 @@ static msg_t shell_thread(void *p) { } } } + /* Atomically broadcasting the event source and terminating the thread, + there is not a chSysUnlock() because the thread terminates upon return.*/ chSysLock(); chEvtBroadcastI(&shell_terminated); - chSysUnlock(); return msg; } diff --git a/readme.txt b/readme.txt index 752703c1d..61054ebdd 100644 --- a/readme.txt +++ b/readme.txt @@ -73,6 +73,8 @@ ***************************************************************************** *** 2.3.3 *** +- FIX: The function chThdExit() triggers an error on shell return when the + system state checker is enabled (bug 3411207)(backported to 2.2.8). - FIX: Some ARMCMx makefiles refer the file rules.mk in the ARM7 port (bug 3411180)(backported to 2.2.8). - FIX: Fixed wrong check on CH_DBG_ENABLE_STACK_CHECK setting (bug 3387671) -- cgit v1.2.3 From c69417e365e3f495588ad7b88e9ee8fc16b3fcdb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Sep 2011 17:10:56 +0000 Subject: Fixed bug 3411207. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3363 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/kernel/src/chthreads.c | 1 - 1 file changed, 1 deletion(-) diff --git a/os/kernel/src/chthreads.c b/os/kernel/src/chthreads.c index b2231ef17..bf43c6c43 100644 --- a/os/kernel/src/chthreads.c +++ b/os/kernel/src/chthreads.c @@ -358,7 +358,6 @@ void chThdExit(msg_t msg) { void chThdExitS(msg_t msg) { Thread *tp = currp; - chSysLock(); tp->p_u.exitcode = msg; #if defined(THREAD_EXT_EXIT_HOOK) THREAD_EXT_EXIT_HOOK(tp); -- cgit v1.2.3 From 2eae0014602871fc7b1d9d0b67830d055e15554f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Sep 2011 17:14:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3365 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/readme.txt b/readme.txt index 61054ebdd..ebaca849d 100644 --- a/readme.txt +++ b/readme.txt @@ -93,6 +93,8 @@ (backported to 2.2.4). - FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420) (backported to 2.2.4). +- NEW: Added new API chThdExitS() in order to allow atomic operations on + thead exit (backported to 2.2.8). - NEW: New I2C driver model and STM32 implementation. (evaluate the option to change the API to a synchronous model) - NEW: New RTC driver model and STM32 implementation. -- cgit v1.2.3 From 01596d8b5e9399d2c4b3e3551cdd3396b4c787bc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Sep 2011 17:33:38 +0000 Subject: Fixed bug 3411774. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3367 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/hal_lld.h | 35 ++++++++++++++++++++----- os/hal/platforms/STM32F1xx/hal_lld_f100.h | 13 +++++----- os/hal/platforms/STM32F1xx/hal_lld_f103.h | 13 +++++----- os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 11 ++++---- os/hal/platforms/STM32F1xx/stm32f10x.h | 36 +++++++++++++++++--------- os/hal/platforms/STM32F2xx/hal_lld.h | 17 +++++++----- os/hal/platforms/STM32L1xx/hal_lld.h | 17 +++++++----- os/hal/platforms/STM32L1xx/platform.mk | 1 + readme.txt | 2 ++ 9 files changed, 96 insertions(+), 49 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index 659fd3fb1..da9e610fd 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -82,6 +82,8 @@ #define STM32_HAS_ETH FALSE +#define STM32_EXTI_NUM_CHANNELS 19 + #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -123,8 +125,9 @@ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART3 FALSE #define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE @@ -150,6 +153,8 @@ #define STM32_HAS_ETH FALSE +#define STM32_EXTI_NUM_CHANNELS 19 + #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -191,8 +196,9 @@ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART3 FALSE #define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE @@ -218,6 +224,8 @@ #define STM32_HAS_ETH FALSE +#define STM32_EXTI_NUM_CHANNELS 19 + #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -259,8 +267,9 @@ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART3 FALSE #define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE @@ -286,6 +295,8 @@ #define STM32_HAS_ETH FALSE +#define STM32_EXTI_NUM_CHANNELS 19 + #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -327,8 +338,9 @@ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART3 FALSE #define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE @@ -354,6 +366,8 @@ #define STM32_HAS_ETH FALSE +#define STM32_EXTI_NUM_CHANNELS 19 + #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -395,8 +409,9 @@ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART3 TRUE #define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 FALSE #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE @@ -422,6 +437,8 @@ #define STM32_HAS_ETH FALSE +#define STM32_EXTI_NUM_CHANNELS 19 + #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -463,8 +480,9 @@ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART3 TRUE #define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 FALSE #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE @@ -490,6 +508,8 @@ #define STM32_HAS_ETH TRUE +#define STM32_EXTI_NUM_CHANNELS 20 + #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -531,8 +551,9 @@ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART3 TRUE #define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 FALSE #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 TRUE diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 5cabd9788..51cdf97e3 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -87,10 +87,11 @@ #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ -#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */ -#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */ -#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */ -#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */ +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as + RTC clock. */ /*===========================================================================*/ /* Platform specific friendly IRQ names. */ @@ -143,8 +144,8 @@ #define USART3_IRQHandler VectorDC /**< USART3. */ #endif #define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTCAlarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ -#define CEC_IRQHandler VectorE8 /**< CEC. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define CEC_IRQHandler VectorE8 /**< CEC. */ #define TIM12_IRQHandler VectorEC /**< TIM12. */ #define TIM13_IRQHandler VectorF0 /**< TIM13. */ #define TIM14_IRQHandler VectorF4 /**< TIM14. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index f14ab5dc4..9ba74d239 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -90,10 +90,11 @@ #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ -#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */ -#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */ -#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */ -#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */ +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as + RTC clock. */ /*===========================================================================*/ /* Platform specific friendly IRQ names. */ @@ -144,8 +145,8 @@ #define USART2_IRQHandler VectorD8 /**< USART2. */ #define USART3_IRQHandler VectorDC /**< USART3. */ #define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTCAlarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ -#define USBWakeUp_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ #define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ #define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ #define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index caed49aca..974b59f34 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -92,10 +92,11 @@ #define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */ #define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */ -#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */ -#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */ -#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */ -#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */ +#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */ +#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */ +#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ +#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as + RTC clock. */ /* RCC_CFGR2 register bits definitions.*/ #define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */ @@ -148,7 +149,7 @@ #define USART2_IRQHandler VectorD8 /**< USART2. */ #define USART3_IRQHandler VectorDC /**< USART3. */ #define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTCAlarm_IRQHandler VectorE4 /**< RTC alarm through EXTI +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarm through EXTI line. */ #define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through EXTI line. */ diff --git a/os/hal/platforms/STM32F1xx/stm32f10x.h b/os/hal/platforms/STM32F1xx/stm32f10x.h index c7f447d18..6697b9648 100644 --- a/os/hal/platforms/STM32F1xx/stm32f10x.h +++ b/os/hal/platforms/STM32F1xx/stm32f10x.h @@ -217,8 +217,10 @@ typedef enum IRQn USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ #endif /* STM32F10X_LD */ #ifdef STM32F10X_LD_VL @@ -236,7 +238,8 @@ typedef enum IRQn USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ TIM7_IRQn = 55 /*!< TIM7 Interrupt */ @@ -266,8 +269,10 @@ typedef enum IRQn USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ #endif /* STM32F10X_MD */ #ifdef STM32F10X_MD_VL @@ -290,7 +295,8 @@ typedef enum IRQn USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ TIM7_IRQn = 55 /*!< TIM7 Interrupt */ @@ -320,8 +326,10 @@ typedef enum IRQn USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ @@ -361,7 +369,8 @@ typedef enum IRQn USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ @@ -405,8 +414,10 @@ typedef enum IRQn USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + USB_FS_WKUP_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ @@ -450,7 +461,8 @@ typedef enum IRQn USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + /* CHIBIOS FIX (making it compatible with STM32L and STM32F2 headers).*/ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h index 764f58529..91135950f 100644 --- a/os/hal/platforms/STM32F2xx/hal_lld.h +++ b/os/hal/platforms/STM32F2xx/hal_lld.h @@ -133,7 +133,7 @@ /* STM32F2xx capabilities.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC3 TRUE #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 TRUE @@ -145,6 +145,8 @@ #define STM32_HAS_ETH TRUE +#define STM32_EXTI_NUM_CHANNELS 23 + #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -171,8 +173,8 @@ #define STM32_HAS_TIM3 TRUE #define STM32_HAS_TIM4 TRUE #define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 TRUE #define STM32_HAS_TIM9 TRUE #define STM32_HAS_TIM10 TRUE @@ -187,10 +189,11 @@ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART3 FALSE -#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 TRUE -#define STM32_HAS_USB TRUE +#define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 TRUE /*===========================================================================*/ @@ -240,7 +243,7 @@ #define USART2_IRQHandler VectorD8 /**< USART2. */ #define USART3_IRQHandler VectorDC /**< USART3. */ #define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTCAlarm_IRQHandler VectorE4 /**< RTC alarm through EXTI +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarm through EXTI line. */ #define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through EXTI line. */ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 2815febb1..2c3d05138 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -148,6 +148,8 @@ #define STM32_HAS_ETH FALSE +#define STM32_EXTI_NUM_CHANNELS 23 + #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -189,8 +191,9 @@ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART3 FALSE #define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE @@ -201,8 +204,10 @@ #define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ #define PVD_IRQHandler Vector44 /**< PVD through EXTI Line detect. */ -#define TAMPER_IRQHandler Vector48 /**< Tamper. */ -#define RTC_IRQHandler Vector4C /**< RTC. */ +#define TAMPER_STAMP_IRQHandler Vector48 /**< Tamper and Time Stamp + through EXTI. */ +#define RTC_WKUP_IRQHandler Vector4C /**< RTC Wakeup Timer through + EXTI. */ #define FLASH_IRQHandler Vector50 /**< Flash. */ #define RCC_IRQHandler Vector54 /**< RCC. */ #define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ @@ -221,7 +226,7 @@ #define USB_HP_IRQHandler Vector8C /**< USB High Priority. */ #define USB_LP_IRQHandler Vector90 /**< USB Low Priority. */ #define DAC_IRQHandler Vector94 /**< DAC. */ -#define COMP_IRQHandler Vector98 /**< COMP. */ +#define COMP_IRQHandler Vector98 /**< Comparator through EXTI. */ #define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ #define TIM9_IRQHandler VectorA0 /**< TIM9. */ #define TIM10_IRQHandler VectorA4 /**< TIM10. */ @@ -240,8 +245,8 @@ #define USART2_IRQHandler VectorD8 /**< USART2. */ #define USART3_IRQHandler VectorDC /**< USART3. */ #define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTCAlarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ -#define USBWakeUp_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ +#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ #define TIM6_IRQHandler VectorEC /**< TIM6. */ #define TIM7_IRQHandler VectorF0 /**< TIM7. */ /** @} */ diff --git a/os/hal/platforms/STM32L1xx/platform.mk b/os/hal/platforms/STM32L1xx/platform.mk index e51234323..047864a79 100644 --- a/os/hal/platforms/STM32L1xx/platform.mk +++ b/os/hal/platforms/STM32L1xx/platform.mk @@ -1,6 +1,7 @@ # List of all the STM32L1xx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ diff --git a/readme.txt b/readme.txt index ebaca849d..3a2875970 100644 --- a/readme.txt +++ b/readme.txt @@ -73,6 +73,8 @@ ***************************************************************************** *** 2.3.3 *** +- FIX: Fixed missing UART5 definition in STM32 HAL (bug 3411774)(backported + to 2.2.8). - FIX: The function chThdExit() triggers an error on shell return when the system state checker is enabled (bug 3411207)(backported to 2.2.8). - FIX: Some ARMCMx makefiles refer the file rules.mk in the ARM7 port (bug -- cgit v1.2.3 From a4a5c507fe744ea10c47f090abe289c5019db0a2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Sep 2011 17:44:29 +0000 Subject: Updated readme.txt. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3370 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/readme.txt b/readme.txt index 3a2875970..799605e52 100644 --- a/readme.txt +++ b/readme.txt @@ -95,8 +95,11 @@ (backported to 2.2.4). - FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420) (backported to 2.2.4). +- NEW: STM32L1xx sub-family support, all STM32 drivers adapted and retested + on the new platform except ADC that will need a specific implementation. - NEW: Added new API chThdExitS() in order to allow atomic operations on thead exit (backported to 2.2.8). +- NEW: New EXT driver model and STM32 implementation. - NEW: New I2C driver model and STM32 implementation. (evaluate the option to change the API to a synchronous model) - NEW: New RTC driver model and STM32 implementation. @@ -147,8 +150,8 @@ redefined. The macro chDbgCheck() no more includes the line number in the description because incompatibility with the Cosmic compiler (backported to 2.2.7). -- NEW: Added provisional support for STM32L1xx and STM32F2xx. Because of this - some directories related to the STM32 have been renamed, your makefiles may +- NEW: Added provisional support for STM32F2xx. Because of this some + directories related to the STM32 have been renamed, your makefiles may require adjustments. (TODO: change to be ported to IAR and Keil build files) - NEW: Added a custom rule to the various rules.mk files, now it is possible -- cgit v1.2.3 From 614b9961352334e3a4e33ef4b2d1b3f78a57f612 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Sep 2011 17:46:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3371 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/various/shell.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/os/various/shell.c b/os/various/shell.c index b0f995757..b62b8e37e 100644 --- a/os/various/shell.c +++ b/os/various/shell.c @@ -34,10 +34,6 @@ #include "shell.h" #include "chprintf.h" -#if SHELL_USE_IPRINTF -#define sprintf siprintf -#endif - /** * @brief Shell termination event source. */ -- cgit v1.2.3 From 450a8fe0c86102a685fa8accde3a9a0aa8a05ae7 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 20 Sep 2011 19:35:20 +0000 Subject: EXT lld driver. Fixed according to new naming conventions in stm32f10x.h git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3372 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/ext_lld.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/os/hal/platforms/STM32/ext_lld.c b/os/hal/platforms/STM32/ext_lld.c index 712ed5a39..ee00fb592 100644 --- a/os/hal/platforms/STM32/ext_lld.c +++ b/os/hal/platforms/STM32/ext_lld.c @@ -310,10 +310,10 @@ void ext_lld_start(EXTDriver *extp) { CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); NVICEnableVector(PVD_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); - NVICEnableVector(RTCAlarm_IRQn, + NVICEnableVector(RTC_Alarm_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); #if STM32_HAS_USB - NVICEnableVector(USBWakeUp_IRQn, + NVICEnableVector(USB_FS_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); #endif #if STM32_HAS_OTG1 @@ -369,9 +369,9 @@ void ext_lld_stop(EXTDriver *extp) { NVICDisableVector(EXTI9_5_IRQn); NVICDisableVector(EXTI15_10_IRQn); NVICDisableVector(PVD_IRQn); - NVICDisableVector(RTCAlarm_IRQn); + NVICDisableVector(RTC_Alarm_IRQn ); #if STM32_HAS_USB - NVICDisableVector(USBWakeUp_IRQn); + NVICDisableVector(USB_FS_WKUP_IRQn); #endif #if STM32_HAS_OTG1 NVICDisableVector(OTG_FS_WKUP_IRQn); -- cgit v1.2.3 From f90273557f060f07b87c1c9e3765f74491910533 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Sep 2011 19:44:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3373 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/ext_lld.c | 226 +++++++++++++++-- os/hal/platforms/STM32/ext_lld.h | 44 ++-- testhal/STM32L1xx/EXT/Makefile | 202 +++++++++++++++ testhal/STM32L1xx/EXT/chconf.h | 535 +++++++++++++++++++++++++++++++++++++++ testhal/STM32L1xx/EXT/halconf.h | 328 ++++++++++++++++++++++++ testhal/STM32L1xx/EXT/main.c | 108 ++++++++ testhal/STM32L1xx/EXT/mcuconf.h | 185 ++++++++++++++ testhal/STM32L1xx/EXT/readme.txt | 30 +++ 8 files changed, 1617 insertions(+), 41 deletions(-) create mode 100644 testhal/STM32L1xx/EXT/Makefile create mode 100644 testhal/STM32L1xx/EXT/chconf.h create mode 100644 testhal/STM32L1xx/EXT/halconf.h create mode 100644 testhal/STM32L1xx/EXT/main.c create mode 100644 testhal/STM32L1xx/EXT/mcuconf.h create mode 100644 testhal/STM32L1xx/EXT/readme.txt diff --git a/os/hal/platforms/STM32/ext_lld.c b/os/hal/platforms/STM32/ext_lld.c index ee00fb592..13eca6f3b 100644 --- a/os/hal/platforms/STM32/ext_lld.c +++ b/os/hal/platforms/STM32/ext_lld.c @@ -141,7 +141,7 @@ CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { CH_IRQ_PROLOGUE(); - pr = EXTI->PR; + pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); EXTI->PR = pr; if (pr & (1 << 5)) EXTD1.config->channels[5].cb(&EXTD1, 5); @@ -167,7 +167,8 @@ CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { CH_IRQ_PROLOGUE(); - pr = EXTI->PR; + pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | + (1 << 15)); EXTI->PR = pr; if (pr & (1 << 10)) EXTD1.config->channels[10].cb(&EXTD1, 10); @@ -215,13 +216,13 @@ CH_IRQ_HANDLER(RTCAlarm_IRQHandler) { CH_IRQ_EPILOGUE(); } -#if STM32_HAS_USB || defined(__DOXYGEN__) +#if defined(STM32L1XX_MD) /** - * @brief EXTI[18] interrupt handler (USB). + * @brief EXTI[18] interrupt handler (USB_FS_WKUP). * * @isr */ -CH_IRQ_HANDLER(USBWakeUp_IRQHandler) { +CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { CH_IRQ_PROLOGUE(); @@ -230,11 +231,136 @@ CH_IRQ_HANDLER(USBWakeUp_IRQHandler) { CH_IRQ_EPILOGUE(); } -#endif /* STM32_HAS_USB */ -#if STM32_HAS_OTG1 || defined(__DOXYGEN__) /** - * @brief EXTI[18] interrupt handler (OTG1). + * @brief EXTI[19] interrupt handler (TAMPER_STAMP). + * + * @isr + */ +CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[20] interrupt handler (RTC_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 20); + EXTD1.config->channels[20].cb(&EXTD1, 20); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[21]...EXTI[22] interrupt handler (COMP). + * + * @isr + */ +CH_IRQ_HANDLER(COMP_IRQHandler) { + uint32_t pr; + + CH_IRQ_PROLOGUE(); + + pr = EXTI->PR & ((1 << 21) | (1 << 22)); + EXTI->PR = pr; + if (pr & (1 << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1 << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + + CH_IRQ_EPILOGUE(); +} + +#elif defined(STM32F2XX) +/** + * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (ETH_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 19); + EXTD1.config->channels[19].cb(&EXTD1, 19); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(OTG_HS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 20); + EXTD1.config->channels[20].cb(&EXTD1, 20); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[21] interrupt handler (TAMPER_STAMP). + * + * @isr + */ +CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 21); + EXTD1.config->channels[21].cb(&EXTD1, 21); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[22] interrupt handler (RTC_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 22); + EXTD1.config->channels[22].cb(&EXTD1, 22); + + CH_IRQ_EPILOGUE(); +} + +#elif defined(STM32F10X_CL) +/** + * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). * * @isr */ @@ -247,11 +373,9 @@ CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { CH_IRQ_EPILOGUE(); } -#endif /* STM32_HAS_OTG1 */ -#if STM32_HAS_ETH || defined(__DOXYGEN__) /** - * @brief EXTI[19] interrupt handler (ETH). + * @brief EXTI[19] interrupt handler (ETH_WKUP). * * @isr */ @@ -264,7 +388,23 @@ CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { CH_IRQ_EPILOGUE(); } -#endif /* STM32_HAS_ETH */ + +#else +/** + * @brief EXTI[18] interrupt handler (USB_FS_WKUP). + * + * @isr + */ +CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + EXTI->PR = (1 << 18); + EXTD1.config->channels[18].cb(&EXTD1, 18); + + CH_IRQ_EPILOGUE(); +} +#endif /*===========================================================================*/ /* Driver exported functions. */ @@ -312,17 +452,38 @@ void ext_lld_start(EXTDriver *extp) { CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); NVICEnableVector(RTC_Alarm_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); -#if STM32_HAS_USB +#if defined(STM32L1XX_MD) + /* EXTI vectors specific to STM32L1xx.*/ NVICEnableVector(USB_FS_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); -#endif -#if STM32_HAS_OTG1 + NVICEnableVector(TAMPER_STAMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); + NVICEnableVector(RTC_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); + NVICEnableVector(COMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); +#elif defined(STM32F2XX) + /* EXTI vectors specific to STM32F2xx.*/ + NVICEnableVector(OTG_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + NVICEnableVector(ETH_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); + NVICEnableVector(OTG_HS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); + NVICEnableVector(TAMPER_STAMP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); + NVICEnableVector(RTC_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY)); +#elif defined(STM32F10X_CL) + /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ NVICEnableVector(OTG_FS_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); -#endif -#if STM32_HAS_ETH NVICEnableVector(ETH_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); +#else + /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ + NVICEnableVector(USB_FS_WKUP_IRQn, + CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); #endif } /* Configuration.*/ @@ -339,10 +500,17 @@ void ext_lld_start(EXTDriver *extp) { ftsr |= (1 << i); } } +#if defined(STM32L1XX_MD) || defined(STM32F2XX) + SYSCFG->EXTICR[0] = extp->config->exti[0]; + SYSCFG->EXTICR[1] = extp->config->exti[1]; + SYSCFG->EXTICR[2] = extp->config->exti[2]; + SYSCFG->EXTICR[3] = extp->config->exti[3]; +#else /* STM32F1XX */ AFIO->EXTICR[0] = extp->config->exti[0]; AFIO->EXTICR[1] = extp->config->exti[1]; AFIO->EXTICR[2] = extp->config->exti[2]; AFIO->EXTICR[3] = extp->config->exti[3]; +#endif /* STM32F1XX */ EXTI->SWIER = 0; EXTI->RTSR = rtsr; EXTI->FTSR = ftsr; @@ -369,15 +537,27 @@ void ext_lld_stop(EXTDriver *extp) { NVICDisableVector(EXTI9_5_IRQn); NVICDisableVector(EXTI15_10_IRQn); NVICDisableVector(PVD_IRQn); - NVICDisableVector(RTC_Alarm_IRQn ); -#if STM32_HAS_USB + NVICDisableVector(RTC_Alarm_IRQn); +#if defined(STM32L1XX_MD) + /* EXTI vectors specific to STM32L1xx.*/ NVICDisableVector(USB_FS_WKUP_IRQn); -#endif -#if STM32_HAS_OTG1 + NVICDisableVector(TAMPER_STAMP_IRQn); + NVICDisableVector(RTC_WKUP_IRQn); + NVICDisableVector(COMP_IRQn); +#elif defined(STM32F2XX) + /* EXTI vectors specific to STM32F2xx.*/ NVICDisableVector(OTG_FS_WKUP_IRQn); -#endif -#if STM32_HAS_ETH NVICDisableVector(ETH_WKUP_IRQn); + NVICDisableVector(OTG_HS_WKUP_IRQn); + NVICDisableVector(TAMPER_STAMP_IRQn); + NVICDisableVector(RTC_WKUP_IRQn); +#elif defined(STM32F10X_CL) + /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ + NVICDisableVector(OTG_FS_WKUP_IRQn); + NVICDisableVector(ETH_WKUP_IRQn); +#else + /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ + NVICDisableVector(USB_FS_WKUP_IRQn); #endif } EXTI->EMR = 0; diff --git a/os/hal/platforms/STM32/ext_lld.h b/os/hal/platforms/STM32/ext_lld.h index 17ea09fb8..753b12608 100644 --- a/os/hal/platforms/STM32/ext_lld.h +++ b/os/hal/platforms/STM32/ext_lld.h @@ -37,21 +37,8 @@ /** * @brief Available number of EXT channels. - * @note The number of available channels varies depending on the STM32 - * subfamily: - * - STM32F10X_CL, 20 channels. - * - STM32F2XX, 23 channels. - * - STM32L1XX_MD, 23 channels. - * - All other STM32F10X_xx, 19 channels. - * . */ -#if defined(STM32F10X_CL) || defined(__DOXYGEN__) -#define EXT_MAX_CHANNELS 20 -#elif defined(STM32F2XX) -#define EXT_MAX_CHANNELS 23 -#else -#define EXT_MAX_CHANNELS 19 -#endif +#define EXT_MAX_CHANNELS STM32_EXTI_NUM_CHANNELS /** * @brief Mask of the available channels. @@ -140,33 +127,54 @@ #endif /** - * @brief EXTI16 (PVD) interrupt priority level setting. + * @brief EXTI16 interrupt priority level setting. */ #if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_EXT_EXTI16_IRQ_PRIORITY 6 #endif /** - * @brief EXTI17 (RTC) interrupt priority level setting. + * @brief EXTI17 interrupt priority level setting. */ #if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_EXT_EXTI17_IRQ_PRIORITY 6 #endif /** - * @brief EXTI18 (USB) interrupt priority level setting. + * @brief EXTI18 interrupt priority level setting. */ #if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #endif /** - * @brief EXTI19 (ETH) interrupt priority level setting. + * @brief EXTI19 interrupt priority level setting. */ #if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #endif +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI22_IRQ_PRIORITY 6 +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/testhal/STM32L1xx/EXT/Makefile b/testhal/STM32L1xx/EXT/Makefile new file mode 100644 index 000000000..9209b441d --- /dev/null +++ b/testhal/STM32L1xx/EXT/Makefile @@ -0,0 +1,202 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/EXT/chconf.h b/testhal/STM32L1xx/EXT/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32L1xx/EXT/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/EXT/halconf.h b/testhal/STM32L1xx/EXT/halconf.h new file mode 100644 index 000000000..d7df1593a --- /dev/null +++ b/testhal/STM32L1xx/EXT/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/EXT/main.c b/testhal/STM32L1xx/EXT/main.c new file mode 100644 index 000000000..7bf0cb54e --- /dev/null +++ b/testhal/STM32L1xx/EXT/main.c @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +static void led4off(void *arg) { + + (void)arg; + palClearPad(GPIOB, GPIOB_LED4); +} + +/* Triggered when the button is pressed or released. The LED4 is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + static VirtualTimer vt4; + + (void)extp; + (void)channel; + palSetPad(GPIOB, GPIOB_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + /* LED4 set to OFF after 200mS.*/ + chVTSetI(&vt4, MS2ST(200), led4off, NULL); + chSysUnlockFromIsr(); +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + }, + EXT_MODE_EXTI(EXT_MODE_GPIOA, /* Button.*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0) +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + EXTI->SWIER = 64; + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + EXTI->SWIER = 64; + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); + } +} diff --git a/testhal/STM32L1xx/EXT/mcuconf.h b/testhal/STM32L1xx/EXT/mcuconf.h new file mode 100644 index 000000000..d214c9d12 --- /dev/null +++ b/testhal/STM32L1xx/EXT/mcuconf.h @@ -0,0 +1,185 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_1P8 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/EXT/readme.txt b/testhal/STM32L1xx/EXT/readme.txt new file mode 100644 index 000000000..b0d1883e9 --- /dev/null +++ b/testhal/STM32L1xx/EXT/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx EXT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From 1c7c4673d2cbd6f4ef0f9198ddc7edbfea56332f Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 20 Sep 2011 20:11:04 +0000 Subject: EXT_WAKEUP test minor improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3374 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/EXT_WAKEUP/main.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/testhal/STM32F1xx/EXT_WAKEUP/main.c b/testhal/STM32F1xx/EXT_WAKEUP/main.c index 522edde72..986721fc9 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/main.c +++ b/testhal/STM32F1xx/EXT_WAKEUP/main.c @@ -17,6 +17,13 @@ You should have received a copy of the GNU General Public License along with this program. If not, see . */ + +/** + * This program demonstrate how to use interrupt from EXTI line for waking + * up MCU from stop mode. EXTI line connected to UART RX pin and generate + * interrupt on falling edge of start bit. + */ + #include "ch.h" #include "hal.h" @@ -32,7 +39,7 @@ static void extcb2(EXTDriver *extp, expchannel_t channel) { (void)channel; chSysLockFromIsr(); - /* we MUST reinit clocks after waking up if use HSE or HSI+PLL */ + /* we must reinit clocks after waking up ESPECIALLY if use HSE or HSI+PLL */ stm32_clock_init(); extChannelDisableI(&EXTD1, 10); @@ -142,23 +149,19 @@ int main(void) { /* Activates the serial driver using the driver default configuration. */ sdStart(&SD1, NULL); - /* Shell manager initialization. */ - shellInit(); + /* Setting up ports. */ palSetPadMode(IOPORT1, 9, PAL_MODE_STM32_ALTERNATE_PUSHPULL); palSetPadMode(IOPORT1, 10, PAL_MODE_INPUT); + /* Shell manager initialization. */ + shellInit(); static WORKING_AREA(waShell, 512); shellCreateStatic(&shell_cfg1, waShell, sizeof(waShell), NORMALPRIO); - /* - * Normal main() thread activity, in this demo it enables and disables the - * button EXT channel using 5 seconds intervals. - */ - + /* Start blink indicating. */ chThdSleepMilliseconds(2000); // timeuot to differ reboot and wake up from sleep while (TRUE) { chThdSleepMilliseconds(100); palTogglePad(IOPORT3, GPIOC_LED); - chThdExit(0); } } -- cgit v1.2.3 From 42e2ea515d9c24187d57cffcd2889c4641384165 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Sep 2011 20:31:20 +0000 Subject: Improved documentation of sleep functions. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3375 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/kernel/include/chthreads.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/os/kernel/include/chthreads.h b/os/kernel/include/chthreads.h index d99b2ee3b..582b4e1e1 100644 --- a/os/kernel/include/chthreads.h +++ b/os/kernel/include/chthreads.h @@ -291,7 +291,7 @@ typedef msg_t (*tfunc_t)(void *); * system clock. * @note The maximum specified value is implementation dependent. * - * @param[in] sec time in seconds + * @param[in] sec time in seconds, must be different from zero * * @api */ @@ -304,7 +304,7 @@ typedef msg_t (*tfunc_t)(void *); * system clock. * @note The maximum specified value is implementation dependent. * - * @param[in] msec time in milliseconds + * @param[in] msec time in milliseconds, must be different from zero * * @api */ @@ -317,7 +317,7 @@ typedef msg_t (*tfunc_t)(void *); * system clock. * @note The maximum specified value is implementation dependent. * - * @param[in] usec time in microseconds + * @param[in] usec time in microseconds, must be different from zero * * @api */ -- cgit v1.2.3 From 95713cae20050dd58b41f52edead1b05c1c982a2 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 21 Sep 2011 12:46:09 +0000 Subject: RTC. API cnahge. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3376 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/rtc.h | 3 +-- os/hal/platforms/STM32/rtc_lld.c | 22 ++++++++++------------ os/hal/platforms/STM32/rtc_lld.h | 3 +-- os/hal/src/rtc.c | 18 ++++++++---------- 4 files changed, 20 insertions(+), 26 deletions(-) diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h index e0a2c50c5..5adf9559c 100644 --- a/os/hal/include/rtc.h +++ b/os/hal/include/rtc.h @@ -75,8 +75,7 @@ extern "C" { #endif /* RTC_SUPPORTS_CALLBACKS */ void rtcSetTime(uint32_t tv_sec); - uint32_t rtcGetSec(void); - uint16_t rtcGetMsec(void); + uint32_t rtcGetTime(uint16_t *msec); void rtcSetAlarm(uint32_t tv_alarm); uint32_t rtcGetAlarm(void); #ifdef __cplusplus diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 465f2f02e..6ae2a4aee 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -125,6 +125,7 @@ void rtc_lld_init(void){ #if STM32_RTC == STM32_RTC_LSE if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ RCC->BDCR |= RCC_BDCR_LSEON; + /* Note: cold start time of LSE oscillator on STM32 is about 3 seconds. */ while(!(RCC->BDCR & RCC_BDCR_LSERDY)) ; RCC->BDCR |= RCC_BDCR_RTCEN; @@ -262,23 +263,20 @@ void rtc_lld_set_time(uint32_t tv_sec){ } /** - * @brief Return current time in UNIX notation. + * @brief Return return seconds since UNIX epoch. * - * @notapi - */ -inline uint32_t rtc_lld_get_sec(void){ - return ((RTC->CNTH << 16) + RTC->CNTL); -} - -/** - * @brief Return fractional part of current time (milliseconds). + * @param[in] msec pointer to variable for storing fractional part of + * time (milliseconds). * * @notapi */ -inline uint16_t rtc_lld_get_msec(void){ +inline uint32_t rtc_lld_get_time(uint16_t *msec){ uint32_t time_frac = 0; - time_frac = (((uint32_t)RTC->DIVH) << 16) + (RTC->DIVL); - return(((STM32_LSECLK - time_frac) * 1000) / STM32_LSECLK); + if(msec != NULL){ + time_frac = (((uint32_t)RTC->DIVH) << 16) + (RTC->DIVL); + *msec = (uint16_t)(((STM32_LSECLK - time_frac) * 1000) / STM32_LSECLK); + } + return ((RTC->CNTH << 16) + RTC->CNTL); } /** diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h index 7d7d703f0..d73d35091 100644 --- a/os/hal/platforms/STM32/rtc_lld.h +++ b/os/hal/platforms/STM32/rtc_lld.h @@ -100,8 +100,7 @@ extern "C" { void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t overflow_cb, rtccb_t second_cb, rtccb_t alarm_cb); void rtc_lld_set_time(uint32_t tv_sec); - uint32_t rtc_lld_get_sec(void); - uint16_t rtc_lld_get_msec(void); + uint32_t rtc_lld_get_time(uint16_t *msec); uint32_t rtc_lld_get_alarm(void); void rtc_lld_set_alarm(uint32_t); #ifdef __cplusplus diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index ab916cf52..3b4b5824b 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -90,17 +90,15 @@ void rtcSetTime(uint32_t tv_sec){ } /** - * @brief Return current time in UNIX notation. - */ -inline uint32_t rtcGetSec(void){ - return rtc_lld_get_sec(); -} - -/** - * @brief Return fractional part of current time (milliseconds). + * @brief Return return seconds since UNIX epoch. + * + * @param[in] msec pointer to variable for storing fractional part of + * time (milliseconds). + * + * @notapi */ -inline uint16_t rtcGetMsec(void){ - return rtc_lld_get_msec(); +inline uint32_t rtcGetTime(uint16_t *msec){ + return rtc_lld_get_time(msec); } /** -- cgit v1.2.3 From ae42ff1857ee56d67feca50d379c5f4b66d7fe69 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 21 Sep 2011 17:10:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3377 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/adc_lld.h | 27 +- os/hal/platforms/STM32L1xx/adc_lld.c | 241 +++++++++++++++ os/hal/platforms/STM32L1xx/adc_lld.h | 447 +++++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/hal_lld.h | 2 +- os/hal/platforms/STM32L1xx/platform.mk | 1 + os/ports/GCC/ARMCMx/port.dox | 49 +-- readme.txt | 6 +- test/test.dox | 6 +- testhal/STM32L1xx/ADC/Makefile | 202 +++++++++++++ testhal/STM32L1xx/ADC/chconf.h | 535 +++++++++++++++++++++++++++++++++ testhal/STM32L1xx/ADC/halconf.h | 328 ++++++++++++++++++++ testhal/STM32L1xx/ADC/main.c | 124 ++++++++ testhal/STM32L1xx/ADC/mcuconf.h | 185 ++++++++++++ testhal/STM32L1xx/ADC/readme.txt | 30 ++ 14 files changed, 2156 insertions(+), 27 deletions(-) create mode 100644 os/hal/platforms/STM32L1xx/adc_lld.c create mode 100644 os/hal/platforms/STM32L1xx/adc_lld.h create mode 100644 testhal/STM32L1xx/ADC/Makefile create mode 100644 testhal/STM32L1xx/ADC/chconf.h create mode 100644 testhal/STM32L1xx/ADC/halconf.h create mode 100644 testhal/STM32L1xx/ADC/main.c create mode 100644 testhal/STM32L1xx/ADC/mcuconf.h create mode 100644 testhal/STM32L1xx/ADC/readme.txt diff --git a/os/hal/platforms/STM32F1xx/adc_lld.h b/os/hal/platforms/STM32F1xx/adc_lld.h index 7180c2b83..1d1052f50 100644 --- a/os/hal/platforms/STM32F1xx/adc_lld.h +++ b/os/hal/platforms/STM32F1xx/adc_lld.h @@ -35,9 +35,18 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @name Triggers selection + * @{ + */ #define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ #define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ +/** @} */ +/** + * @name Available analog channels + * @{ + */ #define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ #define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ #define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ @@ -56,7 +65,12 @@ #define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ #define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ #define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +/** @} */ +/** + * @name Sampling rates + * @{ + */ #define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ #define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ #define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ @@ -65,6 +79,7 @@ #define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ #define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ #define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -206,7 +221,7 @@ typedef struct { uint32_t sqr2; /** * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 0...6. + * @details Conversion group sequence 1...6. */ uint32_t sqr3; } ADCConversionGroup; @@ -281,6 +296,10 @@ struct ADCDriver { /* Driver macros. */ /*===========================================================================*/ +/** + * @name Sequences building helper macros + * @{ + */ /** * @brief Number of channels in a conversion sequence. */ @@ -304,7 +323,12 @@ struct ADCDriver { #define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ #define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ #define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +/** @} */ +/** + * @name Sampling rate settings helper macros + * @{ + */ #define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ #define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ #define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ @@ -326,6 +350,7 @@ struct ADCDriver { sampling time. */ #define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference sampling time. */ +/** @} */ /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c new file mode 100644 index 000000000..9ccb198e4 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -0,0 +1,241 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32L1xx/adc_lld.c + * @brief STM32L1xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_ADC_DMA_ERROR_HOOK) + if ((flags & STM32_DMA_ISR_TEIF) != 0) { + STM32_ADC_DMA_ERROR_HOOK(spip); + } +#else + (void)flags; +#endif + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; + ADC->CCR = STM32_ADC_ADCPRE; +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif + + /* ADC initial setup, just resetting control registers in this case.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + ADC1->CR2 = 0; + dmaStreamRelease(adcp->dmastp); + rccDisableADC1(FALSE); + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode, n; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) + mode |= STM32_DMA_CR_CIRC; + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth; + } + else + n = (uint32_t)grpp->num_channels; + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, n); + dmaStreamSetMode(adcp->dmastp, mode); + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; + adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SMPR3 = grpp->smpr3; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + adcp->adc->SQR4 = grpp->sqr4; + adcp->adc->SQR5 = grpp->sqr5; + /* Must wait the ADC to be ready for conversion, see 9.3.6 "Timing diagram" + in the Reference Manual.*/ + while ((adcp->adc->SR & ADC_SR_ADONS) == 0) + ; + /* ADC start by raising ADC_CR2_SWSTART.*/ + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_DMA | + ADC_CR2_CONT | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR2 = 0; +} + +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableTSVREFE(void) { + + ADC->CCR |= ADC_CCR_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableTSVREFE(void) { + + ADC->CCR &= ~ADC_CCR_TSVREFE; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/adc_lld.h b/os/hal/platforms/STM32L1xx/adc_lld.h new file mode 100644 index 000000000..2889387ab --- /dev/null +++ b/os/hal/platforms/STM32L1xx/adc_lld.h @@ -0,0 +1,447 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32L1xx/adc_lld.h + * @brief STM32L1xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ +#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV1 0 +#define ADC_CCR_ADCPRE_DIV2 1 +#define ADC_CCR_ADCPRE_DIV4 2 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */ +#define ADC_CHANNEL_IN19 19 /**< @brief External analog input 19. */ +#define ADC_CHANNEL_IN20 20 /**< @brief External analog input 20. */ +#define ADC_CHANNEL_IN21 21 /**< @brief External analog input 21. */ +#define ADC_CHANNEL_IN22 22 /**< @brief External analog input 22. */ +#define ADC_CHANNEL_IN23 23 /**< @brief External analog input 23. */ +#define ADC_CHANNEL_IN24 24 /**< @brief External analog input 24. */ +#define ADC_CHANNEL_IN25 25 /**< @brief External analog input 25. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_4 0 /**< @brief 4 cycles sampling time. */ +#define ADC_SAMPLE_9 1 /**< @brief 9 cycles sampling time. */ +#define ADC_SAMPLE_16 2 /**< @brief 16 cycles sampling time. */ +#define ADC_SAMPLE_24 3 /**< @brief 24 cycles sampling time. */ +#define ADC_SAMPLE_48 4 /**< @brief 48 cycles sampling time. */ +#define ADC_SAMPLE_96 5 /**< @brief 96 cycles sampling time. */ +#define ADC_SAMPLE_192 6 /**< @brief 192 cycles sampling time. */ +#define ADC_SAMPLE_384 7 /**< @brief 384 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 TRUE +#endif + +/** + * @brief ADC common clock divider. + * @note This setting is influenced by the VDDA voltage and other + * external conditions, please refer to the STM32L15x datasheet + * for more info.
+ * See section 6.3.15 "12-bit ADC characteristics". + */ +#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1 +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC1 interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_ADC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 20...25. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...19. + */ + uint32_t smpr2; + /** + * @brief ADC SMPR3 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr3; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 25...27 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 19...24. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 13...18. + */ + uint32_t sqr3; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr4; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr5; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated SMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR5_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR5_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR5_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR5_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR5_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR5_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR4_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR4_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR4_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR4_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR4_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR4_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR3_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR3_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR3_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR3_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +#define ADC_SQR3_SQ17_N(n) ((n) << 20) /**< @brief 17th channel in seq.*/ +#define ADC_SQR3_SQ18_N(n) ((n) << 25) /**< @brief 18th channel in seq.*/ + +#define ADC_SQR2_SQ19_N(n) ((n) << 0) /**< @brief 19th channel in seq.*/ +#define ADC_SQR2_SQ20_N(n) ((n) << 5) /**< @brief 20th channel in seq.*/ +#define ADC_SQR2_SQ21_N(n) ((n) << 10) /**< @brief 21th channel in seq.*/ +#define ADC_SQR2_SQ22_N(n) ((n) << 15) /**< @brief 22th channel in seq.*/ +#define ADC_SQR2_SQ23_N(n) ((n) << 20) /**< @brief 23th channel in seq.*/ +#define ADC_SQR2_SQ24_N(n) ((n) << 25) /**< @brief 24th channel in seq.*/ + +#define ADC_SQR1_SQ25_N(n) ((n) << 0) /**< @brief 25th channel in seq.*/ +#define ADC_SQR1_SQ26_N(n) ((n) << 5) /**< @brief 26th channel in seq.*/ +#define ADC_SQR1_SQ27_N(n) ((n) << 10) /**< @brief 27th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR3_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR3_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR3_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR3_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR3_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR3_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR3_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR3_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR3_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR3_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR2_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */ +#define ADC_SMPR2_SMP_AN19(n) ((n) << 27) /**< @brief AN19 sampling time. */ + +#define ADC_SMPR1_SMP_AN20(n) ((n) << 0) /**< @brief AN20 sampling time. */ +#define ADC_SMPR1_SMP_AN21(n) ((n) << 3) /**< @brief AN21 sampling time. */ +#define ADC_SMPR1_SMP_AN22(n) ((n) << 6) /**< @brief AN22 sampling time. */ +#define ADC_SMPR1_SMP_AN23(n) ((n) << 9) /**< @brief AN23 sampling time. */ +#define ADC_SMPR1_SMP_AN24(n) ((n) << 12) /**< @brief AN24 sampling time. */ +#define ADC_SMPR1_SMP_AN25(n) ((n) << 15) /**< @brief AN25 sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 2c3d05138..cf07e8036 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -423,7 +423,7 @@ /** * @brief Maximum HSECLK at current voltage setting. */ -#define STM32_HSECLK_MAX 32000000#if +#define STM32_HSECLK_MAX 32000000 /** * @brief Maximum SYSCLK at current voltage setting. diff --git a/os/hal/platforms/STM32L1xx/platform.mk b/os/hal/platforms/STM32L1xx/platform.mk index 047864a79..45e937ee5 100644 --- a/os/hal/platforms/STM32L1xx/platform.mk +++ b/os/hal/platforms/STM32L1xx/platform.mk @@ -1,5 +1,6 @@ # List of all the STM32L1xx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox index 13ab36d8a..709332a6b 100644 --- a/os/ports/GCC/ARMCMx/port.dox +++ b/os/ports/GCC/ARMCMx/port.dox @@ -70,8 +70,7 @@ * not globally masked but only interrupts with higher priority can preempt * the current handler. The processor is running in exception-privileged * mode. - * - Serving Fast Interrupt. This state is not implemented in the - * ARMv6-M implementation. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific * asynchronous NMI vector and several synchronous fault vectors that can * be considered belonging to this category. @@ -109,9 +108,13 @@ * not globally masked but only interrupts with higher priority can preempt * the current handler. The processor is running in exception-privileged * mode. - * - Serving Fast Interrupt. It is basically the same of the SRI state - * but it is not possible to switch to the I-Locked state because fast - * interrupts can preempt the kernel critical zone. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
+ * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific * asynchronous NMI vector and several synchronous fault vectors that can * be considered belonging to this category. @@ -214,20 +217,28 @@ * @section ARMCMx_STARTUP_2 Expected linker symbols * The startup code starts at the symbol @p ResetHandler and expects the * following symbols to be defined in the linker script: - * - @p __ram_end__ End of RAM. - * - @p __main_stack_base__ Main stack lower boundary. - * - @p __main_stack_end__ Main stack initial position. - * - @p __process_stack_base__ Process stack lower boundary. - * - @p __process_stack_end__ Process stack initial position. - * - @p _textdata Address of the data segment source read only data. - * - @p _data Start of the data segment. - * - @p _edata End of the data segment end location. - * - @p _bss_start Start of the BSS. - * - @p _bss_end End of the BSS segment. - * - @p __init_array_start Start of the constructors array. - * - @p __init_array_end End of the constructors array. - * - @p __fini_array_start Start of the destructors array. - * - @p __fini_array_end End of the destructors array. + * - @p __ram_end__, end of RAM. + * - @p __main_stack_base__, main stack lower boundary. + * - @p __main_stack_end__, main stack initial position. + * - @p __process_stack_base__, process stack lower boundary. + * - @p __process_stack_end__, process stack initial position. + * - @p _textdata, address of the data segment source read only data. + * - @p _data, start of the data segment. + * - @p _edata, end of the data segment end location. + * - @p _bss_start, start of the BSS. + * - @p _bss_end, end of the BSS segment. + * - @p __init_array_start, start of the constructors array. + * - @p __init_array_end, end of the constructors array. + * - @p __fini_array_start, start of the destructors array. + * - @p __fini_array_end, end of the destructors array. + * . + * Additionally the kernel expects the following symbols: + * - @p __main_thread_stack_base__, this symbol is required when the + * stack checking is enabled (CH_DBG_ENABLE_STACK_CHECK==TRUE), + * it is an alias of @p __process_stack_base__ in this port. + * - @p __heap_base__ and @p __heap_end__, those symbols are required + * if the memory core manager is enabled (CH_USE_MEMCORE==TRUE) + * with a default core size set to zero (CH_MEMCORE_SIZE==0). * . * @ingroup ARMCMx */ diff --git a/readme.txt b/readme.txt index 799605e52..005520649 100644 --- a/readme.txt +++ b/readme.txt @@ -106,8 +106,8 @@ (API and functionality review) - NEW: Improved MAC driver model, it now follows the same template of other drivers. - (uIP demo to be adapted) - (implement macStop() in AT91SAM7X implementation) + (TODO: uIP demo to be adapted) + (TODO: implement macStop() in AT91SAM7X implementation) - NEW: New RCC helper driver for STM32F1xx and STM32L1xx, it simplifies the use of the RCC resources and hides most differences found among the various STM32 sub-families. @@ -140,7 +140,7 @@ easier maintenance. - NEW: Improved stack checking and reorganized memory map for the Cortex-Mx demos. Now stacks are allocated at the start of the RAM, an overflow of the - exception stack now triggers an exception (it could went unnoticed before). + exception stack now triggers an exception (it could go unnoticed before). The process stack is organized to be checked on context switch like other threads. Now all threads have an explicit stack boundary pointer. (TODO: documentation to be updated) diff --git a/test/test.dox b/test/test.dox index 296e2145e..ab937f9a2 100644 --- a/test/test.dox +++ b/test/test.dox @@ -52,9 +52,9 @@ * the tests. Speed and size benchmarks for all the supported architectures * are performed, both size and speed regressions are monitored. * - HAL. The HAL high level code and device drivers implementations - * are tested by use in the various demos and/or by users. + * are tested through specific test applications under ./testhal. * - Various. The miscellaneous code is tested by use in the various - * demos and/or by users. + * demos. * - External Code. Not tested, external libraries or components are * used as-is or with minor patching where required, problems are usually * reported upstream. @@ -65,7 +65,7 @@ * subsystems and can report a failure/success status and/or a performance * index as the test suite output.
* The test suite is usually activated in the demo applications by pressing a - * button on the target board, see the readme into the various demos + * button on the target board, see the readme file into the various demos * directories. The test suite output is usually sent through a serial port * and can be examined by using a terminal emulator program. * diff --git a/testhal/STM32L1xx/ADC/Makefile b/testhal/STM32L1xx/ADC/Makefile new file mode 100644 index 000000000..9209b441d --- /dev/null +++ b/testhal/STM32L1xx/ADC/Makefile @@ -0,0 +1,202 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32L_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32L1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32L1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32L152xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32L1xx/ADC/chconf.h b/testhal/STM32L1xx/ADC/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32L1xx/ADC/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/ADC/halconf.h b/testhal/STM32L1xx/ADC/halconf.h new file mode 100644 index 000000000..62cc1e67d --- /dev/null +++ b/testhal/STM32L1xx/ADC/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c new file mode 100644 index 000000000..48616f7d8 --- /dev/null +++ b/testhal/STM32L1xx/ADC/main.c @@ -0,0 +1,124 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 8 +#define ADC_GRP1_BUF_DEPTH 16 + +static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples == buffer) { + nx += n; + } + else { + ny += n; + } +} + +/* + * ADC conversion group. + * Mode: Streaming, continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg = { + TRUE, + ADC_GRP1_NUM_CHANNELS, + adccallback, + 0, 0, /* CR1, CR2 */ + 0, 0, 0, /* SMPR1...SMPR3 */ + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, 0, /* SQR2, SQR3 */ + ADC_SQR4_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR4_SQ7_N(ADC_CHANNEL_VREFINT), + ADC_SQR5_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ5_N(ADC_CHANNEL_IN10) | + ADC_SQR5_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ3_N(ADC_CHANNEL_IN10) | + ADC_SQR5_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOB, GPIOB_LED4); + chThdSleepMilliseconds(500); + palSetPad(GPIOB, GPIOB_LED4); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Setting up analog inputs used by the demo. + */ + palSetGroupMode(GPIOC, PAL_PORT_BIT(0) | PAL_PORT_BIT(1), + PAL_MODE_INPUT_ANALOG); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Starts an ADC continuous conversion. + */ + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + adcStartConversion(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + adcStopConversion(&ADCD1); + adcSTM32DisableTSVREFE(); + } + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32L1xx/ADC/mcuconf.h b/testhal/STM32L1xx/ADC/mcuconf.h new file mode 100644 index 000000000..d214c9d12 --- /dev/null +++ b/testhal/STM32L1xx/ADC/mcuconf.h @@ -0,0 +1,185 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_1P8 +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLMUL_VALUE 6 +#define STM32_PLLDIV_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32L1xx/ADC/readme.txt b/testhal/STM32L1xx/ADC/readme.txt new file mode 100644 index 000000000..adceab611 --- /dev/null +++ b/testhal/STM32L1xx/ADC/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32L1xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx ADC driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From 8dfb19e4364eac8aea8f4fe1196cd0d0d6d4c266 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 21 Sep 2011 17:42:30 +0000 Subject: RTC. Minor documentation improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3378 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/rtc_lld.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c index 6ae2a4aee..c1163d1a1 100644 --- a/os/hal/platforms/STM32/rtc_lld.c +++ b/os/hal/platforms/STM32/rtc_lld.c @@ -109,13 +109,15 @@ CH_IRQ_HANDLER(RTC_IRQHandler) { * @brief Enable access to registers and initialize RTC if BKP domain * was previously reseted. * + * @note: Cold start time of LSE oscillator on STM32 platform + * takes about 3 seconds. + * * @notapi */ void rtc_lld_init(void){ uint32_t preload = 0; rccEnableBKPInterface(FALSE); - //RCC->APB1ENR |= (RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN); /* enable access to BKP registers */ PWR->CR |= PWR_CR_DBP; @@ -124,8 +126,7 @@ void rtc_lld_init(void){ #if STM32_RTC == STM32_RTC_LSE if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ - RCC->BDCR |= RCC_BDCR_LSEON; - /* Note: cold start time of LSE oscillator on STM32 is about 3 seconds. */ + RCC->BDCR |= RCC_BDCR_LSEON; while(!(RCC->BDCR & RCC_BDCR_LSERDY)) ; RCC->BDCR |= RCC_BDCR_RTCEN; -- cgit v1.2.3 From 4ffade31534ae304e78c1992b65fc6f1cd1bddeb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 21 Sep 2011 19:23:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3379 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/spi_lld.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index 7041ef854..194a386a7 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -214,12 +214,12 @@ void spi_lld_start(SPIDriver *spip) { #if STM32_SPI_USE_SPI3 if (&SPID3 == spip) { bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM1, + b = dmaStreamAllocate(STM32_DMA2_STREAM1, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM2, + b = dmaStreamAllocate(STM32_DMA2_STREAM2, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); -- cgit v1.2.3 From 40c7a8982aaef28d6ac7cbbd378708f237711ccf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 21 Sep 2011 19:31:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3380 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/spi_lld.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index 194a386a7..f8ec8546c 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -284,8 +284,8 @@ void spi_lld_stop(SPIDriver *spip) { #endif #if STM32_SPI_USE_SPI3 if (&SPID3 == spip) { - dmaStreamRelease(STM32_DMA1_STREAM1); - dmaStreamRelease(STM32_DMA1_STREAM2); + dmaStreamRelease(STM32_DMA2_STREAM1); + dmaStreamRelease(STM32_DMA2_STREAM2); rccDisableSPI3(FALSE); } #endif -- cgit v1.2.3 From 4a3e3fc01ec6dfb4a710db771bee262d5dc9327e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 22 Sep 2011 14:53:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3381 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/dox/adc.dox | 16 ++++++++--- os/hal/include/adc.h | 49 +++++++++++++++++++++++++++++++++- os/hal/platforms/STM32F1xx/adc_lld.c | 26 +++++++++--------- os/hal/platforms/STM32F1xx/adc_lld.h | 30 ++++++++++++++------- os/hal/platforms/STM32L1xx/adc_lld.c | 51 +++++++++++++++++++++++++++--------- os/hal/platforms/STM32L1xx/adc_lld.h | 34 ++++++++++++++++-------- os/hal/src/adc.c | 7 ++++- readme.txt | 7 ++++- testhal/STM32F1xx/ADC/main.c | 7 +++++ testhal/STM32L1xx/ADC/main.c | 7 +++++ 10 files changed, 182 insertions(+), 52 deletions(-) diff --git a/os/hal/dox/adc.dox b/os/hal/dox/adc.dox index bb8ff014f..53bfb75d2 100644 --- a/os/hal/dox/adc.dox +++ b/os/hal/dox/adc.dox @@ -34,8 +34,9 @@ * @if LATEX_PDF * @dot digraph example { - size="5, 7"; rankdir="LR"; + size="5, 7"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; edge [fontname=Helvetica, fontsize=8]; @@ -43,6 +44,7 @@ uninit [label="ADC_UNINIT", style="bold"]; ready [label="ADC_READY\nClock Enabled"]; active [label="ADC_ACTIVE\nConverting"]; + error [label="ADC_ERROR\nError"]; complete [label="ADC_COMPLETE\nComplete"]; uninit -> stop [label="\n adcInit()", constraint=false]; @@ -53,15 +55,19 @@ ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"]; active -> ready [label="\nadcStopConversion()\nsync return"]; active -> active [label="\nasync callback (half buffer)\nasync callback (full buffer circular)\n>acg_endcb<"]; - active -> complete [label="\nasync callback (full buffer)\n>acg_endcb<"]; + active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"]; + active -> error [label="\n\nasync callback (error)\n>error_cb<"]; complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; complete -> ready [label="\ncallback return"]; + error -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + error -> ready [label="\ncallback return"]; } * @enddot * @else * @dot digraph example { rankdir="LR"; + node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.9", height="0.9"]; edge [fontname=Helvetica, fontsize=8]; @@ -69,6 +75,7 @@ uninit [label="ADC_UNINIT", style="bold"]; ready [label="ADC_READY\nClock Enabled"]; active [label="ADC_ACTIVE\nConverting"]; + error [label="ADC_ERROR\nError"]; complete [label="ADC_COMPLETE\nComplete"]; uninit -> stop [label="\n adcInit()", constraint=false]; @@ -79,9 +86,12 @@ ready -> active [label="\nadcStartConversion() (async)\nadcConvert() (sync)"]; active -> ready [label="\nadcStopConversion()\nsync return"]; active -> active [label="\nasync callback (half buffer)\nasync callback (full buffer circular)\n>acg_endcb<"]; - active -> complete [label="\nasync callback (full buffer)\n>acg_endcb<"]; + active -> complete [label="\n\nasync callback (full buffer)\n>end_cb<"]; + active -> error [label="\n\nasync callback (error)\n>error_cb<"]; complete -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; complete -> ready [label="\ncallback return"]; + error -> active [label="\nadcStartConversionI()\nthen\ncallback return"]; + error -> ready [label="\ncallback return"]; } * @enddot * @endif diff --git a/os/hal/include/adc.h b/os/hal/include/adc.h index 53c7c199a..cb392f4e2 100644 --- a/os/hal/include/adc.h +++ b/os/hal/include/adc.h @@ -80,7 +80,8 @@ typedef enum { ADC_STOP = 1, /**< Stopped. */ ADC_READY = 2, /**< Ready. */ ADC_ACTIVE = 3, /**< Converting. */ - ADC_COMPLETE = 4 /**< Conversion complete. */ + ADC_COMPLETE = 4, /**< Conversion complete. */ + ADC_ERROR = 5 /**< Conversion complete. */ } adcstate_t; #include "adc_lld.h" @@ -144,10 +145,30 @@ typedef enum { } \ } +/** + * @brief Wakes up the waiting thread with a timeout message. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_timeout_isr(adcp) { \ + if ((adcp)->thread != NULL) { \ + Thread *tp; \ + chSysLockFromIsr(); \ + tp = (adcp)->thread; \ + (adcp)->thread = NULL; \ + tp->p_u.rdymsg = RDY_TIMEOUT; \ + chSchReadyI(tp); \ + chSysUnlockFromIsr(); \ + } \ +} + #else /* !ADC_USE_WAIT */ #define _adc_reset_i(adcp) #define _adc_reset_s(adcp) #define _adc_wakeup_isr(adcp) +#define _adc_timeout_isr(adcp) #endif /* !ADC_USE_WAIT */ /** @@ -220,6 +241,32 @@ typedef enum { _adc_wakeup_isr(adcp); \ } \ } + +/** + * @brief Common ISR code, error event. + * @details This code handles the portable part of the ISR code: + * - Callback invocation. + * - Waiting thread timeout signaling, if any. + * - Driver state transitions. + * . + * @note This macro is meant to be used in the low level drivers + * implementation only. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +#define _adc_isr_error_code(adcp, err) { \ + adc_lld_stop_conversion(adcp); \ + if ((adcp)->grpp->error_cb != NULL) { \ + (adcp)->state = ADC_ERROR; \ + (adcp)->grpp->error_cb(adcp, err); \ + if ((adcp)->state == ADC_ERROR) \ + (adcp)->state = ADC_READY; \ + } \ + (adcp)->grpp = NULL; \ + _adc_timeout_isr(adcp); \ +} /** @} */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/adc_lld.c b/os/hal/platforms/STM32F1xx/adc_lld.c index ac74251f8..84b194c0f 100644 --- a/os/hal/platforms/STM32F1xx/adc_lld.c +++ b/os/hal/platforms/STM32F1xx/adc_lld.c @@ -57,20 +57,20 @@ ADCDriver ADCD1; static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { /* DMA errors handling.*/ -#if defined(STM32_ADC_DMA_ERROR_HOOK) if ((flags & STM32_DMA_ISR_TEIF) != 0) { - STM32_ADC_DMA_ERROR_HOOK(spip); + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); } -#else - (void)flags; -#endif - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); + else { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } } } @@ -146,7 +146,7 @@ void adc_lld_start(ADCDriver *adcp) { /* ADC setup, the calibration procedure has already been performed during initialization.*/ - adcp->adc->CR1 = ADC_CR1_SCAN; + adcp->adc->CR1 = 0; adcp->adc->CR2 = 0; } } diff --git a/os/hal/platforms/STM32F1xx/adc_lld.h b/os/hal/platforms/STM32F1xx/adc_lld.h index 1d1052f50..e3a327afa 100644 --- a/os/hal/platforms/STM32F1xx/adc_lld.h +++ b/os/hal/platforms/STM32F1xx/adc_lld.h @@ -108,15 +108,6 @@ #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #endif -/** - * @brief ADC DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_ADC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() -#endif - /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -147,6 +138,15 @@ typedef uint16_t adcsample_t; */ typedef uint16_t adc_channels_num_t; +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */ +} adcerror_t; + /** * @brief Type of a structure representing an ADC driver. */ @@ -162,6 +162,14 @@ typedef struct ADCDriver ADCDriver; */ typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + /** * @brief Conversion group configuration structure. * @details This implementation-dependent structure describes a conversion @@ -183,6 +191,10 @@ typedef struct { * @brief Callback function associated to the group or @p NULL. */ adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; /* End of the mandatory fields.*/ /** * @brief ADC CR1 register initialization data. diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c index 9ccb198e4..a2149b6ae 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.c +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -57,20 +57,20 @@ ADCDriver ADCD1; static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { /* DMA errors handling.*/ -#if defined(STM32_ADC_DMA_ERROR_HOOK) if ((flags & STM32_DMA_ISR_TEIF) != 0) { - STM32_ADC_DMA_ERROR_HOOK(spip); + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); } -#else - (void)flags; -#endif - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); + else { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } } } @@ -78,6 +78,29 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { /* Driver interrupt handlers. */ /*===========================================================================*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +/** + * @brief ADC1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(UART5_IRQHandler) { + uint32_t sr; + + CH_IRQ_PROLOGUE(); + + sr = ADC1->SR; + ADC1->SR = 0; + if (sr & ADC_SR_OVR) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + } + + CH_IRQ_EPILOGUE(); +} +#endif + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -145,6 +168,7 @@ void adc_lld_stop(ADCDriver *adcp) { if (adcp->state == ADC_READY) { #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) { + ADC1->CR1 = 0; ADC1->CR2 = 0; dmaStreamRelease(adcp->dmastp); rccDisableADC1(FALSE); @@ -182,7 +206,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC setup.*/ adcp->adc->SR = 0; - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ adcp->adc->SMPR2 = grpp->smpr2; adcp->adc->SMPR3 = grpp->smpr3; @@ -211,6 +235,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { void adc_lld_stop_conversion(ADCDriver *adcp) { dmaStreamDisable(adcp->dmastp); + adcp->adc->CR1 = 0; adcp->adc->CR2 = 0; } diff --git a/os/hal/platforms/STM32L1xx/adc_lld.h b/os/hal/platforms/STM32L1xx/adc_lld.h index 2889387ab..0ca41c269 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.h +++ b/os/hal/platforms/STM32L1xx/adc_lld.h @@ -39,8 +39,7 @@ * @name Triggers selection * @{ */ -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ -#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ /** @} */ /** @@ -136,15 +135,6 @@ #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #endif -/** - * @brief ADC DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_ADC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() -#endif - /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -175,6 +165,16 @@ typedef uint16_t adcsample_t; */ typedef uint16_t adc_channels_num_t; +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ +} adcerror_t; + /** * @brief Type of a structure representing an ADC driver. */ @@ -190,6 +190,14 @@ typedef struct ADCDriver ADCDriver; */ typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + /** * @brief Conversion group configuration structure. * @details This implementation-dependent structure describes a conversion @@ -211,6 +219,10 @@ typedef struct { * @brief Callback function associated to the group or @p NULL. */ adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; /* End of the mandatory fields.*/ /** * @brief ADC CR1 register initialization data. diff --git a/os/hal/src/adc.c b/os/hal/src/adc.c index c375818a6..08aa830f0 100644 --- a/os/hal/src/adc.c +++ b/os/hal/src/adc.c @@ -162,6 +162,8 @@ void adcStartConversion(ADCDriver *adcp, /** * @brief Starts an ADC conversion. * @details Starts an asynchronous conversion operation. + * @post The callbacks associated to the conversion group will be invoked + * on buffer fill and error events. * @note The buffer is organized as a matrix of M*N elements where M is the * channels number configured into the conversion group and N is the * buffer depth. The samples are sequentially written into the buffer @@ -185,7 +187,8 @@ void adcStartConversionI(ADCDriver *adcp, ((depth == 1) || ((depth & 1) == 0)), "adcStartConversionI"); chDbgAssert((adcp->state == ADC_READY) || - (adcp->state == ADC_COMPLETE), + (adcp->state == ADC_COMPLETE) || + (adcp->state == ADC_ERROR), "adcStartConversionI(), #1", "not ready"); adcp->samples = samples; @@ -268,6 +271,8 @@ void adcStopConversionI(ADCDriver *adcp) { * @retval RDY_RESET The conversion has been stopped using * @p acdStopConversion() or @p acdStopConversionI(), * the result buffer may contain incorrect data. + * @retval RDY_TIMEOUT The conversion has been stopped because an hardware + * error. * * @api */ diff --git a/readme.txt b/readme.txt index 005520649..29dfbdca2 100644 --- a/readme.txt +++ b/readme.txt @@ -95,7 +95,12 @@ (backported to 2.2.4). - FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420) (backported to 2.2.4). -- NEW: STM32L1xx sub-family support, all STM32 drivers adapted and retested +- NEW: STM32L ADC driver implementation. + (TODO: To be tested.) +- NEW: Improved ADC driver model, now it is possible to handle error + conditions during the conversion process. + (TODO: Modify existing STM32 ADC implementation). +- NEW: STM32L1xx sub-family support, all STM32 drivers adapted and re-tested on the new platform except ADC that will need a specific implementation. - NEW: Added new API chThdExitS() in order to allow atomic operations on thead exit (backported to 2.2.8). diff --git a/testhal/STM32F1xx/ADC/main.c b/testhal/STM32F1xx/ADC/main.c index 214f28b5f..bfb717b17 100644 --- a/testhal/STM32F1xx/ADC/main.c +++ b/testhal/STM32F1xx/ADC/main.c @@ -41,6 +41,12 @@ static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { } } +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + /* * ADC conversion group. * Mode: Streaming, continuous, 16 samples of 8 channels, SW triggered. @@ -50,6 +56,7 @@ static const ADCConversionGroup adcgrpcfg = { TRUE, ADC_GRP1_NUM_CHANNELS, adccallback, + adcerrorcallback, 0, ADC_CR2_TSVREFE, 0, diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c index 48616f7d8..82ac4c4d8 100644 --- a/testhal/STM32L1xx/ADC/main.c +++ b/testhal/STM32L1xx/ADC/main.c @@ -41,6 +41,12 @@ static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { } } +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + /* * ADC conversion group. * Mode: Streaming, continuous, 16 samples of 8 channels, SW triggered. @@ -50,6 +56,7 @@ static const ADCConversionGroup adcgrpcfg = { TRUE, ADC_GRP1_NUM_CHANNELS, adccallback, + adcerrorcallback, 0, 0, /* CR1, CR2 */ 0, 0, 0, /* SMPR1...SMPR3 */ ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), -- cgit v1.2.3 From f20a38b371b2e6e65dc58393f581696e3ec623cc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 22 Sep 2011 17:15:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3382 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/SDC/Makefile | 207 +++++++++++++++ testhal/STM32F1xx/SDC/chconf.h | 535 ++++++++++++++++++++++++++++++++++++++ testhal/STM32F1xx/SDC/halconf.h | 328 +++++++++++++++++++++++ testhal/STM32F1xx/SDC/main.c | 113 ++++++++ testhal/STM32F1xx/SDC/mcuconf.h | 182 +++++++++++++ testhal/STM32F1xx/SDC/readme.txt | 26 ++ testhal/STM32F1xx/SDIO/Makefile | 207 --------------- testhal/STM32F1xx/SDIO/chconf.h | 535 -------------------------------------- testhal/STM32F1xx/SDIO/halconf.h | 328 ----------------------- testhal/STM32F1xx/SDIO/main.c | 113 -------- testhal/STM32F1xx/SDIO/mcuconf.h | 182 ------------- testhal/STM32F1xx/SDIO/readme.txt | 26 -- 12 files changed, 1391 insertions(+), 1391 deletions(-) create mode 100644 testhal/STM32F1xx/SDC/Makefile create mode 100644 testhal/STM32F1xx/SDC/chconf.h create mode 100644 testhal/STM32F1xx/SDC/halconf.h create mode 100644 testhal/STM32F1xx/SDC/main.c create mode 100644 testhal/STM32F1xx/SDC/mcuconf.h create mode 100644 testhal/STM32F1xx/SDC/readme.txt delete mode 100644 testhal/STM32F1xx/SDIO/Makefile delete mode 100644 testhal/STM32F1xx/SDIO/chconf.h delete mode 100644 testhal/STM32F1xx/SDIO/halconf.h delete mode 100644 testhal/STM32F1xx/SDIO/main.c delete mode 100644 testhal/STM32F1xx/SDIO/mcuconf.h delete mode 100644 testhal/STM32F1xx/SDIO/readme.txt diff --git a/testhal/STM32F1xx/SDC/Makefile b/testhal/STM32F1xx/SDC/Makefile new file mode 100644 index 000000000..71c4ec604 --- /dev/null +++ b/testhal/STM32F1xx/SDC/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM3210E_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F103xE.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/SDC/chconf.h b/testhal/STM32F1xx/SDC/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F1xx/SDC/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/SDC/halconf.h b/testhal/STM32F1xx/SDC/halconf.h new file mode 100644 index 000000000..9aa7cd21e --- /dev/null +++ b/testhal/STM32F1xx/SDC/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F1xx/SDC/main.c b/testhal/STM32F1xx/SDC/main.c new file mode 100644 index 000000000..9736f0268 --- /dev/null +++ b/testhal/STM32F1xx/SDC/main.c @@ -0,0 +1,113 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/* + * SDIO configuration. + */ +static const SDCConfig sdccfg = { + 0 +}; + +static uint8_t blkbuf[SDC_BLOCK_SIZE * 4 + 1]; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the SDIO drivers. + */ + sdcStart(&SDCD1, &sdccfg); + if (!sdcConnect(&SDCD1)) { + int i; + + /* Single aligned read.*/ + if (sdcRead(&SDCD1, 0, blkbuf, 1)) + chSysHalt(); + + /* Single unaligned read.*/ + if (sdcRead(&SDCD1, 0, blkbuf + 1, 1)) + chSysHalt(); + + /* Multiple aligned read.*/ + if (sdcRead(&SDCD1, 0, blkbuf, 4)) + chSysHalt(); + + /* Multiple unaligned read.*/ + if (sdcRead(&SDCD1, 0, blkbuf + 1, 4)) + chSysHalt(); + + /* Repeated multiple aligned reads.*/ + for (i = 0; i < 1000; i++) { + if (sdcRead(&SDCD1, 0, blkbuf, 4)) + chSysHalt(); + } + + /* Repeated multiple unaligned reads.*/ + for (i = 0; i < 1000; i++) { + if (sdcRead(&SDCD1, 0, blkbuf + 1, 4)) + chSysHalt(); + } + + /* Repeated multiple aligned writes.*/ + for (i = 0; i < 100; i++) { + if (sdcRead(&SDCD1, 0x10000, blkbuf, 4)) + chSysHalt(); + if (sdcWrite(&SDCD1, 0x10000, blkbuf, 4)) + chSysHalt(); + if (sdcWrite(&SDCD1, 0x10000, blkbuf, 4)) + chSysHalt(); + } + + /* Repeated multiple unaligned writes.*/ + for (i = 0; i < 100; i++) { + if (sdcRead(&SDCD1, 0x10000, blkbuf + 1, 4)) + chSysHalt(); + if (sdcWrite(&SDCD1, 0x10000, blkbuf + 1, 4)) + chSysHalt(); + if (sdcWrite(&SDCD1, 0x10000, blkbuf + 1, 4)) + chSysHalt(); + } + + if (sdcDisconnect(&SDCD1)) + chSysHalt(); + } + + /* + * Normal main() thread activity. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F1xx/SDC/mcuconf.h b/testhal/STM32F1xx/SDC/mcuconf.h new file mode 100644 index 000000000..1af95abfd --- /dev/null +++ b/testhal/STM32F1xx/SDC/mcuconf.h @@ -0,0 +1,182 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCO STM32_MCO_NOCLOCK + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_DATATIMEOUT 0x000FFFFF +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F1xx/SDC/readme.txt b/testhal/STM32F1xx/SDC/readme.txt new file mode 100644 index 000000000..de5af6948 --- /dev/null +++ b/testhal/STM32F1xx/SDC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - SDC driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex ST_STM3210E_EVAL board. + +** The Demo ** + +The application demonstrates the use of the STM32 SDC driver. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F1xx/SDIO/Makefile b/testhal/STM32F1xx/SDIO/Makefile deleted file mode 100644 index 71c4ec604..000000000 --- a/testhal/STM32F1xx/SDIO/Makefile +++ /dev/null @@ -1,207 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Enable this if you really want to use the STM FWLib. -ifeq ($(USE_FWLIB),) - USE_FWLIB = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files and paths -CHIBIOS = ../../.. -include $(CHIBIOS)/boards/ST_STM3210E_EVAL/board.mk -include $(CHIBIOS)/os/hal/platforms/STM32F1xx/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -#include $(CHIBIOS)/test/test.mk - -# Define linker script file here -LDSCRIPT= $(PORTLD)/STM32F103xE.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m3 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -ifeq ($(USE_FWLIB),yes) - include $(CHIBIOS)/ext/stm32lib/stm32lib.mk - CSRC += $(STM32SRC) - INCDIR += $(STM32INC) - USE_OPT += -DUSE_STDPERIPH_DRIVER -endif - -include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F1xx/SDIO/chconf.h b/testhal/STM32F1xx/SDIO/chconf.h deleted file mode 100644 index a5d129956..000000000 --- a/testhal/STM32F1xx/SDIO/chconf.h +++ /dev/null @@ -1,535 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_MEMCORE. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread automatically. The application has - * then the responsibility to do one of the following: - * - Spawn a custom idle thread at priority @p IDLEPRIO. - * - Change the main() thread priority to @p IDLEPRIO then enter - * an endless loop. In this scenario the @p main() thread acts as - * the idle thread. - * . - * @note Unless an idle thread is spawned the @p main() thread must not - * enter a sleep state. - */ -#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) -#define CH_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS TRUE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS TRUE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE TRUE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ - /* Add threads custom fields here.*/ -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) -#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* System halt code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_TICK_EVENT_HOOK() { \ - /* System tick event code here.*/ \ -} -#endif - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_HALT_HOOK() { \ - /* System halt code here.*/ \ -} -#endif - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/testhal/STM32F1xx/SDIO/halconf.h b/testhal/STM32F1xx/SDIO/halconf.h deleted file mode 100644 index 9aa7cd21e..000000000 --- a/testhal/STM32F1xx/SDIO/halconf.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC TRUE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Block size for MMC transfers. - */ -#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) -#define MMC_SECTOR_SIZE 512 -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/** - * @brief Number of positive insertion queries before generating the - * insertion event. - */ -#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) -#define MMC_POLLING_INTERVAL 10 -#endif - -/** - * @brief Interval, in milliseconds, between insertion queries. - */ -#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) -#define MMC_POLLING_DELAY 10 -#endif - -/** - * @brief Uses the SPI polled API for small data transfers. - * @details Polled transfers usually improve performance because it - * saves two context switches and interrupt servicing. Note - * that this option has no effect on large transfers which - * are always performed using DMAs/IRQs. - */ -#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) -#define MMC_USE_SPI_POLLING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intevals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 38400 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 64 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/testhal/STM32F1xx/SDIO/main.c b/testhal/STM32F1xx/SDIO/main.c deleted file mode 100644 index 9736f0268..000000000 --- a/testhal/STM32F1xx/SDIO/main.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -/* - * SDIO configuration. - */ -static const SDCConfig sdccfg = { - 0 -}; - -static uint8_t blkbuf[SDC_BLOCK_SIZE * 4 + 1]; - -/* - * Application entry point. - */ -int main(void) { - - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - - /* - * Initializes the SDIO drivers. - */ - sdcStart(&SDCD1, &sdccfg); - if (!sdcConnect(&SDCD1)) { - int i; - - /* Single aligned read.*/ - if (sdcRead(&SDCD1, 0, blkbuf, 1)) - chSysHalt(); - - /* Single unaligned read.*/ - if (sdcRead(&SDCD1, 0, blkbuf + 1, 1)) - chSysHalt(); - - /* Multiple aligned read.*/ - if (sdcRead(&SDCD1, 0, blkbuf, 4)) - chSysHalt(); - - /* Multiple unaligned read.*/ - if (sdcRead(&SDCD1, 0, blkbuf + 1, 4)) - chSysHalt(); - - /* Repeated multiple aligned reads.*/ - for (i = 0; i < 1000; i++) { - if (sdcRead(&SDCD1, 0, blkbuf, 4)) - chSysHalt(); - } - - /* Repeated multiple unaligned reads.*/ - for (i = 0; i < 1000; i++) { - if (sdcRead(&SDCD1, 0, blkbuf + 1, 4)) - chSysHalt(); - } - - /* Repeated multiple aligned writes.*/ - for (i = 0; i < 100; i++) { - if (sdcRead(&SDCD1, 0x10000, blkbuf, 4)) - chSysHalt(); - if (sdcWrite(&SDCD1, 0x10000, blkbuf, 4)) - chSysHalt(); - if (sdcWrite(&SDCD1, 0x10000, blkbuf, 4)) - chSysHalt(); - } - - /* Repeated multiple unaligned writes.*/ - for (i = 0; i < 100; i++) { - if (sdcRead(&SDCD1, 0x10000, blkbuf + 1, 4)) - chSysHalt(); - if (sdcWrite(&SDCD1, 0x10000, blkbuf + 1, 4)) - chSysHalt(); - if (sdcWrite(&SDCD1, 0x10000, blkbuf + 1, 4)) - chSysHalt(); - } - - if (sdcDisconnect(&SDCD1)) - chSysHalt(); - } - - /* - * Normal main() thread activity. - */ - while (TRUE) { - chThdSleepMilliseconds(500); - } -} diff --git a/testhal/STM32F1xx/SDIO/mcuconf.h b/testhal/STM32F1xx/SDIO/mcuconf.h deleted file mode 100644 index 1af95abfd..000000000 --- a/testhal/STM32F1xx/SDIO/mcuconf.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * STM32 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -/* - * HAL driver system settings. - */ -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_USBPRE STM32_USBPRE_DIV1P5 -#define STM32_MCO STM32_MCO_NOCLOCK - -/* - * ADC driver system settings. - */ -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 - -/* - * EXT driver system settings. - */ -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 TRUE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED TRUE -#define STM32_PWM_USE_TIM1 TRUE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_DATATIMEOUT 0x000FFFFF -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 TRUE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 TRUE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F1xx/SDIO/readme.txt b/testhal/STM32F1xx/SDIO/readme.txt deleted file mode 100644 index de5af6948..000000000 --- a/testhal/STM32F1xx/SDIO/readme.txt +++ /dev/null @@ -1,26 +0,0 @@ -***************************************************************************** -** ChibiOS/RT HAL - SDC driver demo for STM32. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex ST_STM3210E_EVAL board. - -** The Demo ** - -The application demonstrates the use of the STM32 SDC driver. - -** Build Procedure ** - -The demo has been tested by using the free Codesourcery GCC-based toolchain -and YAGARTO. -Just modify the TRGT line in the makefile in order to use different GCC ports. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are copyright of -ST Microelectronics and are licensed under a different license. -Also note that not all the files present in the ST library are distribited -with ChibiOS/RT, you can find the whole library on the ST web site: - - http://www.st.com -- cgit v1.2.3 From d2721c36a6d74fd18de7e4de95fdd166083e343e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 22 Sep 2011 17:22:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3383 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/LPC11xx/IRQ_STORM/.cproject | 256 +++++++++++++++++++++++++++ testhal/LPC11xx/IRQ_STORM/.project | 85 +++++++++ testhal/LPC13xx/IRQ_STORM/.cproject | 320 ++++++++++++++++++++++++++++++++++ testhal/LPC13xx/IRQ_STORM/.project | 84 +++++++++ testhal/STM32F1xx/ADC/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/ADC/.project | 85 +++++++++ testhal/STM32F1xx/CAN/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/CAN/.project | 85 +++++++++ testhal/STM32F1xx/EXT/.cproject | 211 ++++++++++++++++++++++ testhal/STM32F1xx/EXT/.project | 85 +++++++++ testhal/STM32F1xx/GPT/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/GPT/.project | 85 +++++++++ testhal/STM32F1xx/IRQ_STORM/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/IRQ_STORM/.project | 85 +++++++++ testhal/STM32F1xx/MAC/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/MAC/.project | 85 +++++++++ testhal/STM32F1xx/PWM-ICU/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/PWM-ICU/.project | 85 +++++++++ testhal/STM32F1xx/SDC/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/SDC/.project | 85 +++++++++ testhal/STM32F1xx/SPI/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/SPI/.project | 85 +++++++++ testhal/STM32F1xx/UART/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/UART/.project | 85 +++++++++ testhal/STM32F1xx/USB_CDC/.cproject | 210 ++++++++++++++++++++++ testhal/STM32F1xx/USB_CDC/.project | 85 +++++++++ testhal/STM32L1xx/ADC/.cproject | 210 ++++++++++++++++++++++ testhal/STM32L1xx/ADC/.project | 85 +++++++++ testhal/STM32L1xx/EXT/.cproject | 211 ++++++++++++++++++++++ testhal/STM32L1xx/EXT/.project | 85 +++++++++ testhal/STM32L1xx/GPT/.cproject | 210 ++++++++++++++++++++++ testhal/STM32L1xx/GPT/.project | 85 +++++++++ testhal/STM32L1xx/IRQ_STORM/.cproject | 210 ++++++++++++++++++++++ testhal/STM32L1xx/IRQ_STORM/.project | 85 +++++++++ testhal/STM32L1xx/PWM-ICU/.cproject | 210 ++++++++++++++++++++++ testhal/STM32L1xx/PWM-ICU/.project | 85 +++++++++ testhal/STM32L1xx/SPI/.cproject | 210 ++++++++++++++++++++++ testhal/STM32L1xx/SPI/.project | 85 +++++++++ testhal/STM32L1xx/UART/.cproject | 210 ++++++++++++++++++++++ testhal/STM32L1xx/UART/.project | 85 +++++++++ 40 files changed, 6057 insertions(+) create mode 100644 testhal/LPC11xx/IRQ_STORM/.cproject create mode 100644 testhal/LPC11xx/IRQ_STORM/.project create mode 100644 testhal/LPC13xx/IRQ_STORM/.cproject create mode 100644 testhal/LPC13xx/IRQ_STORM/.project create mode 100644 testhal/STM32F1xx/ADC/.cproject create mode 100644 testhal/STM32F1xx/ADC/.project create mode 100644 testhal/STM32F1xx/CAN/.cproject create mode 100644 testhal/STM32F1xx/CAN/.project create mode 100644 testhal/STM32F1xx/EXT/.cproject create mode 100644 testhal/STM32F1xx/EXT/.project create mode 100644 testhal/STM32F1xx/GPT/.cproject create mode 100644 testhal/STM32F1xx/GPT/.project create mode 100644 testhal/STM32F1xx/IRQ_STORM/.cproject create mode 100644 testhal/STM32F1xx/IRQ_STORM/.project create mode 100644 testhal/STM32F1xx/MAC/.cproject create mode 100644 testhal/STM32F1xx/MAC/.project create mode 100644 testhal/STM32F1xx/PWM-ICU/.cproject create mode 100644 testhal/STM32F1xx/PWM-ICU/.project create mode 100644 testhal/STM32F1xx/SDC/.cproject create mode 100644 testhal/STM32F1xx/SDC/.project create mode 100644 testhal/STM32F1xx/SPI/.cproject create mode 100644 testhal/STM32F1xx/SPI/.project create mode 100644 testhal/STM32F1xx/UART/.cproject create mode 100644 testhal/STM32F1xx/UART/.project create mode 100644 testhal/STM32F1xx/USB_CDC/.cproject create mode 100644 testhal/STM32F1xx/USB_CDC/.project create mode 100644 testhal/STM32L1xx/ADC/.cproject create mode 100644 testhal/STM32L1xx/ADC/.project create mode 100644 testhal/STM32L1xx/EXT/.cproject create mode 100644 testhal/STM32L1xx/EXT/.project create mode 100644 testhal/STM32L1xx/GPT/.cproject create mode 100644 testhal/STM32L1xx/GPT/.project create mode 100644 testhal/STM32L1xx/IRQ_STORM/.cproject create mode 100644 testhal/STM32L1xx/IRQ_STORM/.project create mode 100644 testhal/STM32L1xx/PWM-ICU/.cproject create mode 100644 testhal/STM32L1xx/PWM-ICU/.project create mode 100644 testhal/STM32L1xx/SPI/.cproject create mode 100644 testhal/STM32L1xx/SPI/.project create mode 100644 testhal/STM32L1xx/UART/.cproject create mode 100644 testhal/STM32L1xx/UART/.project diff --git a/testhal/LPC11xx/IRQ_STORM/.cproject b/testhal/LPC11xx/IRQ_STORM/.cproject new file mode 100644 index 000000000..5f093f95a --- /dev/null +++ b/testhal/LPC11xx/IRQ_STORM/.cproject @@ -0,0 +1,256 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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location="0" size="0x8000"/> +<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> +<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x400" progwithcode="TRUE" size="0x8000"/> +<peripheralInstance derived_from="LPC11_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> +<peripheralInstance derived_from="LPC11_PMU" determined="infoFile" id="PMU" location="0x40038000"/> +<peripheralInstance derived_from="CM0_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> +<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> +<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> +<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> +<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> +<peripheralInstance derived_from="LPC11_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> +<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> +<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> +<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP0" location="0x40040000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40014000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER1" location="0x40018000"/> +<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> +<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> +</chip> +<processor> +<name gcc_name="cortex-m0">Cortex-M0</name> +<family>Cortex-M</family> +</processor> +<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + diff --git a/testhal/LPC11xx/IRQ_STORM/.project b/testhal/LPC11xx/IRQ_STORM/.project new file mode 100644 index 000000000..f5e6fe20e --- /dev/null +++ b/testhal/LPC11xx/IRQ_STORM/.project @@ -0,0 +1,85 @@ + + + TEST-LPC11xx-IRQ_STORM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/LPC13xx/IRQ_STORM/.cproject b/testhal/LPC13xx/IRQ_STORM/.cproject new file mode 100644 index 000000000..c062ba7f7 --- /dev/null +++ b/testhal/LPC13xx/IRQ_STORM/.cproject @@ -0,0 +1,320 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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derived_from="Flash" id="MFlash32" location="0x00000000" size="0x8000"/> +<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> +<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x8000"/> +<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40014000"/> +<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER1" location="0x40018000"/> +<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> +<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP" location="0x40040000"/> +<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> +<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> +<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> +<peripheralInstance derived_from="LPC13_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> +<peripheralInstance derived_from="LPC11_13_PMU" determined="infoFile" id="PMU" location="0x40038000"/> +<peripheralInstance derived_from="LPC11_13_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> +<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> +<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> +<peripheralInstance derived_from="LPC11_13_USBDEV" determined="infoFile" id="USB" location="0x40020000"/> +<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> +</chip> +<processor> +<name gcc_name="cortex-m3">Cortex-M3</name> +<family>Cortex-M</family> +</processor> +<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> +</info> +</infoList> +</TargetConfig> + + diff --git a/testhal/LPC13xx/IRQ_STORM/.project b/testhal/LPC13xx/IRQ_STORM/.project new file mode 100644 index 000000000..b4f093c6c --- /dev/null +++ b/testhal/LPC13xx/IRQ_STORM/.project @@ -0,0 +1,84 @@ + + + TEST-LPC13xx-IRQ_STORM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/ADC/.cproject b/testhal/STM32F1xx/ADC/.cproject new file mode 100644 index 000000000..fba68fe83 --- /dev/null +++ b/testhal/STM32F1xx/ADC/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F1xx/ADC/.project b/testhal/STM32F1xx/ADC/.project new file mode 100644 index 000000000..3610ac9ec --- /dev/null +++ b/testhal/STM32F1xx/ADC/.project @@ -0,0 +1,85 @@ + + + TEST-STM32F1xx-ADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/CAN/.cproject b/testhal/STM32F1xx/CAN/.cproject new file mode 100644 index 000000000..fbcc3a335 --- /dev/null +++ b/testhal/STM32F1xx/CAN/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + 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org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/EXT/.cproject b/testhal/STM32F1xx/EXT/.cproject new file mode 100644 index 000000000..4b2106c19 --- /dev/null +++ b/testhal/STM32F1xx/EXT/.cproject @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/GPT/.cproject b/testhal/STM32F1xx/GPT/.cproject new file mode 100644 index 000000000..10b3e8c03 --- /dev/null +++ b/testhal/STM32F1xx/GPT/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/IRQ_STORM/.cproject b/testhal/STM32F1xx/IRQ_STORM/.cproject new file mode 100644 index 000000000..8771fc884 --- /dev/null +++ b/testhal/STM32F1xx/IRQ_STORM/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/MAC/.cproject b/testhal/STM32F1xx/MAC/.cproject new file mode 100644 index 000000000..954ebcc89 --- /dev/null +++ b/testhal/STM32F1xx/MAC/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/PWM-ICU/.cproject b/testhal/STM32F1xx/PWM-ICU/.cproject new file mode 100644 index 000000000..0108209e1 --- /dev/null +++ b/testhal/STM32F1xx/PWM-ICU/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F1xx/PWM-ICU/.project b/testhal/STM32F1xx/PWM-ICU/.project new file mode 100644 index 000000000..590fdff0d --- /dev/null +++ b/testhal/STM32F1xx/PWM-ICU/.project @@ -0,0 +1,85 @@ + + + TEST-STM32F1xx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/SDC/.cproject b/testhal/STM32F1xx/SDC/.cproject new file mode 100644 index 000000000..e42edb41c --- /dev/null +++ b/testhal/STM32F1xx/SDC/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F1xx/SDC/.project b/testhal/STM32F1xx/SDC/.project new file mode 100644 index 000000000..f656b5f60 --- /dev/null +++ b/testhal/STM32F1xx/SDC/.project @@ -0,0 +1,85 @@ + + + TEST-STM32F1xx-SDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/SPI/.cproject b/testhal/STM32F1xx/SPI/.cproject new file mode 100644 index 000000000..644374b52 --- /dev/null +++ b/testhal/STM32F1xx/SPI/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F1xx/SPI/.project b/testhal/STM32F1xx/SPI/.project new file mode 100644 index 000000000..9818c23f7 --- /dev/null +++ b/testhal/STM32F1xx/SPI/.project @@ -0,0 +1,85 @@ + + + TEST-STM32F1xx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/UART/.cproject b/testhal/STM32F1xx/UART/.cproject new file mode 100644 index 000000000..7b03f8f70 --- /dev/null +++ b/testhal/STM32F1xx/UART/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F1xx/UART/.project b/testhal/STM32F1xx/UART/.project new file mode 100644 index 000000000..04165df15 --- /dev/null +++ b/testhal/STM32F1xx/UART/.project @@ -0,0 +1,85 @@ + + + TEST-STM32F1xx-UART + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32F1xx/USB_CDC/.cproject b/testhal/STM32F1xx/USB_CDC/.cproject new file mode 100644 index 000000000..72767d1c9 --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32F1xx/USB_CDC/.project b/testhal/STM32F1xx/USB_CDC/.project new file mode 100644 index 000000000..643a775d0 --- /dev/null +++ b/testhal/STM32F1xx/USB_CDC/.project @@ -0,0 +1,85 @@ + + + TEST-STM32F1xx-USB_CDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32L1xx/ADC/.cproject b/testhal/STM32L1xx/ADC/.cproject new file mode 100644 index 000000000..46dec9738 --- /dev/null +++ b/testhal/STM32L1xx/ADC/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/ADC/.project b/testhal/STM32L1xx/ADC/.project new file mode 100644 index 000000000..93c7da8ef --- /dev/null +++ b/testhal/STM32L1xx/ADC/.project @@ -0,0 +1,85 @@ + + + TEST-STM32L1xx-ADC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32L1xx/EXT/.cproject b/testhal/STM32L1xx/EXT/.cproject new file mode 100644 index 000000000..8fc88e937 --- /dev/null +++ b/testhal/STM32L1xx/EXT/.cproject @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/EXT/.project b/testhal/STM32L1xx/EXT/.project new file mode 100644 index 000000000..9153ff4a2 --- /dev/null +++ b/testhal/STM32L1xx/EXT/.project @@ -0,0 +1,85 @@ + + + TEST-STM32L1xx-EXT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32L1xx/GPT/.cproject b/testhal/STM32L1xx/GPT/.cproject new file mode 100644 index 000000000..b86a1ca62 --- /dev/null +++ b/testhal/STM32L1xx/GPT/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/GPT/.project b/testhal/STM32L1xx/GPT/.project new file mode 100644 index 000000000..a0bea0071 --- /dev/null +++ b/testhal/STM32L1xx/GPT/.project @@ -0,0 +1,85 @@ + + + TEST-STM32L1xx-GPT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32L1xx/IRQ_STORM/.cproject b/testhal/STM32L1xx/IRQ_STORM/.cproject new file mode 100644 index 000000000..fd11cb653 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/IRQ_STORM/.project b/testhal/STM32L1xx/IRQ_STORM/.project new file mode 100644 index 000000000..bbb5a4a93 --- /dev/null +++ b/testhal/STM32L1xx/IRQ_STORM/.project @@ -0,0 +1,85 @@ + + + TEST-STM32L1xx-IRQ_STORM + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32L1xx/PWM-ICU/.cproject b/testhal/STM32L1xx/PWM-ICU/.cproject new file mode 100644 index 000000000..075107e60 --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/PWM-ICU/.project b/testhal/STM32L1xx/PWM-ICU/.project new file mode 100644 index 000000000..6a4599f39 --- /dev/null +++ b/testhal/STM32L1xx/PWM-ICU/.project @@ -0,0 +1,85 @@ + + + TEST-STM32L1xx-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32L1xx/SPI/.cproject b/testhal/STM32L1xx/SPI/.cproject new file mode 100644 index 000000000..85ae1ed2f --- /dev/null +++ b/testhal/STM32L1xx/SPI/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/SPI/.project b/testhal/STM32L1xx/SPI/.project new file mode 100644 index 000000000..bcd828174 --- /dev/null +++ b/testhal/STM32L1xx/SPI/.project @@ -0,0 +1,85 @@ + + + TEST-STM32L1xx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + diff --git a/testhal/STM32L1xx/UART/.cproject b/testhal/STM32L1xx/UART/.cproject new file mode 100644 index 000000000..68e20f694 --- /dev/null +++ b/testhal/STM32L1xx/UART/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/STM32L1xx/UART/.project b/testhal/STM32L1xx/UART/.project new file mode 100644 index 000000000..ad5b96f16 --- /dev/null +++ b/testhal/STM32L1xx/UART/.project @@ -0,0 +1,85 @@ + + + TEST-STM32L1xx-UART + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + -- cgit v1.2.3 From c39d08fc2ae9c43f73114e24292520306bddde19 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 23 Sep 2011 15:48:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3384 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/.cproject | 211 ++++++++++++++++++ demos/ARM7-AT91SAM7S-FATFS-GCC/.project | 95 +++++++++ demos/ARM7-AT91SAM7S-GCC/.cproject | 211 ++++++++++++++++++ demos/ARM7-AT91SAM7S-GCC/.project | 90 ++++++++ demos/ARM7-AT91SAM7X-FATFS-GCC/.cproject | 211 ++++++++++++++++++ demos/ARM7-AT91SAM7X-FATFS-GCC/.project | 95 +++++++++ demos/ARM7-AT91SAM7X-GCC/.cproject | 274 ++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-GCC/.project | 94 ++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/.cproject | 230 ++++++++++++++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/.project | 94 ++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/.cproject | 210 ++++++++++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/.project | 94 ++++++++ demos/ARM7-LPC214x-FATFS-GCC/.cproject | 230 ++++++++++++++++++++ demos/ARM7-LPC214x-FATFS-GCC/.project | 94 ++++++++ demos/ARM7-LPC214x-G++/.cproject | 330 +++++++++++++++++++++++++++++ demos/ARM7-LPC214x-G++/.project | 91 ++++++++ demos/ARM7-LPC214x-GCC/.cproject | 252 ++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/.project | 90 ++++++++ demos/ARMCM0-LPC1114-LPCXPRESSO/.cproject | 211 ++++++++++++++++++ demos/ARMCM0-LPC1114-LPCXPRESSO/.project | 90 ++++++++ demos/ARMCM3-GENERIC-KERNEL/.cproject | 211 ++++++++++++++++++ demos/ARMCM3-GENERIC-KERNEL/.project | 90 ++++++++ demos/ARMCM3-LPC1343-LPCXPRESSO/.cproject | 211 ++++++++++++++++++ demos/ARMCM3-LPC1343-LPCXPRESSO/.project | 90 ++++++++ demos/ARMCM3-STM32F100-DISCOVERY/.cproject | 211 ++++++++++++++++++ demos/ARMCM3-STM32F100-DISCOVERY/.project | 90 ++++++++ demos/ARMCM3-STM32F103-FATFS/.cproject | 211 ++++++++++++++++++ demos/ARMCM3-STM32F103-FATFS/.project | 95 +++++++++ demos/ARMCM3-STM32F103-G++/.cproject | 211 ++++++++++++++++++ demos/ARMCM3-STM32F103-G++/.project | 90 ++++++++ demos/ARMCM3-STM32F103/.cproject | 222 +++++++++++++++++++ demos/ARMCM3-STM32F103/.project | 90 ++++++++ demos/ARMCM3-STM32F103ZG-FATFS/.cproject | 211 ++++++++++++++++++ demos/ARMCM3-STM32F103ZG-FATFS/.project | 95 +++++++++ demos/ARMCM3-STM32F107/.cproject | 211 ++++++++++++++++++ demos/ARMCM3-STM32F107/.project | 90 ++++++++ demos/ARMCM3-STM32L152-DISCOVERY/.cproject | 225 ++++++++++++++++++++ demos/ARMCM3-STM32L152-DISCOVERY/.project | 95 +++++++++ demos/AVR-AT90CANx-GCC/.cproject | 237 +++++++++++++++++++++ demos/AVR-AT90CANx-GCC/.project | 90 ++++++++ demos/AVR-ATmega128-GCC/.cproject | 237 +++++++++++++++++++++ demos/AVR-ATmega128-GCC/.project | 90 ++++++++ demos/MSP430-MSP430x1611-GCC/.cproject | 239 +++++++++++++++++++++ demos/MSP430-MSP430x1611-GCC/.project | 90 ++++++++ demos/PPC-SPC563-GCC/.cproject | 221 +++++++++++++++++++ demos/PPC-SPC563-GCC/.project | 89 ++++++++ demos/Posix-GCC/.cproject | 211 ++++++++++++++++++ demos/Posix-GCC/.project | 90 ++++++++ demos/Win32-MinGW/.cproject | 224 ++++++++++++++++++++ demos/Win32-MinGW/.project | 94 ++++++++ docs/src/concepts.dox | 16 +- os/hal/include/adc.h | 1 + os/hal/platforms/STM32F1xx/platform.dox | 20 +- os/hal/platforms/STM32L1xx/adc_lld.c | 5 +- os/hal/platforms/STM32L1xx/platform.dox | 40 +++- os/hal/templates/ext_lld.c | 7 + os/hal/templates/ext_lld.h | 19 +- os/kernel/src/chsys.c | 5 +- os/kernel/src/chthreads.c | 2 - os/ports/IAR/ARMCMx/port.dox | 26 +-- os/ports/RVCT/ARMCMx/port.dox | 26 +-- os/various/shell.c | 66 +++--- os/various/shell.h | 19 +- readme.txt | 13 +- test/test.c | 2 + test/test.dox | 4 +- testhal/STM32L1xx/ADC/readme.txt | 3 +- 67 files changed, 8120 insertions(+), 112 deletions(-) create mode 100644 demos/ARM7-AT91SAM7S-FATFS-GCC/.cproject create mode 100644 demos/ARM7-AT91SAM7S-FATFS-GCC/.project create mode 100644 demos/ARM7-AT91SAM7S-GCC/.cproject create mode 100644 demos/ARM7-AT91SAM7S-GCC/.project create mode 100644 demos/ARM7-AT91SAM7X-FATFS-GCC/.cproject create mode 100644 demos/ARM7-AT91SAM7X-FATFS-GCC/.project create mode 100644 demos/ARM7-AT91SAM7X-GCC/.cproject create mode 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+ + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/demos/ARMCM3-GENERIC-KERNEL/.cproject b/demos/ARMCM3-GENERIC-KERNEL/.cproject new file mode 100644 index 000000000..ad80b4b01 --- /dev/null +++ b/demos/ARMCM3-GENERIC-KERNEL/.cproject @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + 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file mode 100644 index 000000000..eb9549d21 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/.cproject @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F103-FATFS/.project b/demos/ARMCM3-STM32F103-FATFS/.project new file mode 100644 index 000000000..a91b339e0 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS/.project @@ -0,0 +1,95 @@ + + + ARMCM3-STM32F103-FATFS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + 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b/demos/ARMCM3-STM32F103-G++/.cproject new file mode 100644 index 000000000..d5333dc9b --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/.cproject @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F103-G++/.project b/demos/ARMCM3-STM32F103-G++/.project new file mode 100644 index 000000000..788add339 --- /dev/null +++ b/demos/ARMCM3-STM32F103-G++/.project @@ -0,0 +1,90 @@ + + + ARMCM3-STM32F103-G++ + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + 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a/demos/ARMCM3-STM32F103ZG-FATFS/.cproject b/demos/ARMCM3-STM32F103ZG-FATFS/.cproject new file mode 100644 index 000000000..7098fe8ab --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/.cproject @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/.project b/demos/ARMCM3-STM32F103ZG-FATFS/.project new file mode 100644 index 000000000..d1d8b526d --- /dev/null +++ b/demos/ARMCM3-STM32F103ZG-FATFS/.project @@ -0,0 +1,95 @@ + + + ARMCM3-STM32F103ZG-FATFS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + ext + 2 + WORKSPACE_LOC/ext + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/demos/ARMCM3-STM32F107/.cproject b/demos/ARMCM3-STM32F107/.cproject new file mode 100644 index 000000000..11dd04335 --- /dev/null +++ b/demos/ARMCM3-STM32F107/.cproject @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32F107/.project b/demos/ARMCM3-STM32F107/.project new file mode 100644 index 000000000..494b612bd --- /dev/null +++ b/demos/ARMCM3-STM32F107/.project @@ -0,0 +1,90 @@ + + + ARMCM3-STM32F107 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/.cproject b/demos/ARMCM3-STM32L152-DISCOVERY/.cproject new file mode 100644 index 000000000..5b1ca5446 --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/.cproject @@ -0,0 +1,225 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/.project b/demos/ARMCM3-STM32L152-DISCOVERY/.project new file mode 100644 index 000000000..8d768056f --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/.project @@ -0,0 +1,95 @@ + + + ARMCM3-STM32L152-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + ST_STM32L_DISCOVERY + 2 + WORKSPACE_LOC/boards/ST_STM32L_DISCOVERY + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/demos/AVR-AT90CANx-GCC/.cproject b/demos/AVR-AT90CANx-GCC/.cproject new file mode 100644 index 000000000..31d9e0ba0 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/.cproject @@ -0,0 +1,237 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/AVR-AT90CANx-GCC/.project b/demos/AVR-AT90CANx-GCC/.project new file mode 100644 index 000000000..70de8c973 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/.project @@ -0,0 +1,90 @@ + + + AVR-AT90CANx-GCC + + + _Common Files + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.cnature + + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/demos/AVR-ATmega128-GCC/.cproject b/demos/AVR-ATmega128-GCC/.cproject new file mode 100644 index 000000000..56d3ad8a5 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/.cproject @@ -0,0 +1,237 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/AVR-ATmega128-GCC/.project b/demos/AVR-ATmega128-GCC/.project new file mode 100644 index 000000000..d19dece00 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/.project @@ -0,0 +1,90 @@ + + + AVR-ATmega128-GCC + + + _Common Files + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.cnature + + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/demos/MSP430-MSP430x1611-GCC/.cproject b/demos/MSP430-MSP430x1611-GCC/.cproject new file mode 100644 index 000000000..a82daa0dc --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/.cproject @@ -0,0 +1,239 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/MSP430-MSP430x1611-GCC/.project b/demos/MSP430-MSP430x1611-GCC/.project new file mode 100644 index 000000000..58084f2d5 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/.project @@ -0,0 +1,90 @@ + + + MSP430-MSP430x1611-GCC + + + _Common Files + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.cnature + + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/demos/PPC-SPC563-GCC/.cproject b/demos/PPC-SPC563-GCC/.cproject new file mode 100644 index 000000000..346bab103 --- /dev/null +++ b/demos/PPC-SPC563-GCC/.cproject @@ -0,0 +1,221 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/PPC-SPC563-GCC/.project b/demos/PPC-SPC563-GCC/.project new file mode 100644 index 000000000..5acfbf892 --- /dev/null +++ b/demos/PPC-SPC563-GCC/.project @@ -0,0 +1,89 @@ + + + PPC-SPC563-GCC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.cnature + + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/demos/Posix-GCC/.cproject b/demos/Posix-GCC/.cproject new file mode 100644 index 000000000..aa34b8c17 --- /dev/null +++ b/demos/Posix-GCC/.cproject @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/Posix-GCC/.project b/demos/Posix-GCC/.project new file mode 100644 index 000000000..ec2a443c0 --- /dev/null +++ b/demos/Posix-GCC/.project @@ -0,0 +1,90 @@ + + + Posix-GCC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/demos/Win32-MinGW/.cproject b/demos/Win32-MinGW/.cproject new file mode 100644 index 000000000..5342c0657 --- /dev/null +++ b/demos/Win32-MinGW/.cproject @@ -0,0 +1,224 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/Win32-MinGW/.project b/demos/Win32-MinGW/.project new file mode 100644 index 000000000..fda7a8f5b --- /dev/null +++ b/demos/Win32-MinGW/.project @@ -0,0 +1,94 @@ + + + Win32-MinGW + + + _Common Files + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?children? + ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.cnature + + + + os + 2 + WORKSPACE_LOC/os + + + test + 2 + WORKSPACE_LOC/test + + + diff --git a/docs/src/concepts.dox b/docs/src/concepts.dox index f1047b6e0..a0c6a4f76 100644 --- a/docs/src/concepts.dox +++ b/docs/src/concepts.dox @@ -34,8 +34,8 @@ * ChibiOS/RT APIs are all named following this convention: * @a ch\\\(). * The possible groups are: @a Sys, @a Sch, @a Time, @a VT, @a Thd, @a Sem, - * @a Mtx, @a Cond, @a Evt, @a Msg, @a SequentialStream, @a IO, @a IQ, @a OQ, - * @a Dbg, @a Core, @a Heap, @a Pool. + * @a Mtx, @a Cond, @a Evt, @a Msg, @a Reg, @a SequentialStream, @a IO, @a IQ, + * @a OQ, @a Dbg, @a Core, @a Heap, @a Pool. * * @section api_suffixes API Name Suffixes * The suffix can be one of the following: @@ -308,17 +308,20 @@ * @if LATEX_PDF * @dot digraph example { - size="5, 7"; rankdir="LR"; node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; + size="5, 7"; + edge [fontname=Helvetica, fontsize=8]; start [label="Start", style="bold"]; + run [label="Running"]; ready [label="Ready"]; suspend [label="Suspended"]; sleep [label="Sleeping"]; stop [label="Stop", style="bold"]; - start -> suspend [label="chThdInit()", constraint=false]; + + start -> suspend [label="\n chThdCreateI()", constraint=false, dir=back]; start -> run [label="chThdCreate()"]; start -> ready [label="chThdCreate()"]; run -> ready [label="Reschedule", dir="both"]; @@ -335,14 +338,17 @@ digraph example { rankdir="LR"; node [shape=circle, fontname=Helvetica, fontsize=8, fixedsize="true", width="0.75", height="0.75"]; + edge [fontname=Helvetica, fontsize=8]; start [label="Start", style="bold"]; + run [label="Running"]; ready [label="Ready"]; suspend [label="Suspended"]; sleep [label="Sleeping"]; stop [label="Stop", style="bold"]; - start -> suspend [label="chThdInit()", constraint=false]; + + start -> suspend [label="\n chThdCreateI()", constraint=false, dir=back]; start -> run [label="chThdCreate()"]; start -> ready [label="chThdCreate()"]; run -> ready [label="Reschedule", dir="both"]; diff --git a/os/hal/include/adc.h b/os/hal/include/adc.h index cb392f4e2..ff9e6b18f 100644 --- a/os/hal/include/adc.h +++ b/os/hal/include/adc.h @@ -253,6 +253,7 @@ typedef enum { * implementation only. * * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] err platform dependent error code * * @notapi */ diff --git a/os/hal/platforms/STM32F1xx/platform.dox b/os/hal/platforms/STM32F1xx/platform.dox index 83c33a868..de8d9a5d9 100644 --- a/os/hal/platforms/STM32F1xx/platform.dox +++ b/os/hal/platforms/STM32F1xx/platform.dox @@ -62,7 +62,7 @@ * - Programmable ADC interrupt priority level. * - Programmable DMA bus priority for each DMA channel. * - Programmable DMA interrupt priority for each DMA channel. - * - Programmable DMA error hook. + * - DMA errors detection. * . * @ingroup STM32F1xx_DRIVERS */ @@ -93,9 +93,25 @@ * - DMA2 (where present). * . * @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features - * - Automatic DMA clock stop when not in use by other drivers. * - Exports helper functions/macros to the other drivers that share the * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_EXT STM32F1xx EXT Support + * @details The STM32F1xx EXT driver uses the EXTI peripheral. + * + * @section stm32f1xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32f1xx_ext_2 STM32F1xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. * . * @ingroup STM32F1xx_DRIVERS */ diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c index a2149b6ae..74c9a6ee3 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.c +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -84,7 +84,7 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { * * @isr */ -CH_IRQ_HANDLER(UART5_IRQHandler) { +CH_IRQ_HANDLER(ADC1_IRQHandler) { uint32_t sr; CH_IRQ_PROLOGUE(); @@ -96,6 +96,7 @@ CH_IRQ_HANDLER(UART5_IRQHandler) { to read data fast enough.*/ _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); } + /* TODO: Add here analog watchdog handling.*/ CH_IRQ_EPILOGUE(); } @@ -146,6 +147,8 @@ void adc_lld_start(ADCDriver *adcp) { chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); rccEnableADC1(FALSE); + NVICEnableVector(ADC1_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC_ADC1_IRQ_PRIORITY)); } #endif diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox index 7abe18e5e..910fdf7bd 100644 --- a/os/hal/platforms/STM32L1xx/platform.dox +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -20,7 +20,7 @@ /** * @defgroup STM32L1xx_DRIVERS STM32L1xx Drivers - * @details This section describes all the supported drivers on the STM32F1xx + * @details This section describes all the supported drivers on the STM32L1xx * platform and the implementation details of the single drivers. * * @ingroup platforms @@ -46,6 +46,26 @@ * @ingroup STM32L1xx_DRIVERS */ +/** + * @defgroup STM32L1xx_ADC STM32L1xx ADC Support + * @details The STM32L1xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32l1xx_adc_1 Supported HW resources + * - ADC1. + * - DMA1. + * . + * @section stm32l1xx_adc_2 STM32L1xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA and ADC errors detection. + * . + * @ingroup STM32L1xx_DRIVERS + */ + /** * @defgroup STM32L1xx_DMA STM32L1xx DMA Support * @details This DMA helper driver is used by the other drivers in order to @@ -56,9 +76,25 @@ * - DMA1. * . * @section stm32l1xx_dma_2 STM32L1xx DMA driver implementation features - * - Automatic DMA clock stop when not in use by other drivers. * - Exports helper functions/macros to the other drivers that share the * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_EXT STM32L1xx EXT Support + * @details The STM32L1xx EXT driver uses the EXTI peripheral. + * + * @section stm32l1xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32l1xx_ext_2 STM32L1xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. * . * @ingroup STM32L1xx_DRIVERS */ diff --git a/os/hal/templates/ext_lld.c b/os/hal/templates/ext_lld.c index 45bc1c3dc..fc9c2181d 100644 --- a/os/hal/templates/ext_lld.c +++ b/os/hal/templates/ext_lld.c @@ -39,6 +39,11 @@ /* Driver exported variables. */ /*===========================================================================*/ +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + /*===========================================================================*/ /* Driver local variables. */ /*===========================================================================*/ @@ -62,6 +67,8 @@ */ void ext_lld_init(void) { + /* Driver initialization.*/ + extObjectInit(&EXTD1); } /** diff --git a/os/hal/templates/ext_lld.h b/os/hal/templates/ext_lld.h index 494cef1b9..f299a8914 100644 --- a/os/hal/templates/ext_lld.h +++ b/os/hal/templates/ext_lld.h @@ -63,14 +63,23 @@ typedef uint32_t expchannel_t; * @param[in] extp pointer to the @p EXPDriver object triggering the * callback */ -typedef void (*extcallback_t)(EXTDriver *extp); +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); /** * @brief Channel configuration structure. */ typedef struct { - uint32_t mode; /**< @brief Channel mode. */ - extcallback_t cb; /**< @brief Channel callback. */ + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + * @details In the STM32 implementation a @p NULL callback pointer is + * valid and configures the channel as an event sources instead + * of an interrupt source. + */ + extcallback_t cb; } EXTChannelConfig; /** @@ -108,6 +117,10 @@ struct EXTDriver { /* External declarations. */ /*===========================================================================*/ +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/kernel/src/chsys.c b/os/kernel/src/chsys.c index 866ee81a8..78caa88f6 100644 --- a/os/kernel/src/chsys.c +++ b/os/kernel/src/chsys.c @@ -36,10 +36,7 @@ #include "ch.h" #if !CH_NO_IDLE_THREAD || defined(__DOXYGEN__) -/** - * @brief Idle thread working area. - * @see PORT_IDLE_THREAD_STACK_SIZE - */ +/* Idle thread working area.*/ WORKING_AREA(_idle_thread_wa, PORT_IDLE_THREAD_STACK_SIZE); /** diff --git a/os/kernel/src/chthreads.c b/os/kernel/src/chthreads.c index bf43c6c43..7b48f2b00 100644 --- a/os/kernel/src/chthreads.c +++ b/os/kernel/src/chthreads.c @@ -32,8 +32,6 @@ * area. In this scenario static variables are shared among all * threads while automatic variables are local to the thread.
* Operations defined for threads: - * - Init, a thread is prepared and put in the suspended - * state. * - Create, a thread is started on the specified thread * function. This operation is available in multiple variants, * both static and dynamic. diff --git a/os/ports/IAR/ARMCMx/port.dox b/os/ports/IAR/ARMCMx/port.dox index 3e10318ce..b85b6fa07 100644 --- a/os/ports/IAR/ARMCMx/port.dox +++ b/os/ports/IAR/ARMCMx/port.dox @@ -70,8 +70,7 @@ * not globally masked but only interrupts with higher priority can preempt * the current handler. The processor is running in exception-privileged * mode. - * - Serving Fast Interrupt. This state is not implemented in the - * ARMv6-M implementation. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific * asynchronous NMI vector and several synchronous fault vectors that can * be considered belonging to this category. @@ -109,9 +108,13 @@ * not globally masked but only interrupts with higher priority can preempt * the current handler. The processor is running in exception-privileged * mode. - * - Serving Fast Interrupt. It is basically the same of the SRI state - * but it is not possible to switch to the I-Locked state because fast - * interrupts can preempt the kernel critical zone. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
+ * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific * asynchronous NMI vector and several synchronous fault vectors that can * be considered belonging to this category. @@ -126,19 +129,6 @@ * stack where all the interrupts and exceptions are processed. * - The threads are started in thread-privileged mode. * - Interrupt nesting and the other advanced core/NVIC features are supported. - * - When using an STM32 one of the following macros must be defined on the - * compiler command line or in a file named board.h: - * - @p STM32F10X_LD - * - @p STM32F10X_LD_VL - * - @p STM32F10X_MD - * - @p STM32F10X_MD_VL - * - @p STM32F10X_HD - * - @p STM32F10X_XL - * - @p STM32F10X_CL - * . - * This is required in order to include a vectors table with the correct - * length for the STM32 model, see the file - * ./os/ports/IAR/ARMCMx/STM32/vectors.s. * - The Cortex-Mx port is perfectly generic, support for more devices can be * easily added by adding a subdirectory under ./os/ports/IAR/ARMCMx * and giving it the name of the new device, then copy the files from another diff --git a/os/ports/RVCT/ARMCMx/port.dox b/os/ports/RVCT/ARMCMx/port.dox index c69fcdd27..28886bb61 100644 --- a/os/ports/RVCT/ARMCMx/port.dox +++ b/os/ports/RVCT/ARMCMx/port.dox @@ -70,8 +70,7 @@ * not globally masked but only interrupts with higher priority can preempt * the current handler. The processor is running in exception-privileged * mode. - * - Serving Fast Interrupt. This state is not implemented in the - * ARMv6-M implementation. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific * asynchronous NMI vector and several synchronous fault vectors that can * be considered belonging to this category. @@ -109,9 +108,13 @@ * not globally masked but only interrupts with higher priority can preempt * the current handler. The processor is running in exception-privileged * mode. - * - Serving Fast Interrupt. It is basically the same of the SRI state - * but it is not possible to switch to the I-Locked state because fast - * interrupts can preempt the kernel critical zone. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
+ * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific * asynchronous NMI vector and several synchronous fault vectors that can * be considered belonging to this category. @@ -126,19 +129,6 @@ * stack where all the interrupts and exceptions are processed. * - The threads are started in thread-privileged mode. * - Interrupt nesting and the other advanced core/NVIC features are supported. - * - When using an STM32 one of the following macros must be defined on the - * compiler command line or in a file named board.h: - * - @p STM32F10X_LD - * - @p STM32F10X_LD_VL - * - @p STM32F10X_MD - * - @p STM32F10X_MD_VL - * - @p STM32F10X_HD - * - @p STM32F10X_XL - * - @p STM32F10X_CL - * . - * This is required in order to include a vectors table with the correct - * length for the STM32 model, see the file - * ./os/ports/RVCT/ARMCMx/STM32/vectors.s. * - The Cortex-Mx port is perfectly generic, support for more devices can be * easily added by adding a subdirectory under ./os/ports/RVCT/ARMCMx * and giving it the name of the new device, then copy the files from another diff --git a/os/various/shell.c b/os/various/shell.c index b62b8e37e..a99f2657c 100644 --- a/os/various/shell.c +++ b/os/various/shell.c @@ -35,7 +35,7 @@ #include "chprintf.h" /** - * @brief Shell termination event source. + * @brief Shell termination event source. */ EventSource shell_terminated; @@ -117,7 +117,7 @@ static void cmd_systime(BaseChannel *chp, int argc, char *argv[]) { } /** - * @brief Array of the default commands. + * @brief Array of the default commands. */ static ShellCommand local_commands[] = { {"info", cmd_info}, @@ -139,12 +139,12 @@ static bool_t cmdexec(const ShellCommand *scp, BaseChannel *chp, } /** - * @brief Shell thread function. + * @brief Shell thread function. * - * @param[in] p pointer to a @p BaseChannel object - * @return Termination reason. - * @retval RDY_OK terminated by command. - * @retval RDY_RESET terminated by reset condition on the I/O channel. + * @param[in] p pointer to a @p BaseChannel object + * @return Termination reason. + * @retval RDY_OK terminated by command. + * @retval RDY_RESET terminated by reset condition on the I/O channel. */ static msg_t shell_thread(void *p) { int n; @@ -208,7 +208,7 @@ static msg_t shell_thread(void *p) { } /** - * @brief Shell manager initialization. + * @brief Shell manager initialization. */ void shellInit(void) { @@ -216,16 +216,14 @@ void shellInit(void) { } /** - * @brief Spawns a new shell. + * @brief Spawns a new shell. + * @pre @p CH_USE_MALLOC_HEAP and @p CH_USE_DYNAMIC must be enabled. * - * @pre @p CH_USE_MALLOC_HEAP and @p CH_USE_DYNAMIC must be enabled. - * - * @param[in] scp pointer to a @p ShellConfig object - * @param[in] size size of the shell working area to be allocated - * @param[in] prio the priority level for the new shell - * - * @return A pointer to the shell thread. - * @retval NULL thread creation failed because memory allocation. + * @param[in] scp pointer to a @p ShellConfig object + * @param[in] size size of the shell working area to be allocated + * @param[in] prio priority level for the new shell + * @return A pointer to the shell thread. + * @retval NULL thread creation failed because memory allocation. */ #if CH_USE_HEAP && CH_USE_DYNAMIC Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) { @@ -235,14 +233,13 @@ Thread *shellCreate(const ShellConfig *scp, size_t size, tprio_t prio) { #endif /** - * @brief Create statically allocated shell thread. - * - * @param[in] scp pointer to a @p ShellConfig object - * @param[in] wsp pointer to a working area dedicated to the shell thread stack - * @param[in] size size of the shell working area to be allocated - * @param[in] prio the priority level for the new shell + * @brief Create statically allocated shell thread. * - * @return A pointer to the shell thread. + * @param[in] scp pointer to a @p ShellConfig object + * @param[in] wsp pointer to a working area dedicated to the shell thread stack + * @param[in] size size of the shell working area + * @param[in] prio priority level for the new shell + * @return A pointer to the shell thread. */ Thread *shellCreateStatic(const ShellConfig *scp, void *wsp, size_t size, tprio_t prio) { @@ -250,22 +247,15 @@ Thread *shellCreateStatic(const ShellConfig *scp, void *wsp, return chThdCreateStatic(wsp, size, prio, shell_thread, (void *)scp); } - - - - - - /** - * @brief Reads a whole line from the input channel. - * - * @param[in] chp pointer to a @p BaseChannel object - * @param[in] line pointer to the line buffer - * @param[in] size buffer maximum length + * @brief Reads a whole line from the input channel. * - * @return The operation status. - * @retval TRUE the channel was reset or CTRL-D pressed. - * @retval FALSE operation successful. + * @param[in] chp pointer to a @p BaseChannel object + * @param[in] line pointer to the line buffer + * @param[in] size buffer maximum length + * @return The operation status. + * @retval TRUE the channel was reset or CTRL-D pressed. + * @retval FALSE operation successful. */ bool_t shellGetLine(BaseChannel *chp, char *line, unsigned size) { char *p = line; diff --git a/os/various/shell.h b/os/various/shell.h index 2946df947..53ddd48e3 100644 --- a/os/various/shell.h +++ b/os/various/shell.h @@ -30,33 +30,26 @@ #define _SHELL_H_ /** - * @brief Shell maximum input line length. + * @brief Shell maximum input line length. */ #if !defined(SHELL_MAX_LINE_LENGTH) || defined(__DOXYGEN__) #define SHELL_MAX_LINE_LENGTH 64 #endif /** - * @brief Shell maximum arguments per command. + * @brief Shell maximum arguments per command. */ #if !defined(SHELL_MAX_ARGUMENTS) || defined(__DOXYGEN__) #define SHELL_MAX_ARGUMENTS 4 #endif /** - * @brief Enforces the use of iprintf() on newlib. - */ -#if !defined(SHELL_USE_IPRINTF) || defined(__DOXYGEN__) -#define SHELL_USE_IPRINTF TRUE -#endif - -/** - * @brief Command handler function type. + * @brief Command handler function type. */ typedef void (*shellcmd_t)(BaseChannel *chp, int argc, char *argv[]); /** - * @brief Custom command entry type. + * @brief Custom command entry type. */ typedef struct { const char *sc_name; /**< @brief Command name. */ @@ -64,7 +57,7 @@ typedef struct { } ShellCommand; /** - * @brief Shell descriptor type. + * @brief Shell descriptor type. */ typedef struct { BaseChannel *sc_channel; /**< @brief I/O channel associated @@ -73,7 +66,9 @@ typedef struct { table. */ } ShellConfig; +#if !defined(__DOXYGEN__) extern EventSource shell_terminated; +#endif #ifdef __cplusplus extern "C" { diff --git a/readme.txt b/readme.txt index 29dfbdca2..3e8616418 100644 --- a/readme.txt +++ b/readme.txt @@ -73,8 +73,9 @@ ***************************************************************************** *** 2.3.3 *** -- FIX: Fixed missing UART5 definition in STM32 HAL (bug 3411774)(backported - to 2.2.8). +- FIX: Fixed wrong parameter passed to the DMA error hook in STM32 ADC driver, + the DMA error hook has been removed entirely in the new ADC driver model + (bug 3413214)(to be fixed in 2.2.8). - FIX: The function chThdExit() triggers an error on shell return when the system state checker is enabled (bug 3411207)(backported to 2.2.8). - FIX: Some ARMCMx makefiles refer the file rules.mk in the ARM7 port (bug @@ -95,11 +96,14 @@ (backported to 2.2.4). - FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420) (backported to 2.2.4). +- NEW: Added Eclipse project files to all makefile-based demos in order to + allow an easier import. The Eclipse workspace is assumed to be created + inside the ChibiOS/RT main directory. - NEW: STM32L ADC driver implementation. (TODO: To be tested.) - NEW: Improved ADC driver model, now it is possible to handle error conditions during the conversion process. - (TODO: Modify existing STM32 ADC implementation). + (TODO: To be tested.) - NEW: STM32L1xx sub-family support, all STM32 drivers adapted and re-tested on the new platform except ADC that will need a specific implementation. - NEW: Added new API chThdExitS() in order to allow atomic operations on @@ -193,7 +197,8 @@ is new and makes the kernel *much* smaller and generally faster but does not support fast interrupts (backported to 2.2.5). - NEW: Now the port layer exports info regarding the compiler and the port - options. The info are printed into the test reports. + options. The info are printed into the test reports. Date and time also + added. - CHANGE: Removed the option CH_USE_NESTED_LOCK, lwIP no more requires it and it would have conflicted with CH_DBG_SYSTEM_STATE_CHECK which is far more useful. diff --git a/test/test.c b/test/test.c index 41662308c..74069415c 100644 --- a/test/test.c +++ b/test/test.c @@ -328,6 +328,8 @@ msg_t TestThread(void *p) { test_println("***"); test_print("*** Kernel: "); test_println(CH_KERNEL_VERSION); + test_print("*** Compiled: "); + test_println(__DATE__ " - " __TIME__); #ifdef CH_COMPILER_NAME test_print("*** Compiler: "); test_println(CH_COMPILER_NAME); diff --git a/test/test.dox b/test/test.dox index ab937f9a2..114b2af85 100644 --- a/test/test.dox +++ b/test/test.dox @@ -46,13 +46,13 @@ * for this execution test, it is done automatically by a script because * the entire sequence can take hours).
* All the tests results are included as reports in the OS distribution - * under @p ./docs/reports. + * under ./docs/reports. * - Ports. The port code is tested by executing the kernel test * suite on the target hardware. A port is validated only if it passes all * the tests. Speed and size benchmarks for all the supported architectures * are performed, both size and speed regressions are monitored. * - HAL. The HAL high level code and device drivers implementations - * are tested through specific test applications under ./testhal. + * are tested through specific test applications under ./testhal. * - Various. The miscellaneous code is tested by use in the various * demos. * - External Code. Not tested, external libraries or components are diff --git a/testhal/STM32L1xx/ADC/readme.txt b/testhal/STM32L1xx/ADC/readme.txt index adceab611..157c3b93e 100644 --- a/testhal/STM32L1xx/ADC/readme.txt +++ b/testhal/STM32L1xx/ADC/readme.txt @@ -12,7 +12,8 @@ The application demonstrates the use of the STM32L1xx ADC driver. ** Board Setup ** -None required. +- Remove the LCD module. +- Connect PC0 to 3.3V and PC1 to GND for analog measurements. ** Build Procedure ** -- cgit v1.2.3 From a24fe0108e2f7e05db454048ccf3ae9262109bb4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 23 Sep 2011 18:18:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3385 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/ADC/chconf.h | 12 ++++++------ testhal/STM32L1xx/ADC/main.c | 2 -- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/testhal/STM32L1xx/ADC/chconf.h b/testhal/STM32L1xx/ADC/chconf.h index a5d129956..9dd831c96 100644 --- a/testhal/STM32L1xx/ADC/chconf.h +++ b/testhal/STM32L1xx/ADC/chconf.h @@ -361,7 +361,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#define CH_DBG_SYSTEM_STATE_CHECK FALSE #endif /** @@ -372,7 +372,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS TRUE +#define CH_DBG_ENABLE_CHECKS FALSE #endif /** @@ -384,7 +384,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS TRUE +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** @@ -395,7 +395,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE TRUE +#define CH_DBG_ENABLE_TRACE FALSE #endif /** @@ -409,7 +409,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -421,7 +421,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c index 82ac4c4d8..c7c7622a8 100644 --- a/testhal/STM32L1xx/ADC/main.c +++ b/testhal/STM32L1xx/ADC/main.c @@ -81,7 +81,6 @@ static msg_t Thread1(void *arg) { palSetPad(GPIOB, GPIOB_LED4); chThdSleepMilliseconds(500); } - return 0; } /* @@ -127,5 +126,4 @@ int main(void) { } chThdSleepMilliseconds(500); } - return 0; } -- cgit v1.2.3 From 09d93604e7d02274f433d0854f9bfdfcab53cc9f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 23 Sep 2011 20:38:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3386 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/adc_lld.c | 5 +++-- testhal/STM32L1xx/ADC/main.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c index 74c9a6ee3..dfd1883f0 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.c +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -213,7 +213,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ adcp->adc->SMPR2 = grpp->smpr2; adcp->adc->SMPR3 = grpp->smpr3; - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_CONT | + ADC_CR2_ADON; adcp->adc->SQR1 = grpp->sqr1; adcp->adc->SQR2 = grpp->sqr2; adcp->adc->SQR3 = grpp->sqr3; @@ -224,7 +225,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { while ((adcp->adc->SR & ADC_SR_ADONS) == 0) ; /* ADC start by raising ADC_CR2_SWSTART.*/ - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_DMA | + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_CONT | ADC_CR2_ADON; } diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c index c7c7622a8..706ec690e 100644 --- a/testhal/STM32L1xx/ADC/main.c +++ b/testhal/STM32L1xx/ADC/main.c @@ -78,7 +78,7 @@ static msg_t Thread1(void *arg) { while (TRUE) { palSetPad(GPIOB, GPIOB_LED4); chThdSleepMilliseconds(500); - palSetPad(GPIOB, GPIOB_LED4); + palClearPad(GPIOB, GPIOB_LED4); chThdSleepMilliseconds(500); } } -- cgit v1.2.3 From 5bf43b6500206391495dee6ea06c892dc450dcf2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 06:53:13 +0000 Subject: STM32L driver tested and working. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3387 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/adc_lld.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c index dfd1883f0..eeae18f68 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.c +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -188,23 +188,24 @@ void adc_lld_stop(ADCDriver *adcp) { * @notapi */ void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode, n; + uint32_t mode, cr2; const ADCConversionGroup *grpp = adcp->grpp; /* DMA setup.*/ mode = adcp->dmamode; - if (grpp->circular) + cr2 = grpp->cr2; + if (grpp->circular) { mode |= STM32_DMA_CR_CIRC; + cr2 |= ADC_CR2_CONT; + } if (adcp->depth > 1) { /* If the buffer depth is greater than one then the half transfer interrupt interrupt is enabled in order to allows streaming processing.*/ mode |= STM32_DMA_CR_HTIE; - n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth; } - else - n = (uint32_t)grpp->num_channels; dmaStreamSetMemory0(adcp->dmastp, adcp->samples); - dmaStreamSetTransactionSize(adcp->dmastp, n); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); dmaStreamSetMode(adcp->dmastp, mode); /* ADC setup.*/ @@ -213,8 +214,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ adcp->adc->SMPR2 = grpp->smpr2; adcp->adc->SMPR3 = grpp->smpr3; - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_CONT | - ADC_CR2_ADON; + adcp->adc->CR2 = cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON; adcp->adc->SQR1 = grpp->sqr1; adcp->adc->SQR2 = grpp->sqr2; adcp->adc->SQR3 = grpp->sqr3; @@ -225,8 +225,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) { while ((adcp->adc->SR & ADC_SR_ADONS) == 0) ; /* ADC start by raising ADC_CR2_SWSTART.*/ - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_DMA | ADC_CR2_DDS | - ADC_CR2_CONT | ADC_CR2_ADON; + adcp->adc->CR2 = cr2 | ADC_CR2_SWSTART | ADC_CR2_DMA | ADC_CR2_DDS | + ADC_CR2_ADON; } /** -- cgit v1.2.3 From 76d35140c961634760955219d0dc1406dee58a12 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 07:11:11 +0000 Subject: IAR startup updated to export symbol __main_thread_stack_base__. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3388 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/ports/IAR/ARMCMx/cstartup.s | 2 ++ readme.txt | 4 +--- testhal/STM32L1xx/ADC/chconf.h | 12 ++++++------ 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/os/ports/IAR/ARMCMx/cstartup.s b/os/ports/IAR/ARMCMx/cstartup.s index 677cd5248..49746b373 100644 --- a/os/ports/IAR/ARMCMx/cstartup.s +++ b/os/ports/IAR/ARMCMx/cstartup.s @@ -31,6 +31,8 @@ CONTROL_USE_PSP SET 2 SECTION .intvec:CODE:NOROOT(3) SECTION CSTACK:DATA:NOROOT(3) + PUBLIC __main_thread_stack_base__ +__main_thread_stack_base__: PUBLIC __heap_end__ __heap_end__: diff --git a/readme.txt b/readme.txt index 3e8616418..5ea8fc151 100644 --- a/readme.txt +++ b/readme.txt @@ -100,7 +100,6 @@ allow an easier import. The Eclipse workspace is assumed to be created inside the ChibiOS/RT main directory. - NEW: STM32L ADC driver implementation. - (TODO: To be tested.) - NEW: Improved ADC driver model, now it is possible to handle error conditions during the conversion process. (TODO: To be tested.) @@ -152,7 +151,6 @@ exception stack now triggers an exception (it could go unnoticed before). The process stack is organized to be checked on context switch like other threads. Now all threads have an explicit stack boundary pointer. - (TODO: documentation to be updated) - NEW: Added debug plugin for Eclipse under ./tools/eclipse (backported to 2.2.7). - NEW: The debug macros chDbgCheck() and chDbgAssert() now can be externally @@ -162,7 +160,7 @@ - NEW: Added provisional support for STM32F2xx. Because of this some directories related to the STM32 have been renamed, your makefiles may require adjustments. - (TODO: change to be ported to IAR and Keil build files) + (TODO: change to be ported to Keil build files) - NEW: Added a custom rule to the various rules.mk files, now it is possible to add an user rule into the Makefiles. - NEW: Improvements to the trace buffer, now it stores a full thread pointer diff --git a/testhal/STM32L1xx/ADC/chconf.h b/testhal/STM32L1xx/ADC/chconf.h index 9dd831c96..a5d129956 100644 --- a/testhal/STM32L1xx/ADC/chconf.h +++ b/testhal/STM32L1xx/ADC/chconf.h @@ -361,7 +361,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#define CH_DBG_SYSTEM_STATE_CHECK TRUE #endif /** @@ -372,7 +372,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE +#define CH_DBG_ENABLE_CHECKS TRUE #endif /** @@ -384,7 +384,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE +#define CH_DBG_ENABLE_ASSERTS TRUE #endif /** @@ -395,7 +395,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE +#define CH_DBG_ENABLE_TRACE TRUE #endif /** @@ -409,7 +409,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -421,7 +421,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS TRUE #endif /** -- cgit v1.2.3 From 5f8971c537d72bfe1327598747e422d5a8e4e9b7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 07:29:46 +0000 Subject: Added symbol __main_thread_stack_base__ to Keil startup file. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3389 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103/keil/ch.uvproj | 83 ++++------------------------------- os/ports/RVCT/ARMCMx/cstartup.s | 2 + 2 files changed, 11 insertions(+), 74 deletions(-) diff --git a/demos/ARMCM3-STM32F103/keil/ch.uvproj b/demos/ARMCM3-STM32F103/keil/ch.uvproj index 3f8ff22bd..59cab5187 100644 --- a/demos/ARMCM3-STM32F103/keil/ch.uvproj +++ b/demos/ARMCM3-STM32F103/keil/ch.uvproj @@ -346,7 +346,7 @@ __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base - ..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\boards\OLIMEX_STM32_P103;..\..\..\test + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\common\ARMCMx\CMSIS\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32\GPIOv1;..\..\..\os\hal\platforms\STM32\DMAv1;..\..\..\os\hal\platforms\STM32\USBv1;..\..\..\os\hal\platforms\STM32F1xx;..\..\..\boards\OLIMEX_STM32_P103;..\..\..\test @@ -361,7 +361,7 @@ --cpreproc - ..\;..\..\..\boards\OLIMEX_STM32_P103;..\..\..\os\ports\RVCT\ARMCMx\STM32 + ..\;..\..\..\boards\OLIMEX_STM32_P103;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx @@ -409,7 +409,7 @@ vectors.s 2 - ..\..\..\os\ports\RVCT\ARMCMx\STM32\vectors.s + D:\Progetti\ChibiOS-RT\os\ports\RVCT\ARMCMx\STM32F1xx\vectors.s chcoreasm_v7m.s @@ -791,110 +791,45 @@ platform - - adc_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\adc_lld.c - - - can_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\can_lld.c - hal_lld.c 1 - ..\..\..\os\hal\platforms\STM32\hal_lld.c + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld.c pal_lld.c 1 - ..\..\..\os\hal\platforms\STM32\pal_lld.c - - - pwm_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\pwm_lld.c + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\GPIOv1\pal_lld.c serial_lld.c 1 ..\..\..\os\hal\platforms\STM32\serial_lld.c - - spi_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\spi_lld.c - - - stm32_dma.c - 1 - ..\..\..\os\hal\platforms\STM32\stm32_dma.c - - - uart_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\uart_lld.c - - - adc_lld.h - 5 - ..\..\..\os\hal\platforms\STM32\adc_lld.h - - - can_lld.h - 5 - ..\..\..\os\hal\platforms\STM32\can_lld.h - - - core_cm3.h - 5 - ..\..\..\os\hal\platforms\STM32\core_cm3.h - hal_lld.h 5 - ..\..\..\os\hal\platforms\STM32\hal_lld.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld.h hal_lld_f103.h 5 - ..\..\..\os\hal\platforms\STM32\hal_lld_f103.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld_f103.h pal_lld.h 5 - ..\..\..\os\hal\platforms\STM32\pal_lld.h - - - pwm_lld.h - 5 - ..\..\..\os\hal\platforms\STM32\pwm_lld.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\GPIOv1\pal_lld.h serial_lld.h 5 ..\..\..\os\hal\platforms\STM32\serial_lld.h - - spi_lld.h - 5 - ..\..\..\os\hal\platforms\STM32\spi_lld.h - - - stm32_dma.h - 5 - ..\..\..\os\hal\platforms\STM32\stm32_dma.h - stm32f10x.h 5 - ..\..\..\os\hal\platforms\STM32\stm32f10x.h - - - uart_lld.h - 5 - ..\..\..\os\hal\platforms\STM32\uart_lld.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\stm32f10x.h diff --git a/os/ports/RVCT/ARMCMx/cstartup.s b/os/ports/RVCT/ARMCMx/cstartup.s index 95f2f0f48..3c0fde7c9 100644 --- a/os/ports/RVCT/ARMCMx/cstartup.s +++ b/os/ports/RVCT/ARMCMx/cstartup.s @@ -41,6 +41,8 @@ main_stack_mem SPACE main_stack_size __initial_msp AREA CSTACK, NOINIT, READWRITE, ALIGN=3 +__main_thread_stack_base__ + EXPORT __main_thread_stack_base__ proc_stack_mem SPACE proc_stack_size EXPORT __initial_sp __initial_sp -- cgit v1.2.3 From d528722d4e7c0b64894495c5387c9df3101b43d4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 07:30:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3390 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/readme.txt b/readme.txt index 5ea8fc151..9653ea87e 100644 --- a/readme.txt +++ b/readme.txt @@ -160,7 +160,7 @@ - NEW: Added provisional support for STM32F2xx. Because of this some directories related to the STM32 have been renamed, your makefiles may require adjustments. - (TODO: change to be ported to Keil build files) + (TODO: change to be ported to IAR and Keil build files) - NEW: Added a custom rule to the various rules.mk files, now it is possible to add an user rule into the Makefiles. - NEW: Improvements to the trace buffer, now it stores a full thread pointer -- cgit v1.2.3 From 23d7c00ed3fa216ae84ce1c9f631d905dd5ddb51 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 07:31:20 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3391 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103/chconf.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/demos/ARMCM3-STM32F103/chconf.h b/demos/ARMCM3-STM32F103/chconf.h index a5d129956..9dd831c96 100644 --- a/demos/ARMCM3-STM32F103/chconf.h +++ b/demos/ARMCM3-STM32F103/chconf.h @@ -361,7 +361,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#define CH_DBG_SYSTEM_STATE_CHECK FALSE #endif /** @@ -372,7 +372,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS TRUE +#define CH_DBG_ENABLE_CHECKS FALSE #endif /** @@ -384,7 +384,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS TRUE +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** @@ -395,7 +395,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE TRUE +#define CH_DBG_ENABLE_TRACE FALSE #endif /** @@ -409,7 +409,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -421,7 +421,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE +#define CH_DBG_FILL_THREADS FALSE #endif /** -- cgit v1.2.3 From 859c2c759973f52bfacbd33a7cc56d12a1eab581 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 07:39:20 +0000 Subject: Modified STM32L HAL test applications to run always in full debug mode. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3392 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/GPT/chconf.h | 12 ++++++------ testhal/STM32L1xx/IRQ_STORM/chconf.h | 12 ++++++------ testhal/STM32L1xx/PWM-ICU/chconf.h | 12 ++++++------ testhal/STM32L1xx/UART/chconf.h | 12 ++++++------ 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/testhal/STM32L1xx/GPT/chconf.h b/testhal/STM32L1xx/GPT/chconf.h index 9dd831c96..a5d129956 100644 --- a/testhal/STM32L1xx/GPT/chconf.h +++ b/testhal/STM32L1xx/GPT/chconf.h @@ -361,7 +361,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#define CH_DBG_SYSTEM_STATE_CHECK TRUE #endif /** @@ -372,7 +372,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE +#define CH_DBG_ENABLE_CHECKS TRUE #endif /** @@ -384,7 +384,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE +#define CH_DBG_ENABLE_ASSERTS TRUE #endif /** @@ -395,7 +395,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE +#define CH_DBG_ENABLE_TRACE TRUE #endif /** @@ -409,7 +409,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -421,7 +421,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS TRUE #endif /** diff --git a/testhal/STM32L1xx/IRQ_STORM/chconf.h b/testhal/STM32L1xx/IRQ_STORM/chconf.h index 9dd831c96..a5d129956 100644 --- a/testhal/STM32L1xx/IRQ_STORM/chconf.h +++ b/testhal/STM32L1xx/IRQ_STORM/chconf.h @@ -361,7 +361,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#define CH_DBG_SYSTEM_STATE_CHECK TRUE #endif /** @@ -372,7 +372,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE +#define CH_DBG_ENABLE_CHECKS TRUE #endif /** @@ -384,7 +384,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE +#define CH_DBG_ENABLE_ASSERTS TRUE #endif /** @@ -395,7 +395,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE +#define CH_DBG_ENABLE_TRACE TRUE #endif /** @@ -409,7 +409,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -421,7 +421,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS TRUE #endif /** diff --git a/testhal/STM32L1xx/PWM-ICU/chconf.h b/testhal/STM32L1xx/PWM-ICU/chconf.h index 9dd831c96..a5d129956 100644 --- a/testhal/STM32L1xx/PWM-ICU/chconf.h +++ b/testhal/STM32L1xx/PWM-ICU/chconf.h @@ -361,7 +361,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#define CH_DBG_SYSTEM_STATE_CHECK TRUE #endif /** @@ -372,7 +372,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE +#define CH_DBG_ENABLE_CHECKS TRUE #endif /** @@ -384,7 +384,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE +#define CH_DBG_ENABLE_ASSERTS TRUE #endif /** @@ -395,7 +395,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE +#define CH_DBG_ENABLE_TRACE TRUE #endif /** @@ -409,7 +409,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -421,7 +421,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS TRUE #endif /** diff --git a/testhal/STM32L1xx/UART/chconf.h b/testhal/STM32L1xx/UART/chconf.h index 9dd831c96..a5d129956 100644 --- a/testhal/STM32L1xx/UART/chconf.h +++ b/testhal/STM32L1xx/UART/chconf.h @@ -361,7 +361,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#define CH_DBG_SYSTEM_STATE_CHECK TRUE #endif /** @@ -372,7 +372,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE +#define CH_DBG_ENABLE_CHECKS TRUE #endif /** @@ -384,7 +384,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE +#define CH_DBG_ENABLE_ASSERTS TRUE #endif /** @@ -395,7 +395,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE +#define CH_DBG_ENABLE_TRACE TRUE #endif /** @@ -409,7 +409,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -421,7 +421,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS TRUE #endif /** -- cgit v1.2.3 From a91a8ffdbf5679a2afdf37944483488e7fef4ad3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 07:45:22 +0000 Subject: Removed ADC DMA error hook macro from the various mcuconf.h, it is no more required. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3393 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h | 1 - demos/ARMCM3-STM32F103-FATFS/mcuconf.h | 1 - demos/ARMCM3-STM32F103-G++/mcuconf.h | 1 - demos/ARMCM3-STM32F103/mcuconf.h | 1 - demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h | 1 - demos/ARMCM3-STM32F107/mcuconf.h | 1 - demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h | 1 - testhal/STM32F1xx/ADC/mcuconf.h | 1 - testhal/STM32F1xx/CAN/mcuconf.h | 1 - testhal/STM32F1xx/EXT/mcuconf.h | 1 - testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h | 1 - testhal/STM32F1xx/GPT/mcuconf.h | 1 - testhal/STM32F1xx/IRQ_STORM/mcuconf.h | 1 - testhal/STM32F1xx/MAC/mcuconf.h | 1 - testhal/STM32F1xx/PWM-ICU/mcuconf.h | 1 - testhal/STM32F1xx/SDC/mcuconf.h | 1 - testhal/STM32F1xx/SPI/mcuconf.h | 1 - testhal/STM32F1xx/UART/mcuconf.h | 1 - testhal/STM32F1xx/USB_CDC/mcuconf.h | 1 - testhal/STM32F1xx/USB_MSC/mcuconf.h | 1 - testhal/STM32L1xx/ADC/mcuconf.h | 1 - testhal/STM32L1xx/EXT/mcuconf.h | 1 - testhal/STM32L1xx/GPT/mcuconf.h | 1 - testhal/STM32L1xx/IRQ_STORM/mcuconf.h | 1 - testhal/STM32L1xx/PWM-ICU/mcuconf.h | 1 - testhal/STM32L1xx/SPI/mcuconf.h | 1 - testhal/STM32L1xx/UART/mcuconf.h | 1 - 27 files changed, 27 deletions(-) diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h index d92b02937..e0b78e3ed 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h @@ -51,7 +51,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/demos/ARMCM3-STM32F103-FATFS/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS/mcuconf.h index 32e0c7964..a563b0e49 100644 --- a/demos/ARMCM3-STM32F103-FATFS/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/demos/ARMCM3-STM32F103-G++/mcuconf.h b/demos/ARMCM3-STM32F103-G++/mcuconf.h index 32e0c7964..a563b0e49 100644 --- a/demos/ARMCM3-STM32F103-G++/mcuconf.h +++ b/demos/ARMCM3-STM32F103-G++/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/demos/ARMCM3-STM32F103/mcuconf.h b/demos/ARMCM3-STM32F103/mcuconf.h index 6d9091165..23694e0e6 100644 --- a/demos/ARMCM3-STM32F103/mcuconf.h +++ b/demos/ARMCM3-STM32F103/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h index 078a38f24..bb01745f7 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h +++ b/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/demos/ARMCM3-STM32F107/mcuconf.h b/demos/ARMCM3-STM32F107/mcuconf.h index 8516c02a1..360788253 100644 --- a/demos/ARMCM3-STM32F107/mcuconf.h +++ b/demos/ARMCM3-STM32F107/mcuconf.h @@ -59,7 +59,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h index a87325ff7..4071c4507 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h @@ -62,7 +62,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/ADC/mcuconf.h b/testhal/STM32F1xx/ADC/mcuconf.h index 32e0c7964..a563b0e49 100644 --- a/testhal/STM32F1xx/ADC/mcuconf.h +++ b/testhal/STM32F1xx/ADC/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/CAN/mcuconf.h b/testhal/STM32F1xx/CAN/mcuconf.h index 32e0c7964..a563b0e49 100644 --- a/testhal/STM32F1xx/CAN/mcuconf.h +++ b/testhal/STM32F1xx/CAN/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/EXT/mcuconf.h b/testhal/STM32F1xx/EXT/mcuconf.h index 6d9091165..23694e0e6 100644 --- a/testhal/STM32F1xx/EXT/mcuconf.h +++ b/testhal/STM32F1xx/EXT/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h index 26a7a4945..7ec218f04 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/GPT/mcuconf.h b/testhal/STM32F1xx/GPT/mcuconf.h index 8c0187fc0..37eddd3d3 100644 --- a/testhal/STM32F1xx/GPT/mcuconf.h +++ b/testhal/STM32F1xx/GPT/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/IRQ_STORM/mcuconf.h b/testhal/STM32F1xx/IRQ_STORM/mcuconf.h index 94328b5fa..4398818f7 100644 --- a/testhal/STM32F1xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32F1xx/IRQ_STORM/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/MAC/mcuconf.h b/testhal/STM32F1xx/MAC/mcuconf.h index 8516c02a1..360788253 100644 --- a/testhal/STM32F1xx/MAC/mcuconf.h +++ b/testhal/STM32F1xx/MAC/mcuconf.h @@ -59,7 +59,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/PWM-ICU/mcuconf.h b/testhal/STM32F1xx/PWM-ICU/mcuconf.h index 32e0c7964..a563b0e49 100644 --- a/testhal/STM32F1xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32F1xx/PWM-ICU/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/SDC/mcuconf.h b/testhal/STM32F1xx/SDC/mcuconf.h index 1af95abfd..49ae48fff 100644 --- a/testhal/STM32F1xx/SDC/mcuconf.h +++ b/testhal/STM32F1xx/SDC/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/SPI/mcuconf.h b/testhal/STM32F1xx/SPI/mcuconf.h index 32e0c7964..a563b0e49 100644 --- a/testhal/STM32F1xx/SPI/mcuconf.h +++ b/testhal/STM32F1xx/SPI/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/UART/mcuconf.h b/testhal/STM32F1xx/UART/mcuconf.h index b0a57b539..4c46b0213 100644 --- a/testhal/STM32F1xx/UART/mcuconf.h +++ b/testhal/STM32F1xx/UART/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/USB_CDC/mcuconf.h b/testhal/STM32F1xx/USB_CDC/mcuconf.h index 32e0c7964..a563b0e49 100644 --- a/testhal/STM32F1xx/USB_CDC/mcuconf.h +++ b/testhal/STM32F1xx/USB_CDC/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32F1xx/USB_MSC/mcuconf.h b/testhal/STM32F1xx/USB_MSC/mcuconf.h index 32e0c7964..a563b0e49 100644 --- a/testhal/STM32F1xx/USB_MSC/mcuconf.h +++ b/testhal/STM32F1xx/USB_MSC/mcuconf.h @@ -52,7 +52,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/ADC/mcuconf.h b/testhal/STM32L1xx/ADC/mcuconf.h index d214c9d12..3702fa62f 100644 --- a/testhal/STM32L1xx/ADC/mcuconf.h +++ b/testhal/STM32L1xx/ADC/mcuconf.h @@ -62,7 +62,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/EXT/mcuconf.h b/testhal/STM32L1xx/EXT/mcuconf.h index d214c9d12..3702fa62f 100644 --- a/testhal/STM32L1xx/EXT/mcuconf.h +++ b/testhal/STM32L1xx/EXT/mcuconf.h @@ -62,7 +62,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/GPT/mcuconf.h b/testhal/STM32L1xx/GPT/mcuconf.h index d214c9d12..3702fa62f 100644 --- a/testhal/STM32L1xx/GPT/mcuconf.h +++ b/testhal/STM32L1xx/GPT/mcuconf.h @@ -62,7 +62,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h index 5839ef86a..2562d6b67 100644 --- a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h @@ -62,7 +62,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/PWM-ICU/mcuconf.h b/testhal/STM32L1xx/PWM-ICU/mcuconf.h index ac551ee4f..4f9182094 100644 --- a/testhal/STM32L1xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32L1xx/PWM-ICU/mcuconf.h @@ -62,7 +62,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/SPI/mcuconf.h b/testhal/STM32L1xx/SPI/mcuconf.h index a87325ff7..4071c4507 100644 --- a/testhal/STM32L1xx/SPI/mcuconf.h +++ b/testhal/STM32L1xx/SPI/mcuconf.h @@ -62,7 +62,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/UART/mcuconf.h b/testhal/STM32L1xx/UART/mcuconf.h index a210c468b..33119bd78 100644 --- a/testhal/STM32L1xx/UART/mcuconf.h +++ b/testhal/STM32L1xx/UART/mcuconf.h @@ -62,7 +62,6 @@ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() /* * CAN driver system settings. -- cgit v1.2.3 From 8976b7b89888c036744db65a70fa167748bd38ae Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 08:16:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3394 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/IRQ_STORM/chconf.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/testhal/STM32L1xx/IRQ_STORM/chconf.h b/testhal/STM32L1xx/IRQ_STORM/chconf.h index a5d129956..9dd831c96 100644 --- a/testhal/STM32L1xx/IRQ_STORM/chconf.h +++ b/testhal/STM32L1xx/IRQ_STORM/chconf.h @@ -361,7 +361,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#define CH_DBG_SYSTEM_STATE_CHECK FALSE #endif /** @@ -372,7 +372,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS TRUE +#define CH_DBG_ENABLE_CHECKS FALSE #endif /** @@ -384,7 +384,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS TRUE +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** @@ -395,7 +395,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE TRUE +#define CH_DBG_ENABLE_TRACE FALSE #endif /** @@ -409,7 +409,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -421,7 +421,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE +#define CH_DBG_FILL_THREADS FALSE #endif /** -- cgit v1.2.3 From f4d189fe8e498de3b6d8e6b7057f39c759891bbe Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 09:13:08 +0000 Subject: STM32 IAR projects updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3395 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.ewp | 233 +++++++++++++++++++------ demos/ARMCM3-STM32F103/iar/ch.ewp | 249 +++++++++++++++++++-------- demos/ARMCM3-STM32F103ZG-FATFS/iar/ch.ewp | 258 ++++++++++++++++------------ demos/ARMCM3-STM32F107/iar/ch.ewp | 232 +++++++++++++++++-------- demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp | 47 ++++- readme.txt | 2 +- 6 files changed, 709 insertions(+), 312 deletions(-) diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.ewp b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.ewp index 287b56a00..a277d1719 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.ewp +++ b/demos/ARMCM3-STM32F100-DISCOVERY/iar/ch.ewp @@ -12,7 +12,7 @@ General 3 - 18 + 21 1 1 + + + + ICCARM 2 - 26 + 28 1 1 @@ -364,11 +387,15 @@ 1 + @@ -523,7 +550,8 @@ @@ -876,7 +920,7 @@ General 3 - 18 + 21 1 0 + + + + ICCARM 2 - 26 + 28 1 0 @@ -1228,11 +1295,15 @@ 1 + @@ -1387,7 +1458,8 @@ @@ -1751,12 +1839,21 @@ $PROJ_DIR$\..\..\..\os\hal\include\can.h + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + $PROJ_DIR$\..\..\..\os\hal\include\hal.h $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + $PROJ_DIR$\..\..\..\os\hal\include\mac.h @@ -1772,15 +1869,30 @@ $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + $PROJ_DIR$\..\..\..\os\hal\include\spi.h $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + src @@ -1790,12 +1902,21 @@ $PROJ_DIR$\..\..\..\os\hal\src\can.c + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + $PROJ_DIR$\..\..\..\os\hal\src\hal.c $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + $PROJ_DIR$\..\..\..\os\hal\src\mac.c @@ -1808,15 +1929,27 @@ $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + $PROJ_DIR$\..\..\..\os\hal\src\spi.c $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + @@ -1951,40 +2084,31 @@ platform - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\adc_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\adc_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\adc_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\can_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\adc_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\can_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\core_cm3.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f100.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f100.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f105_f107.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f103.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f105_f107.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pal_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pal_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c @@ -2005,30 +2129,27 @@ $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32_dma.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32_dma.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32f10x.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h port - STM32 + STM32F1xx - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\cmparams.h + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\cmparams.h - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\vectors.s + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\vectors.s diff --git a/demos/ARMCM3-STM32F103/iar/ch.ewp b/demos/ARMCM3-STM32F103/iar/ch.ewp index 085175d5f..6add8178f 100644 --- a/demos/ARMCM3-STM32F103/iar/ch.ewp +++ b/demos/ARMCM3-STM32F103/iar/ch.ewp @@ -12,7 +12,7 @@ General 3 - 18 + 21 1 1 + + + + ICCARM 2 - 26 + 28 1 1 @@ -364,11 +387,15 @@ 1 + @@ -523,8 +550,8 @@ @@ -877,7 +920,7 @@ General 3 - 18 + 21 1 0 + + + + ICCARM 2 - 26 + 28 1 0 @@ -1229,11 +1295,15 @@ 1 + @@ -1388,8 +1458,8 @@ @@ -1753,12 +1839,21 @@ $PROJ_DIR$\..\..\..\os\hal\include\can.h + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + $PROJ_DIR$\..\..\..\os\hal\include\hal.h $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + $PROJ_DIR$\..\..\..\os\hal\include\mac.h @@ -1774,15 +1869,30 @@ $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + $PROJ_DIR$\..\..\..\os\hal\include\spi.h $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + src @@ -1792,12 +1902,21 @@ $PROJ_DIR$\..\..\..\os\hal\src\can.c + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + $PROJ_DIR$\..\..\..\os\hal\src\hal.c $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + $PROJ_DIR$\..\..\..\os\hal\src\mac.c @@ -1810,15 +1929,27 @@ $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + $PROJ_DIR$\..\..\..\os\hal\src\spi.c $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + @@ -1953,46 +2084,25 @@ platform - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\adc_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\adc_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\can_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\can_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\core_cm3.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f100.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f105_f107.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f100.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f103.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f105_f107.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pal_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pal_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.c @@ -2001,36 +2111,27 @@ $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32_dma.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32_dma.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32f10x.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h port - STM32 + STM32F1xx - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\cmparams.h + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\cmparams.h - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\vectors.s + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\vectors.s diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/iar/ch.ewp b/demos/ARMCM3-STM32F103ZG-FATFS/iar/ch.ewp index a66a70295..c62ba7e3b 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/iar/ch.ewp +++ b/demos/ARMCM3-STM32F103ZG-FATFS/iar/ch.ewp @@ -12,7 +12,7 @@ General 3 - 18 + 21 1 1 + + + + ICCARM 2 - 26 + 28 1 1 + @@ -525,8 +552,8 @@ @@ -879,7 +922,7 @@ General 3 - 18 + 21 1 0 + + + + ICCARM 2 - 26 + 28 1 0 + @@ -1393,8 +1462,8 @@ @@ -1782,6 +1867,9 @@ $PROJ_DIR$\..\..\..\os\hal\include\can.h + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h @@ -1809,6 +1897,9 @@ $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h @@ -1839,6 +1930,9 @@ $PROJ_DIR$\..\..\..\os\hal\src\can.c + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c @@ -1863,6 +1957,9 @@ $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c @@ -1890,9 +1987,6 @@ $PROJ_DIR$\..\..\..\os\kernel\include\ch.h - - $PROJ_DIR$\..\..\..\os\kernel\include\chbsem.h - $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h @@ -1905,9 +1999,6 @@ $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h - - $PROJ_DIR$\..\..\..\os\kernel\include\chfiles.h - $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h @@ -2021,58 +2112,25 @@ platform - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\adc_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\adc_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\can_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\can_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\core_cm3.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\gpt_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f100.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\gpt_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f105_f107.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f100.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f103.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f105_f107.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\icu_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\icu_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pal_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pal_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\sdc_lld.c @@ -2087,45 +2145,27 @@ $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32_dma.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32_dma.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32_usb.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32f10x.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\usb_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\usb_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h port - STM32 + STM32F1xx - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\cmparams.h + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\cmparams.h - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\vectors.s + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\vectors.s @@ -2158,6 +2198,12 @@ various + + $PROJ_DIR$\..\..\..\os\various\chprintf.c + + + $PROJ_DIR$\..\..\..\os\various\chprintf.h + $PROJ_DIR$\..\..\..\os\various\shell.c diff --git a/demos/ARMCM3-STM32F107/iar/ch.ewp b/demos/ARMCM3-STM32F107/iar/ch.ewp index df3095c33..ae69e614f 100644 --- a/demos/ARMCM3-STM32F107/iar/ch.ewp +++ b/demos/ARMCM3-STM32F107/iar/ch.ewp @@ -12,7 +12,7 @@ General 3 - 18 + 21 1 1 + + + + ICCARM 2 - 26 + 28 1 1 @@ -364,11 +387,15 @@ 1 + @@ -523,7 +550,8 @@ @@ -876,7 +920,7 @@ General 3 - 18 + 21 1 0 + + + + ICCARM 2 - 26 + 28 1 0 @@ -1229,11 +1295,15 @@ 1 + @@ -1388,7 +1458,8 @@ @@ -1752,6 +1839,9 @@ $PROJ_DIR$\..\..\..\os\hal\include\can.h + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h @@ -1761,6 +1851,9 @@ $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + $PROJ_DIR$\..\..\..\os\hal\include\mac.h @@ -1776,6 +1869,12 @@ $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + $PROJ_DIR$\..\..\..\os\hal\include\serial.h @@ -1791,6 +1890,9 @@ $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + src @@ -1800,6 +1902,9 @@ $PROJ_DIR$\..\..\..\os\hal\src\can.c + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c @@ -1809,6 +1914,9 @@ $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + $PROJ_DIR$\..\..\..\os\hal\src\mac.c @@ -1821,6 +1929,12 @@ $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + $PROJ_DIR$\..\..\..\os\hal\src\serial.c @@ -1970,46 +2084,25 @@ platform - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\adc_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\adc_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\can_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f100.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\can_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\core_cm3.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f105_f107.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f100.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f103.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\hal_lld_f105_f107.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pal_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pal_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.c @@ -2018,36 +2111,27 @@ $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32_dma.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32_dma.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.c - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32f10x.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.c + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h port - STM32 + STM32F1xx - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\cmparams.h + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\cmparams.h - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\vectors.s + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F1xx\vectors.s diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp index d84ff7beb..d6c066984 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp +++ b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp @@ -99,7 +99,7 @@ src @@ -1878,12 +1902,21 @@ $PROJ_DIR$\..\..\..\os\hal\src\can.c + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + $PROJ_DIR$\..\..\..\os\hal\src\hal.c $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + $PROJ_DIR$\..\..\..\os\hal\src\mac.c @@ -1896,15 +1929,27 @@ $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + $PROJ_DIR$\..\..\..\os\hal\src\spi.c $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + diff --git a/readme.txt b/readme.txt index 9653ea87e..5ea8fc151 100644 --- a/readme.txt +++ b/readme.txt @@ -160,7 +160,7 @@ - NEW: Added provisional support for STM32F2xx. Because of this some directories related to the STM32 have been renamed, your makefiles may require adjustments. - (TODO: change to be ported to IAR and Keil build files) + (TODO: change to be ported to Keil build files) - NEW: Added a custom rule to the various rules.mk files, now it is possible to add an user rule into the Makefiles. - NEW: Improvements to the trace buffer, now it stores a full thread pointer -- cgit v1.2.3 From da02a90b8cbe29a6304e7af0c1396c0274a4a9ce Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 10:34:03 +0000 Subject: Fixed bug 3413558. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3396 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/icu_lld.c | 18 +++++++++--------- os/hal/platforms/STM32/icu_lld.h | 4 ++++ os/hal/platforms/STM32/pwm_lld.c | 18 +++++++++--------- os/hal/platforms/STM32/pwm_lld.h | 4 ++++ readme.txt | 1 + 5 files changed, 27 insertions(+), 18 deletions(-) diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c index eaf98ec12..33eff67d5 100644 --- a/os/hal/platforms/STM32/icu_lld.c +++ b/os/hal/platforms/STM32/icu_lld.c @@ -281,7 +281,7 @@ void icu_lld_init(void) { * @notapi */ void icu_lld_start(ICUDriver *icup) { - uint32_t clock, psc; + uint32_t psc; if (icup->state == ICU_STOP) { /* Clock activation and timer reset.*/ @@ -291,7 +291,7 @@ void icu_lld_start(ICUDriver *icup) { rccResetTIM1(); NVICEnableVector(TIM1_CC_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM1_IRQ_PRIORITY)); - clock = STM32_TIMCLK2; + icup->clock = STM32_TIMCLK2; } #endif #if STM32_ICU_USE_TIM2 @@ -300,7 +300,7 @@ void icu_lld_start(ICUDriver *icup) { rccResetTIM2(); NVICEnableVector(TIM2_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM2_IRQ_PRIORITY)); - clock = STM32_TIMCLK1; + icup->clock = STM32_TIMCLK1; } #endif #if STM32_ICU_USE_TIM3 @@ -309,7 +309,7 @@ void icu_lld_start(ICUDriver *icup) { rccResetTIM3(); NVICEnableVector(TIM3_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM3_IRQ_PRIORITY)); - clock = STM32_TIMCLK1; + icup->clock = STM32_TIMCLK1; } #endif #if STM32_ICU_USE_TIM4 @@ -318,7 +318,7 @@ void icu_lld_start(ICUDriver *icup) { rccResetTIM4(); NVICEnableVector(TIM4_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM4_IRQ_PRIORITY)); - clock = STM32_TIMCLK1; + icup->clock = STM32_TIMCLK1; } #endif @@ -328,7 +328,7 @@ void icu_lld_start(ICUDriver *icup) { rccResetTIM5(); NVICEnableVector(TIM5_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM5_IRQ_PRIORITY)); - clock = STM32_TIMCLK1; + icup->clock = STM32_TIMCLK1; } #endif #if STM32_ICU_USE_TIM8 @@ -337,7 +337,7 @@ void icu_lld_start(ICUDriver *icup) { rccResetTIM5(); NVICEnableVector(TIM8_CC_IRQn, CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); - clock = STM32_TIMCLK2; + icup->clock = STM32_TIMCLK2; } #endif } @@ -352,9 +352,9 @@ void icu_lld_start(ICUDriver *icup) { } /* Timer configuration.*/ - psc = (clock / icup->config->frequency) - 1; + psc = (icup->clock / icup->config->frequency) - 1; chDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * icup->config->frequency) == clock, + ((psc + 1) * icup->config->frequency) == icup->clock, "icu_lld_start(), #1", "invalid frequency"); icup->tim->PSC = (uint16_t)psc; icup->tim->ARR = 0xFFFF; diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h index e7321e794..4c440b868 100644 --- a/os/hal/platforms/STM32/icu_lld.h +++ b/os/hal/platforms/STM32/icu_lld.h @@ -233,6 +233,10 @@ struct ICUDriver { ICU_DRIVER_EXT_FIELDS #endif /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; /** * @brief Pointer to the TIMx registers block. */ diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index 901474091..d8f98a432 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -341,7 +341,7 @@ void pwm_lld_init(void) { * @notapi */ void pwm_lld_start(PWMDriver *pwmp) { - uint32_t clock, psc; + uint32_t psc; uint16_t ccer; if (pwmp->state == PWM_STOP) { @@ -354,7 +354,7 @@ void pwm_lld_start(PWMDriver *pwmp) { CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); NVICEnableVector(TIM1_CC_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY)); - clock = STM32_TIMCLK2; + pwmp->clock = STM32_TIMCLK2; } #endif #if STM32_PWM_USE_TIM2 @@ -363,7 +363,7 @@ void pwm_lld_start(PWMDriver *pwmp) { rccResetTIM2(); NVICEnableVector(TIM2_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY)); - clock = STM32_TIMCLK1; + pwmp->clock = STM32_TIMCLK1; } #endif #if STM32_PWM_USE_TIM3 @@ -372,7 +372,7 @@ void pwm_lld_start(PWMDriver *pwmp) { rccResetTIM3(); NVICEnableVector(TIM3_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY)); - clock = STM32_TIMCLK1; + pwmp->clock = STM32_TIMCLK1; } #endif #if STM32_PWM_USE_TIM4 @@ -381,7 +381,7 @@ void pwm_lld_start(PWMDriver *pwmp) { rccResetTIM4(); NVICEnableVector(TIM4_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY)); - clock = STM32_TIMCLK1; + pwmp->clock = STM32_TIMCLK1; } #endif @@ -391,7 +391,7 @@ void pwm_lld_start(PWMDriver *pwmp) { rccResetTIM5(); NVICEnableVector(TIM5_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY)); - clock = STM32_TIMCLK1; + pwmp->clock = STM32_TIMCLK1; } #endif #if STM32_PWM_USE_TIM8 @@ -402,7 +402,7 @@ void pwm_lld_start(PWMDriver *pwmp) { CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); NVICEnableVector(TIM8_CC_IRQn, CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY)); - clock = STM32_TIMCLK2; + pwmp->clock = STM32_TIMCLK2; } #endif @@ -430,9 +430,9 @@ void pwm_lld_start(PWMDriver *pwmp) { } /* Timer configuration.*/ - psc = (clock / pwmp->config->frequency) - 1; + psc = (pwmp->clock / pwmp->config->frequency) - 1; chDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * pwmp->config->frequency) == clock, + ((psc + 1) * pwmp->config->frequency) == pwmp->clock, "pwm_lld_start(), #1", "invalid frequency"); pwmp->tim->PSC = (uint16_t)psc; pwmp->tim->ARR = (uint16_t)(pwmp->period - 1); diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index fb5a83790..d084b3dc7 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -315,6 +315,10 @@ struct PWMDriver { PWM_DRIVER_EXT_FIELDS #endif /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; /** * @brief Pointer to the TIMx registers block. */ diff --git a/readme.txt b/readme.txt index 5ea8fc151..c8cb07e7d 100644 --- a/readme.txt +++ b/readme.txt @@ -73,6 +73,7 @@ ***************************************************************************** *** 2.3.3 *** +- FIX: Fixed uninitialized variable in STM32 PWM and ICU drivers (bug 3413558). - FIX: Fixed wrong parameter passed to the DMA error hook in STM32 ADC driver, the DMA error hook has been removed entirely in the new ADC driver model (bug 3413214)(to be fixed in 2.2.8). -- cgit v1.2.3 From d379346fad1898bc2f7c62516ab282a87bc66e15 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 10:41:58 +0000 Subject: Updated Keil demos. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3397 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj | 31 +++--- demos/ARMCM3-STM32F103/keil/ch.uvproj | 75 +++++++++++++++ demos/ARMCM3-STM32F107/keil/ch.uvproj | 121 ++++++++++++------------ readme.txt | 1 - 4 files changed, 151 insertions(+), 77 deletions(-) diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj b/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj index cffe0a6e8..723042027 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj +++ b/demos/ARMCM3-STM32F100-DISCOVERY/keil/ch.uvproj @@ -346,7 +346,7 @@ __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base - ..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\boards\ST_STM32VL_DISCOVERY;..\..\..\test + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32\GPIOv1;..\..\..\os\hal\platforms\STM32\DMAv1;..\..\..\os\hal\platforms\STM32\USBv1;..\..\..\os\hal\platforms\STM32F1xx;..\..\..\boards\ST_STM32VL_DISCOVERY;..\..\..\test @@ -361,7 +361,7 @@ --cpreproc - ..\..\..\boards\ST_STM32VL_DISCOVERY;..\..\..\os\ports\RVCT\ARMCMx\STM32 + ..\;..\..\..\boards\ST_STM32VL_DISCOVERY;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx @@ -409,7 +409,7 @@ vectors.s 2 - ..\..\..\os\ports\RVCT\ARMCMx\STM32\vectors.s + D:\Progetti\ChibiOS-RT\os\ports\RVCT\ARMCMx\STM32F1xx\vectors.s chcoreasm_v7m.s @@ -794,7 +794,7 @@ adc_lld.c 1 - ..\..\..\os\hal\platforms\STM32\adc_lld.c + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\adc_lld.c can_lld.c @@ -804,12 +804,12 @@ hal_lld.c 1 - ..\..\..\os\hal\platforms\STM32\hal_lld.c + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld.c pal_lld.c 1 - ..\..\..\os\hal\platforms\STM32\pal_lld.c + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\GPIOv1\pal_lld.c pwm_lld.c @@ -829,7 +829,7 @@ stm32_dma.c 1 - ..\..\..\os\hal\platforms\STM32\stm32_dma.c + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\DMAv1\stm32_dma.c uart_lld.c @@ -839,32 +839,27 @@ adc_lld.h 5 - ..\..\..\os\hal\platforms\STM32\adc_lld.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\adc_lld.h can_lld.h 5 ..\..\..\os\hal\platforms\STM32\can_lld.h - - core_cm3.h - 5 - ..\..\..\os\hal\platforms\STM32\core_cm3.h - hal_lld.h 5 - ..\..\..\os\hal\platforms\STM32\hal_lld.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld.h hal_lld_f103.h 5 - ..\..\..\os\hal\platforms\STM32\hal_lld_f103.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\hal_lld_f103.h pal_lld.h 5 - ..\..\..\os\hal\platforms\STM32\pal_lld.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\GPIOv1\pal_lld.h pwm_lld.h @@ -884,12 +879,12 @@ stm32_dma.h 5 - ..\..\..\os\hal\platforms\STM32\stm32_dma.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32\DMAv1\stm32_dma.h stm32f10x.h 5 - ..\..\..\os\hal\platforms\STM32\stm32f10x.h + D:\Progetti\ChibiOS-RT\os\hal\platforms\STM32F1xx\stm32f10x.h uart_lld.h diff --git a/demos/ARMCM3-STM32F103/keil/ch.uvproj b/demos/ARMCM3-STM32F103/keil/ch.uvproj index 59cab5187..80066e03a 100644 --- a/demos/ARMCM3-STM32F103/keil/ch.uvproj +++ b/demos/ARMCM3-STM32F103/keil/ch.uvproj @@ -786,6 +786,81 @@ 5 ..\..\..\os\hal\include\uart.h + + ext.c + 1 + ..\..\..\os\hal\src\ext.c + + + gpt.c + 1 + ..\..\..\os\hal\src\gpt.c + + + icu.c + 1 + ..\..\..\os\hal\src\icu.c + + + rtc.c + 1 + ..\..\..\os\hal\src\rtc.c + + + sdc.c + 1 + ..\..\..\os\hal\src\sdc.c + + + serial_usb.c + 1 + ..\..\..\os\hal\src\serial_usb.c + + + usb.c + 1 + ..\..\..\os\hal\src\usb.c + + + ext.h + 5 + ..\..\..\os\hal\include\ext.h + + + gpt.h + 5 + ..\..\..\os\hal\include\gpt.h + + + icu.h + 5 + ..\..\..\os\hal\include\icu.h + + + rtc.h + 5 + ..\..\..\os\hal\include\rtc.h + + + sdc.h + 5 + ..\..\..\os\hal\include\sdc.h + + + serial_usb.h + 5 + ..\..\..\os\hal\include\serial_usb.h + + + usb.h + 5 + ..\..\..\os\hal\include\usb.h + + + usb_cdc.h + 5 + ..\..\..\os\hal\include\usb_cdc.h + diff --git a/demos/ARMCM3-STM32F107/keil/ch.uvproj b/demos/ARMCM3-STM32F107/keil/ch.uvproj index 71bb839e7..3600bb519 100644 --- a/demos/ARMCM3-STM32F107/keil/ch.uvproj +++ b/demos/ARMCM3-STM32F107/keil/ch.uvproj @@ -346,7 +346,7 @@ __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base - ..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\various;..\..\..\boards\OLIMEX_STM32_P107;..\..\..\test + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32F1xx;..\..\..\os\hal\platforms\STM32\GPIOv1;..\..\..\os\hal\platforms\STM32\DMAv1;..\..\..\os\various;..\..\..\boards\OLIMEX_STM32_P107;..\..\..\test @@ -361,7 +361,7 @@ --cpreproc - ..\..\..\boards\OLIMEX_STM32_P107;..\..\..\os\ports\RVCT\ARMCMx\STM32 + ..\;..\..\..\boards\OLIMEX_STM32_P107;..\..\..\os\ports\RVCT\ARMCMx\STM32F1xx @@ -409,7 +409,7 @@ vectors.s 2 - ..\..\..\os\ports\RVCT\ARMCMx\STM32\vectors.s + D:\Progetti\ChibiOS-RT\os\ports\RVCT\ARMCMx\STM32F1xx\vectors.s chcoreasm_v7m.s @@ -816,115 +816,120 @@ 5 ..\..\..\os\hal\include\usb.h - - - - platform - - adc_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\adc_lld.c + ext.h + 5 + ..\..\..\os\hal\include\ext.h - can_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\can_lld.c + icu.h + 5 + ..\..\..\os\hal\include\icu.h - hal_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\hal_lld.c + rtc.h + 5 + ..\..\..\os\hal\include\rtc.h - pal_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\pal_lld.c + sdc.h + 5 + ..\..\..\os\hal\include\sdc.h - pwm_lld.c - 1 - ..\..\..\os\hal\platforms\STM32\pwm_lld.c + usb_cdc.h + 5 + ..\..\..\os\hal\include\usb_cdc.h - serial_lld.c + ext.c 1 - ..\..\..\os\hal\platforms\STM32\serial_lld.c + ..\..\..\os\hal\src\ext.c - spi_lld.c + icu.c 1 - ..\..\..\os\hal\platforms\STM32\spi_lld.c + ..\..\..\os\hal\src\icu.c - stm32_dma.c + rtc.c 1 - ..\..\..\os\hal\platforms\STM32\stm32_dma.c + ..\..\..\os\hal\src\rtc.c - uart_lld.c + sdc.c 1 - ..\..\..\os\hal\platforms\STM32\uart_lld.c + ..\..\..\os\hal\src\sdc.c + + + + platform + - adc_lld.h + serial_lld.h 5 - ..\..\..\os\hal\platforms\STM32\adc_lld.h + ..\..\..\os\hal\platforms\STM32\serial_lld.h - can_lld.h - 5 - ..\..\..\os\hal\platforms\STM32\can_lld.h + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\serial_lld.c - core_cm3.h + stm32_dma.h 5 - ..\..\..\os\hal\platforms\STM32\core_cm3.h + ..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.h - hal_lld.h - 5 - ..\..\..\os\hal\platforms\STM32\hal_lld.h + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.c - hal_lld_f103.h + pal_lld.h 5 - ..\..\..\os\hal\platforms\STM32\hal_lld_f103.h + ..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.h - pal_lld.h - 5 - ..\..\..\os\hal\platforms\STM32\pal_lld.h + pal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\GPIOv1\pal_lld.c - pwm_lld.h + stm32f10x.h 5 - ..\..\..\os\hal\platforms\STM32\pwm_lld.h + ..\..\..\os\hal\platforms\STM32F1xx\stm32f10x.h - serial_lld.h + hal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld.c + + + hal_lld.h 5 - ..\..\..\os\hal\platforms\STM32\serial_lld.h + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld.h - spi_lld.h + hal_lld_f100.h 5 - ..\..\..\os\hal\platforms\STM32\spi_lld.h + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f100.h - stm32_dma.h + hal_lld_f103.h 5 - ..\..\..\os\hal\platforms\STM32\stm32_dma.h + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f103.h - stm32f10x.h + hal_lld_f105_f107.h 5 - ..\..\..\os\hal\platforms\STM32\stm32f10x.h + ..\..\..\os\hal\platforms\STM32F1xx\hal_lld_f105_f107.h - uart_lld.h + stm32_rcc.h 5 - ..\..\..\os\hal\platforms\STM32\uart_lld.h + ..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h diff --git a/readme.txt b/readme.txt index c8cb07e7d..6165592a8 100644 --- a/readme.txt +++ b/readme.txt @@ -161,7 +161,6 @@ - NEW: Added provisional support for STM32F2xx. Because of this some directories related to the STM32 have been renamed, your makefiles may require adjustments. - (TODO: change to be ported to Keil build files) - NEW: Added a custom rule to the various rules.mk files, now it is possible to add an user rule into the Makefiles. - NEW: Improvements to the trace buffer, now it stores a full thread pointer -- cgit v1.2.3 From f02cdbe2e8ad426e86b2da576f2f9f43cf186503 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 14:18:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3398 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32L152-DISCOVERY/halconf.h | 6 +- demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp | 18 +++ demos/ARMCM3-STM32L152-DISCOVERY/main.c | 178 ++++++++++++++++++++++++---- demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h | 6 +- 4 files changed, 180 insertions(+), 28 deletions(-) diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h index b9bee3656..e8acd1f13 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h @@ -45,7 +45,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE +#define HAL_USE_ADC TRUE #endif /** @@ -101,7 +101,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE +#define HAL_USE_PWM TRUE #endif /** @@ -129,7 +129,7 @@ * @brief Enables the SPI subsystem. */ #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE +#define HAL_USE_SPI TRUE #endif /** diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp index d6c066984..c70831761 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp +++ b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp @@ -2083,6 +2083,12 @@ platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\adc_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\adc_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32L1xx\hal_lld.c @@ -2095,12 +2101,24 @@ $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.c $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.h + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.c diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/main.c b/demos/ARMCM3-STM32L152-DISCOVERY/main.c index c5b0dd974..61532bcbd 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32L152-DISCOVERY/main.c @@ -22,24 +22,149 @@ #include "hal.h" #include "test.h" +static void pwmpcb(PWMDriver *pwmp); +static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); +static void spicb(SPIDriver *spip); + +/* Total number of channels to be sampled by a single ADC operation.*/ +#define ADC_GRP1_NUM_CHANNELS 2 + +/* Depth of the conversion buffer, channels are sampled four times each.*/ +#define ADC_GRP1_BUF_DEPTH 4 + +/* + * ADC samples buffer. + */ +static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; + +/* + * ADC conversion group. + * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. + * Channels: IN10 (48 cycles sample time) + * Sensor (192 cycles sample time) + */ +static const ADCConversionGroup adcgrpcfg = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + adccb, + NULL, + /* HW dependent part.*/ + 0, + 0, + 0, + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192), + 0, + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, + 0, + 0, + ADC_SQR5_SQ2_N(ADC_CHANNEL_IN10) | ADC_SQR5_SQ1_N(ADC_CHANNEL_SENSOR) +}; + +/* + * PWM configuration structure. + * Cyclic callback enabled, channels 3 and 4 enabled without callbacks, + * the active state is a logic one. + */ +static PWMConfig pwmcfg = { + 10000, /* 10KHz PWM clock frequency. */ + 10000, /* PWM period 1S (in ticks). */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + /* HW dependent part.*/ + 0 +}; + +/* + * SPI configuration structure. + * Maximum speed (12MHz), CPHA=0, CPOL=0, 16bits frames, MSb transmitted first. + * The slave select line is the pin GPIOA_SPI1NSS on the port GPIOA. + */ +static const SPIConfig spicfg = { + spicb, + /* HW dependent part.*/ + GPIOB, + 12, + SPI_CR1_DFF +}; + +/* + * PWM cyclic callback. + * A new ADC conversion is started. + */ +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + + /* Starts an asynchronous ADC conversion operation, the conversion + will be executed in parallel to the current PWM cycle and will + terminate before the next PWM cycle.*/ + chSysLockFromIsr(); + adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + chSysUnlockFromIsr(); +} + +/* + * ADC end conversion callback. + * The PWM channels are reprogrammed using the latest ADC samples. + * The latest samples are transmitted into a single SPI transaction. + */ +void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void) buffer; (void) n; + /* Note, only in the ADC_COMPLETE state because the ADC driver fires an + intermediate callback when the buffer is half full.*/ + if (adcp->state == ADC_COMPLETE) { + adcsample_t avg_ch1, avg_ch2; + + /* Calculates the average values from the ADC samples.*/ + avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; + avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; + + chSysLockFromIsr(); + + /* Changes the channels pulse width, the change will be effective + starting from the next cycle.*/ + pwmEnableChannelI(&PWMD4, 0, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch1)); + pwmEnableChannelI(&PWMD4, 1, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); + + /* SPI slave selection and transmission start.*/ + spiSelectI(&SPID2); + spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); + + chSysUnlockFromIsr(); + } +} + +/* + * SPI end transfer callback. + */ +static void spicb(SPIDriver *spip) { + + /* On transfer end just releases the slave select line.*/ + chSysLockFromIsr(); + spiUnselectI(spip); + chSysUnlockFromIsr(); +} + /* * This is a periodic thread that does absolutely nothing except increasing * a seconds counter. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { + static uint32_t seconds_counter; (void)arg; - chRegSetThreadName("blinker"); + chRegSetThreadName("counter"); while (TRUE) { - palSetPad(GPIOB, GPIOB_LED3); - chThdSleepMilliseconds(250); - palClearPad(GPIOB, GPIOB_LED3); - chThdSleepMilliseconds(250); - palSetPad(GPIOB, GPIOB_LED4); - chThdSleepMilliseconds(250); - palClearPad(GPIOB, GPIOB_LED4); - chThdSleepMilliseconds(250); + chThdSleepMilliseconds(1000); + seconds_counter++; } } @@ -75,27 +200,36 @@ int main(void) { TestThread(&SD1); /* - * Initializes the SPI driver 1. + * Initializes the SPI driver 2. The SPI2 signals are routed as follow: + * PB12 - NSS. + * PB13 - SCK. + * PB14 - MISO. + * PB15 - MOSI. */ -// spiStart(&SPID1, &spicfg); + spiStart(&SPID2, &spicfg); + palSetPad(GPIOB, 12); + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* NSS. */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ /* - * Initializes the ADC driver 1. + * Initializes the ADC driver 1 and enable the thermal sensor. * The pin PC0 on the port GPIOC is programmed as analog input. */ -// adcStart(&ADCD1, NULL); -// palSetGroupMode(GPIOC, PAL_PORT_BIT(0), PAL_MODE_INPUT_ANALOG); + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); /* - * Initializes the PWM driver 1, re-routes the TIM3 outputs, programs the - * pins as alternate functions. - * Note, the AFIO access routes the TIM3 output pins on the PC6...PC9 - * where the LEDs are connected. + * Initializes the PWM driver 4, routes the TIM4 outputs to the board LEDs. */ -// pwmStart(&PWMD3, &pwmcfg); -// AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_0 | AFIO_MAPR_TIM3_REMAP_1; -// palSetGroupMode(GPIOC, PAL_PORT_BIT(GPIOC_LED3) | PAL_PORT_BIT(GPIOC_LED4), -// PAL_MODE_STM32_ALTERNATE_PUSHPULL); + pwmStart(&PWMD4, &pwmcfg); + palSetPadMode(GPIOB, GPIOB_LED4, PAL_MODE_ALTERNATE(2)); + palSetPadMode(GPIOB, GPIOB_LED3, PAL_MODE_ALTERNATE(2)); /* * Creates the example thread. diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h index 4071c4507..3aa958d8f 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h @@ -122,8 +122,8 @@ #define STM32_PWM_USE_ADVANCED FALSE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 TRUE -#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 TRUE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM8 FALSE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 @@ -150,7 +150,7 @@ /* * SPI driver system settings. */ -#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 TRUE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_SPI1_DMA_PRIORITY 1 -- cgit v1.2.3 From 7d30f4c821023de001cd4459c83a1fdae2f8cb07 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Sep 2011 15:04:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3399 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/adc_lld.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c index eeae18f68..bc04df615 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.c +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -188,15 +188,13 @@ void adc_lld_stop(ADCDriver *adcp) { * @notapi */ void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode, cr2; + uint32_t mode; const ADCConversionGroup *grpp = adcp->grpp; /* DMA setup.*/ mode = adcp->dmamode; - cr2 = grpp->cr2; if (grpp->circular) { mode |= STM32_DMA_CR_CIRC; - cr2 |= ADC_CR2_CONT; } if (adcp->depth > 1) { /* If the buffer depth is greater than one then the half transfer interrupt @@ -214,7 +212,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ adcp->adc->SMPR2 = grpp->smpr2; adcp->adc->SMPR3 = grpp->smpr3; - adcp->adc->CR2 = cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS | + ADC_CR2_ADON; adcp->adc->SQR1 = grpp->sqr1; adcp->adc->SQR2 = grpp->sqr2; adcp->adc->SQR3 = grpp->sqr3; @@ -225,8 +224,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) { while ((adcp->adc->SR & ADC_SR_ADONS) == 0) ; /* ADC start by raising ADC_CR2_SWSTART.*/ - adcp->adc->CR2 = cr2 | ADC_CR2_SWSTART | ADC_CR2_DMA | ADC_CR2_DDS | - ADC_CR2_ADON; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_CONT | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; } /** -- cgit v1.2.3 From a6310af1976c528e7eae1c757cff6e4d14aa37a1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Sep 2011 05:41:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3400 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/ADC/main.c | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c index 706ec690e..75729108e 100644 --- a/testhal/STM32L1xx/ADC/main.c +++ b/testhal/STM32L1xx/ADC/main.c @@ -49,10 +49,30 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { /* * ADC conversion group. - * Mode: Streaming, continuous, 16 samples of 8 channels, SW triggered. + * Mode: Linear buffer, 16 samples of 8 channels, SW triggered. * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. */ -static const ADCConversionGroup adcgrpcfg = { +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + 0, 0, /* CR1, CR2 */ + 0, 0, 0, /* SMPR1...SMPR3 */ + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, 0, /* SQR2, SQR3 */ + ADC_SQR4_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR4_SQ7_N(ADC_CHANNEL_VREFINT), + ADC_SQR5_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ5_N(ADC_CHANNEL_IN10) | + ADC_SQR5_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ3_N(ADC_CHANNEL_IN10) | + ADC_SQR5_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg2 = { TRUE, ADC_GRP1_NUM_CHANNELS, adccallback, @@ -110,11 +130,21 @@ int main(void) { chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); /* - * Starts an ADC continuous conversion. + * Activates the ADC1 driver and the thermal sensor. */ adcStart(&ADCD1, NULL); adcSTM32EnableTSVREFE(); - adcStartConversion(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples, ADC_GRP1_BUF_DEPTH); /* * Normal main() thread activity, in this demo it does nothing. -- cgit v1.2.3 From 4c37f7b08813f3c0b805c605780938d7d2ef8ae6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Sep 2011 05:55:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3401 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32L1xx/ADC/main.c | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c index 75729108e..9f740a49c 100644 --- a/testhal/STM32L1xx/ADC/main.c +++ b/testhal/STM32L1xx/ADC/main.c @@ -21,10 +21,14 @@ #include "ch.h" #include "hal.h" -#define ADC_GRP1_NUM_CHANNELS 8 -#define ADC_GRP1_BUF_DEPTH 16 +#define ADC_GRP1_NUM_CHANNELS 1 +#define ADC_GRP1_BUF_DEPTH 8 -static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; /* * ADC streaming callback. @@ -33,7 +37,7 @@ size_t nx = 0, ny = 0; static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { (void)adcp; - if (samples == buffer) { + if (samples2 == buffer) { nx += n; } else { @@ -58,13 +62,12 @@ static const ADCConversionGroup adcgrpcfg1 = { NULL, adcerrorcallback, 0, 0, /* CR1, CR2 */ - 0, 0, 0, /* SMPR1...SMPR3 */ + 0, /* SMPR1 */ + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_9), + 0, /* SMPR3 */ ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), - 0, 0, /* SQR2, SQR3 */ - ADC_SQR4_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR4_SQ7_N(ADC_CHANNEL_VREFINT), - ADC_SQR5_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ5_N(ADC_CHANNEL_IN10) | - ADC_SQR5_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ3_N(ADC_CHANNEL_IN10) | - ADC_SQR5_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) + 0, 0, 0, /* SQR2, SQR3, SQR4 */ + ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) }; /* @@ -74,12 +77,15 @@ static const ADCConversionGroup adcgrpcfg1 = { */ static const ADCConversionGroup adcgrpcfg2 = { TRUE, - ADC_GRP1_NUM_CHANNELS, + ADC_GRP2_NUM_CHANNELS, adccallback, adcerrorcallback, 0, 0, /* CR1, CR2 */ - 0, 0, 0, /* SMPR1...SMPR3 */ - ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, /* SMPR1 */ + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192) | + ADC_SMPR2_SMP_VREF(ADC_SAMPLE_192), + 0, /* SMPR3 */ + ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), 0, 0, /* SQR2, SQR3 */ ADC_SQR4_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR4_SQ7_N(ADC_CHANNEL_VREFINT), ADC_SQR5_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ5_N(ADC_CHANNEL_IN10) | @@ -138,13 +144,13 @@ int main(void) { /* * Linear conversion. */ - adcConvert(&ADCD1, &adcgrpcfg1, samples, ADC_GRP1_BUF_DEPTH); + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); chThdSleepMilliseconds(1000); /* * Starts an ADC continuous conversion. */ - adcStartConversion(&ADCD1, &adcgrpcfg2, samples, ADC_GRP1_BUF_DEPTH); + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); /* * Normal main() thread activity, in this demo it does nothing. -- cgit v1.2.3 From 81d6a0d4b67af3260dc5367314510187781640f2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Sep 2011 06:20:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3402 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 1 - testhal/STM32F1xx/ADC/main.c | 61 ++++++++++++++++++++++++++++++++++---------- testhal/STM32L1xx/ADC/main.c | 2 +- 3 files changed, 48 insertions(+), 16 deletions(-) diff --git a/readme.txt b/readme.txt index 6165592a8..e0d604ae7 100644 --- a/readme.txt +++ b/readme.txt @@ -103,7 +103,6 @@ - NEW: STM32L ADC driver implementation. - NEW: Improved ADC driver model, now it is possible to handle error conditions during the conversion process. - (TODO: To be tested.) - NEW: STM32L1xx sub-family support, all STM32 drivers adapted and re-tested on the new platform except ADC that will need a specific implementation. - NEW: Added new API chThdExitS() in order to allow atomic operations on diff --git a/testhal/STM32F1xx/ADC/main.c b/testhal/STM32F1xx/ADC/main.c index bfb717b17..9cc316fa8 100644 --- a/testhal/STM32F1xx/ADC/main.c +++ b/testhal/STM32F1xx/ADC/main.c @@ -21,10 +21,14 @@ #include "ch.h" #include "hal.h" -#define ADC_GRP1_NUM_CHANNELS 8 -#define ADC_GRP1_BUF_DEPTH 16 +#define ADC_GRP1_NUM_CHANNELS 1 +#define ADC_GRP1_BUF_DEPTH 8 -static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; /* * ADC streaming callback. @@ -33,7 +37,7 @@ size_t nx = 0, ny = 0; static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { (void)adcp; - if (samples == buffer) { + if (samples2 == buffer) { nx += n; } else { @@ -49,19 +53,38 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { /* * ADC conversion group. - * Mode: Streaming, continuous, 16 samples of 8 channels, SW triggered. + * Mode: Linear buffer, 16 samples of 8 channels, SW triggered. * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. */ -static const ADCConversionGroup adcgrpcfg = { - TRUE, +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, ADC_GRP1_NUM_CHANNELS, - adccallback, + NULL, adcerrorcallback, - 0, - ADC_CR2_TSVREFE, - 0, - 0, + 0, 0, /* CR1, CR2 */ + ADC_SMPR1_SMP_AN10(ADC_SAMPLE_1P5), + 0, /* SMPR2 */ ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, /* SQR2 */ + ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + 0, ADC_CR2_TSVREFE, /* CR1, CR2 */ + ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | + ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5) | + ADC_SMPR1_SMP_VREF(ADC_SAMPLE_239P5), + 0, /* SMPR2 */ + ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), ADC_SQR2_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ7_N(ADC_CHANNEL_VREFINT), ADC_SQR3_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ5_N(ADC_CHANNEL_IN10) | ADC_SQR3_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ3_N(ADC_CHANNEL_IN10) | @@ -112,10 +135,20 @@ int main(void) { chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); /* - * Starts an ADC continuous conversion. + * Activates the ADC1 driver and the thermal sensor. */ adcStart(&ADCD1, NULL); - adcStartConversion(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); /* * Normal main() thread activity, in this demo it does nothing. diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c index 9f740a49c..b9890100e 100644 --- a/testhal/STM32L1xx/ADC/main.c +++ b/testhal/STM32L1xx/ADC/main.c @@ -63,7 +63,7 @@ static const ADCConversionGroup adcgrpcfg1 = { adcerrorcallback, 0, 0, /* CR1, CR2 */ 0, /* SMPR1 */ - ADC_SMPR2_SMP_AN10(ADC_SAMPLE_9), + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_4), 0, /* SMPR3 */ ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), 0, 0, 0, /* SQR2, SQR3, SQR4 */ -- cgit v1.2.3 From 00278617267aba8d6483bc0cc1290d771b6c2f93 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Sep 2011 09:31:19 +0000 Subject: Documentation related fixes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3403 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/DMAv1/stm32_dma.c | 1 + os/hal/platforms/STM32/DMAv1/stm32_dma.h | 2 +- os/hal/platforms/STM32/DMAv2/stm32_dma.c | 1 + os/hal/platforms/STM32/USBv1/usb_lld.c | 2 +- os/hal/platforms/STM32/USBv1/usb_lld.h | 2 +- os/hal/platforms/STM32F1xx/hal_lld_f100.h | 2 +- os/hal/platforms/STM32F1xx/hal_lld_f103.h | 2 +- os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 2 +- os/hal/platforms/STM32F1xx/platform.dox | 114 ++++++++++++++++++------- 9 files changed, 91 insertions(+), 37 deletions(-) diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.c b/os/hal/platforms/STM32/DMAv1/stm32_dma.c index 29ee02360..3fb1b2dc6 100644 --- a/os/hal/platforms/STM32/DMAv1/stm32_dma.c +++ b/os/hal/platforms/STM32/DMAv1/stm32_dma.c @@ -411,6 +411,7 @@ void dmaInit(void) { * @note This function can be invoked in both ISR or thread context. * * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream * @param[in] func handling function pointer, can be @p NULL * @param[in] param a parameter to be passed to the handling function * @return The operation status. diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.h b/os/hal/platforms/STM32/DMAv1/stm32_dma.h index ca9c429f7..22be4a67e 100644 --- a/os/hal/platforms/STM32/DMAv1/stm32_dma.h +++ b/os/hal/platforms/STM32/DMAv1/stm32_dma.h @@ -217,7 +217,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @brief DMA stream enable. * @note This function can be invoked in both ISR or thread context. * - * @param[in] dmachp pointer to a stm32_dma_stream_t structure + * @param[in] dmastp pointer to a stm32_dma_stream_t structure * * @special */ diff --git a/os/hal/platforms/STM32/DMAv2/stm32_dma.c b/os/hal/platforms/STM32/DMAv2/stm32_dma.c index 2b6851ad6..70f412083 100644 --- a/os/hal/platforms/STM32/DMAv2/stm32_dma.c +++ b/os/hal/platforms/STM32/DMAv2/stm32_dma.c @@ -450,6 +450,7 @@ void dmaInit(void) { * @note This function can be invoked in both ISR or thread context. * * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream * @param[in] func handling function pointer, can be @p NULL * @param[in] param a parameter to be passed to the handling function * @return The operation status. diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.c b/os/hal/platforms/STM32/USBv1/usb_lld.c index b22f8f0da..01bc50090 100644 --- a/os/hal/platforms/STM32/USBv1/usb_lld.c +++ b/os/hal/platforms/STM32/USBv1/usb_lld.c @@ -19,7 +19,7 @@ */ /** - * @file STM32/usb_lld.c + * @file STM32/USBv1/usb_lld.c * @brief STM32 USB subsystem low level driver source. * * @addtogroup USB diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.h b/os/hal/platforms/STM32/USBv1/usb_lld.h index 9b5e9dad2..47160af56 100644 --- a/os/hal/platforms/STM32/USBv1/usb_lld.h +++ b/os/hal/platforms/STM32/USBv1/usb_lld.h @@ -19,7 +19,7 @@ */ /** - * @file STM32/usb_lld.h + * @file STM32/USBv1/usb_lld.h * @brief STM32 USB subsystem low level driver header. * * @addtogroup USB diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 51cdf97e3..012cf0c11 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -26,7 +26,7 @@ */ /** - * @file STM32/hal_lld_f100.h + * @file STM32F1xx/hal_lld_f100.h * @brief STM32F100 Value Line HAL subsystem low level driver header. * * @addtogroup STM32F100_HAL diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 9ba74d239..7f493ee01 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -26,7 +26,7 @@ */ /** - * @file STM32/hal_lld_f103.h + * @file STM32F1xx/hal_lld_f103.h * @brief STM32F103 Performance Line HAL subsystem low level driver header. * * @addtogroup STM32F103_HAL diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 974b59f34..25e28c62d 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -26,7 +26,7 @@ */ /** - * @file STM32/hal_lld_f105_f107.h + * @file STM32F1xx/hal_lld_f105_f107.h * @brief STM32F10x Connectivity Line HAL subsystem low level driver header. * * @addtogroup STM32F10X_CL_HAL diff --git a/os/hal/platforms/STM32F1xx/platform.dox b/os/hal/platforms/STM32F1xx/platform.dox index de8d9a5d9..89f7520c5 100644 --- a/os/hal/platforms/STM32F1xx/platform.dox +++ b/os/hal/platforms/STM32F1xx/platform.dox @@ -19,7 +19,7 @@ */ /** - * @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers + * @defgroup STM32_DRIVERS STM32F1xx Drivers * @details This section describes all the supported drivers on the STM32F1xx * platform and the implementation details of the single drivers. * @@ -27,7 +27,7 @@ */ /** - * @defgroup STM32F1xx_HAL STM32F1xx Initialization Support + * @defgroup STM32_HAL STM32F1xx Initialization Support * @details The STM32F1xx HAL support is responsible for system initialization. * * @section stm32f1xx_hal_1 Supported HW resources @@ -44,11 +44,11 @@ * - SYSTICK initialization based on current clock and kernel required rate. * - DMA support initialization. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_ADC STM32F1xx ADC Support + * @defgroup STM32_ADC STM32F1xx ADC Support * @details The STM32F1xx ADC driver supports the ADC peripherals using DMA * channels for maximum performance. * @@ -64,11 +64,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - DMA errors detection. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_CAN STM32F1xx CAN Support + * @defgroup STM32_CAN STM32F1xx CAN Support * @details The STM32F1xx CAN driver uses the CAN peripherals. * * @section stm32f1xx_can_1 Supported HW resources @@ -79,11 +79,11 @@ * - Support for bxCAN sleep mode. * - Programmable bxCAN interrupts priority level. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_DMA STM32F1xx DMA Support + * @defgroup STM32_DMA STM32F1xx DMA Support * @details This DMA helper driver is used by the other drivers in order to * access the shared DMA resources in a consistent way. * @@ -98,11 +98,11 @@ * - Automatic DMA clock stop when not in use by any driver. * - DMA streams and interrupt vectors sharing among multiple drivers. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_EXT STM32F1xx EXT Support + * @defgroup STM32_EXT STM32F1xx EXT Support * @details The STM32F1xx EXT driver uses the EXTI peripheral. * * @section stm32f1xx_ext_1 Supported HW resources @@ -113,11 +113,11 @@ * - Programmable EXTI interrupts priority level. * - Capability to work as event sources (WFE) rather than interrupt sources. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_GPT STM32F1xx GPT Support + * @defgroup STM32_GPT STM32F1xx GPT Support * @details The STM32F1xx GPT driver uses the TIMx peripherals. * * @section stm32f1xx_gpt_1 Supported HW resources @@ -132,11 +132,27 @@ * peripherals are left in low power mode. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_ICU STM32F1xx ICU Support + * @defgroup STM32_I2C STM32F1xx I2C Support + * @details The STM32F1xx I2C driver uses the I2Cx peripherals. + * + * @section stm32f1xx_i2c_1 Supported HW resources + * - I2C1. + * - I2C2. + * . + * @section stm32f1xx_i2c_2 STM32F1xx I2C driver implementation features + * - Each I2C port can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable I2Cx interrupts priority level. + * . + * @ingroup STM32_DRIVERS + */ + +/** + * @defgroup STM32_ICU STM32F1xx ICU Support * @details The STM32F1xx ICU driver uses the TIMx peripherals. * * @section stm32f1xx_icu_1 Supported HW resources @@ -151,11 +167,21 @@ * peripherals are left in low power mode. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS + */ + +/** + * @defgroup STM32_MAC STM32 MAC Support + * @details The STM32 MAC driver supports the ETH peripheral. + * + * @section at91sam7_mac_1 Supported HW resources + * - ETH. + * . + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_PAL STM32F1xx PAL Support + * @defgroup STM32_PAL STM32F1xx PAL Support * @details The STM32F1xx PAL driver uses the GPIO peripherals. * * @section stm32f1xx_pal_1 Supported HW resources @@ -187,8 +213,8 @@ * - @p PAL_MODE_INPUT_ANALOG. * - @p PAL_MODE_OUTPUT_PUSHPULL. * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard). - * - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard). + * - @p PAL_MODE_STM32_ALTERNATE_PUSHPULL (non standard). + * - @p PAL_MODE_STM32_ALTERNATE_OPENDRAIN (non standard). * . * Any attempt to setup an invalid mode is ignored. * @@ -201,11 +227,11 @@ * resistor can change the resistor setting because the output latch is * used for resistor selection. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_PWM STM32F1xx PWM Support + * @defgroup STM32_PWM STM32F1xx PWM Support * @details The STM32F1xx PWM driver uses the TIMx peripherals. * * @section stm32f1xx_pwm_1 Supported HW resources @@ -221,11 +247,37 @@ * - Four independent PWM channels per timer. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS + */ + +/** + * @defgroup STM32_RCC STM32F1xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f1xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Periplerals clock disable. + * . + * @ingroup STM32_DRIVERS + */ + +/** + * @defgroup STM32_RTC STM32F1xx RTC Support + * @details The STM32F1xx RTC driver uses the RTC peripheral. + * + * @section stm32f1xx_rtc_1 Supported HW resources + * - RTC. + * . + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_SDC STM32F1xx SDC Support + * @defgroup STM32_SDC STM32F1xx SDC Support * @details The STM32F1xx SDC driver uses the SDIO peripheral. * * @section stm32f1xx_sdc_1 Supported HW resources @@ -238,11 +290,11 @@ * - DMA is used for receiving and transmitting. * - Programmable DMA bus priority for each DMA channel. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support + * @defgroup STM32_SERIAL STM32F1xx Serial Support * @details The STM32F1xx Serial driver uses the USART/UART peripherals in a * buffered, interrupt driven, implementation. * @@ -261,11 +313,11 @@ * - Fully interrupt driven. * - Programmable priority levels for each UART/USART. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_SPI STM32F1xx SPI Support + * @defgroup STM32_SPI STM32F1xx SPI Support * @details The SPI driver supports the STM32F1xx SPI peripherals using DMA * channels for maximum performance. * @@ -286,11 +338,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - Programmable DMA error hook. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_UART STM32F1xx UART Support + * @defgroup STM32_UART STM32F1xx UART Support * @details The UART driver supports the STM32F1xx USART peripherals using DMA * channels for maximum performance. * @@ -313,11 +365,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - Programmable DMA error hook. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32F1xx_USB STM32F1xx USB Support + * @defgroup STM32_USB STM32F1xx USB Support * @details The USB driver supports the STM32F1xx USB peripheral. * * @section stm32f1xx_usb_1 Supported HW resources @@ -329,5 +381,5 @@ * - Programmable interrupt priority levels. * - Each endpoint programmable in Control, Bulk and Interrupt modes. * . - * @ingroup STM32F1xx_DRIVERS + * @ingroup STM32_DRIVERS */ -- cgit v1.2.3 From 5edc2c8b69cd60a1c53b565e529e099c36a243c4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Sep 2011 09:34:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3404 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/platform.dox | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32F1xx/platform.dox b/os/hal/platforms/STM32F1xx/platform.dox index 89f7520c5..624a5b12f 100644 --- a/os/hal/platforms/STM32F1xx/platform.dox +++ b/os/hal/platforms/STM32F1xx/platform.dox @@ -171,7 +171,7 @@ */ /** - * @defgroup STM32_MAC STM32 MAC Support + * @defgroup STM32_MAC STM32F1xx MAC Support * @details The STM32 MAC driver supports the ETH peripheral. * * @section at91sam7_mac_1 Supported HW resources -- cgit v1.2.3 From 41fd0fb5fb2d446605e7a99c11f46d7c28071500 Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 25 Sep 2011 10:03:59 +0000 Subject: RTC. API changes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3405 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/rtc.h | 18 +- os/hal/platforms/STM32/RTCv1/rtc_lld.c | 334 +++++++++++++++++++++++++++++++++ os/hal/platforms/STM32/RTCv1/rtc_lld.h | 131 +++++++++++++ os/hal/platforms/STM32/rtc_lld.c | 321 ------------------------------- os/hal/platforms/STM32/rtc_lld.h | 114 ----------- os/hal/platforms/STM32F1xx/platform.mk | 5 +- os/hal/src/rtc.c | 38 ++-- 7 files changed, 504 insertions(+), 457 deletions(-) create mode 100644 os/hal/platforms/STM32/RTCv1/rtc_lld.c create mode 100644 os/hal/platforms/STM32/RTCv1/rtc_lld.h delete mode 100644 os/hal/platforms/STM32/rtc_lld.c delete mode 100644 os/hal/platforms/STM32/rtc_lld.h diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h index 5adf9559c..02aec2ceb 100644 --- a/os/hal/include/rtc.h +++ b/os/hal/include/rtc.h @@ -74,10 +74,20 @@ extern "C" { rtccb_t secondcb, rtccb_t alarmcb); #endif /* RTC_SUPPORTS_CALLBACKS */ - void rtcSetTime(uint32_t tv_sec); - uint32_t rtcGetTime(uint16_t *msec); - void rtcSetAlarm(uint32_t tv_alarm); - uint32_t rtcGetAlarm(void); + void rtcSetTime(RTCDateTime *timespec); + void rtcGetTime(RTCDateTime *timespec); + + + + + void rtcSetAlarm(RTCDateTime *timespec); + void rtcGetAlarm(RTCDateTime *timespec); + + + + + + #ifdef __cplusplus } #endif diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c new file mode 100644 index 000000000..a3329544e --- /dev/null +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c @@ -0,0 +1,334 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/rtc_lld.c + * @brief STM32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#include "ch.h" +#include "hal.h" + + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief RTC driver identifier.*/ +RTCDriver RTCD; + + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] rtcp pointer to a @p RTCDriver object + * + * @notapi + */ +#if RTC_SUPPORTS_CALLBACKS + +static void rtc_lld_serve_interrupt(RTCDriver *rtcp){ + chSysLockFromIsr(); + + if ((RTC->CRH & RTC_CRH_SECIE) && \ + (RTC->CRL & RTC_CRL_SECF) && \ + (rtcp->second_cb != NULL)){ + rtcp->second_cb(rtcp); + RTC->CRL &= ~RTC_CRL_SECF; + } + if ((RTC->CRH & RTC_CRH_ALRIE) && \ + (RTC->CRL & RTC_CRL_ALRF) && \ + (rtcp->alarm_cb != NULL)){ + rtcp->alarm_cb(rtcp); + RTC->CRL &= ~RTC_CRL_ALRF; + } + if ((RTC->CRH & RTC_CRH_OWIE) && \ + (RTC->CRL & RTC_CRL_OWF) && \ + (rtcp->overflow_cb != NULL)){ + rtcp->overflow_cb(rtcp); + RTC->CRL &= ~RTC_CRL_OWF; + } + + chSysUnlockFromIsr(); +} +#endif /* RTC_SUPPORTS_CALLBACKS */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief RTC interrupt handler. + * @isr + */ +#if RTC_SUPPORTS_CALLBACKS + +CH_IRQ_HANDLER(RTC_IRQHandler) { + CH_IRQ_PROLOGUE(); + rtc_lld_serve_interrupt(&RTCD); + CH_IRQ_EPILOGUE(); +} + +#endif /* RTC_SUPPORTS_CALLBACKS */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enable access to registers and initialize RTC if BKP domain + * was previously reseted. + * + * @note: Cold start time of LSE oscillator on STM32 platform + * takes about 3 seconds. + * + * @notapi + */ +void rtc_lld_init(void){ + uint32_t preload = 0; + + rccEnableBKPInterface(FALSE); + + /* enable access to BKP registers */ + PWR->CR |= PWR_CR_DBP; + /* select clock source */ + RCC->BDCR |= STM32_RTC; + +#if STM32_RTC == STM32_RTC_LSE + if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ + RCC->BDCR |= RCC_BDCR_LSEON; + while(!(RCC->BDCR & RCC_BDCR_LSERDY)) + ; + RCC->BDCR |= RCC_BDCR_RTCEN; + } + preload = STM32_LSECLK - 1; + +#elif STM32_RTC == STM32_RTC_LSI + RCC->CSR |= RCC_CSR_LSION; + while(!(RCC->CSR & RCC_CSR_LSIRDY)) + ; + /* According to errata sheet we must wait additional 100 uS for stabilization */ + uint32_t tmo = (STM32_SYSCLK / 1000000 ) * 100; + while(tmo--) + ; + RCC->BDCR |= RCC_BDCR_RTCEN; + preload = STM32_LSICLK - 1; + +#elif STM32_RTC == STM32_RTC_HSE + preload = (STM32_HSICLK / 128) - 1; + +#else +#error "RTC clock source not selected" +#endif + + /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling + * clocking on APB1, because these values only update when APB1 functioning.*/ + RTC->CRL &= ~(RTC_CRL_RSF); + while (!(RTC->CRL & RTC_CRL_RSF)) + ; + + /* Write preload register only if its value changed */ + if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLL)){ + while(!(RTC->CRL & RTC_CRL_RTOFF)) + ; + + RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ + RTC->PRLH = (uint16_t)((preload >> 16) & 0b1111); /* write preloader */ + RTC->PRLL = (uint16_t)(preload & 0xFFFF); + RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ + ; + } + + /* disable all interrupts and clear all even flags just to be safe */ + RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE); + RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + +#if RTC_SUPPORTS_CALLBACKS + RTCD.alarm_cb = NULL; + RTCD.overflow_cb = NULL; + RTCD.second_cb = NULL; +#endif /* RTC_SUPPORTS_CALLBACKS */ +} + +/** + * @brief Enables and disables callbacks on the fly. + * + * @details Pass callback function(s) in argument(s) to enable callback(s). + * Pass NULL to disable callback. + * + * @pre To use this function you must set @p RTC_SUPPORTS_CALLBACKS + * to @p TRUE. + * + * @param[in] rtcp pointer to RTC driver structure. + * @param[in] overflowcb overflow callback function. + * @param[in] secondcb every second callback function. + * @param[in] alarmcb alarm callback function. + * + * @notapi + */ +#if RTC_SUPPORTS_CALLBACKS +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t overflowcb, + rtccb_t secondcb, rtccb_t alarmcb){ + + uint16_t isr_flags = 0; + + if (overflowcb != NULL){ + rtcp->overflow_cb = *overflowcb; + isr_flags |= RTC_CRH_OWIE; + } + else{ + rtcp->overflow_cb = NULL; + isr_flags &= ~RTC_CRH_OWIE; + } + + if (alarmcb != NULL){ + rtcp->alarm_cb = *alarmcb; + isr_flags |= RTC_CRH_ALRIE; + } + else{ + rtcp->alarm_cb = NULL; + isr_flags &= ~RTC_CRH_ALRIE; + } + + if (secondcb != NULL){ + rtcp->second_cb = *secondcb; + isr_flags |= RTC_CRH_SECIE; + } + else{ + rtcp->second_cb = NULL; + isr_flags &= ~RTC_CRH_SECIE; + } + + if(isr_flags != 0){ + NVICEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); + RTC->CRH |= isr_flags; + } + else{ + NVICDisableVector(RTC_IRQn); + RTC->CRH = 0; + } +} +#endif /* RTC_SUPPORTS_CALLBACKS */ + +/** + * @brief Set current time. + * + * @param[in] timespec pointer to variable storing time. + * + * @note Fractional part will be silently ignored. There is no possibility + * to change it on STM32F1xx platform. + * @notapi + */ +void rtc_lld_set_time(RTCDateTime *timespec){ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) + ; + + RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ + RTC->CNTH = (uint16_t)((timespec->tv_sec >> 16) & 0xFFFF); + RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF); + RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ + ; +} + +/** + * @brief Get current time. + * + * @param[in] msec pointer to variable for storing fractional part of + * time (milliseconds). + * + * @notapi + */ +inline void rtc_lld_get_time(RTCDateTime *timespec){ + uint32_t time_frac = 0; + time_frac = (((uint32_t)RTC->DIVH) << 16) + (RTC->DIVL); + + timespec->tv_msec = (uint16_t)(((STM32_LSECLK - time_frac) * 1000) / STM32_LSECLK); + timespec->tv_sec = (RTC->CNTH << 16) + RTC->CNTL; +} + +/** + * @brief Set alarm time. + * + * @param[in] timespec pointer to variable storing time of alarm. + * + * @note Fractional part will be silently ignored. There is no possibility + * to change it on STM32F1xx platform. + * + * @note Default value after BKP domain reset is 0xFFFFFFFF + * + * @notapi + */ +void rtc_lld_set_alarm(RTCDateTime *timespec){ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) + ; + + RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ + RTC->ALRH = (uint16_t)((timespec->tv_sec >> 16) & 0xFFFF); + RTC->ALRL = (uint16_t)(timespec->tv_sec & 0xFFFF); + RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ + +#if !(RTC_SUPPORTS_CALLBACKS) + RTC->CRL &= ~RTC_CRL_ALRF; + RTC->CRH |= RTC_CRH_ALRIE; +#endif /* !(RTC_SUPPORTS_CALLBACKS) */ + + while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ + ; +} + +/** + * @brief Get current alarm time. + * + * @param[in] timespec pointer to variable storing time of alarm. + * + * @note Fractional part will be silently ignored. There is no possibility + * to change it on STM32F1xx platform. + * + * @note Default value after BKP domain reset is 0xFFFFFFFF + * + * @notapi + */ +inline void rtc_lld_get_alarm(RTCDateTime *timespec){ + timespec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL); +} + + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/os/hal/platforms/STM32/RTCv1/rtc_lld.h new file mode 100644 index 000000000..125b6c11e --- /dev/null +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.h @@ -0,0 +1,131 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/rtc_lld.h + * @brief STM32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef _RTC_LLD_H_ +#define _RTC_LLD_H_ + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @brief Switch to TRUE if you need callbacks from RTC. Switch to FALSE + * if you need only time keeping. + * @note Default is true. + */ +#if !defined(RTC_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) +#define RTC_SUPPORTS_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !STM32_HAS_RTC +#error "RTC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + + + + + +typedef struct { + uint32_t tv_sec; + uint32_t tv_msec; +}RTCDateTime; + + + + + + + +/** + * @brief Structure representing an RTC driver. + * @note This driver if dummy when callbacks disabled. + */ +struct RTCDriver{ +#if RTC_SUPPORTS_CALLBACKS + /** + * @brief Overflow callback. Set it to NULL if not used. + */ + rtccb_t overflow_cb; + + /** + * @brief Every second callback. Set it to NULL if not used. + */ + rtccb_t second_cb; + + /** + * @brief Alarm callback. Set it to NULL if not used. + */ + rtccb_t alarm_cb; +#endif /* RTC_SUPPORTS_CALLBACKS */ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern RTCDriver RTCD; + + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_init(void); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t overflow_cb, + rtccb_t second_cb, rtccb_t alarm_cb); + + void rtc_lld_set_time(RTCDateTime *timespec); + void rtc_lld_get_time(RTCDateTime *timespec); + + void rtc_lld_get_alarm(RTCDateTime *timespec); + void rtc_lld_set_alarm(RTCDateTime *timespec); +#ifdef __cplusplus +} +#endif + + +#endif /* HAL_USE_RTC */ +#endif /* _RTC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c deleted file mode 100644 index c1163d1a1..000000000 --- a/os/hal/platforms/STM32/rtc_lld.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/rtc_lld.c - * @brief STM32 RTC subsystem low level driver header. - * - * @addtogroup RTC - * @{ - */ - -#include "ch.h" -#include "hal.h" - - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief RTC driver identifier.*/ -RTCDriver RTCD; - - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared IRQ handler. - * - * @param[in] rtcp pointer to a @p RTCDriver object - * - * @notapi - */ -#if RTC_SUPPORTS_CALLBACKS - -static void rtc_lld_serve_interrupt(RTCDriver *rtcp){ - chSysLockFromIsr(); - - if ((RTC->CRH & RTC_CRH_SECIE) && \ - (RTC->CRL & RTC_CRL_SECF) && \ - (rtcp->second_cb != NULL)){ - rtcp->second_cb(rtcp); - RTC->CRL &= ~RTC_CRL_SECF; - } - if ((RTC->CRH & RTC_CRH_ALRIE) && \ - (RTC->CRL & RTC_CRL_ALRF) && \ - (rtcp->alarm_cb != NULL)){ - rtcp->alarm_cb(rtcp); - RTC->CRL &= ~RTC_CRL_ALRF; - } - if ((RTC->CRH & RTC_CRH_OWIE) && \ - (RTC->CRL & RTC_CRL_OWF) && \ - (rtcp->overflow_cb != NULL)){ - rtcp->overflow_cb(rtcp); - RTC->CRL &= ~RTC_CRL_OWF; - } - - chSysUnlockFromIsr(); -} -#endif /* RTC_SUPPORTS_CALLBACKS */ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief RTC interrupt handler. - * @isr - */ -#if RTC_SUPPORTS_CALLBACKS - -CH_IRQ_HANDLER(RTC_IRQHandler) { - CH_IRQ_PROLOGUE(); - rtc_lld_serve_interrupt(&RTCD); - CH_IRQ_EPILOGUE(); -} - -#endif /* RTC_SUPPORTS_CALLBACKS */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enable access to registers and initialize RTC if BKP domain - * was previously reseted. - * - * @note: Cold start time of LSE oscillator on STM32 platform - * takes about 3 seconds. - * - * @notapi - */ -void rtc_lld_init(void){ - uint32_t preload = 0; - - rccEnableBKPInterface(FALSE); - - /* enable access to BKP registers */ - PWR->CR |= PWR_CR_DBP; - /* select clock source */ - RCC->BDCR |= STM32_RTC; - -#if STM32_RTC == STM32_RTC_LSE - if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ - RCC->BDCR |= RCC_BDCR_LSEON; - while(!(RCC->BDCR & RCC_BDCR_LSERDY)) - ; - RCC->BDCR |= RCC_BDCR_RTCEN; - } - preload = STM32_LSECLK - 1; - -#elif STM32_RTC == STM32_RTC_LSI - RCC->CSR |= RCC_CSR_LSION; - while(!(RCC->CSR & RCC_CSR_LSIRDY)) - ; - /* According to errata sheet we must wait additional 100 uS for stabilization */ - uint32_t tmo = (STM32_SYSCLK / 1000000 ) * 100; - while(tmo--) - ; - RCC->BDCR |= RCC_BDCR_RTCEN; - preload = STM32_LSICLK - 1; - -#elif STM32_RTC == STM32_RTC_HSE - preload = (STM32_HSICLK / 128) - 1; - -#else -#error "RTC clock source not selected" -#endif - - /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling - * clocking on APB1, because these values only update when APB1 functioning.*/ - RTC->CRL &= ~(RTC_CRL_RSF); - while (!(RTC->CRL & RTC_CRL_RSF)) - ; - - /* Write preload register only if its value changed */ - if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLL)){ - while(!(RTC->CRL & RTC_CRL_RTOFF)) - ; - - RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ - RTC->PRLH = (uint16_t)((preload >> 16) & 0b1111); /* write preloader */ - RTC->PRLL = (uint16_t)(preload & 0xFFFF); - RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ - - while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ - ; - } - - /* disable all interrupts and clear all even flags just to be safe */ - RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE); - RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); - -#if RTC_SUPPORTS_CALLBACKS - RTCD.alarm_cb = NULL; - RTCD.overflow_cb = NULL; - RTCD.second_cb = NULL; -#endif /* RTC_SUPPORTS_CALLBACKS */ -} - -/** - * @brief Enables and disables callbacks on the fly. - * - * @details Pass callback function(s) in argument(s) to enable callback(s). - * Pass NULL to disable callback. - * - * @pre To use this function you must set @p RTC_SUPPORTS_CALLBACKS - * to @p TRUE. - * - * @param[in] rtcp pointer to RTC driver structure. - * @param[in] overflowcb overflow callback function. - * @param[in] secondcb every second callback function. - * @param[in] alarmcb alarm callback function. - * - * @notapi - */ -#if RTC_SUPPORTS_CALLBACKS -void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t overflowcb, - rtccb_t secondcb, rtccb_t alarmcb){ - - uint16_t isr_flags = 0; - - if (overflowcb != NULL){ - rtcp->overflow_cb = *overflowcb; - isr_flags |= RTC_CRH_OWIE; - } - else{ - rtcp->overflow_cb = NULL; - isr_flags &= ~RTC_CRH_OWIE; - } - - if (alarmcb != NULL){ - rtcp->alarm_cb = *alarmcb; - isr_flags |= RTC_CRH_ALRIE; - } - else{ - rtcp->alarm_cb = NULL; - isr_flags &= ~RTC_CRH_ALRIE; - } - - if (secondcb != NULL){ - rtcp->second_cb = *secondcb; - isr_flags |= RTC_CRH_SECIE; - } - else{ - rtcp->second_cb = NULL; - isr_flags &= ~RTC_CRH_SECIE; - } - - if(isr_flags != 0){ - NVICEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); - RTC->CRH |= isr_flags; - } - else{ - NVICDisableVector(RTC_IRQn); - RTC->CRH = 0; - } -} -#endif /* RTC_SUPPORTS_CALLBACKS */ - -/** - * @brief Set current time. - * - * @param[in] tv_sec time value in UNIX notation. - * - * @notapi - */ -void rtc_lld_set_time(uint32_t tv_sec){ - - while(!(RTC->CRL & RTC_CRL_RTOFF)) - ; - - RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ - RTC->CNTH = (uint16_t)((tv_sec >> 16) & 0xFFFF); /* write time */ - RTC->CNTL = (uint16_t)(tv_sec & 0xFFFF); - RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ - - while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ - ; -} - -/** - * @brief Return return seconds since UNIX epoch. - * - * @param[in] msec pointer to variable for storing fractional part of - * time (milliseconds). - * - * @notapi - */ -inline uint32_t rtc_lld_get_time(uint16_t *msec){ - uint32_t time_frac = 0; - if(msec != NULL){ - time_frac = (((uint32_t)RTC->DIVH) << 16) + (RTC->DIVL); - *msec = (uint16_t)(((STM32_LSECLK - time_frac) * 1000) / STM32_LSECLK); - } - return ((RTC->CNTH << 16) + RTC->CNTL); -} - -/** - * @brief Set alarm date in UNIX notation. - * @note Default value after BKP domain reset is 0xFFFFFFFF - * - * @notapi - */ -void rtc_lld_set_alarm(uint32_t tv_alarm){ - - while(!(RTC->CRL & RTC_CRL_RTOFF)) - ; - - RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ - RTC->ALRH = (uint16_t)((tv_alarm >> 16) & 0xFFFF); /* write time */ - RTC->ALRL = (uint16_t)(tv_alarm & 0xFFFF); - RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ - -#if !(RTC_SUPPORTS_CALLBACKS) - RTC->CRL &= ~RTC_CRL_ALRF; - RTC->CRH |= RTC_CRH_ALRIE; -#endif /* !(RTC_SUPPORTS_CALLBACKS) */ - - while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ - ; -} - -/** - * @brief Get current alarm date in UNIX notation. - * @note Default value after BKP domain reset is 0xFFFFFFFF - * - * @notapi - */ -inline uint32_t rtc_lld_get_alarm(void){ - return ((RTC->ALRH << 16) + RTC->ALRL); -} - - -#endif /* HAL_USE_RTC */ - -/** @} */ diff --git a/os/hal/platforms/STM32/rtc_lld.h b/os/hal/platforms/STM32/rtc_lld.h deleted file mode 100644 index d73d35091..000000000 --- a/os/hal/platforms/STM32/rtc_lld.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/rtc_lld.h - * @brief STM32 RTC subsystem low level driver header. - * - * @addtogroup RTC - * @{ - */ - -#ifndef _RTC_LLD_H_ -#define _RTC_LLD_H_ - -#if HAL_USE_RTC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @brief Switch to TRUE if you need callbacks from RTC. Switch to FALSE - * if you need only time keeping. - * @note Default is true. - */ -#if !defined(RTC_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) -#define RTC_SUPPORTS_CALLBACKS TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if HAL_USE_RTC && !STM32_HAS_RTC -#error "RTC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Structure representing an RTC driver. - * @note This driver if dummy when callbacks disabled. - */ -struct RTCDriver{ -#if RTC_SUPPORTS_CALLBACKS - /** - * @brief Overflow callback. Set it to NULL if not used. - */ - rtccb_t overflow_cb; - - /** - * @brief Every second callback. Set it to NULL if not used. - */ - rtccb_t second_cb; - - /** - * @brief Alarm callback. Set it to NULL if not used. - */ - rtccb_t alarm_cb; -#endif /* RTC_SUPPORTS_CALLBACKS */ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern RTCDriver RTCD; - - -#ifdef __cplusplus -extern "C" { -#endif - void rtc_lld_init(void); - void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t overflow_cb, - rtccb_t second_cb, rtccb_t alarm_cb); - void rtc_lld_set_time(uint32_t tv_sec); - uint32_t rtc_lld_get_time(uint16_t *msec); - uint32_t rtc_lld_get_alarm(void); - void rtc_lld_set_alarm(uint32_t); -#ifdef __cplusplus -} -#endif - - -#endif /* HAL_USE_RTC */ -#endif /* _RTC_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk index 51601731e..a73f1b4f3 100644 --- a/os/hal/platforms/STM32F1xx/platform.mk +++ b/os/hal/platforms/STM32F1xx/platform.mk @@ -15,11 +15,12 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/rtc_lld.c + ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \ ${CHIBIOS}/os/hal/platforms/STM32 \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \ ${CHIBIOS}/os/hal/platforms/STM32/DMAv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/USBv1 + ${CHIBIOS}/os/hal/platforms/STM32/USBv1 \ + ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index 3b4b5824b..0c8959ea6 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -83,36 +83,42 @@ void rtcSetCallback(RTCDriver *rtcp, rtccb_t overflowcb, /** * @brief Set current time. - * @param[in] tv_sec - time value in UNIX notation. + * + * @param[in] timespec pointer to variable storing time. */ -void rtcSetTime(uint32_t tv_sec){ - rtc_lld_set_time(tv_sec); +void rtcSetTime(RTCDateTime *timespec){ + chDbgCheck((timespec != NULL), "rtcSetTime"); + rtc_lld_set_time(timespec); } /** - * @brief Return return seconds since UNIX epoch. - * - * @param[in] msec pointer to variable for storing fractional part of - * time (milliseconds). + * @brief Get current time. * - * @notapi + * @param[in] timespec pointer to variable storing time. */ -inline uint32_t rtcGetTime(uint16_t *msec){ - return rtc_lld_get_time(msec); +void rtcGetTime(RTCDateTime *timespec){ + chDbgCheck((timespec != NULL), "rtcGetTime"); + rtc_lld_get_time(timespec); } /** - * @brief Set alarm date in UNIX notation. + * @brief Set alarm time. + * + * @param[in] timespec pointer to variable storing time of alarm. */ -void rtcSetAlarm(uint32_t tv_alarm){ - rtc_lld_set_alarm(tv_alarm); +void rtcSetAlarm(RTCDateTime *timespec){ + chDbgCheck((timespec != NULL), "rtcSetAlarm"); + rtc_lld_set_alarm(timespec); } /** - * @brief Get current alarm date in UNIX notation. + * @brief Get current alarm. + * + * @param[in] timespec pointer to variable to store alarm time. */ -inline uint32_t rtcGetAlarm(void){ - return rtc_lld_get_alarm(); +void rtcGetAlarm(RTCDateTime *timespec){ + chDbgCheck((timespec != NULL), "rtcGetAlarm"); + rtc_lld_get_alarm(timespec); } #endif /* HAL_USE_RTC */ -- cgit v1.2.3 From 17a20fe36a9356f8d73088ad0411486710210e24 Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 25 Sep 2011 10:06:23 +0000 Subject: RTC. Documentation improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3406 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/RTCv1/rtc_lld.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/os/hal/platforms/STM32/RTCv1/rtc_lld.h index 125b6c11e..37f8e105e 100644 --- a/os/hal/platforms/STM32/RTCv1/rtc_lld.h +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.h @@ -59,24 +59,24 @@ /* Driver data structures and types. */ /*===========================================================================*/ - - - - +/** + * @brief Structure representing an RTC time value. + */ typedef struct { + /** + * @brief Seconds sins UNIX epoch. + */ uint32_t tv_sec; + /** + * @brief Fractional part. + */ uint32_t tv_msec; }RTCDateTime; - - - - - /** * @brief Structure representing an RTC driver. - * @note This driver if dummy when callbacks disabled. + * @note This driver is dummy when callbacks disabled. */ struct RTCDriver{ #if RTC_SUPPORTS_CALLBACKS -- cgit v1.2.3 From fa0a7f52dbe51185794b3fa5c0279738790ee131 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Sep 2011 10:11:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3407 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2c.h | 105 ++++++++++++++++++++++++--------------------------- 1 file changed, 50 insertions(+), 55 deletions(-) diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index acf09ec9c..cf4d47713 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -34,24 +34,27 @@ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ -#define I2CD_NO_ERROR 0 -/** @brief Bus Error.*/ -#define I2CD_BUS_ERROR 0x01 -/** @brief Arbitration Lost (master mode).*/ -#define I2CD_ARBITRATION_LOST 0x02 -/** @brief Acknowledge Failure.*/ -#define I2CD_ACK_FAILURE 0x04 -/** @brief Overrun/Underrun.*/ -#define I2CD_OVERRUN 0x08 -/** @brief PEC Error in reception.*/ -#define I2CD_PEC_ERROR 0x10 -/** @brief Timeout or Tlow Error.*/ -#define I2CD_TIMEOUT 0x20 -/** @brief SMBus Alert.*/ -#define I2CD_SMB_ALERT 0x40 + +/** + * @name I2C bus error conditions + * @{ + */ +#define I2CD_NO_ERROR 0x00 /**< @brief No error. */ +#define I2CD_BUS_ERROR 0x01 /**< @brief Bus Error. */ +#define I2CD_ARBITRATION_LOST 0x02 /**< @brief Arbitration Lost + (master mode). */ +#define I2CD_ACK_FAILURE 0x04 /**< @brief Acknowledge Failure.*/ +#define I2CD_OVERRUN 0x08 /**< @brief Overrun/Underrun. */ +#define I2CD_PEC_ERROR 0x10 /**< @brief PEC Error in + reception. */ +#define I2CD_TIMEOUT 0x20 /**< @brief Timeout Error. */ +#define I2CD_SMB_ALERT 0x40 /**< @brief SMBus Alert. */ +/** @} */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -66,6 +69,7 @@ /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ + #if I2C_USE_MUTUAL_EXCLUSION && !CH_USE_MUTEXES && !CH_USE_SEMAPHORES #error "I2C_USE_MUTUAL_EXCLUSION requires CH_USE_MUTEXES and/or CH_USE_SEMAPHORES" #endif @@ -78,27 +82,20 @@ * @brief Driver state machine possible states. */ typedef enum { - /* master part */ - I2C_UNINIT = 0, /**< @brief Not initialized. */ - I2C_STOP = 1, /**< @brief Stopped. */ - I2C_READY = 2, /**< @brief Ready. */ - I2C_ACTIVE_TRANSMIT = 3, /**< @brief Transmit in progress. */ - I2C_ACTIVE_RECEIVE = 4, /**< @brief Receive in progress. */ - I2C_ACTIVE_TRANSCEIVE = 5, /**< @brief Receive after transmit in progress. */ - - /* Slave part. Not realized. */ - I2C_SACTIVE = 10, - I2C_STRANSMIT = 11, - I2C_SRECEIVE = 12, + I2C_UNINIT = 0, /**< Not initialized. */ + I2C_STOP = 1, /**< Stopped. */ + I2C_READY = 2, /**< Ready. */ + I2C_ACTIVE_TRANSMIT = 3, /**< Transmitting. */ + I2C_ACTIVE_RECEIVE = 4, /**< Receiving. */ + I2C_ACTIVE_TRANSCEIVE = 5, /**< Receiving after transmit. */ } i2cstate_t; - #include "i2c_lld.h" /** * @brief I2C notification callback type. * @details This callback invoked when byte transfer finish event occurs, - * No matter sending or reading. + * no matter if sending or reading. * * @param[in] i2cp pointer to the @p I2CDriver object triggering the * callback @@ -107,7 +104,6 @@ typedef enum { */ typedef void (*i2ccallback_t)(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg); - /** * @brief I2C error notification callback type. * @@ -119,13 +115,11 @@ typedef void (*i2ccallback_t)(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg); typedef void (*i2cerrorcallback_t)(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg); - /** - * @brief I2C transmission data block size. + * @brief I2C transmission data block size. */ typedef uint8_t i2cblock_t; - /** * @brief Structure representing an I2C slave configuration. * @details Each slave device has its own config structure with input and @@ -138,7 +132,6 @@ struct I2CSlaveConfig{ * If set to @p NULL then the callback is disabled. */ i2ccallback_t id_callback; - /** * @brief Callback pointer. * @note This callback will be invoked when error condition occur. @@ -150,7 +143,6 @@ struct I2CSlaveConfig{ #endif }; - /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ @@ -209,17 +201,18 @@ struct I2CSlaveConfig{ * implementation only. * * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object * * @notapi */ -#define _i2c_isr_code(i2cp, i2cscfg) { \ - if(((i2cp)->id_slave_config)->id_callback) { \ - ((i2cp)->id_slave_config)->id_callback(i2cp, i2cscfg); \ - (i2cp)->id_state = I2C_READY; \ - } \ - else \ - (i2cp)->id_state = I2C_READY; \ - _i2c_wakeup_isr(i2cp); \ +#define _i2c_isr_code(i2cp, i2cscfg) { \ + if(((i2cp)->id_slave_config)->id_callback) { \ + ((i2cp)->id_slave_config)->id_callback(i2cp, i2cscfg); \ + (i2cp)->id_state = I2C_READY; \ + } \ + else \ + (i2cp)->id_state = I2C_READY; \ + _i2c_wakeup_isr(i2cp); \ } /** @@ -233,22 +226,24 @@ struct I2CSlaveConfig{ * implementation only. * * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object * * @notapi */ -#define _i2c_isr_err_code(i2cp, i2cscfg) { \ - if(((i2cp)->id_slave_config)->id_err_callback) { \ - ((i2cp)->id_slave_config)->id_err_callback(i2cp, i2cscfg); \ - (i2cp)->id_state = I2C_READY; \ - } \ - else \ - (i2cp)->id_state = I2C_READY; \ - _i2c_wakeup_isr(i2cp); \ +#define _i2c_isr_err_code(i2cp, i2cscfg) { \ + if(((i2cp)->id_slave_config)->id_err_callback) { \ + ((i2cp)->id_slave_config)->id_err_callback(i2cp, i2cscfg); \ + (i2cp)->id_state = I2C_READY; \ + } \ + else \ + (i2cp)->id_state = I2C_READY; \ + _i2c_wakeup_isr(i2cp); \ } /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ + #ifdef __cplusplus extern "C" { #endif @@ -257,11 +252,11 @@ extern "C" { void i2cStart(I2CDriver *i2cp, const I2CConfig *config); void i2cStop(I2CDriver *i2cp); void i2cMasterTransmit(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, - uint16_t slave_addr, - uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes); + uint16_t slave_addr, + uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes); void i2cMasterReceive(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, - uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes); + uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes); void i2cMasterStart(I2CDriver *i2cp); void i2cMasterStop(I2CDriver *i2cp); void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask); -- cgit v1.2.3 From 0af85bab42eda2d80ce6efd2a0c1f5a94bad5f34 Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 25 Sep 2011 10:32:39 +0000 Subject: RTC. Test updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3408 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/src/rtc.c | 2 +- testhal/STM32F1xx/RTC/main.c | 36 +++++++++++++++++++++++------------- 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index 0c8959ea6..17c83f4b3 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -76,7 +76,7 @@ void rtcInit(void){ */ void rtcSetCallback(RTCDriver *rtcp, rtccb_t overflowcb, rtccb_t secondcb, rtccb_t alarmcb){ - chDbgCheck((rtcp != NULL), "rtcStart"); + chDbgCheck((rtcp != NULL), "rtcSetCallback"); rtc_lld_set_callback(rtcp, overflowcb, secondcb, alarmcb); } #endif /* RTC_SUPPORTS_CALLBACKS */ diff --git a/testhal/STM32F1xx/RTC/main.c b/testhal/STM32F1xx/RTC/main.c index d68919ecf..070ac50f2 100644 --- a/testhal/STM32F1xx/RTC/main.c +++ b/testhal/STM32F1xx/RTC/main.c @@ -21,30 +21,36 @@ #include "ch.h" #include "hal.h" -//#define TEST_DEEPSLEEP_ENABLE -#ifdef TEST_DEEPSLEEP_ENABLE +RTCDateTime timespec; +RTCDateTime alarmspec; +#define TEST_ALARM_WAKEUP FALSE + + + +#if TEST_ALARM_WAKEUP + +/* sleep indicator thread */ static WORKING_AREA(blinkWA, 128); static msg_t blink_thd(void *arg){ (void)arg; while (TRUE) { - chThdSleepMilliseconds(500); + chThdSleepMilliseconds(100); palTogglePad(IOPORT3, GPIOC_LED); } return 0; } - - - int main(void) { halInit(); chSysInit(); chThdCreateStatic(blinkWA, sizeof(blinkWA), NORMALPRIO, blink_thd, NULL); /* set alarm in near future */ - rtcSetAlarm(rtcGetSec() + 60); + rtcGetTime(×pec); + alarmspec.tv_sec = timespec.tv_sec + 60; + rtcSetAlarm(&alarmspec); while (TRUE){ chThdSleepSeconds(10); @@ -60,12 +66,11 @@ int main(void) { -#else /* TEST_DEEPSLEEP_ENABLE */ +#else /* TEST_ALARM_WAKEUP */ static void my_overflowcb(RTCDriver *rtcp){ (void)rtcp; palTogglePad(IOPORT3, GPIOC_LED); - rtcSetAlarm(rtcGetSec() + 10); } static void my_secondcb(RTCDriver *rtcp){ @@ -76,7 +81,9 @@ static void my_secondcb(RTCDriver *rtcp){ static void my_alarmcb(RTCDriver *rtcp){ (void)rtcp; palTogglePad(IOPORT3, GPIOC_LED); - rtcSetAlarm(rtcGetSec() + 10); + rtcGetTime(×pec); + alarmspec.tv_sec = timespec.tv_sec + 10; + rtcSetAlarm(&alarmspec); } @@ -84,11 +91,14 @@ int main(void) { halInit(); chSysInit(); - rtcSetAlarm(rtcGetSec() + 10); - rtcSetCallback(&RTCD, NULL, my_secondcb, my_alarmcb); + rtcGetTime(×pec); + alarmspec.tv_sec = timespec.tv_sec + 10; + rtcSetAlarm(&alarmspec); + + rtcSetCallback(&RTCD, my_overflowcb, my_secondcb, my_alarmcb); while (TRUE){ chThdSleepMilliseconds(500); } return 0; } -#endif /* TEST_DEEPSLEEP_ENABLE */ +#endif /* TEST_ALARM_WAKEUP */ -- cgit v1.2.3 From aba41323fcc5ac96be23e8e498527397c66b5a71 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Sep 2011 10:56:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3409 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/RTCv1/rtc_lld.c | 2 +- os/hal/platforms/STM32/RTCv1/rtc_lld.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c index a3329544e..df90bcc11 100644 --- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c @@ -19,7 +19,7 @@ */ /** - * @file STM32/rtc_lld.c + * @file STM32/RTCv1/rtc_lld.c * @brief STM32 RTC subsystem low level driver header. * * @addtogroup RTC diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/os/hal/platforms/STM32/RTCv1/rtc_lld.h index 37f8e105e..f8256ae31 100644 --- a/os/hal/platforms/STM32/RTCv1/rtc_lld.h +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.h @@ -19,7 +19,7 @@ */ /** - * @file STM32/rtc_lld.h + * @file STM32/RTCv1/rtc_lld.h * @brief STM32 RTC subsystem low level driver header. * * @addtogroup RTC -- cgit v1.2.3 From bede8d6781661d679475d2b60d87fb7f43cc5e8e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Sep 2011 15:18:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3410 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/.cproject | 24 +-- os/hal/platforms/AVR/pal_lld.c | 134 ++++++++++++++++ os/hal/platforms/AVR/pal_lld.h | 265 ++++++++++++++++++++++++++++++++ os/hal/platforms/AVR/platform.dox | 14 ++ os/hal/platforms/AVR/platform.mk | 1 + os/hal/platforms/LPC11xx/pal_lld.h | 20 --- os/hal/platforms/LPC13xx/pal_lld.h | 20 --- os/hal/platforms/Posix/pal_lld.h | 8 - os/hal/platforms/STM32/GPIOv1/pal_lld.c | 2 - os/hal/platforms/STM32/GPIOv1/pal_lld.h | 12 -- os/hal/platforms/STM32/GPIOv2/pal_lld.c | 2 - os/hal/platforms/STM32/GPIOv2/pal_lld.h | 12 -- os/hal/platforms/STM8L/pal_lld.c | 2 - os/hal/platforms/STM8L/pal_lld.h | 8 - os/hal/platforms/STM8S/pal_lld.c | 2 - os/hal/platforms/STM8S/pal_lld.h | 8 - os/hal/platforms/Win32/pal_lld.h | 8 - os/hal/templates/pal_lld.h | 28 ---- readme.txt | 2 + 19 files changed, 431 insertions(+), 141 deletions(-) create mode 100644 os/hal/platforms/AVR/pal_lld.c create mode 100644 os/hal/platforms/AVR/pal_lld.h diff --git a/demos/AVR-ATmega128-GCC/.cproject b/demos/AVR-ATmega128-GCC/.cproject index 56d3ad8a5..68ce07ecb 100644 --- a/demos/AVR-ATmega128-GCC/.cproject +++ b/demos/AVR-ATmega128-GCC/.cproject @@ -27,10 +27,12 @@ @@ -38,10 +40,12 @@ @@ -49,10 +53,12 @@ diff --git a/os/hal/platforms/AVR/pal_lld.c b/os/hal/platforms/AVR/pal_lld.c new file mode 100644 index 000000000..4bfd7bd04 --- /dev/null +++ b/os/hal/platforms/AVR/pal_lld.c @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file AVR/pal_lld.c + * @brief AVR GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief AVR GPIO ports configuration. + * @details GPIO registers initialization. + * + * @param[in] config the AVR ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + +#if defined(PORTA) || defined(__DOXYGEN__) + PORTA = config->porta.out; + DDRA = config->porta.dir; +#endif + +#if defined(PORTB) || defined(__DOXYGEN__) + PORTB = config->portb.out; + DDRB = config->portb.dir; +#endif + +#if defined(PORTC) || defined(__DOXYGEN__) + PORTC = config->portc.out; + DDRC = config->portc.dir; +#endif + +#if defined(PORTD) || defined(__DOXYGEN__) + PORTD = config->portd.out; + DDRD = config->portd.dir; +#endif + +#if defined(PORTE) || defined(__DOXYGEN__) + PORTE = config->porte.out; + DDRE = config->porte.dir; +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @note This function is not meant to be invoked directly by the application + * code. + * @note @p PAL_MODE_UNCONNECTED is implemented as output as recommended by + * the AVR Family User's Guide. Unconnected pads are set to input + * with pull-up by default. + * + * @notapi + * + * TODO: check PAL_MODE_UNCONNECTED mode recommended for AVR + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->dir &= ~mask; + break; + case PAL_MODE_INPUT_ANALOG: + port->dir &= ~mask; + port->out &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + case PAL_MODE_INPUT_PULLUP: + port->dir &= ~mask; + port->out |= mask; + case PAL_MODE_OUTPUT_PUSHPULL: + port->dir |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/AVR/pal_lld.h b/os/hal/platforms/AVR/pal_lld.h new file mode 100644 index 000000000..a2d1f8714 --- /dev/null +++ b/os/hal/platforms/AVR/pal_lld.h @@ -0,0 +1,265 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file AVR/pal_lld.h + * @brief AVR GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief AVR setup registers. + */ +typedef struct { + uint8_t out; + uint8_t dir; +} avr_gpio_setup_t; + +typedef struct { + volatile uint8_t in; + volatile uint8_t dir; + volatile uint8_t out; +} avr_gpio_registers_t; + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if defined(PORTA) || defined(__DOXYGEN__) + avr_gpio_setup_t porta; +#endif +#if defined(PORTB) || defined(__DOXYGEN__) + avr_gpio_setup_t portb; +#endif +#if defined(PORTC) || defined(__DOXYGEN__) + avr_gpio_setup_t portc; +#endif +#if defined(PORTD) || defined(__DOXYGEN__) + avr_gpio_setup_t portd; +#endif +#if defined(PORTE) || defined(__DOXYGEN__) + avr_gpio_setup_t porte; +#endif +} PALConfig; + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint8_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef avr_gpio_registers_t *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +#if defined(PORTA) || defined(__DOXYGEN__) +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 ((volatile avr_gpio_registers_t *)&PINA) +#endif + +#if defined(PORTB) || defined(__DOXYGEN__) +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 ((volatile avr_gpio_registers_t *)&PINB) +#endif + +#if defined(PORTC) || defined(__DOXYGEN__) +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 ((volatile avr_gpio_registers_t *)&PINC) +#endif + +#if defined(PORTD) || defined(__DOXYGEN__) +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 ((volatile avr_gpio_registers_t *)&PIND) +#endif + +#if defined(PORTE) || defined(__DOXYGEN__) +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 ((volatile avr_gpio_registers_t *)&PINE) +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config the architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port the port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->in) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port the port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->out) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port the port identifier + * @param[in] bits the bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->out = bits) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, mode) _pal_lld_setgroupmode(port, mask, mode) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * + * @param[in] port the port identifier + * @param[in] pad the pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ +__asm__ __volatile__ \ +( \ + "sbi %0,%1\n\t" \ + : \ + : "I" (_SFR_IO_ADDR(port->out)), \ + "I" (pad) \ + \ +) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * + * @param[in] port the port identifier + * @param[in] pad the pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ +__asm__ __volatile__ \ +( \ + "cbi %0,%1\n\t" \ + : \ + : "I" (_SFR_IO_ADDR(port->out)), \ + "I" (pad) \ + \ +) + +extern ROMCONST PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AVR/platform.dox b/os/hal/platforms/AVR/platform.dox index bc29954b6..2ac2256b9 100644 --- a/os/hal/platforms/AVR/platform.dox +++ b/os/hal/platforms/AVR/platform.dox @@ -35,6 +35,20 @@ * @ingroup AVR_DRIVERS */ +/** + * @defgroup AVR_PAL AVR PAL Support + * @details The AVR PAL driver uses the GPIO peripherals. + * + * @section avr_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * . + * @ingroup AVR_DRIVERS + */ + /** * @defgroup AVR_SERIAL AVR Serial Support * @details The AVR Serial driver uses the USART peripherals in a diff --git a/os/hal/platforms/AVR/platform.mk b/os/hal/platforms/AVR/platform.mk index fdc5390bb..e31413c79 100644 --- a/os/hal/platforms/AVR/platform.mk +++ b/os/hal/platforms/AVR/platform.mk @@ -1,5 +1,6 @@ # List of all the AVR platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AVR/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AVR/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/AVR/serial_lld.c # Required include directories diff --git a/os/hal/platforms/LPC11xx/pal_lld.h b/os/hal/platforms/LPC11xx/pal_lld.h index b46362aeb..2e99f0697 100644 --- a/os/hal/platforms/LPC11xx/pal_lld.h +++ b/os/hal/platforms/LPC11xx/pal_lld.h @@ -147,8 +147,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The port bits. @@ -161,8 +159,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; * @brief Reads the output latch. * @details The purpose of this function is to read back the latched output * value. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The latched logical states. @@ -173,8 +169,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @param[in] bits bits to be written on the specified port @@ -185,8 +179,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Sets a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -200,8 +192,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Clears a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -215,8 +205,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Reads a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -233,8 +221,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Writes a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -254,8 +240,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note Programming an unknown or unsupported mode is silently ignored. * * @param[in] port port identifier @@ -287,8 +271,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Sets a pad logical state to @p PAL_HIGH. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -303,8 +285,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Clears a pad logical state to @p PAL_LOW. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. diff --git a/os/hal/platforms/LPC13xx/pal_lld.h b/os/hal/platforms/LPC13xx/pal_lld.h index 6e291dfc9..0673c11f1 100644 --- a/os/hal/platforms/LPC13xx/pal_lld.h +++ b/os/hal/platforms/LPC13xx/pal_lld.h @@ -147,8 +147,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The port bits. @@ -161,8 +159,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; * @brief Reads the output latch. * @details The purpose of this function is to read back the latched output * value. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The latched logical states. @@ -173,8 +169,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @param[in] bits bits to be written on the specified port @@ -185,8 +179,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Sets a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -200,8 +192,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Clears a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -215,8 +205,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Reads a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -233,8 +221,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Writes a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -254,8 +240,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note Programming an unknown or unsupported mode is silently ignored. * * @param[in] port port identifier @@ -287,8 +271,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Sets a pad logical state to @p PAL_HIGH. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -303,8 +285,6 @@ typedef LPC_GPIO_TypeDef *ioportid_t; /** * @brief Clears a pad logical state to @p PAL_LOW. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. diff --git a/os/hal/platforms/Posix/pal_lld.h b/os/hal/platforms/Posix/pal_lld.h index d76eacf25..f8e2a8702 100644 --- a/os/hal/platforms/Posix/pal_lld.h +++ b/os/hal/platforms/Posix/pal_lld.h @@ -140,8 +140,6 @@ typedef sim_vio_port_t *ioportid_t; /** * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The port bits. @@ -152,8 +150,6 @@ typedef sim_vio_port_t *ioportid_t; * @brief Reads the output latch. * @details The purpose of this function is to read back the latched output * value. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The latched logical states. @@ -162,8 +158,6 @@ typedef sim_vio_port_t *ioportid_t; /** * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @param[in] bits bits to be written on the specified port @@ -174,8 +168,6 @@ typedef sim_vio_port_t *ioportid_t; * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note Programming an unknown or unsupported mode is silently ignored. * * @param[in] port port identifier diff --git a/os/hal/platforms/STM32/GPIOv1/pal_lld.c b/os/hal/platforms/STM32/GPIOv1/pal_lld.c index 274d8b6c0..6b4b806b9 100644 --- a/os/hal/platforms/STM32/GPIOv1/pal_lld.c +++ b/os/hal/platforms/STM32/GPIOv1/pal_lld.c @@ -117,8 +117,6 @@ void _pal_lld_init(const PALConfig *config) { * @brief Pads mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched diff --git a/os/hal/platforms/STM32/GPIOv1/pal_lld.h b/os/hal/platforms/STM32/GPIOv1/pal_lld.h index 65e660944..c9bb99de7 100644 --- a/os/hal/platforms/STM32/GPIOv1/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv1/pal_lld.h @@ -219,8 +219,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Writes on a I/O port. * @details This function is implemented by writing the GPIO ODR register, the * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -236,8 +234,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Sets a bits mask on a I/O port. * @details This function is implemented by writing the GPIO BSRR register, the * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -253,8 +249,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Clears a bits mask on a I/O port. * @details This function is implemented by writing the GPIO BRR register, the * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -270,8 +264,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Writes a group of bits. * @details This function is implemented by writing the GPIO BSRR register, the * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -292,8 +284,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -309,8 +299,6 @@ typedef GPIO_TypeDef * ioportid_t; /** * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/os/hal/platforms/STM32/GPIOv2/pal_lld.c index 8f84f225e..bde24db25 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.c +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.c @@ -125,8 +125,6 @@ void _pal_lld_init(const PALConfig *config) { * @brief Pads mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum * speed. * diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h index 6c799c14c..7f8c2e17a 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -347,8 +347,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Writes on a I/O port. * @details This function is implemented by writing the GPIO ODR register, the * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -364,8 +362,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Sets a bits mask on a I/O port. * @details This function is implemented by writing the GPIO BSRR register, the * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -381,8 +377,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Clears a bits mask on a I/O port. * @details This function is implemented by writing the GPIO BSRR register, the * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -398,8 +392,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Writes a group of bits. * @details This function is implemented by writing the GPIO BSRR register, the * implementation has no side effects. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -420,8 +412,6 @@ typedef GPIO_TypeDef * ioportid_t; * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. @@ -437,8 +427,6 @@ typedef GPIO_TypeDef * ioportid_t; /** * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. * @note Writing on pads programmed as pull-up or pull-down has the side * effect to modify the resistor setting because the output latched * data is used for the resistor selection. diff --git a/os/hal/platforms/STM8L/pal_lld.c b/os/hal/platforms/STM8L/pal_lld.c index 40dcdf8d2..aba1565cb 100644 --- a/os/hal/platforms/STM8L/pal_lld.c +++ b/os/hal/platforms/STM8L/pal_lld.c @@ -55,8 +55,6 @@ * @brief Pads mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. * * @param[in] port the port identifier diff --git a/os/hal/platforms/STM8L/pal_lld.h b/os/hal/platforms/STM8L/pal_lld.h index 30fef0e82..22d048c74 100644 --- a/os/hal/platforms/STM8L/pal_lld.h +++ b/os/hal/platforms/STM8L/pal_lld.h @@ -184,8 +184,6 @@ typedef GPIO_TypeDef *ioportid_t; /** * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The port bits. @@ -198,8 +196,6 @@ typedef GPIO_TypeDef *ioportid_t; * @brief Reads the output latch. * @details The purpose of this function is to read back the latched output * value. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The latched logical states. @@ -210,8 +206,6 @@ typedef GPIO_TypeDef *ioportid_t; /** * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @param[in] bits bits to be written on the specified port @@ -224,8 +218,6 @@ typedef GPIO_TypeDef *ioportid_t; * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note Programming an unknown or unsupported mode is silently ignored. * * @param[in] port port identifier diff --git a/os/hal/platforms/STM8S/pal_lld.c b/os/hal/platforms/STM8S/pal_lld.c index cebf349aa..e1e6d919e 100644 --- a/os/hal/platforms/STM8S/pal_lld.c +++ b/os/hal/platforms/STM8S/pal_lld.c @@ -55,8 +55,6 @@ * @brief Pads mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. * * @param[in] port the port identifier diff --git a/os/hal/platforms/STM8S/pal_lld.h b/os/hal/platforms/STM8S/pal_lld.h index 954a11361..d38406b2f 100644 --- a/os/hal/platforms/STM8S/pal_lld.h +++ b/os/hal/platforms/STM8S/pal_lld.h @@ -169,8 +169,6 @@ typedef GPIO_TypeDef *ioportid_t; /** * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The port bits. @@ -183,8 +181,6 @@ typedef GPIO_TypeDef *ioportid_t; * @brief Reads the output latch. * @details The purpose of this function is to read back the latched output * value. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The latched logical states. @@ -195,8 +191,6 @@ typedef GPIO_TypeDef *ioportid_t; /** * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @param[in] bits bits to be written on the specified port @@ -209,8 +203,6 @@ typedef GPIO_TypeDef *ioportid_t; * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note Programming an unknown or unsupported mode is silently ignored. * * @param[in] port port identifier diff --git a/os/hal/platforms/Win32/pal_lld.h b/os/hal/platforms/Win32/pal_lld.h index ad70eeebc..e0f03e135 100644 --- a/os/hal/platforms/Win32/pal_lld.h +++ b/os/hal/platforms/Win32/pal_lld.h @@ -140,8 +140,6 @@ typedef sim_vio_port_t *ioportid_t; /** * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The port bits. @@ -152,8 +150,6 @@ typedef sim_vio_port_t *ioportid_t; * @brief Reads the output latch. * @details The purpose of this function is to read back the latched output * value. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The latched logical states. @@ -162,8 +158,6 @@ typedef sim_vio_port_t *ioportid_t; /** * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @param[in] bits bits to be written on the specified port @@ -174,8 +168,6 @@ typedef sim_vio_port_t *ioportid_t; * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note Programming an unknown or unsupported mode is silently ignored. * * @param[in] port port identifier diff --git a/os/hal/templates/pal_lld.h b/os/hal/templates/pal_lld.h index 46f5a3d39..60bac5e5c 100644 --- a/os/hal/templates/pal_lld.h +++ b/os/hal/templates/pal_lld.h @@ -108,8 +108,6 @@ typedef uint32_t ioportid_t; /** * @brief Reads the physical I/O port states. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The port bits. @@ -122,8 +120,6 @@ typedef uint32_t ioportid_t; * @brief Reads the output latch. * @details The purpose of this function is to read back the latched output * value. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @return The latched logical states. @@ -134,8 +130,6 @@ typedef uint32_t ioportid_t; /** * @brief Writes a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * * @param[in] port port identifier * @param[in] bits bits to be written on the specified port @@ -146,8 +140,6 @@ typedef uint32_t ioportid_t; /** * @brief Sets a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -161,8 +153,6 @@ typedef uint32_t ioportid_t; /** * @brief Clears a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -176,8 +166,6 @@ typedef uint32_t ioportid_t; /** * @brief Toggles a bits mask on a I/O port. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -191,8 +179,6 @@ typedef uint32_t ioportid_t; /** * @brief Reads a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -208,8 +194,6 @@ typedef uint32_t ioportid_t; /** * @brief Writes a group of bits. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -228,8 +212,6 @@ typedef uint32_t ioportid_t; * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port * with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note Programming an unknown or unsupported mode is silently ignored. * * @param[in] port port identifier @@ -242,8 +224,6 @@ typedef uint32_t ioportid_t; /** * @brief Reads a logical state from an I/O pad. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -277,8 +257,6 @@ typedef uint32_t ioportid_t; /** * @brief Sets a pad logical state to @p PAL_HIGH. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -292,8 +270,6 @@ typedef uint32_t ioportid_t; /** * @brief Clears a pad logical state to @p PAL_LOW. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -307,8 +283,6 @@ typedef uint32_t ioportid_t; /** * @brief Toggles a pad logical state. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. @@ -323,8 +297,6 @@ typedef uint32_t ioportid_t; /** * @brief Pad mode setup. * @details This function programs a pad with the specified mode. - * @note This function is not meant to be invoked directly by the - * application code. * @note The @ref PAL provides a default software implementation of this * functionality, implement this function if can optimize it by using * special hardware functionalities or special coding. diff --git a/readme.txt b/readme.txt index e0d604ae7..83f326e66 100644 --- a/readme.txt +++ b/readme.txt @@ -97,6 +97,8 @@ (backported to 2.2.4). - FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420) (backported to 2.2.4). +- NEW: Added AVR implementation of the PAL driver contributed by Leszek. + (TODO: Update demos to use it) - NEW: Added Eclipse project files to all makefile-based demos in order to allow an easier import. The Eclipse workspace is assumed to be created inside the ChibiOS/RT main directory. -- cgit v1.2.3 From 8ce9365e009b1f1555bcd4901118ebf8de2eaa3d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Sep 2011 15:31:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3411 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/.cproject | 211 ------------------ demos/ARM7-AT91SAM7S-FATFS-GCC/.project | 95 --------- demos/ARM7-AT91SAM7S-GCC/.cproject | 211 ------------------ demos/ARM7-AT91SAM7S-GCC/.project | 90 -------- demos/ARM7-AT91SAM7X-FATFS-GCC/.cproject | 211 ------------------ demos/ARM7-AT91SAM7X-FATFS-GCC/.project | 95 --------- demos/ARM7-AT91SAM7X-GCC/.cproject | 274 ------------------------ demos/ARM7-AT91SAM7X-GCC/.project | 94 -------- demos/ARM7-AT91SAM7X-LWIP-GCC/.cproject | 230 -------------------- demos/ARM7-AT91SAM7X-LWIP-GCC/.project | 94 -------- demos/ARM7-AT91SAM7X-UIP-GCC/.cproject | 210 ------------------ demos/ARM7-AT91SAM7X-UIP-GCC/.project | 94 -------- demos/ARM7-LPC214x-FATFS-GCC/.cproject | 230 -------------------- demos/ARM7-LPC214x-FATFS-GCC/.project | 94 -------- demos/ARM7-LPC214x-G++/.cproject | 330 ----------------------------- demos/ARM7-LPC214x-G++/.project | 91 -------- demos/ARM7-LPC214x-GCC/.cproject | 252 ---------------------- demos/ARM7-LPC214x-GCC/.project | 90 -------- demos/ARMCM0-LPC1114-LPCXPRESSO/.cproject | 211 ------------------ demos/ARMCM0-LPC1114-LPCXPRESSO/.project | 90 -------- demos/ARMCM3-GENERIC-KERNEL/.cproject | 211 ------------------ demos/ARMCM3-GENERIC-KERNEL/.project | 90 -------- demos/ARMCM3-LPC1343-LPCXPRESSO/.cproject | 211 ------------------ demos/ARMCM3-LPC1343-LPCXPRESSO/.project | 90 -------- demos/ARMCM3-STM32F100-DISCOVERY/.cproject | 211 ------------------ demos/ARMCM3-STM32F100-DISCOVERY/.project | 90 -------- demos/ARMCM3-STM32F103-FATFS/.cproject | 211 ------------------ demos/ARMCM3-STM32F103-FATFS/.project | 95 --------- demos/ARMCM3-STM32F103-G++/.cproject | 211 ------------------ demos/ARMCM3-STM32F103-G++/.project | 90 -------- demos/ARMCM3-STM32F103/.cproject | 222 ------------------- demos/ARMCM3-STM32F103/.project | 90 -------- demos/ARMCM3-STM32F103ZG-FATFS/.cproject | 211 ------------------ demos/ARMCM3-STM32F103ZG-FATFS/.project | 95 --------- demos/ARMCM3-STM32F107/.cproject | 211 ------------------ demos/ARMCM3-STM32F107/.project | 90 -------- demos/ARMCM3-STM32L152-DISCOVERY/.cproject | 225 -------------------- demos/ARMCM3-STM32L152-DISCOVERY/.project | 95 --------- demos/AVR-AT90CANx-GCC/.cproject | 237 --------------------- demos/AVR-AT90CANx-GCC/.project | 90 -------- demos/AVR-ATmega128-GCC/.cproject | 243 --------------------- demos/AVR-ATmega128-GCC/.project | 90 -------- demos/MSP430-MSP430x1611-GCC/.cproject | 239 --------------------- demos/MSP430-MSP430x1611-GCC/.project | 90 -------- demos/PPC-SPC563-GCC/.cproject | 221 ------------------- demos/PPC-SPC563-GCC/.project | 89 -------- demos/Posix-GCC/.cproject | 211 ------------------ demos/Posix-GCC/.project | 90 -------- demos/Win32-MinGW/.cproject | 224 -------------------- demos/Win32-MinGW/.project | 94 -------- readme.txt | 3 - testhal/LPC11xx/IRQ_STORM/.cproject | 256 ---------------------- testhal/LPC11xx/IRQ_STORM/.project | 85 -------- testhal/LPC13xx/IRQ_STORM/.cproject | 320 ---------------------------- testhal/LPC13xx/IRQ_STORM/.project | 84 -------- testhal/STM32F1xx/ADC/.cproject | 210 ------------------ testhal/STM32F1xx/ADC/.project | 85 -------- testhal/STM32F1xx/CAN/.cproject | 210 ------------------ testhal/STM32F1xx/CAN/.project | 85 -------- testhal/STM32F1xx/EXT/.cproject | 211 ------------------ testhal/STM32F1xx/EXT/.project | 85 -------- testhal/STM32F1xx/GPT/.cproject | 210 ------------------ testhal/STM32F1xx/GPT/.project | 85 -------- testhal/STM32F1xx/IRQ_STORM/.cproject | 210 ------------------ testhal/STM32F1xx/IRQ_STORM/.project | 85 -------- testhal/STM32F1xx/MAC/.cproject | 210 ------------------ testhal/STM32F1xx/MAC/.project | 85 -------- testhal/STM32F1xx/PWM-ICU/.cproject | 210 ------------------ testhal/STM32F1xx/PWM-ICU/.project | 85 -------- testhal/STM32F1xx/SDC/.cproject | 210 ------------------ testhal/STM32F1xx/SDC/.project | 85 -------- testhal/STM32F1xx/SPI/.cproject | 210 ------------------ testhal/STM32F1xx/SPI/.project | 85 -------- testhal/STM32F1xx/UART/.cproject | 210 ------------------ testhal/STM32F1xx/UART/.project | 85 -------- testhal/STM32F1xx/USB_CDC/.cproject | 210 ------------------ testhal/STM32F1xx/USB_CDC/.project | 85 -------- testhal/STM32L1xx/ADC/.cproject | 210 ------------------ testhal/STM32L1xx/ADC/.project | 85 -------- testhal/STM32L1xx/EXT/.cproject | 211 ------------------ testhal/STM32L1xx/EXT/.project | 85 -------- testhal/STM32L1xx/GPT/.cproject | 210 ------------------ testhal/STM32L1xx/GPT/.project | 85 -------- testhal/STM32L1xx/IRQ_STORM/.cproject | 210 ------------------ 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01a5feeee..000000000 --- a/demos/ARMCM3-LPC1343-LPCXPRESSO/.cproject +++ /dev/null @@ -1,211 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/.project b/demos/ARMCM3-LPC1343-LPCXPRESSO/.project deleted file mode 100644 index bc190d1e1..000000000 --- a/demos/ARMCM3-LPC1343-LPCXPRESSO/.project +++ /dev/null @@ -1,90 +0,0 @@ - - - ARMCM3-LPC1343-LPCXPRESSO - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - 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b/demos/ARMCM3-STM32F100-DISCOVERY/.cproject deleted file mode 100644 index 1c26c0631..000000000 --- a/demos/ARMCM3-STM32F100-DISCOVERY/.cproject +++ /dev/null @@ -1,211 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/.project b/demos/ARMCM3-STM32F100-DISCOVERY/.project deleted file mode 100644 index 48e6d0ee3..000000000 --- a/demos/ARMCM3-STM32F100-DISCOVERY/.project +++ /dev/null @@ -1,90 +0,0 @@ - - - ARMCM3-STM32F100-DISCOVERY - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - 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- - org.eclipse.cdt.make.core.useDefaultBuildCmd - false - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.core.cnature - - - - os - 2 - WORKSPACE_LOC/os - - - test - 2 - WORKSPACE_LOC/test - - - diff --git a/demos/Posix-GCC/.cproject b/demos/Posix-GCC/.cproject deleted file mode 100644 index aa34b8c17..000000000 --- a/demos/Posix-GCC/.cproject +++ /dev/null @@ -1,211 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/demos/Posix-GCC/.project b/demos/Posix-GCC/.project deleted file mode 100644 index ec2a443c0..000000000 --- a/demos/Posix-GCC/.project +++ /dev/null @@ -1,90 +0,0 @@ - - - Posix-GCC - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - mingw32-make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - false - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - WORKSPACE_LOC/os - - - test - 2 - WORKSPACE_LOC/test - - - diff --git a/demos/Win32-MinGW/.cproject b/demos/Win32-MinGW/.cproject deleted file mode 100644 index 5342c0657..000000000 --- a/demos/Win32-MinGW/.cproject +++ /dev/null @@ -1,224 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/demos/Win32-MinGW/.project b/demos/Win32-MinGW/.project deleted file mode 100644 index fda7a8f5b..000000000 --- a/demos/Win32-MinGW/.project +++ /dev/null @@ -1,94 +0,0 @@ - - - Win32-MinGW - - - _Common Files - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?children? - ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - mingw32-make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - false - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.core.cnature - - - - os - 2 - WORKSPACE_LOC/os - - - test - 2 - WORKSPACE_LOC/test - - - diff --git a/readme.txt b/readme.txt index 83f326e66..e0b7bed9a 100644 --- a/readme.txt +++ b/readme.txt @@ -99,9 +99,6 @@ (backported to 2.2.4). - NEW: Added AVR implementation of the PAL driver contributed by Leszek. (TODO: Update demos to use it) -- NEW: Added Eclipse project files to all makefile-based demos in order to - allow an easier import. The Eclipse workspace is assumed to be created - inside the ChibiOS/RT main directory. - NEW: STM32L ADC driver implementation. - NEW: Improved ADC driver model, now it is possible to handle error conditions during the conversion process. diff --git a/testhal/LPC11xx/IRQ_STORM/.cproject b/testhal/LPC11xx/IRQ_STORM/.cproject deleted file mode 100644 index 5f093f95a..000000000 --- a/testhal/LPC11xx/IRQ_STORM/.cproject +++ /dev/null @@ -1,256 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1114/301" property_count="5" version="1"/> -<infoList vendor="NXP"> -<info chip="LPC1114/301" match_id="0x0444102b" name="LPC1114/301" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC1114/301</name> -<family>LPC11xx</family> -<vendor>NXP</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash32" location="0" size="0x8000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x400" progwithcode="TRUE" size="0x8000"/> -<peripheralInstance derived_from="LPC11_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> -<peripheralInstance derived_from="LPC11_PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="CM0_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> -<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> -<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> -<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> -<peripheralInstance derived_from="LPC11_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> -<peripheralInstance derived_from="LPC11_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> -<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> -<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP0" location="0x40040000"/> -<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> -<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> -<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40014000"/> -<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER1" location="0x40018000"/> -<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> -<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -</chip> -<processor> -<name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig> - - diff --git a/testhal/LPC11xx/IRQ_STORM/.project b/testhal/LPC11xx/IRQ_STORM/.project deleted file mode 100644 index f5e6fe20e..000000000 --- a/testhal/LPC11xx/IRQ_STORM/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - TEST-LPC11xx-IRQ_STORM - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - WORKSPACE_LOC/os - - - diff --git a/testhal/LPC13xx/IRQ_STORM/.cproject b/testhal/LPC13xx/IRQ_STORM/.cproject deleted file mode 100644 index c062ba7f7..000000000 --- a/testhal/LPC13xx/IRQ_STORM/.cproject +++ /dev/null @@ -1,320 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1343" property_count="5" version="1"/> -<infoList vendor="NXP"> -<info chip="LPC1343" match_id="0x3d00002b" name="LPC1343" stub="crt_emu_lpc11_13_nxp"> -<chip> -<name>LPC1343</name> -<family>LPC13xx</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash32" location="0x00000000" size="0x8000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x8000"/> -<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> -<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER0" location="0x40014000"/> -<peripheralInstance derived_from="LPC11_13_TIMER32" determined="infoFile" id="TIMER1" location="0x40018000"/> -<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" id="UART0" location="0x40008000"/> -<peripheralInstance derived_from="LPC11_13_SSP" determined="infoFile" id="SSP" location="0x40040000"/> -<peripheralInstance derived_from="LPC11_13_ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="LPC11_13_I2C" determined="infoFile" id="I2C0" location="0x40000000"/> -<peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> -<peripheralInstance derived_from="LPC13_SYSCTL" determined="infoFile" id="SYSCTL" location="0x40048000"/> -<peripheralInstance derived_from="LPC11_13_PMU" determined="infoFile" id="PMU" location="0x40038000"/> -<peripheralInstance derived_from="LPC11_13_IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO0" location="0x50000000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO1" location="0x50010000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO2" location="0x50020000"/> -<peripheralInstance derived_from="LPC11_13_GPIO" determined="infoFile" id="GPIO3" location="0x50030000"/> -<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR160" location="0x4000c000"/> -<peripheralInstance derived_from="LPC11_13_TIMER16" determined="infoFile" id="TMR161" location="0x40010000"/> -<peripheralInstance derived_from="LPC11_13_USBDEV" determined="infoFile" id="USB" location="0x40020000"/> -<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/> -</chip> -<processor> -<name gcc_name="cortex-m3">Cortex-M3</name> -<family>Cortex-M</family> -</processor> -<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig> - - diff --git a/testhal/LPC13xx/IRQ_STORM/.project b/testhal/LPC13xx/IRQ_STORM/.project deleted file mode 100644 index b4f093c6c..000000000 --- a/testhal/LPC13xx/IRQ_STORM/.project +++ /dev/null @@ -1,84 +0,0 @@ - - - TEST-LPC13xx-IRQ_STORM - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - 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org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - WORKSPACE_LOC/os - - - diff --git a/testhal/STM32F1xx/CAN/.cproject b/testhal/STM32F1xx/CAN/.cproject deleted file mode 100644 index fbcc3a335..000000000 --- a/testhal/STM32F1xx/CAN/.cproject +++ /dev/null @@ -1,210 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/testhal/STM32F1xx/CAN/.project b/testhal/STM32F1xx/CAN/.project deleted file mode 100644 index 0a6433ba8..000000000 --- a/testhal/STM32F1xx/CAN/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - TEST-STM32F1xx-CAN - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - WORKSPACE_LOC/os - - - diff --git a/testhal/STM32F1xx/EXT/.cproject b/testhal/STM32F1xx/EXT/.cproject deleted file mode 100644 index 4b2106c19..000000000 --- a/testhal/STM32F1xx/EXT/.cproject +++ /dev/null @@ -1,211 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/testhal/STM32F1xx/EXT/.project b/testhal/STM32F1xx/EXT/.project deleted file mode 100644 index 4a734975b..000000000 --- a/testhal/STM32F1xx/EXT/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - TEST-STM32F1xx-EXT - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/testhal/STM32F1xx/IRQ_STORM/.project b/testhal/STM32F1xx/IRQ_STORM/.project deleted file mode 100644 index 1d001b292..000000000 --- a/testhal/STM32F1xx/IRQ_STORM/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - TEST-STM32F1xx-IRQ_STORM - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - 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- - - - - - - diff --git a/testhal/STM32F1xx/SPI/.project b/testhal/STM32F1xx/SPI/.project deleted file mode 100644 index 9818c23f7..000000000 --- a/testhal/STM32F1xx/SPI/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - TEST-STM32F1xx-SPI - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - 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- - TEST-STM32F1xx-UART - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - WORKSPACE_LOC/os - - - diff --git a/testhal/STM32F1xx/USB_CDC/.cproject b/testhal/STM32F1xx/USB_CDC/.cproject deleted file mode 100644 index 72767d1c9..000000000 --- a/testhal/STM32F1xx/USB_CDC/.cproject +++ /dev/null @@ -1,210 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/testhal/STM32F1xx/USB_CDC/.project b/testhal/STM32F1xx/USB_CDC/.project deleted file mode 100644 index 643a775d0..000000000 --- a/testhal/STM32F1xx/USB_CDC/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - TEST-STM32F1xx-USB_CDC - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - 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- - diff --git a/testhal/STM32L1xx/ADC/.cproject b/testhal/STM32L1xx/ADC/.cproject deleted file mode 100644 index 46dec9738..000000000 --- a/testhal/STM32L1xx/ADC/.cproject +++ /dev/null @@ -1,210 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/testhal/STM32L1xx/ADC/.project b/testhal/STM32L1xx/ADC/.project deleted file mode 100644 index 93c7da8ef..000000000 --- a/testhal/STM32L1xx/ADC/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - TEST-STM32L1xx-ADC - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - 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false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - WORKSPACE_LOC/os - - - diff --git a/testhal/STM32L1xx/PWM-ICU/.cproject b/testhal/STM32L1xx/PWM-ICU/.cproject deleted file mode 100644 index 075107e60..000000000 --- a/testhal/STM32L1xx/PWM-ICU/.cproject +++ /dev/null @@ -1,210 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - WORKSPACE_LOC/os - - - diff --git a/testhal/STM32L1xx/SPI/.cproject b/testhal/STM32L1xx/SPI/.cproject deleted file mode 100644 index 85ae1ed2f..000000000 --- a/testhal/STM32L1xx/SPI/.cproject +++ /dev/null @@ -1,210 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - WORKSPACE_LOC/os - - - diff --git a/testhal/STM32L1xx/UART/.cproject b/testhal/STM32L1xx/UART/.cproject deleted file mode 100644 index 68e20f694..000000000 --- a/testhal/STM32L1xx/UART/.cproject +++ /dev/null @@ -1,210 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/testhal/STM32L1xx/UART/.project b/testhal/STM32L1xx/UART/.project deleted file mode 100644 index ad5b96f16..000000000 --- a/testhal/STM32L1xx/UART/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - TEST-STM32L1xx-UART - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - WORKSPACE_LOC/os - - - -- cgit v1.2.3 From d2fa0e3fdee679a6cdd5dd6616aca527eca3f080 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 26 Sep 2011 08:23:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3412 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/rtc.h | 29 ++++++++--------------- os/hal/src/rtc.c | 65 ++++++++++++++++++++++++++++++---------------------- 2 files changed, 48 insertions(+), 46 deletions(-) diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h index 02aec2ceb..aa2562c69 100644 --- a/os/hal/include/rtc.h +++ b/os/hal/include/rtc.h @@ -26,12 +26,9 @@ * @{ */ - #ifndef _RTC_H_ #define _RTC_H_ - - #if HAL_USE_RTC || defined(__DOXYGEN__) /*===========================================================================*/ @@ -50,8 +47,14 @@ /* Driver data structures and types. */ /*===========================================================================*/ +/** + * @brief Type of a structure representing an RTC driver. + */ typedef struct RTCDriver RTCDriver; +/** + * @brief Type of an RTC callback. + */ typedef void (*rtccb_t)(RTCDriver *rtcp); #include "rtc_lld.h" @@ -68,26 +71,14 @@ typedef void (*rtccb_t)(RTCDriver *rtcp); extern "C" { #endif void rtcInit(void); - - #if RTC_SUPPORTS_CALLBACKS - void rtcSetCallback(RTCDriver *rtcp, rtccb_t overflowcb, - rtccb_t secondcb, rtccb_t alarmcb); - #endif /* RTC_SUPPORTS_CALLBACKS */ - +#if RTC_SUPPORTS_CALLBACKS + void rtcSetCallback(RTCDriver *rtcp, rtccb_t overflowcb, + rtccb_t secondcb, rtccb_t alarmcb); +#endif /* RTC_SUPPORTS_CALLBACKS */ void rtcSetTime(RTCDateTime *timespec); void rtcGetTime(RTCDateTime *timespec); - - - - void rtcSetAlarm(RTCDateTime *timespec); void rtcGetAlarm(RTCDateTime *timespec); - - - - - - #ifdef __cplusplus } #endif diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index 17c83f4b3..24ccce84e 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -20,7 +20,7 @@ /** * @file rtc.c - * @brief Real Time Clock Abstraction Layer code. + * @brief RTC Driver code. * * @addtogroup RTC * @{ @@ -50,74 +50,85 @@ /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ + /** - * @brief Enable access to registers and initialize RTC if BKP doamin - * was previously reseted. - * + * @brief Enable access to registers and initialize RTC if BKP domain + * was previously reset. * @note This function is implicitly invoked by @p halInit(), there is * no need to explicitly initialize the driver. + * + * @init */ -void rtcInit(void){ +void rtcInit(void) { rtc_lld_init(); } -#if RTC_SUPPORTS_CALLBACKS +#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__) /** - * @brief Enables and disables callbacks on the fly. - * @details Pass callback function(s) in argument(s) to enable callback(s). - * Pass NULL to disable callback. - * @pre To use this function you must set @p RTC_SUPPORTS_CALLBACKS - * to @p TRUE. + * @brief Enables or disables callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * @pre To use this function you must set @p RTC_SUPPORTS_CALLBACKS + * to @p TRUE. * - * @param[in] rtcp - pointer to RTC driver structure. - * @param[in] overflowcb - overflow callback function. - * @param[in] secondcb - every second callback function. - * @param[in] alarmcb - alarm callback function. + * @param[in] rtcp pointer to RTC driver structure + * @param[in] overflowcb overflow callback function + * @param[in] secondcb every second callback function + * @param[in] alarmcb alarm callback function */ void rtcSetCallback(RTCDriver *rtcp, rtccb_t overflowcb, - rtccb_t secondcb, rtccb_t alarmcb){ + rtccb_t secondcb, rtccb_t alarmcb) { + chDbgCheck((rtcp != NULL), "rtcSetCallback"); + rtc_lld_set_callback(rtcp, overflowcb, secondcb, alarmcb); } #endif /* RTC_SUPPORTS_CALLBACKS */ /** - * @brief Set current time. + * @brief Set current time. * - * @param[in] timespec pointer to variable storing time. + * @param[in] timespec pointer to a @p RTCDateTime structure */ -void rtcSetTime(RTCDateTime *timespec){ +void rtcSetTime(RTCDateTime *timespec) { + chDbgCheck((timespec != NULL), "rtcSetTime"); + rtc_lld_set_time(timespec); } /** - * @brief Get current time. + * @brief Get current time. * - * @param[in] timespec pointer to variable storing time. + * @param[in] timespec pointer to a @p RTCDateTime structure */ -void rtcGetTime(RTCDateTime *timespec){ +void rtcGetTime(RTCDateTime *timespec) { + chDbgCheck((timespec != NULL), "rtcGetTime"); rtc_lld_get_time(timespec); } /** - * @brief Set alarm time. + * @brief Set alarm time. * - * @param[in] timespec pointer to variable storing time of alarm. + * @param[in] timespec pointer to a @p RTCDateTime structure */ -void rtcSetAlarm(RTCDateTime *timespec){ +void rtcSetAlarm(RTCDateTime *timespec) { + chDbgCheck((timespec != NULL), "rtcSetAlarm"); + rtc_lld_set_alarm(timespec); } /** - * @brief Get current alarm. + * @brief Get current alarm. * - * @param[in] timespec pointer to variable to store alarm time. + * @param[in] timespec pointer to a @p RTCDateTime structure */ void rtcGetAlarm(RTCDateTime *timespec){ + chDbgCheck((timespec != NULL), "rtcGetAlarm"); + rtc_lld_get_alarm(timespec); } -- cgit v1.2.3 From 2950a0a7b8316a742a7a67b5acb4f224a98397ff Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 1 Oct 2011 08:04:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3413 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/rtc.h | 33 +++- os/hal/platforms/STM32/RTCv1/rtc_lld.c | 333 ++++++++++++++++----------------- os/hal/platforms/STM32/RTCv1/rtc_lld.h | 105 +++++++---- os/hal/platforms/STM32F1xx/stm32_rcc.h | 12 +- os/hal/platforms/STM32L1xx/hal_lld.h | 4 +- os/hal/src/rtc.c | 95 ++++++---- testhal/STM32F1xx/RTC/Makefile | 6 +- testhal/STM32F1xx/RTC/main.c | 44 ++--- 8 files changed, 336 insertions(+), 296 deletions(-) diff --git a/os/hal/include/rtc.h b/os/hal/include/rtc.h index aa2562c69..1264c5bd8 100644 --- a/os/hal/include/rtc.h +++ b/os/hal/include/rtc.h @@ -35,6 +35,18 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @name Date/Time bit masks + * @{ + */ +#define RTC_TIME_SECONDS_MASK 0x0000001F /* @brief Seconds mask. */ +#define RTC_TIME_MINUTES_MASK 0x000007E0 /* @brief Minutes mask. */ +#define RTC_TIME_HOURS_MASK 0x0000F800 /* @brief Hours mask. */ +#define RTC_DATE_DAYS_MASK 0x001F0000 /* @brief Days mask. */ +#define RTC_DATE_MONTHS_MASK 0x01E00000 /* @brief Months mask. */ +#define RTC_DATE_YEARS_MASK 0xFE000000 /* @brief Years mask. */ +/** @} */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -53,9 +65,9 @@ typedef struct RTCDriver RTCDriver; /** - * @brief Type of an RTC callback. + * @brief Type of a structure representing an RTC time stamp. */ -typedef void (*rtccb_t)(RTCDriver *rtcp); +typedef struct RTCTime RTCTime; #include "rtc_lld.h" @@ -71,14 +83,17 @@ typedef void (*rtccb_t)(RTCDriver *rtcp); extern "C" { #endif void rtcInit(void); + void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec); + void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec); +#if RTC_ALARMS > 0 + void rtcSetAlarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec); + void rtcGetAlarm(RTCDriver *rtcp, rtcalarm_t alarm, RTCAlarm *alarmspec); +#endif #if RTC_SUPPORTS_CALLBACKS - void rtcSetCallback(RTCDriver *rtcp, rtccb_t overflowcb, - rtccb_t secondcb, rtccb_t alarmcb); -#endif /* RTC_SUPPORTS_CALLBACKS */ - void rtcSetTime(RTCDateTime *timespec); - void rtcGetTime(RTCDateTime *timespec); - void rtcSetAlarm(RTCDateTime *timespec); - void rtcGetAlarm(RTCDateTime *timespec); + void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback); +#endif #ifdef __cplusplus } #endif diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c index df90bcc11..2876b990d 100644 --- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c @@ -29,16 +29,16 @@ #include "ch.h" #include "hal.h" - #if HAL_USE_RTC || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief RTC driver identifier.*/ -RTCDriver RTCD; - +/** + * @brief RTC driver identifier. + */ +RTCDriver RTCD1; /*===========================================================================*/ /* Driver local variables. */ @@ -55,33 +55,37 @@ RTCDriver RTCD; * * @notapi */ -#if RTC_SUPPORTS_CALLBACKS +static void rtc_lld_serve_interrupt(RTCDriver *rtcp) { -static void rtc_lld_serve_interrupt(RTCDriver *rtcp){ chSysLockFromIsr(); - if ((RTC->CRH & RTC_CRH_SECIE) && \ - (RTC->CRL & RTC_CRL_SECF) && \ - (rtcp->second_cb != NULL)){ - rtcp->second_cb(rtcp); + if ((RTC->CRH & RTC_CRH_SECIE) && (RTC->CRL & RTC_CRL_SECF)) { + rtcp->rtc_cb(rtcp, RTC_EVENT_SECOND); RTC->CRL &= ~RTC_CRL_SECF; } - if ((RTC->CRH & RTC_CRH_ALRIE) && \ - (RTC->CRL & RTC_CRL_ALRF) && \ - (rtcp->alarm_cb != NULL)){ - rtcp->alarm_cb(rtcp); + if ((RTC->CRH & RTC_CRH_ALRIE) && (RTC->CRL & RTC_CRL_ALRF)) { + rtcp->rtc_cb(rtcp, RTC_EVENT_ALARM); RTC->CRL &= ~RTC_CRL_ALRF; } - if ((RTC->CRH & RTC_CRH_OWIE) && \ - (RTC->CRL & RTC_CRL_OWF) && \ - (rtcp->overflow_cb != NULL)){ - rtcp->overflow_cb(rtcp); + if ((RTC->CRH & RTC_CRH_OWIE) && (RTC->CRL & RTC_CRL_OWF)) { + rtcp->rtc_cb(rtcp, RTC_EVENT_OVERFLOW); RTC->CRL &= ~RTC_CRL_OWF; } chSysUnlockFromIsr(); } -#endif /* RTC_SUPPORTS_CALLBACKS */ + +/** + * @brief Waits for the previous registers write to finish. + * + * @notapi + */ +static void rtc_lld_wait_write(void) { + + /* Waits registers write completion.*/ + while (!(RTC->CRL & RTC_CRL_RTOFF)) + ; +} /*===========================================================================*/ /* Driver interrupt handlers. */ @@ -89,18 +93,18 @@ static void rtc_lld_serve_interrupt(RTCDriver *rtcp){ /** * @brief RTC interrupt handler. + * * @isr */ -#if RTC_SUPPORTS_CALLBACKS - CH_IRQ_HANDLER(RTC_IRQHandler) { + CH_IRQ_PROLOGUE(); - rtc_lld_serve_interrupt(&RTCD); + + rtc_lld_serve_interrupt(&RTCD1); + CH_IRQ_EPILOGUE(); } -#endif /* RTC_SUPPORTS_CALLBACKS */ - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -108,226 +112,207 @@ CH_IRQ_HANDLER(RTC_IRQHandler) { /** * @brief Enable access to registers and initialize RTC if BKP domain * was previously reseted. - * * @note: Cold start time of LSE oscillator on STM32 platform * takes about 3 seconds. * * @notapi */ void rtc_lld_init(void){ - uint32_t preload = 0; + uint32_t preload; rccEnableBKPInterface(FALSE); - /* enable access to BKP registers */ + /* Enables access to BKP registers.*/ PWR->CR |= PWR_CR_DBP; - /* select clock source */ - RCC->BDCR |= STM32_RTC; -#if STM32_RTC == STM32_RTC_LSE - if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){ - RCC->BDCR |= RCC_BDCR_LSEON; - while(!(RCC->BDCR & RCC_BDCR_LSERDY)) - ; - RCC->BDCR |= RCC_BDCR_RTCEN; - } - preload = STM32_LSECLK - 1; + /* If the RTC is not enabled then performs a reset of the backup domain.*/ + if (!(RCC->BDCR & RCC_BDCR_RTCEN)) { + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } -#elif STM32_RTC == STM32_RTC_LSI - RCC->CSR |= RCC_CSR_LSION; - while(!(RCC->CSR & RCC_CSR_LSIRDY)) - ; - /* According to errata sheet we must wait additional 100 uS for stabilization */ - uint32_t tmo = (STM32_SYSCLK / 1000000 ) * 100; - while(tmo--) +#if STM32_RTC == STM32_RTC_LSE + if (!(RCC->BDCR & RCC_BDCR_LSEON)) { + RCC->BDCR |= RCC_BDCR_LSEON; + while (!(RCC->BDCR & RCC_BDCR_LSERDY)) ; - RCC->BDCR |= RCC_BDCR_RTCEN; - preload = STM32_LSICLK - 1; - + } + preload = STM32_LSECLK - 1; +#elif STM32_RTC == STM32_RTC_LSI + /* TODO: Move the LSI clock initialization in the HAL low level driver.*/ + RCC->CSR |= RCC_CSR_LSION; + while (!(RCC->CSR & RCC_CSR_LSIRDY)) + ; + /* According to errata sheet we must wait additional 100 uS for + stabilization. + TODO: Change this code, software loops are not reliable.*/ + uint32_t tmo = (STM32_SYSCLK / 1000000) * 100; + while (tmo--) + ; + preload = STM32_LSICLK - 1; #elif STM32_RTC == STM32_RTC_HSE - preload = (STM32_HSICLK / 128) - 1; - -#else -#error "RTC clock source not selected" + preload = (STM32_HSICLK / 128) - 1; #endif + /* Selects clock source (previously enabled and stabilized.*/ + RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTC; + + /* RTC enabled regardless its previous status.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling - * clocking on APB1, because these values only update when APB1 functioning.*/ - RTC->CRL &= ~(RTC_CRL_RSF); + clocking on APB1, because these values only update when APB1 + functioning.*/ + RTC->CRL = 0; while (!(RTC->CRL & RTC_CRL_RSF)) ; - /* Write preload register only if its value changed */ - if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLL)){ - while(!(RTC->CRL & RTC_CRL_RTOFF)) - ; + /* Write preload register only if its value differs.*/ + if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + (uint32_t)RTC->PRLL)) { - RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ - RTC->PRLH = (uint16_t)((preload >> 16) & 0b1111); /* write preloader */ - RTC->PRLL = (uint16_t)(preload & 0xFFFF); - RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ + rtc_lld_wait_write(); - while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ - ; + /* Enters configuration mode and writes PRLx registers then leaves the + configuration mode.*/ + RTC->CRL |= RTC_CRL_CNF; + RTC->PRLH = (uint16_t)(preload >> 16); + RTC->PRLL = (uint16_t)(preload & 0xFFFF); + RTC->CRL &= ~RTC_CRL_CNF; } - /* disable all interrupts and clear all even flags just to be safe */ - RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE); - RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + /* All interrupts initially disabled.*/ + RTC->CRH = 0; -#if RTC_SUPPORTS_CALLBACKS - RTCD.alarm_cb = NULL; - RTCD.overflow_cb = NULL; - RTCD.second_cb = NULL; -#endif /* RTC_SUPPORTS_CALLBACKS */ + /* Callback initially disabled.*/ + RTCD1.rtc_cb = NULL; } /** - * @brief Enables and disables callbacks on the fly. + * @brief Set current time. + * @note Fractional part will be silently ignored. There is no possibility + * to change it on STM32F1xx platform. * - * @details Pass callback function(s) in argument(s) to enable callback(s). - * Pass NULL to disable callback. - * - * @pre To use this function you must set @p RTC_SUPPORTS_CALLBACKS - * to @p TRUE. - * - * @param[in] rtcp pointer to RTC driver structure. - * @param[in] overflowcb overflow callback function. - * @param[in] secondcb every second callback function. - * @param[in] alarmcb alarm callback function. + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCTime structure * * @notapi */ -#if RTC_SUPPORTS_CALLBACKS -void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t overflowcb, - rtccb_t secondcb, rtccb_t alarmcb){ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) { - uint16_t isr_flags = 0; + (void)rtcp; - if (overflowcb != NULL){ - rtcp->overflow_cb = *overflowcb; - isr_flags |= RTC_CRH_OWIE; - } - else{ - rtcp->overflow_cb = NULL; - isr_flags &= ~RTC_CRH_OWIE; - } + rtc_lld_wait_write(); - if (alarmcb != NULL){ - rtcp->alarm_cb = *alarmcb; - isr_flags |= RTC_CRH_ALRIE; - } - else{ - rtcp->alarm_cb = NULL; - isr_flags &= ~RTC_CRH_ALRIE; - } - - if (secondcb != NULL){ - rtcp->second_cb = *secondcb; - isr_flags |= RTC_CRH_SECIE; - } - else{ - rtcp->second_cb = NULL; - isr_flags &= ~RTC_CRH_SECIE; - } - - if(isr_flags != 0){ - NVICEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); - RTC->CRH |= isr_flags; - } - else{ - NVICDisableVector(RTC_IRQn); - RTC->CRH = 0; - } + RTC->CRL |= RTC_CRL_CNF; + RTC->CNTH = (uint16_t)(timespec->tv_sec >> 16); + RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF); + RTC->CRL &= ~RTC_CRL_CNF; } -#endif /* RTC_SUPPORTS_CALLBACKS */ /** - * @brief Set current time. + * @brief Get current time. * - * @param[in] timespec pointer to variable storing time. + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCTime structure * - * @note Fractional part will be silently ignored. There is no possibility - * to change it on STM32F1xx platform. * @notapi */ -void rtc_lld_set_time(RTCDateTime *timespec){ +void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) { + uint32_t time_frac; - while(!(RTC->CRL & RTC_CRL_RTOFF)) - ; + (void)rtcp; - RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ - RTC->CNTH = (uint16_t)((timespec->tv_sec >> 16) & 0xFFFF); - RTC->CNTL = (uint16_t)(timespec->tv_sec & 0xFFFF); - RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ - - while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ - ; + time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL; + timespec->tv_msec = (uint16_t)(((STM32_LSECLK - time_frac) * 1000) / + STM32_LSECLK); + timespec->tv_sec = (RTC->CNTH << 16) + RTC->CNTL; } /** - * @brief Get current time. + * @brief Set alarm time. + * + * @note Default value after BKP domain reset is 0xFFFFFFFF * - * @param[in] msec pointer to variable for storing fractional part of - * time (milliseconds). + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure * * @notapi */ -inline void rtc_lld_get_time(RTCDateTime *timespec){ - uint32_t time_frac = 0; - time_frac = (((uint32_t)RTC->DIVH) << 16) + (RTC->DIVL); +void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec) { - timespec->tv_msec = (uint16_t)(((STM32_LSECLK - time_frac) * 1000) / STM32_LSECLK); - timespec->tv_sec = (RTC->CNTH << 16) + RTC->CNTL; + (void)rtcp; + (void)alarm; + + rtc_lld_wait_write(); + + /* Enters configuration mode and writes ALRHx registers then leaves the + configuration mode.*/ + RTC->CRL |= RTC_CRL_CNF; + if (alarmspec != NULL) { + RTC->ALRH = (uint16_t)(alarmspec->tv_sec >> 16); + RTC->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF); + } + else { + RTC->ALRH = 0; + RTC->ALRL = 0; + } + RTC->CRL &= ~RTC_CRL_CNF; } /** - * @brief Set alarm time. + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. * - * @param[in] timespec pointer to variable storing time of alarm. + * @note Default value after BKP domain reset is 0xFFFFFFFF. * - * @note Fractional part will be silently ignored. There is no possibility - * to change it on STM32F1xx platform. - * - * @note Default value after BKP domain reset is 0xFFFFFFFF + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure * * @notapi */ -void rtc_lld_set_alarm(RTCDateTime *timespec){ +void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec) { - while(!(RTC->CRL & RTC_CRL_RTOFF)) - ; - - RTC->CRL |= RTC_CRL_CNF; /* switch on configure mode */ - RTC->ALRH = (uint16_t)((timespec->tv_sec >> 16) & 0xFFFF); - RTC->ALRL = (uint16_t)(timespec->tv_sec & 0xFFFF); - RTC->CRL &= ~RTC_CRL_CNF; /* switch off configure mode */ - -#if !(RTC_SUPPORTS_CALLBACKS) - RTC->CRL &= ~RTC_CRL_ALRF; - RTC->CRH |= RTC_CRH_ALRIE; -#endif /* !(RTC_SUPPORTS_CALLBACKS) */ + (void)rtcp; + (void)alarm; - while(!(RTC->CRL & RTC_CRL_RTOFF)) /* wait for completion */ - ; + alarmspec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL); } /** - * @brief Get current alarm time. - * - * @param[in] timespec pointer to variable storing time of alarm. + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. * - * @note Fractional part will be silently ignored. There is no possibility - * to change it on STM32F1xx platform. - * - * @note Default value after BKP domain reset is 0xFFFFFFFF + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL * * @notapi */ -inline void rtc_lld_get_alarm(RTCDateTime *timespec){ - timespec->tv_sec = ((RTC->ALRH << 16) + RTC->ALRL); -} +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { + + if (callback != NULL) { + rtcp->rtc_cb = callback; + NVICEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(STM32_RTC_IRQ_PRIORITY)); + /* Interrupts are enabled only after setting up the callback, this + way there is no need to check for the NULL callback pointer inside + the IRQ handler.*/ + RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); + RTC->CRH |= RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE; + } + else { + NVICDisableVector(RTC_IRQn); + RTC->CRL = 0; + RTC->CRH = 0; + } +} #endif /* HAL_USE_RTC */ diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/os/hal/platforms/STM32/RTCv1/rtc_lld.h index f8256ae31..e3ce0e365 100644 --- a/os/hal/platforms/STM32/RTCv1/rtc_lld.h +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.h @@ -35,17 +35,19 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @brief This RTC implementation supports callbacks. + */ +#define RTC_SUPPORTS_CALLBACKS TRUE + +/** + * @brief One alarm comparator available. + */ +#define RTC_ALARMS 1 + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ -/** - * @brief Switch to TRUE if you need callbacks from RTC. Switch to FALSE - * if you need only time keeping. - * @note Default is true. - */ -#if !defined(RTC_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) -#define RTC_SUPPORTS_CALLBACKS TRUE -#endif /*===========================================================================*/ /* Derived constants and error checks. */ @@ -55,46 +57,71 @@ #error "RTC not present in the selected device" #endif +#if !(STM32_RTC == STM32_RTC_LSE) && !(STM32_RTC == STM32_RTC_LSI) && \ + !(STM32_RTC == STM32_RTC_HSE) +#error "invalid source selected for RTC clock" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ /** - * @brief Structure representing an RTC time value. + * @brief Type of a structure representing an RTC alarm stamp. + */ +typedef struct RTCAlarm RTCAlarm; + +/** + * @brief Type of an RTC alarm. + */ +typedef uint32_t rtcalarm_t; + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_SECOND = 0, /** Triggered every second. */ + RTC_EVENT_ALARM = 1, /** Triggered on alarm. */ + RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. */ -typedef struct { +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Structure representing an RTC time stamp. + */ +struct RTCTime { /** - * @brief Seconds sins UNIX epoch. + * @brief Seconds since UNIX epoch. */ uint32_t tv_sec; /** * @brief Fractional part. */ uint32_t tv_msec; -}RTCDateTime; - +}; /** - * @brief Structure representing an RTC driver. - * @note This driver is dummy when callbacks disabled. + * @brief Structure representing an RTC alarm specification. */ -struct RTCDriver{ -#if RTC_SUPPORTS_CALLBACKS +struct RTCAlarm { /** - * @brief Overflow callback. Set it to NULL if not used. + * @brief Seconds since UNIX epoch. */ - rtccb_t overflow_cb; - - /** - * @brief Every second callback. Set it to NULL if not used. - */ - rtccb_t second_cb; + uint32_t tv_sec; +}; +/** + * @brief Structure representing an RTC driver. + */ +struct RTCDriver{ /** - * @brief Alarm callback. Set it to NULL if not used. + * @brief Callback pointer. */ - rtccb_t alarm_cb; -#endif /* RTC_SUPPORTS_CALLBACKS */ + rtccb_t rtc_cb; }; /*===========================================================================*/ @@ -105,27 +132,29 @@ struct RTCDriver{ /* External declarations. */ /*===========================================================================*/ -extern RTCDriver RTCD; - +#if !defined(__DOXYGEN__) +extern RTCDriver RTCD1; +#endif #ifdef __cplusplus extern "C" { #endif void rtc_lld_init(void); - void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t overflow_cb, - rtccb_t second_cb, rtccb_t alarm_cb); - - void rtc_lld_set_time(RTCDateTime *timespec); - void rtc_lld_get_time(RTCDateTime *timespec); - - void rtc_lld_get_alarm(RTCDateTime *timespec); - void rtc_lld_set_alarm(RTCDateTime *timespec); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec); + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); #ifdef __cplusplus } #endif - #endif /* HAL_USE_RTC */ + #endif /* _RTC_LLD_H_ */ /** @} */ diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h index 9ca1140e9..0f19f7b07 100644 --- a/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -214,8 +214,8 @@ * * @api */ -#define rccEnableBKPInterface(lp) \ - rccEnableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp); +#define rccEnableBKPInterface(lp) \ + rccEnableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp) /** * @brief Disables BKP interface clock. @@ -225,22 +225,22 @@ * * @api */ -#define rccDisableBKPInterface(lp) \ - rccDisableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp); +#define rccDisableBKPInterface(lp) \ + rccDisableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp) /** * @brief Resets the Backup Domain interface. * * @api */ -#define rccResetBKPInterface() rccResetAPB1(RCC_APB1ENR_BKPRST); +#define rccResetBKPInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) /** * @brief Resets the entire Backup Domain. * * @api */ -#define rccResetBKP() (RCC->BDCR |= RCC_BDCR_BDRST); +#define rccResetBKP() (RCC->BDCR |= RCC_BDCR_BDRST) /** @} */ /** diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index cf07e8036..6efee2ca7 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -514,11 +514,11 @@ #if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000) #error "STM32_LSECLK outside acceptable range (1...1000KHz)" #endif -#else /* !#if STM32_LSE_ENABLED */ +#else /* !STM32_LSE_ENABLED */ #if STM_RTCCLK == STM32_LSECLK #error "required LSE clock is not enabled" #endif -#endif /* !#if STM32_LSE_ENABLED */ +#endif /* !STM32_LSE_ENABLED */ /* PLL related checks.*/ #if STM32_USB_CLOCK_ENABLED || \ diff --git a/os/hal/src/rtc.c b/os/hal/src/rtc.c index 24ccce84e..dda5a9c95 100644 --- a/os/hal/src/rtc.c +++ b/os/hal/src/rtc.c @@ -52,88 +52,107 @@ /*===========================================================================*/ /** - * @brief Enable access to registers and initialize RTC if BKP domain - * was previously reset. + * @brief RTC Driver initialization. * @note This function is implicitly invoked by @p halInit(), there is * no need to explicitly initialize the driver. * * @init */ void rtcInit(void) { + rtc_lld_init(); } -#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__) /** - * @brief Enables or disables callbacks. - * @details This function enables or disables callbacks, use a @p NULL pointer - * in order to disable a callback. - * @pre To use this function you must set @p RTC_SUPPORTS_CALLBACKS - * to @p TRUE. + * @brief Set current time. * * @param[in] rtcp pointer to RTC driver structure - * @param[in] overflowcb overflow callback function - * @param[in] secondcb every second callback function - * @param[in] alarmcb alarm callback function + * @param[in] timespec pointer to a @p RTCTime structure + * + * @api */ -void rtcSetCallback(RTCDriver *rtcp, rtccb_t overflowcb, - rtccb_t secondcb, rtccb_t alarmcb) { +void rtcSetTime(RTCDriver *rtcp, const RTCTime *timespec) { - chDbgCheck((rtcp != NULL), "rtcSetCallback"); + chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcSetTime"); - rtc_lld_set_callback(rtcp, overflowcb, secondcb, alarmcb); + rtc_lld_set_time(rtcp, timespec); } -#endif /* RTC_SUPPORTS_CALLBACKS */ /** - * @brief Set current time. + * @brief Get current time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] timespec pointer to a @p RTCTime structure * - * @param[in] timespec pointer to a @p RTCDateTime structure + * @api */ -void rtcSetTime(RTCDateTime *timespec) { +void rtcGetTime(RTCDriver *rtcp, RTCTime *timespec) { - chDbgCheck((timespec != NULL), "rtcSetTime"); + chDbgCheck((rtcp != NULL) && (timespec != NULL), "rtcGetTime"); - rtc_lld_set_time(timespec); + rtc_lld_get_time(rtcp, timespec); } +#if (RTC_ALARMS > 0) || defined(__DOXYGEN__) /** - * @brief Get current time. + * @brief Set alarm time. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure or @p NULL * - * @param[in] timespec pointer to a @p RTCDateTime structure + * @api */ -void rtcGetTime(RTCDateTime *timespec) { +void rtcSetAlarm(RTCDriver *rtcp, + rtcalarm_t alarm, + const RTCAlarm *alarmspec) { - chDbgCheck((timespec != NULL), "rtcGetTime"); - rtc_lld_get_time(timespec); + chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS), "rtcSetAlarm"); + + rtc_lld_set_alarm(rtcp, alarm, alarmspec); } /** - * @brief Set alarm time. + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure * - * @param[in] timespec pointer to a @p RTCDateTime structure + * @api */ -void rtcSetAlarm(RTCDateTime *timespec) { +void rtcGetAlarm(RTCDriver *rtcp, + rtcalarm_t alarm, + RTCAlarm *alarmspec) { - chDbgCheck((timespec != NULL), "rtcSetAlarm"); + chDbgCheck((rtcp != NULL) && (alarm < RTC_ALARMS) && (alarmspec != NULL), + "rtcGetAlarm"); - rtc_lld_set_alarm(timespec); + rtc_lld_get_alarm(rtcp, alarm, alarmspec); } +#endif /* RTC_ALARMS > 0 */ +#if RTC_SUPPORTS_CALLBACKS || defined(__DOXYGEN__) /** - * @brief Get current alarm. + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL * - * @param[in] timespec pointer to a @p RTCDateTime structure + * @api */ -void rtcGetAlarm(RTCDateTime *timespec){ +void rtcSetCallback(RTCDriver *rtcp, rtccb_t callback) { - chDbgCheck((timespec != NULL), "rtcGetAlarm"); + chDbgCheck((rtcp != NULL), "rtcSetCallback"); - rtc_lld_get_alarm(timespec); + rtc_lld_set_callback(rtcp, callback); } +#endif /* RTC_SUPPORTS_CALLBACKS */ #endif /* HAL_USE_RTC */ /** @} */ - - diff --git a/testhal/STM32F1xx/RTC/Makefile b/testhal/STM32F1xx/RTC/Makefile index 2f471c293..7748841bd 100644 --- a/testhal/STM32F1xx/RTC/Makefile +++ b/testhal/STM32F1xx/RTC/Makefile @@ -12,7 +12,7 @@ ifeq ($(USE_OPT),) # If all calls to a given function are integrated, and the function is declared static, then the function is normally not output as assembler code in its own right. # Enabled at level '-O3'. - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 #USE_OPT = -O1 -ggdb -fomit-frame-pointer -falign-functions=16 -fno-inline #USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -fno-strict-aliasing #USE_OPT = -O3 -ggdb -fomit-frame-pointer -falign-functions=16 @@ -86,7 +86,6 @@ CSRC = $(PORTSRC) \ $(CHIBIOS)/os/various/evtimer.c \ $(CHIBIOS)/os/various/syscalls.c \ main.c \ - # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -215,6 +214,3 @@ ifeq ($(USE_FWLIB),yes) endif include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk - - - diff --git a/testhal/STM32F1xx/RTC/main.c b/testhal/STM32F1xx/RTC/main.c index 070ac50f2..ea7155f47 100644 --- a/testhal/STM32F1xx/RTC/main.c +++ b/testhal/STM32F1xx/RTC/main.c @@ -21,14 +21,11 @@ #include "ch.h" #include "hal.h" - -RTCDateTime timespec; -RTCDateTime alarmspec; +RTCTime timespec; +RTCAlarm alarmspec; #define TEST_ALARM_WAKEUP FALSE - - #if TEST_ALARM_WAKEUP /* sleep indicator thread */ @@ -64,38 +61,37 @@ int main(void) { return 0; } - - #else /* TEST_ALARM_WAKEUP */ -static void my_overflowcb(RTCDriver *rtcp){ - (void)rtcp; - palTogglePad(IOPORT3, GPIOC_LED); -} +static void my_cb(RTCDriver *rtcp, rtcevent_t event) { -static void my_secondcb(RTCDriver *rtcp){ (void)rtcp; - //palTogglePad(IOPORT3, GPIOC_LED); -} -static void my_alarmcb(RTCDriver *rtcp){ - (void)rtcp; - palTogglePad(IOPORT3, GPIOC_LED); - rtcGetTime(×pec); - alarmspec.tv_sec = timespec.tv_sec + 10; - rtcSetAlarm(&alarmspec); + switch (event) { + case RTC_EVENT_OVERFLOW: + palTogglePad(GPIOC, GPIOC_LED); + break; + case RTC_EVENT_SECOND: + //palTogglePad(GPIOC, GPIOC_LED); + break; + case RTC_EVENT_ALARM: + palTogglePad(GPIOC, GPIOC_LED); + rtcGetTime(&RTCD1, ×pec); + alarmspec.tv_sec = timespec.tv_sec + 10; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + break; + } } - int main(void) { halInit(); chSysInit(); - rtcGetTime(×pec); + rtcGetTime(&RTCD1, ×pec); alarmspec.tv_sec = timespec.tv_sec + 10; - rtcSetAlarm(&alarmspec); + rtcSetAlarm(&RTCD1, 0, &alarmspec); - rtcSetCallback(&RTCD, my_overflowcb, my_secondcb, my_alarmcb); + rtcSetCallback(&RTCD1, my_cb); while (TRUE){ chThdSleepMilliseconds(500); } -- cgit v1.2.3 From 4ab87c6ded40d1797a8d2f8ddc22ee91f6392320 Mon Sep 17 00:00:00 2001 From: barthess Date: Sat, 1 Oct 2011 20:20:53 +0000 Subject: RTC. Insert forgotten closing brace in documentation. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3414 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/RTCv1/rtc_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c index 2876b990d..cae23525f 100644 --- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c +++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c @@ -154,7 +154,7 @@ void rtc_lld_init(void){ preload = (STM32_HSICLK / 128) - 1; #endif - /* Selects clock source (previously enabled and stabilized.*/ + /* Selects clock source (previously enabled and stabilized).*/ RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTC; /* RTC enabled regardless its previous status.*/ -- cgit v1.2.3 From 741b20ffb6c153686bc49e234f9cf190f4ae93ce Mon Sep 17 00:00:00 2001 From: barthess Date: Sat, 1 Oct 2011 20:37:17 +0000 Subject: RTC. Redefinition of RTC_SUPPORTS_CALLBACKS deleted from test. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3415 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/RTC/halconf.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h index 4dcef13da..4932b25f4 100644 --- a/testhal/STM32F1xx/RTC/halconf.h +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -212,12 +212,6 @@ /*===========================================================================*/ /* RTC driver related settings. */ /*===========================================================================*/ -/** - * @brief Switch to TRUE if you need callbacks from RTC. - */ -#if !defined(RTC_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) -#define RTC_SUPPORTS_CALLBACKS TRUE -#endif /*===========================================================================*/ /* MAC driver related settings. */ -- cgit v1.2.3 From 25fd95662814fd189c3616a804f234c19c6b6a58 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 2 Oct 2011 10:19:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3416 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/USBv1/stm32_usb.h | 6 ++-- os/hal/platforms/STM32L1xx/platform.dox | 54 ++++++++++++++++---------------- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/os/hal/platforms/STM32/USBv1/stm32_usb.h b/os/hal/platforms/STM32/USBv1/stm32_usb.h index 51e7510c4..7ba03350a 100644 --- a/os/hal/platforms/STM32/USBv1/stm32_usb.h +++ b/os/hal/platforms/STM32/USBv1/stm32_usb.h @@ -21,10 +21,10 @@ /** * @file stm32_usb.h * @brief STM32 USB registers layout header. - * @note This file requires definitions from the ST STM32 header file - * stm3232f10x.h. + * @note This file requires definitions from the ST STM32 header files + * stm32f10x.h or stm32l1xx.h. * - * @addtogroup STM32_USB + * @addtogroup USB * @{ */ diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox index 910fdf7bd..dc7b26905 100644 --- a/os/hal/platforms/STM32L1xx/platform.dox +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -19,7 +19,7 @@ */ /** - * @defgroup STM32L1xx_DRIVERS STM32L1xx Drivers + * @defgroup STM32_DRIVERS STM32L1xx Drivers * @details This section describes all the supported drivers on the STM32L1xx * platform and the implementation details of the single drivers. * @@ -27,7 +27,7 @@ */ /** - * @defgroup STM32L1xx_HAL STM32L1xx Initialization Support + * @defgroup STM32_HAL STM32L1xx Initialization Support * @details The STM32L1xx HAL support is responsible for system initialization. * * @section stm32l1xx_hal_1 Supported HW resources @@ -43,11 +43,11 @@ * - SYSTICK initialization based on current clock and kernel required rate. * - DMA support initialization. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_ADC STM32L1xx ADC Support + * @defgroup STM32_ADC STM32L1xx ADC Support * @details The STM32L1xx ADC driver supports the ADC peripherals using DMA * channels for maximum performance. * @@ -63,11 +63,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - DMA and ADC errors detection. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_DMA STM32L1xx DMA Support + * @defgroup STM32_DMA STM32L1xx DMA Support * @details This DMA helper driver is used by the other drivers in order to * access the shared DMA resources in a consistent way. * @@ -81,11 +81,11 @@ * - Automatic DMA clock stop when not in use by any driver. * - DMA streams and interrupt vectors sharing among multiple drivers. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_EXT STM32L1xx EXT Support + * @defgroup STM32_EXT STM32L1xx EXT Support * @details The STM32L1xx EXT driver uses the EXTI peripheral. * * @section stm32l1xx_ext_1 Supported HW resources @@ -96,11 +96,11 @@ * - Programmable EXTI interrupts priority level. * - Capability to work as event sources (WFE) rather than interrupt sources. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_GPT STM32L1xx GPT Support + * @defgroup STM32_GPT STM32L1xx GPT Support * @details The STM32L1xx GPT driver uses the TIMx peripherals. * * @section stm32l1xx_gpt_1 Supported HW resources @@ -113,11 +113,11 @@ * peripherals are left in low power mode. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_ICU STM32L1xx ICU Support + * @defgroup STM32_ICU STM32L1xx ICU Support * @details The STM32L1xx ICU driver uses the TIMx peripherals. * * @section stm32l1xx_icu_1 Supported HW resources @@ -130,11 +130,11 @@ * peripherals are left in low power mode. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_PAL STM32L1xx PAL Support + * @defgroup STM32_PAL STM32L1xx PAL Support * @details The STM32L1xx PAL driver uses the GPIO peripherals. * * @section stm32l1xx_pal_1 Supported HW resources @@ -164,8 +164,8 @@ * - @p PAL_MODE_INPUT_ANALOG. * - @p PAL_MODE_OUTPUT_PUSHPULL. * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * - @p PAL_MODE_STM32L1xx_ALTERNATE_PUSHPULL (non standard). - * - @p PAL_MODE_STM32L1xx_ALTERNATE_OPENDRAIN (non standard). + * - @p PAL_MODE_STM32_ALTERNATE_PUSHPULL (non standard). + * - @p PAL_MODE_STM32_ALTERNATE_OPENDRAIN (non standard). * . * Any attempt to setup an invalid mode is ignored. * @@ -175,11 +175,11 @@ * - Pad/port toggling operations are not atomic. * - Pad/group mode setup is not atomic. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_PWM STM32L1xx PWM Support + * @defgroup STM32_PWM STM32L1xx PWM Support * @details The STM32L1xx PWM driver uses the TIMx peripherals. * * @section stm32l1xx_pwm_1 Supported HW resources @@ -195,11 +195,11 @@ * - Four independent PWM channels per timer. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_SERIAL STM32L1xx Serial Support + * @defgroup STM32_SERIAL STM32L1xx Serial Support * @details The STM32L1xx Serial driver uses the USART/UART peripherals in a * buffered, interrupt driven, implementation. * @@ -218,11 +218,11 @@ * - Fully interrupt driven. * - Programmable priority levels for each UART/USART. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_SPI STM32L1xx SPI Support + * @defgroup STM32_SPI STM32L1xx SPI Support * @details The SPI driver supports the STM32L1xx SPI peripherals using DMA * channels for maximum performance. * @@ -243,11 +243,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - Programmable DMA error hook. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_UART STM32L1xx UART Support + * @defgroup STM32_UART STM32L1xx UART Support * @details The UART driver supports the STM32L1xx USART peripherals using DMA * channels for maximum performance. * @@ -270,11 +270,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - Programmable DMA error hook. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ /** - * @defgroup STM32L1xx_USB STM32L1xx USB Support + * @defgroup STM32_USB STM32L1xx USB Support * @details The USB driver supports the STM32L1xx USB peripheral. * * @section stm32l1xx_usb_1 Supported HW resources @@ -286,5 +286,5 @@ * - Programmable interrupt priority levels. * - Each endpoint programmable in Control, Bulk and Interrupt modes. * . - * @ingroup STM32L1xx_DRIVERS + * @ingroup STM32_DRIVERS */ -- cgit v1.2.3 From e3262e950c778403d9d8303e6f70cdb5912a5b5d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 2 Oct 2011 10:21:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3417 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/platform.dox | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox index dc7b26905..3737cc10d 100644 --- a/os/hal/platforms/STM32L1xx/platform.dox +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -164,8 +164,7 @@ * - @p PAL_MODE_INPUT_ANALOG. * - @p PAL_MODE_OUTPUT_PUSHPULL. * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * - @p PAL_MODE_STM32_ALTERNATE_PUSHPULL (non standard). - * - @p PAL_MODE_STM32_ALTERNATE_OPENDRAIN (non standard). + * - @p PAL_MODE_ALTERNATE (non standard). * . * Any attempt to setup an invalid mode is ignored. * -- cgit v1.2.3 From 2913907698510dc37049990dff13da0a11140b6a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 2 Oct 2011 10:23:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3418 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/platform.dox | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox index 3737cc10d..773785a5b 100644 --- a/os/hal/platforms/STM32L1xx/platform.dox +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -197,6 +197,22 @@ * @ingroup STM32_DRIVERS */ +/** + * @defgroup STM32_RCC STM32F1xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f1xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Periplerals clock disable. + * . + * @ingroup STM32_DRIVERS + */ + /** * @defgroup STM32_SERIAL STM32L1xx Serial Support * @details The STM32L1xx Serial driver uses the USART/UART peripherals in a -- cgit v1.2.3 From 9a25b3d92870112cfad854f7d146e9d607ead491 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 2 Oct 2011 10:59:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3419 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/platform.dox | 78 ++++++++++++++++----------------- os/hal/platforms/STM32L1xx/platform.dox | 56 +++++++++++------------ 2 files changed, 67 insertions(+), 67 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/platform.dox b/os/hal/platforms/STM32F1xx/platform.dox index 624a5b12f..2f282e4d5 100644 --- a/os/hal/platforms/STM32F1xx/platform.dox +++ b/os/hal/platforms/STM32F1xx/platform.dox @@ -19,7 +19,7 @@ */ /** - * @defgroup STM32_DRIVERS STM32F1xx Drivers + * @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers * @details This section describes all the supported drivers on the STM32F1xx * platform and the implementation details of the single drivers. * @@ -27,7 +27,7 @@ */ /** - * @defgroup STM32_HAL STM32F1xx Initialization Support + * @defgroup STM32F1xx_HAL STM32F1xx Initialization Support * @details The STM32F1xx HAL support is responsible for system initialization. * * @section stm32f1xx_hal_1 Supported HW resources @@ -44,11 +44,11 @@ * - SYSTICK initialization based on current clock and kernel required rate. * - DMA support initialization. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_ADC STM32F1xx ADC Support + * @defgroup STM32F1xx_ADC STM32F1xx ADC Support * @details The STM32F1xx ADC driver supports the ADC peripherals using DMA * channels for maximum performance. * @@ -64,11 +64,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - DMA errors detection. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_CAN STM32F1xx CAN Support + * @defgroup STM32F1xx_CAN STM32F1xx CAN Support * @details The STM32F1xx CAN driver uses the CAN peripherals. * * @section stm32f1xx_can_1 Supported HW resources @@ -79,11 +79,11 @@ * - Support for bxCAN sleep mode. * - Programmable bxCAN interrupts priority level. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_DMA STM32F1xx DMA Support + * @defgroup STM32F1xx_DMA STM32F1xx DMA Support * @details This DMA helper driver is used by the other drivers in order to * access the shared DMA resources in a consistent way. * @@ -98,11 +98,11 @@ * - Automatic DMA clock stop when not in use by any driver. * - DMA streams and interrupt vectors sharing among multiple drivers. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_EXT STM32F1xx EXT Support + * @defgroup STM32F1xx_EXT STM32F1xx EXT Support * @details The STM32F1xx EXT driver uses the EXTI peripheral. * * @section stm32f1xx_ext_1 Supported HW resources @@ -113,11 +113,11 @@ * - Programmable EXTI interrupts priority level. * - Capability to work as event sources (WFE) rather than interrupt sources. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_GPT STM32F1xx GPT Support + * @defgroup STM32F1xx_GPT STM32F1xx GPT Support * @details The STM32F1xx GPT driver uses the TIMx peripherals. * * @section stm32f1xx_gpt_1 Supported HW resources @@ -132,11 +132,11 @@ * peripherals are left in low power mode. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_I2C STM32F1xx I2C Support + * @defgroup STM32F1xx_I2C STM32F1xx I2C Support * @details The STM32F1xx I2C driver uses the I2Cx peripherals. * * @section stm32f1xx_i2c_1 Supported HW resources @@ -148,11 +148,11 @@ * peripherals are left in low power mode. * - Programmable I2Cx interrupts priority level. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_ICU STM32F1xx ICU Support + * @defgroup STM32F1xx_ICU STM32F1xx ICU Support * @details The STM32F1xx ICU driver uses the TIMx peripherals. * * @section stm32f1xx_icu_1 Supported HW resources @@ -167,21 +167,21 @@ * peripherals are left in low power mode. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_MAC STM32F1xx MAC Support + * @defgroup STM32F1xx_MAC STM32F1xx MAC Support * @details The STM32 MAC driver supports the ETH peripheral. * * @section at91sam7_mac_1 Supported HW resources * - ETH. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_PAL STM32F1xx PAL Support + * @defgroup STM32F1xx_PAL STM32F1xx PAL Support * @details The STM32F1xx PAL driver uses the GPIO peripherals. * * @section stm32f1xx_pal_1 Supported HW resources @@ -213,8 +213,8 @@ * - @p PAL_MODE_INPUT_ANALOG. * - @p PAL_MODE_OUTPUT_PUSHPULL. * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * - @p PAL_MODE_STM32_ALTERNATE_PUSHPULL (non standard). - * - @p PAL_MODE_STM32_ALTERNATE_OPENDRAIN (non standard). + * - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard). + * - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard). * . * Any attempt to setup an invalid mode is ignored. * @@ -227,11 +227,11 @@ * resistor can change the resistor setting because the output latch is * used for resistor selection. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_PWM STM32F1xx PWM Support + * @defgroup STM32F1xx_PWM STM32F1xx PWM Support * @details The STM32F1xx PWM driver uses the TIMx peripherals. * * @section stm32f1xx_pwm_1 Supported HW resources @@ -247,11 +247,11 @@ * - Four independent PWM channels per timer. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_RCC STM32F1xx RCC Support + * @defgroup STM32F1xx_RCC STM32F1xx RCC Support * @details This RCC helper driver is used by the other drivers in order to * access the shared RCC resources in a consistent way. * @@ -263,21 +263,21 @@ * - Peripherals clock enable. * - Periplerals clock disable. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_RTC STM32F1xx RTC Support + * @defgroup STM32F1xx_RTC STM32F1xx RTC Support * @details The STM32F1xx RTC driver uses the RTC peripheral. * * @section stm32f1xx_rtc_1 Supported HW resources * - RTC. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_SDC STM32F1xx SDC Support + * @defgroup STM32F1xx_SDC STM32F1xx SDC Support * @details The STM32F1xx SDC driver uses the SDIO peripheral. * * @section stm32f1xx_sdc_1 Supported HW resources @@ -290,11 +290,11 @@ * - DMA is used for receiving and transmitting. * - Programmable DMA bus priority for each DMA channel. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_SERIAL STM32F1xx Serial Support + * @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support * @details The STM32F1xx Serial driver uses the USART/UART peripherals in a * buffered, interrupt driven, implementation. * @@ -313,11 +313,11 @@ * - Fully interrupt driven. * - Programmable priority levels for each UART/USART. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_SPI STM32F1xx SPI Support + * @defgroup STM32F1xx_SPI STM32F1xx SPI Support * @details The SPI driver supports the STM32F1xx SPI peripherals using DMA * channels for maximum performance. * @@ -338,11 +338,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - Programmable DMA error hook. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_UART STM32F1xx UART Support + * @defgroup STM32F1xx_UART STM32F1xx UART Support * @details The UART driver supports the STM32F1xx USART peripherals using DMA * channels for maximum performance. * @@ -365,11 +365,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - Programmable DMA error hook. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ /** - * @defgroup STM32_USB STM32F1xx USB Support + * @defgroup STM32F1xx_USB STM32F1xx USB Support * @details The USB driver supports the STM32F1xx USB peripheral. * * @section stm32f1xx_usb_1 Supported HW resources @@ -381,5 +381,5 @@ * - Programmable interrupt priority levels. * - Each endpoint programmable in Control, Bulk and Interrupt modes. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32F1xx_DRIVERS */ diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox index 773785a5b..18a788ed0 100644 --- a/os/hal/platforms/STM32L1xx/platform.dox +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -19,7 +19,7 @@ */ /** - * @defgroup STM32_DRIVERS STM32L1xx Drivers + * @defgroup STM32L1xx_DRIVERS STM32L1xx Drivers * @details This section describes all the supported drivers on the STM32L1xx * platform and the implementation details of the single drivers. * @@ -27,7 +27,7 @@ */ /** - * @defgroup STM32_HAL STM32L1xx Initialization Support + * @defgroup STM32L1xx_HAL STM32L1xx Initialization Support * @details The STM32L1xx HAL support is responsible for system initialization. * * @section stm32l1xx_hal_1 Supported HW resources @@ -43,11 +43,11 @@ * - SYSTICK initialization based on current clock and kernel required rate. * - DMA support initialization. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_ADC STM32L1xx ADC Support + * @defgroup STM32L1xx_ADC STM32L1xx ADC Support * @details The STM32L1xx ADC driver supports the ADC peripherals using DMA * channels for maximum performance. * @@ -63,11 +63,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - DMA and ADC errors detection. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_DMA STM32L1xx DMA Support + * @defgroup STM32L1xx_DMA STM32L1xx DMA Support * @details This DMA helper driver is used by the other drivers in order to * access the shared DMA resources in a consistent way. * @@ -81,11 +81,11 @@ * - Automatic DMA clock stop when not in use by any driver. * - DMA streams and interrupt vectors sharing among multiple drivers. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_EXT STM32L1xx EXT Support + * @defgroup STM32L1xx_EXT STM32L1xx EXT Support * @details The STM32L1xx EXT driver uses the EXTI peripheral. * * @section stm32l1xx_ext_1 Supported HW resources @@ -96,11 +96,11 @@ * - Programmable EXTI interrupts priority level. * - Capability to work as event sources (WFE) rather than interrupt sources. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_GPT STM32L1xx GPT Support + * @defgroup STM32L1xx_GPT STM32L1xx GPT Support * @details The STM32L1xx GPT driver uses the TIMx peripherals. * * @section stm32l1xx_gpt_1 Supported HW resources @@ -113,11 +113,11 @@ * peripherals are left in low power mode. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_ICU STM32L1xx ICU Support + * @defgroup STM32L1xx_ICU STM32L1xx ICU Support * @details The STM32L1xx ICU driver uses the TIMx peripherals. * * @section stm32l1xx_icu_1 Supported HW resources @@ -130,11 +130,11 @@ * peripherals are left in low power mode. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_PAL STM32L1xx PAL Support + * @defgroup STM32L1xx_PAL STM32L1xx PAL Support * @details The STM32L1xx PAL driver uses the GPIO peripherals. * * @section stm32l1xx_pal_1 Supported HW resources @@ -174,11 +174,11 @@ * - Pad/port toggling operations are not atomic. * - Pad/group mode setup is not atomic. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_PWM STM32L1xx PWM Support + * @defgroup STM32L1xx_PWM STM32L1xx PWM Support * @details The STM32L1xx PWM driver uses the TIMx peripherals. * * @section stm32l1xx_pwm_1 Supported HW resources @@ -194,27 +194,27 @@ * - Four independent PWM channels per timer. * - Programmable TIMx interrupts priority level. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_RCC STM32F1xx RCC Support + * @defgroup STM32L1xx_RCC STM32L1xx RCC Support * @details This RCC helper driver is used by the other drivers in order to * access the shared RCC resources in a consistent way. * * @section stm32f1xx_rcc_1 Supported HW resources * - RCC. * . - * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features + * @section stm32l1xx_rcc_2 STM32L1xx RCC driver implementation features * - Peripherals reset. * - Peripherals clock enable. * - Periplerals clock disable. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_SERIAL STM32L1xx Serial Support + * @defgroup STM32L1xx_SERIAL STM32L1xx Serial Support * @details The STM32L1xx Serial driver uses the USART/UART peripherals in a * buffered, interrupt driven, implementation. * @@ -233,11 +233,11 @@ * - Fully interrupt driven. * - Programmable priority levels for each UART/USART. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_SPI STM32L1xx SPI Support + * @defgroup STM32L1xx_SPI STM32L1xx SPI Support * @details The SPI driver supports the STM32L1xx SPI peripherals using DMA * channels for maximum performance. * @@ -258,11 +258,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - Programmable DMA error hook. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_UART STM32L1xx UART Support + * @defgroup STM32L1xx_UART STM32L1xx UART Support * @details The UART driver supports the STM32L1xx USART peripherals using DMA * channels for maximum performance. * @@ -285,11 +285,11 @@ * - Programmable DMA interrupt priority for each DMA channel. * - Programmable DMA error hook. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ /** - * @defgroup STM32_USB STM32L1xx USB Support + * @defgroup STM32L1xx_USB STM32L1xx USB Support * @details The USB driver supports the STM32L1xx USB peripheral. * * @section stm32l1xx_usb_1 Supported HW resources @@ -301,5 +301,5 @@ * - Programmable interrupt priority levels. * - Each endpoint programmable in Control, Bulk and Interrupt modes. * . - * @ingroup STM32_DRIVERS + * @ingroup STM32L1xx_DRIVERS */ -- cgit v1.2.3 From 65d15d42c446b5f30e549fdeadfe88f963d2ee55 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 2 Oct 2011 11:20:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3420 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/platform.dox | 79 ++++++++++++++++++--------------- os/hal/platforms/STM32L1xx/platform.dox | 77 ++++++++++++++++++-------------- 2 files changed, 87 insertions(+), 69 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/platform.dox b/os/hal/platforms/STM32F1xx/platform.dox index 2f282e4d5..c9d43a80e 100644 --- a/os/hal/platforms/STM32F1xx/platform.dox +++ b/os/hal/platforms/STM32F1xx/platform.dox @@ -82,25 +82,6 @@ * @ingroup STM32F1xx_DRIVERS */ -/** - * @defgroup STM32F1xx_DMA STM32F1xx DMA Support - * @details This DMA helper driver is used by the other drivers in order to - * access the shared DMA resources in a consistent way. - * - * @section stm32f1xx_dma_1 Supported HW resources - * The DMA driver can support any of the following hardware resources: - * - DMA1. - * - DMA2 (where present). - * . - * @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features - * - Exports helper functions/macros to the other drivers that share the - * DMA resource. - * - Automatic DMA clock stop when not in use by any driver. - * - DMA streams and interrupt vectors sharing among multiple drivers. - * . - * @ingroup STM32F1xx_DRIVERS - */ - /** * @defgroup STM32F1xx_EXT STM32F1xx EXT Support * @details The STM32F1xx EXT driver uses the EXTI peripheral. @@ -250,22 +231,6 @@ * @ingroup STM32F1xx_DRIVERS */ -/** - * @defgroup STM32F1xx_RCC STM32F1xx RCC Support - * @details This RCC helper driver is used by the other drivers in order to - * access the shared RCC resources in a consistent way. - * - * @section stm32f1xx_rcc_1 Supported HW resources - * - RCC. - * . - * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features - * - Peripherals reset. - * - Peripherals clock enable. - * - Periplerals clock disable. - * . - * @ingroup STM32F1xx_DRIVERS - */ - /** * @defgroup STM32F1xx_RTC STM32F1xx RTC Support * @details The STM32F1xx RTC driver uses the RTC peripheral. @@ -383,3 +348,47 @@ * . * @ingroup STM32F1xx_DRIVERS */ + +/** + * @defgroup STM32F1xx_PLATFORM_DRIVERS STM32F1xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32F1xx_DRIVERS + */ + +/** + * @defgroup STM32F1xx_DMA STM32F1xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32f1xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * - DMA2 (where present). + * . + * @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32F1xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F1xx_RCC STM32F1xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f1xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Periplerals clock disable. + * . + * @ingroup STM32F1xx_PLATFORM_DRIVERS + */ diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox index 18a788ed0..33bf706ab 100644 --- a/os/hal/platforms/STM32L1xx/platform.dox +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -66,24 +66,6 @@ * @ingroup STM32L1xx_DRIVERS */ -/** - * @defgroup STM32L1xx_DMA STM32L1xx DMA Support - * @details This DMA helper driver is used by the other drivers in order to - * access the shared DMA resources in a consistent way. - * - * @section stm32l1xx_dma_1 Supported HW resources - * The DMA driver can support any of the following hardware resources: - * - DMA1. - * . - * @section stm32l1xx_dma_2 STM32L1xx DMA driver implementation features - * - Exports helper functions/macros to the other drivers that share the - * DMA resource. - * - Automatic DMA clock stop when not in use by any driver. - * - DMA streams and interrupt vectors sharing among multiple drivers. - * . - * @ingroup STM32L1xx_DRIVERS - */ - /** * @defgroup STM32L1xx_EXT STM32L1xx EXT Support * @details The STM32L1xx EXT driver uses the EXTI peripheral. @@ -197,22 +179,6 @@ * @ingroup STM32L1xx_DRIVERS */ -/** - * @defgroup STM32L1xx_RCC STM32L1xx RCC Support - * @details This RCC helper driver is used by the other drivers in order to - * access the shared RCC resources in a consistent way. - * - * @section stm32f1xx_rcc_1 Supported HW resources - * - RCC. - * . - * @section stm32l1xx_rcc_2 STM32L1xx RCC driver implementation features - * - Peripherals reset. - * - Peripherals clock enable. - * - Periplerals clock disable. - * . - * @ingroup STM32L1xx_DRIVERS - */ - /** * @defgroup STM32L1xx_SERIAL STM32L1xx Serial Support * @details The STM32L1xx Serial driver uses the USART/UART peripherals in a @@ -303,3 +269,46 @@ * . * @ingroup STM32L1xx_DRIVERS */ + +/** + * @defgroup STM32L1xx_PLATFORM_DRIVERS STM32L1xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32L1xx_DRIVERS + */ + +/** + * @defgroup STM32L1xx_DMA STM32L1xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32l1xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * . + * @section stm32l1xx_dma_2 STM32L1xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32L1xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32L1xx_RCC STM32L1xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f1xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32l1xx_rcc_2 STM32L1xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Periplerals clock disable. + * . + * @ingroup STM32L1xx_PLATFORM_DRIVERS + */ -- cgit v1.2.3 From a2109bf01e8910ca1cc16a109cf6911fbd2323fa Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 2 Oct 2011 11:30:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3421 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/stm32_rcc.h | 2 +- os/hal/platforms/STM32L1xx/stm32_rcc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h index 0f19f7b07..2a5daaadd 100644 --- a/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -24,7 +24,7 @@ * @note This file requires definitions from the ST header file * @p stm32f10x.h. * - * @addtogroup STM32_RCC + * @addtogroup STM32F1xx_RCC * @{ */ diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/platforms/STM32L1xx/stm32_rcc.h index abad4f96b..e2460a41f 100644 --- a/os/hal/platforms/STM32L1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32L1xx/stm32_rcc.h @@ -24,7 +24,7 @@ * @note This file requires definitions from the ST header file * @p stm32l1xx.h. * - * @addtogroup STM32_RCC + * @addtogroup STM32L1xx_RCC * @{ */ -- cgit v1.2.3 From 0138ec13a29d7688ba454ed2e19f88d1114bfa89 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 2 Oct 2011 12:08:01 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3422 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/reports/STM32F103-72-GCC.txt | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/docs/reports/STM32F103-72-GCC.txt b/docs/reports/STM32F103-72-GCC.txt index 486964e49..f0bcdafa5 100644 --- a/docs/reports/STM32F103-72-GCC.txt +++ b/docs/reports/STM32F103-72-GCC.txt @@ -6,7 +6,8 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) *** ChibiOS/RT test suite *** *** Kernel: 2.3.3unstable -*** Compiler: GCC 4.5.2 +*** Compiled: Oct 2 2011 - 13:53:22 +*** Compiler: GCC 4.6.0 *** Architecture: ARMv7-M *** Core Variant: Cortex-M3 *** Port Info: Advanced kernel mode @@ -99,56 +100,56 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.1 (Benchmark, messages #1) ---- Score : 248463 msgs/S, 496926 ctxswc/S +--- Score : 266998 msgs/S, 533996 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.2 (Benchmark, messages #2) ---- Score : 198907 msgs/S, 397814 ctxswc/S +--- Score : 213748 msgs/S, 427496 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.3 (Benchmark, messages #3) ---- Score : 198907 msgs/S, 397814 ctxswc/S +--- Score : 213748 msgs/S, 427496 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.4 (Benchmark, context switch) ---- Score : 838640 ctxswc/S +--- Score : 962440 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 156788 threads/S +--- Score : 159606 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 235439 threads/S +--- Score : 236259 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 61111 reschedules/S, 366666 ctxswc/S +--- Score : 64703 reschedules/S, 388218 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 477916 ctxswc/S +--- Score : 468656 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 592296 bytes/S +--- Score : 651460 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 646974 timers/S +--- Score : 647048 timers/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 786988 wait+signal/S +--- Score : 787100 wait+signal/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 586240 lock+unlock/S +--- Score : 596028 lock+unlock/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 368 bytes ---- Thread: 68 bytes +--- System: 376 bytes +--- Thread: 72 bytes --- Timer : 20 bytes --- Semaph: 12 bytes --- EventS: 4 bytes -- cgit v1.2.3 From 9422ad779cb626290d92db6144bce33eaa5758f1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 4 Oct 2011 20:01:46 +0000 Subject: Fixed bug 3418620. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3424 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/pwm_lld.c | 2 +- readme.txt | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index d8f98a432..ab3c1c2bb 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -327,7 +327,7 @@ void pwm_lld_init(void) { #if STM32_PWM_USE_TIM8 /* Driver initialization.*/ pwmObjectInit(&PWMD8); - PWMD5.tim = TIM8; + PWMD8.tim = TIM8; #endif } diff --git a/readme.txt b/readme.txt index e0b7bed9a..2f3c20335 100644 --- a/readme.txt +++ b/readme.txt @@ -72,6 +72,9 @@ *** Releases *** ***************************************************************************** +*** 2.3.4 *** +- FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). + *** 2.3.3 *** - FIX: Fixed uninitialized variable in STM32 PWM and ICU drivers (bug 3413558). - FIX: Fixed wrong parameter passed to the DMA error hook in STM32 ADC driver, -- cgit v1.2.3 From 85cf040f27470066f73aa53401b738e1dff47200 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 4 Oct 2011 20:25:26 +0000 Subject: Fixed bug 3418626. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3425 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103/mcuconf.h | 9 ++++++--- readme.txt | 1 + testhal/STM32F1xx/EXT/mcuconf.h | 9 ++++++--- testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h | 9 ++++++--- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/demos/ARMCM3-STM32F103/mcuconf.h b/demos/ARMCM3-STM32F103/mcuconf.h index 23694e0e6..8fbf4710c 100644 --- a/demos/ARMCM3-STM32F103/mcuconf.h +++ b/demos/ARMCM3-STM32F103/mcuconf.h @@ -82,7 +82,8 @@ #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM8 FALSE#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 @@ -96,7 +97,8 @@ #define STM32_ICU_USE_TIM3 FALSE #define STM32_ICU_USE_TIM4 TRUE #define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 #define STM32_ICU_TIM2_IRQ_PRIORITY 7 #define STM32_ICU_TIM3_IRQ_PRIORITY 7 #define STM32_ICU_TIM4_IRQ_PRIORITY 7 @@ -111,7 +113,8 @@ #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 #define STM32_PWM_TIM4_IRQ_PRIORITY 7 diff --git a/readme.txt b/readme.txt index 2f3c20335..d4ea10acd 100644 --- a/readme.txt +++ b/readme.txt @@ -74,6 +74,7 @@ *** 2.3.4 *** - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). +- FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). *** 2.3.3 *** - FIX: Fixed uninitialized variable in STM32 PWM and ICU drivers (bug 3413558). diff --git a/testhal/STM32F1xx/EXT/mcuconf.h b/testhal/STM32F1xx/EXT/mcuconf.h index 23694e0e6..8fbf4710c 100644 --- a/testhal/STM32F1xx/EXT/mcuconf.h +++ b/testhal/STM32F1xx/EXT/mcuconf.h @@ -82,7 +82,8 @@ #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM8 FALSE#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 @@ -96,7 +97,8 @@ #define STM32_ICU_USE_TIM3 FALSE #define STM32_ICU_USE_TIM4 TRUE #define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 #define STM32_ICU_TIM2_IRQ_PRIORITY 7 #define STM32_ICU_TIM3_IRQ_PRIORITY 7 #define STM32_ICU_TIM4_IRQ_PRIORITY 7 @@ -111,7 +113,8 @@ #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 #define STM32_PWM_TIM4_IRQ_PRIORITY 7 diff --git a/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h index 7ec218f04..95b5ebd73 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h @@ -82,7 +82,8 @@ #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM8 FALSE#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 @@ -96,7 +97,8 @@ #define STM32_ICU_USE_TIM3 FALSE #define STM32_ICU_USE_TIM4 TRUE #define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 #define STM32_ICU_TIM2_IRQ_PRIORITY 7 #define STM32_ICU_TIM3_IRQ_PRIORITY 7 #define STM32_ICU_TIM4_IRQ_PRIORITY 7 @@ -111,7 +113,8 @@ #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 #define STM32_PWM_TIM4_IRQ_PRIORITY 7 -- cgit v1.2.3 From 1351fded5a9c460166637d276616a73be0b72392 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 5 Oct 2011 17:00:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3426 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/DMAv1/stm32_dma.c | 4 +-- os/hal/platforms/STM32/DMAv1/stm32_dma.h | 55 ++++++++++++++++++++++++++++++++ os/ports/GCC/ARMCMx/crt0.c | 7 ++-- readme.txt | 4 ++- todo.txt | 44 +++++++++++-------------- 5 files changed, 82 insertions(+), 32 deletions(-) diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.c b/os/hal/platforms/STM32/DMAv1/stm32_dma.c index 3fb1b2dc6..84e372c26 100644 --- a/os/hal/platforms/STM32/DMAv1/stm32_dma.c +++ b/os/hal/platforms/STM32/DMAv1/stm32_dma.c @@ -100,8 +100,8 @@ const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { * @brief DMA ISR redirector type. */ typedef struct { - stm32_dmaisr_t dma_func; - void *dma_param; + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ } dma_isr_redir_t; /** diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.h b/os/hal/platforms/STM32/DMAv1/stm32_dma.h index 22be4a67e..f209898d4 100644 --- a/os/hal/platforms/STM32/DMAv1/stm32_dma.h +++ b/os/hal/platforms/STM32/DMAv1/stm32_dma.h @@ -153,6 +153,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Associates a peripheral data register to a DMA stream. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @param[in] addr value to be written in the CPAR register @@ -166,6 +168,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Associates a memory destination to a DMA stream. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @param[in] addr value to be written in the CMAR register @@ -179,6 +183,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Sets the number of transfers to be performed. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @param[in] size value to be written in the CNDTR register @@ -192,6 +198,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Returns the number of transfers to be performed. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @return The number of transfers to be performed. @@ -203,6 +211,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Programs the stream mode settings. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @param[in] mode value to be written in the CCR register @@ -216,6 +226,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief DMA stream enable. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @@ -228,6 +240,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief DMA stream disable. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @@ -240,6 +254,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief DMA stream interrupt sources clear. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @@ -249,6 +265,45 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ } +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamGetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) \ + while (((dmastp)->channel->CNDTR > 0) && \ + ((dmastp)->channel->CCR & STM32_DMA_CR_EN)) + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ diff --git a/os/ports/GCC/ARMCMx/crt0.c b/os/ports/GCC/ARMCMx/crt0.c index e2cb2b3de..0737c467b 100644 --- a/os/ports/GCC/ARMCMx/crt0.c +++ b/os/ports/GCC/ARMCMx/crt0.c @@ -251,13 +251,14 @@ __attribute__((naked)) void ResetHandler(void) { uint32_t psp, ctl; - /* Process Stack initialization, it is allocated below the main stack. The - main stack is assumed to be allocated starting from @p __ram_end__ - extending downward.*/ + /* Process Stack initialization, it is allocated starting from the + symbol __process_stack_end__ and its lower limit is the symbol + __process_stack_base__.*/ asm volatile ("cpsid i"); psp = SYMVAL(__process_stack_end__); asm volatile ("msr PSP, %0" : : "r" (psp)); + /* CPU mode initialization.*/ ctl = CRT0_CONTROL_INIT; asm volatile ("msr CONTROL, %0" : : "r" (ctl)); asm volatile ("isb"); diff --git a/readme.txt b/readme.txt index d4ea10acd..155ae8506 100644 --- a/readme.txt +++ b/readme.txt @@ -63,7 +63,8 @@ +--testhal/ - HAL integration test demos. | +--LPC11xx/ - LPC11xx HAL test demos. | +--LPC13xx/ - LPC13xx HAL test demos. - | +--STM32/ - STM32 HAL test demos. + | +--STM32F1xx/ - STM32F1xx HAL test demos. + | +--STM32L1xx/ - STM32L1xx HAL test demos. | +--STM8S/ - STM8S HAL test demos. +--tools - Various tools. +--eclipse - Eclipse enhancements. @@ -75,6 +76,7 @@ *** 2.3.4 *** - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). +- NEW: Added memory copy functionality to the STM32 DMA driver. *** 2.3.3 *** - FIX: Fixed uninitialized variable in STM32 PWM and ICU drivers (bug 3413558). diff --git a/todo.txt b/todo.txt index 5f38eb2a1..51f3c6795 100644 --- a/todo.txt +++ b/todo.txt @@ -6,39 +6,31 @@ X = In progress, some work done. N = Decided against. Current Pipeline (2.3.x): -* lwIP 1.4.0 integration and test. -* Named threads. -* Call protocol check debug option. -* Improved stack overflow checking, support main() thread. - * Move main stack to low memory in ARMCMx ports. -* Eclipse plugin. -* FatFs 0.8x integration. -* Kernel-only demo for users not interested in HAL (Cortex-Mx only). -- USB and USB_SERIAL APIs reclassification (if needed), incorporate the USB - bus attach/detach handling in usbStart()/usbStop(). -- USB double buffering support for STM32 implementation. -X STM32L1xx support (verify and test existing STM32F1xx drivers). - - Specific ADC driver for STM32L1xx. - X STM32L-Discovery demo and article. -X STM32F2xx support (adapt and re-verify all drivers). - * New STM32 DMA helper driver abstracting differences between STM32F2xx and - other sub-families. - ? Specific ADC driver for STM32F2xx. +- USB driver enhancements. + - USB and USB_SERIAL APIs reclassification. + - Incorporate the USB bus attach/detach handling in usbStart()/usbStop(). + - Fix zero size packets handling in USB_SERIAL driver. + - USB double buffering support for STM32 implementation. + - Evaluate using DMA channels for buffer copy. +X I2C device driver class support and at least one implementation. + X Evaluate a modified I2C API where the synchronous mode is default and the + callback mode optional. + - Software I2C implementation using a GPT instance for timings. +X STM32F2xx/STM32F4xx support (adapt and re-verify all drivers). + * New STM32 DMA helper driver abstracting differences between + STM32F2xx/STM32F4xx and other sub-families. + - Specific ADC driver for STM32F2xx/STM32F4xx. - MMC_SPI driver revision and speedup. +- FatFs 0.9x integration. + +Within 2.x.x +X File System infrastructure. X Implement the "transmission end" serial driver event on those platforms supporting the feature, so far only done in STM32 driver. -X I2C device driver class support and at least one implementation. -X Evaluate a modified I2C API where the synchronous mode is default and the - callback mode optional. This would allow a portable I2C driver based on - a GPT instance. - - Software I2C implementation. - Add a CH_THREAD macro for threads declaration in order to hide compiler-specific optimizations for thread functions. All demos will have to be updated. - LPC17xx support. - -Within 2.x.x -X File System infrastructure. - Test suite overhaul, the API should be more generic in order to be used with different subsystems and not just the kernel. - Reduce number of demos globally, add demos to a repository or on web site. -- cgit v1.2.3 From 538f257a6710eebea358e12845ae241437d70031 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 09:22:34 +0000 Subject: New build system for GCC ARM ports. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3428 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_LPC_P2148/board.mk | 7 +- demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile | 6 +- demos/ARM7-AT91SAM7S-GCC/Makefile | 6 +- demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile | 6 +- demos/ARM7-AT91SAM7X-GCC/Makefile | 6 +- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 6 +- demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 6 +- demos/ARM7-LPC214x-FATFS-GCC/Makefile | 6 +- demos/ARM7-LPC214x-G++/Makefile | 6 +- demos/ARM7-LPC214x-GCC/Makefile | 6 +- demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile | 6 +- demos/ARMCM3-GENERIC-KERNEL/Makefile | 6 +- demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile | 6 +- demos/ARMCM3-STM32F100-DISCOVERY/Makefile | 6 +- demos/ARMCM3-STM32F103-FATFS/Makefile | 6 +- demos/ARMCM3-STM32F103-G++/Makefile | 6 +- demos/ARMCM3-STM32F103/Makefile | 6 +- demos/ARMCM3-STM32F103ZG-FATFS/Makefile | 6 +- demos/ARMCM3-STM32F107/Makefile | 6 +- demos/ARMCM3-STM32L152-DISCOVERY/Makefile | 6 +- os/ports/GCC/ARM/AT91SAM7/port.mk | 2 - os/ports/GCC/ARM/LPC214x/port.mk | 2 - os/ports/GCC/ARM/rules.mk | 173 ++++++++++++++++++++---------- os/ports/GCC/ARMCMx/rules.mk | 173 ++++++++++++++++++++---------- readme.txt | 5 + testhal/LPC11xx/IRQ_STORM/Makefile | 6 +- testhal/LPC13xx/IRQ_STORM/Makefile | 6 +- testhal/STM32F1xx/ADC/Makefile | 6 +- testhal/STM32F1xx/CAN/Makefile | 6 +- testhal/STM32F1xx/EXT/Makefile | 6 +- testhal/STM32F1xx/EXT_WAKEUP/Makefile | 6 +- testhal/STM32F1xx/GPT/Makefile | 6 +- testhal/STM32F1xx/I2C/Makefile | 6 +- testhal/STM32F1xx/IRQ_STORM/Makefile | 6 +- testhal/STM32F1xx/MAC/Makefile | 6 +- testhal/STM32F1xx/PWM-ICU/Makefile | 6 +- testhal/STM32F1xx/RTC/Makefile | 6 +- testhal/STM32F1xx/SDC/Makefile | 6 +- testhal/STM32F1xx/SPI/Makefile | 6 +- testhal/STM32F1xx/UART/Makefile | 6 +- testhal/STM32F1xx/USB_CDC/Makefile | 6 +- testhal/STM32F1xx/USB_MSC/Makefile | 6 +- testhal/STM32L1xx/ADC/Makefile | 6 +- testhal/STM32L1xx/EXT/Makefile | 6 +- testhal/STM32L1xx/GPT/Makefile | 6 +- testhal/STM32L1xx/IRQ_STORM/Makefile | 6 +- testhal/STM32L1xx/PWM-ICU/Makefile | 6 +- testhal/STM32L1xx/SPI/Makefile | 6 +- testhal/STM32L1xx/UART/Makefile | 6 +- todo.txt | 2 +- 50 files changed, 371 insertions(+), 251 deletions(-) diff --git a/boards/OLIMEX_LPC_P2148/board.mk b/boards/OLIMEX_LPC_P2148/board.mk index d41ed5dd4..5d0937e6d 100644 --- a/boards/OLIMEX_LPC_P2148/board.mk +++ b/boards/OLIMEX_LPC_P2148/board.mk @@ -1,8 +1,5 @@ -# Board directory path -BOARDPATH = ${CHIBIOS}/boards/OLIMEX_LPC_P2148/ - # List of all the mandatory board related files. -BOARDSRC = ${BOARDPATH}/board.c +BOARDSRC = ${CHIBIOS}/boards/OLIMEX_LPC_P2148/board.c # Required include directories -BOARDINC = ${BOARDPATH} +BOARDINC = ${CHIBIOS}/boards/OLIMEX_LPC_P2148 diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile index 2a2c9e910..adc817ee5 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = no endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARM7-AT91SAM7S-GCC/Makefile b/demos/ARM7-AT91SAM7S-GCC/Makefile index fb169d6e1..4b9b64dac 100644 --- a/demos/ARM7-AT91SAM7S-GCC/Makefile +++ b/demos/ARM7-AT91SAM7S-GCC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = no endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile index 4b8fc0650..fa7345ac3 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = no endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 2fae31137..02aef99ab 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = no endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index 3f1aaa275..1ec4e05ff 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = no endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile index c1724acc9..5ce1c763c 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = no endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARM7-LPC214x-FATFS-GCC/Makefile b/demos/ARM7-LPC214x-FATFS-GCC/Makefile index bb3b93ed4..79373b307 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/Makefile +++ b/demos/ARM7-LPC214x-FATFS-GCC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = no endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 5d5723568..58fda12e8 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = no endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 67116791e..521670bde 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = no endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile b/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile index 8f455c75f..780883687 100644 --- a/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM3-GENERIC-KERNEL/Makefile b/demos/ARMCM3-GENERIC-KERNEL/Makefile index 358d3474e..18ba489eb 100644 --- a/demos/ARMCM3-GENERIC-KERNEL/Makefile +++ b/demos/ARMCM3-GENERIC-KERNEL/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile b/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile index f544b4f57..e54b4243c 100644 --- a/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/Makefile b/demos/ARMCM3-STM32F100-DISCOVERY/Makefile index b34f9edf1..9d97a1866 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/Makefile +++ b/demos/ARMCM3-STM32F100-DISCOVERY/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM3-STM32F103-FATFS/Makefile b/demos/ARMCM3-STM32F103-FATFS/Makefile index 0d31e021a..9aeb9d4e4 100644 --- a/demos/ARMCM3-STM32F103-FATFS/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM3-STM32F103-G++/Makefile b/demos/ARMCM3-STM32F103-G++/Makefile index e88957c87..6a7b3f97e 100644 --- a/demos/ARMCM3-STM32F103-G++/Makefile +++ b/demos/ARMCM3-STM32F103-G++/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM3-STM32F103/Makefile b/demos/ARMCM3-STM32F103/Makefile index 4d4ba0246..7d9fd52f6 100644 --- a/demos/ARMCM3-STM32F103/Makefile +++ b/demos/ARMCM3-STM32F103/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/Makefile b/demos/ARMCM3-STM32F103ZG-FATFS/Makefile index 2485c272c..52fb87144 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/Makefile +++ b/demos/ARMCM3-STM32F103ZG-FATFS/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM3-STM32F107/Makefile b/demos/ARMCM3-STM32F107/Makefile index 90607b250..17d3bc855 100644 --- a/demos/ARMCM3-STM32F107/Makefile +++ b/demos/ARMCM3-STM32F107/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/Makefile b/demos/ARMCM3-STM32L152-DISCOVERY/Makefile index 603ceb433..35f22d9d6 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/Makefile +++ b/demos/ARMCM3-STM32L152-DISCOVERY/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/os/ports/GCC/ARM/AT91SAM7/port.mk b/os/ports/GCC/ARM/AT91SAM7/port.mk index e28d9b78e..2cafd01aa 100644 --- a/os/ports/GCC/ARM/AT91SAM7/port.mk +++ b/os/ports/GCC/ARM/AT91SAM7/port.mk @@ -5,9 +5,7 @@ PORTASM = ${CHIBIOS}/os/ports/GCC/ARM/crt0.s \ ${CHIBIOS}/os/ports/GCC/ARM/chcoreasm.s \ ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7/vectors.s - PORTINC = ${CHIBIOS}/os/ports/GCC/ARM \ ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7 PORTLD = ${CHIBIOS}/os/ports/GCC/ARM/AT91SAM7/ld - diff --git a/os/ports/GCC/ARM/LPC214x/port.mk b/os/ports/GCC/ARM/LPC214x/port.mk index 1fcd858e5..339f1d66a 100644 --- a/os/ports/GCC/ARM/LPC214x/port.mk +++ b/os/ports/GCC/ARM/LPC214x/port.mk @@ -5,9 +5,7 @@ PORTASM = ${CHIBIOS}/os/ports/GCC/ARM/crt0.s \ ${CHIBIOS}/os/ports/GCC/ARM/chcoreasm.s \ ${CHIBIOS}/os/ports/GCC/ARM/LPC214x/vectors.s - PORTINC = ${CHIBIOS}/os/ports/GCC/ARM \ ${CHIBIOS}/os/ports/GCC/ARM/LPC214x PORTLD = ${CHIBIOS}/os/ports/GCC/ARM/LPC214x/ld - diff --git a/os/ports/GCC/ARM/rules.mk b/os/ports/GCC/ARM/rules.mk index 71aec3a35..e63e7c373 100644 --- a/os/ports/GCC/ARM/rules.mk +++ b/os/ports/GCC/ARM/rules.mk @@ -1,26 +1,23 @@ # ARM7/9 common makefile scripts and rules. -# Output -OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp +# Output directory and files ifeq ($(BUILDDIR),) - BUILDDIR = . - CLEANDIR = -else - CLEANDIR = $(BUILDDIR) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build endif -ENSUREBUILDDIR = $(shell test -d $(BUILDDIR) || mkdir $(BUILDDIR)) +OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp # Automatic compiler options OPT = $(USE_OPT) CPPOPT = $(USE_CPPOPT) -ifeq ($(USE_CURRP_CACHING),yes) - OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' -endif ifeq ($(USE_LINK_GC),yes) OPT += -ffunction-sections -fdata-sections endif -# Source files groups +# Source files groups and paths ifeq ($(USE_THUMB),yes) TCSRC += $(CSRC) TCPPSRC += $(CPPSRC) @@ -28,35 +25,39 @@ else ACSRC += $(CSRC) ACPPSRC += $(CPPSRC) endif -ASRC = $(ACSRC)$(ACPPSRC) -TSRC = $(TCSRC)$(TCPPSRC) -SRC = $(ASRC)$(TSRC) +ASRC = $(ACSRC) $(ACPPSRC) +TSRC = $(TCSRC) $(TCPPSRC) +SRCPATHS = $(sort $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) + +# Various directories +OBJDIR = $(BUILDDIR)/obj +LSTDIR = $(BUILDDIR)/lst # Object files groups -ACOBJS = $(ACSRC:.c=.o) -ACPPOBJS = $(ACPPSRC:.cpp=.o) -TCOBJS = $(TCSRC:.c=.o) -TCPPOBJS = $(TCPPSRC:.cpp=.o) -ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) +ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) +ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) +TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) +TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) +ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) # Paths -IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) # Macros -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) # Libs -LIBS = $(DLIBS) $(ULIBS) +LIBS = $(DLIBS) $(ULIBS) # Various settings -MCFLAGS = -mcpu=$(MCU) -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS) +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) ifeq ($(USE_LINK_GC),yes) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) else @@ -65,80 +66,140 @@ endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) - CFLAGS += -DTHUMB_PRESENT + CFLAGS += -DTHUMB_PRESENT CPPFLAGS += -DTHUMB_PRESENT - ASFLAGS += -DTHUMB_PRESENT + ASFLAGS += -DTHUMB_PRESENT ifneq ($(ASRC),) # Mixed ARM and THUMB mode. - CFLAGS += -mthumb-interwork + CFLAGS += -mthumb-interwork CPPFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork else # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb - LDFLAGS += -mno-thumb-interwork -mthumb + ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb + LDFLAGS += -mno-thumb-interwork -mthumb endif else # Pure ARM mode - CFLAGS += -mno-thumb-interwork + CFLAGS += -mno-thumb-interwork CPPFLAGS += -mno-thumb-interwork - ASFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork + ASFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information -CFLAGS += -MD -MP -MF .dep/$(@F).d +CFLAGS += -MD -MP -MF .dep/$(@F).d CPPFLAGS += -MD -MP -MF .dep/$(@F).d +# Paths where to search for sources +VPATH = $(SRCPATHS) + # # Makefile rules # -all: $(ENSUREBUILDDIR) $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK +all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK MAKE_ALL_RULE_HOOK: -$(ACPPOBJS) : %.o : %.cpp +$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR) + +$(BUILDDIR): + @echo $(SRCPATHS) + mkdir $(BUILDDIR) + +$(OBJDIR): + mkdir $(OBJDIR) + +$(LSTDIR): + mkdir $(LSTDIR) + +$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ +endif -$(TCPPOBJS) : %.o : %.cpp +$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ +endif -$(ACOBJS) : %.o : %.c +$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ +endif -$(TCOBJS) : %.o : %.c +$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ +endif -$(ASMOBJS) : %.o : %.s +$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ +endif -%elf: $(OBJS) +%.elf: $(OBJS) $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +else + @echo Linking $@ + @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +endif -%hex: %elf +%.hex: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) $(HEX) $< $@ +else + @echo Creating $@ + @$(HEX) $< $@ +endif -%bin: %elf +%.bin: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) $(BIN) $< $@ +else + @echo Creating $@ + @$(BIN) $< $@ +endif -%dmp: %elf +%.dmp: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) $(OD) $(ODFLAGS) $< > $@ +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo Done +endif clean: - -rm -f $(OBJS) - -rm -f $(ACSRC:.c=.lst) $(TCSRC:.c=.lst) $(ACPPSRC:.cpp=.lst) $(TCPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst) - -rm -f $(OUTFILES) $(BUILDDIR)/$(PROJECT).map - -rm -fR .dep $(CLEANDIR) + @echo Cleaning + -rm -fR .dep $(BUILDDIR) + @echo Done # # Include the dependency files, should be the last of the makefile diff --git a/os/ports/GCC/ARMCMx/rules.mk b/os/ports/GCC/ARMCMx/rules.mk index 1a25db247..1fc867931 100644 --- a/os/ports/GCC/ARMCMx/rules.mk +++ b/os/ports/GCC/ARMCMx/rules.mk @@ -1,26 +1,23 @@ # ARM Cortex-Mx common makefile scripts and rules. -# Output -OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp +# Output directory and files ifeq ($(BUILDDIR),) - BUILDDIR = . - CLEANDIR = -else - CLEANDIR = $(BUILDDIR) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build endif -ENSUREBUILDDIR = $(shell test -d $(BUILDDIR) || mkdir $(BUILDDIR)) +OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp # Automatic compiler options OPT = $(USE_OPT) CPPOPT = $(USE_CPPOPT) -ifeq ($(USE_CURRP_CACHING),yes) - OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' -endif ifeq ($(USE_LINK_GC),yes) OPT += -ffunction-sections -fdata-sections endif -# Source files groups +# Source files groups and paths ifeq ($(USE_THUMB),yes) TCSRC += $(CSRC) TCPPSRC += $(CPPSRC) @@ -28,35 +25,39 @@ else ACSRC += $(CSRC) ACPPSRC += $(CPPSRC) endif -ASRC = $(ACSRC)$(ACPPSRC) -TSRC = $(TCSRC)$(TCPPSRC) -SRC = $(ASRC)$(TSRC) +ASRC = $(ACSRC) $(ACPPSRC) +TSRC = $(TCSRC) $(TCPPSRC) +SRCPATHS = $(sort $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) + +# Various directories +OBJDIR = $(BUILDDIR)/obj +LSTDIR = $(BUILDDIR)/lst # Object files groups -ACOBJS = $(ACSRC:.c=.o) -ACPPOBJS = $(ACPPSRC:.cpp=.o) -TCOBJS = $(TCSRC:.c=.o) -TCPPOBJS = $(TCPPSRC:.cpp=.o) -ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) +ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) +ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) +TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) +TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) +ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) # Paths -IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) -LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) # Macros -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) # Libs -LIBS = $(DLIBS) $(ULIBS) +LIBS = $(DLIBS) $(ULIBS) # Various settings -MCFLAGS = -mcpu=$(MCU) -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS) +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) ifeq ($(USE_LINK_GC),yes) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) else @@ -65,80 +66,140 @@ endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) - CFLAGS += -DTHUMB_PRESENT + CFLAGS += -DTHUMB_PRESENT CPPFLAGS += -DTHUMB_PRESENT - ASFLAGS += -DTHUMB_PRESENT + ASFLAGS += -DTHUMB_PRESENT ifneq ($(ASRC),) # Mixed ARM and THUMB mode. - CFLAGS += -mthumb-interwork + CFLAGS += -mthumb-interwork CPPFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork else # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING - ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb - LDFLAGS += -mno-thumb-interwork -mthumb + ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb + LDFLAGS += -mno-thumb-interwork -mthumb endif else # Pure ARM mode - CFLAGS += -mno-thumb-interwork + CFLAGS += -mno-thumb-interwork CPPFLAGS += -mno-thumb-interwork - ASFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork + ASFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information -CFLAGS += -MD -MP -MF .dep/$(@F).d +CFLAGS += -MD -MP -MF .dep/$(@F).d CPPFLAGS += -MD -MP -MF .dep/$(@F).d +# Paths where to search for sources +VPATH = $(SRCPATHS) + # # Makefile rules # -all: $(ENSUREBUILDDIR) $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK +all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK MAKE_ALL_RULE_HOOK: -$(ACPPOBJS) : %.o : %.cpp +$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR) + +$(BUILDDIR): + @echo $(SRCPATHS) + mkdir $(BUILDDIR) + +$(OBJDIR): + mkdir $(OBJDIR) + +$(LSTDIR): + mkdir $(LSTDIR) + +$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ +endif -$(TCPPOBJS) : %.o : %.cpp +$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ +endif -$(ACOBJS) : %.o : %.c +$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ +endif -$(TCOBJS) : %.o : %.c +$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ +endif -$(ASMOBJS) : %.o : %.s +$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ +else + @echo Compiling $< + @$(AS) -c $(ASFLAGS) -I . $(IINCDIR) $< -o $@ +endif -%elf: $(OBJS) +%.elf: $(OBJS) $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +else + @echo Linking $@ + @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +endif -%hex: %elf +%.hex: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) $(HEX) $< $@ +else + @echo Creating $@ + @$(HEX) $< $@ +endif -%bin: %elf +%.bin: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) $(BIN) $< $@ +else + @echo Creating $@ + @$(BIN) $< $@ +endif -%dmp: %elf +%.dmp: %.elf $(LDSCRIPT) +ifeq ($(USE_VERBOSE_COMPILE),yes) $(OD) $(ODFLAGS) $< > $@ +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo Done +endif clean: - -rm -f $(OBJS) - -rm -f $(ACSRC:.c=.lst) $(TCSRC:.c=.lst) $(ACPPSRC:.cpp=.lst) $(TCPPSRC:.cpp=.lst) $(ASMSRC:.s=.lst) - -rm -f $(OUTFILES) $(BUILDDIR)/$(PROJECT).map - -rm -fR .dep $(CLEANDIR) + @echo Cleaning + -rm -fR .dep $(BUILDDIR) + @echo Done # # Include the dependency files, should be the last of the makefile diff --git a/readme.txt b/readme.txt index 155ae8506..ed4ea9a95 100644 --- a/readme.txt +++ b/readme.txt @@ -77,6 +77,11 @@ - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). - NEW: Added memory copy functionality to the STM32 DMA driver. +- NEW: Implemented new makefile system for ARM GCC ports, now objects, + listings and out files are generated into a "build" directory and not + together with sources. Also implemented a simplified output log mode. + Now makefiles and load stript files are requirements and trigger a + rebuild if touched. *** 2.3.3 *** - FIX: Fixed uninitialized variable in STM32 PWM and ICU drivers (bug 3413558). diff --git a/testhal/LPC11xx/IRQ_STORM/Makefile b/testhal/LPC11xx/IRQ_STORM/Makefile index d5c1b4cbd..d81cc6208 100644 --- a/testhal/LPC11xx/IRQ_STORM/Makefile +++ b/testhal/LPC11xx/IRQ_STORM/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/LPC13xx/IRQ_STORM/Makefile b/testhal/LPC13xx/IRQ_STORM/Makefile index cb53a7761..ce797ce3e 100644 --- a/testhal/LPC13xx/IRQ_STORM/Makefile +++ b/testhal/LPC13xx/IRQ_STORM/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/ADC/Makefile b/testhal/STM32F1xx/ADC/Makefile index 9ae228410..a225f325c 100644 --- a/testhal/STM32F1xx/ADC/Makefile +++ b/testhal/STM32F1xx/ADC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/CAN/Makefile b/testhal/STM32F1xx/CAN/Makefile index 9ae228410..a225f325c 100644 --- a/testhal/STM32F1xx/CAN/Makefile +++ b/testhal/STM32F1xx/CAN/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/EXT/Makefile b/testhal/STM32F1xx/EXT/Makefile index 32cec391d..ef8dc610b 100644 --- a/testhal/STM32F1xx/EXT/Makefile +++ b/testhal/STM32F1xx/EXT/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/EXT_WAKEUP/Makefile b/testhal/STM32F1xx/EXT_WAKEUP/Makefile index 96cfa2e2e..f81417481 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/Makefile +++ b/testhal/STM32F1xx/EXT_WAKEUP/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/GPT/Makefile b/testhal/STM32F1xx/GPT/Makefile index 9ae228410..a225f325c 100644 --- a/testhal/STM32F1xx/GPT/Makefile +++ b/testhal/STM32F1xx/GPT/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/I2C/Makefile b/testhal/STM32F1xx/I2C/Makefile index b8b1b0741..8bbb71015 100644 --- a/testhal/STM32F1xx/I2C/Makefile +++ b/testhal/STM32F1xx/I2C/Makefile @@ -24,9 +24,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/IRQ_STORM/Makefile b/testhal/STM32F1xx/IRQ_STORM/Makefile index 9ae228410..a225f325c 100644 --- a/testhal/STM32F1xx/IRQ_STORM/Makefile +++ b/testhal/STM32F1xx/IRQ_STORM/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/MAC/Makefile b/testhal/STM32F1xx/MAC/Makefile index 7712f2057..f493e4a2d 100644 --- a/testhal/STM32F1xx/MAC/Makefile +++ b/testhal/STM32F1xx/MAC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/PWM-ICU/Makefile b/testhal/STM32F1xx/PWM-ICU/Makefile index 9ae228410..a225f325c 100644 --- a/testhal/STM32F1xx/PWM-ICU/Makefile +++ b/testhal/STM32F1xx/PWM-ICU/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/RTC/Makefile b/testhal/STM32F1xx/RTC/Makefile index 7748841bd..fa40730f9 100644 --- a/testhal/STM32F1xx/RTC/Makefile +++ b/testhal/STM32F1xx/RTC/Makefile @@ -34,9 +34,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/SDC/Makefile b/testhal/STM32F1xx/SDC/Makefile index 71c4ec604..f1195d4b0 100644 --- a/testhal/STM32F1xx/SDC/Makefile +++ b/testhal/STM32F1xx/SDC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/SPI/Makefile b/testhal/STM32F1xx/SPI/Makefile index 9ae228410..a225f325c 100644 --- a/testhal/STM32F1xx/SPI/Makefile +++ b/testhal/STM32F1xx/SPI/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/UART/Makefile b/testhal/STM32F1xx/UART/Makefile index 9ae228410..a225f325c 100644 --- a/testhal/STM32F1xx/UART/Makefile +++ b/testhal/STM32F1xx/UART/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/USB_CDC/Makefile b/testhal/STM32F1xx/USB_CDC/Makefile index 45218c328..ee6f94363 100644 --- a/testhal/STM32F1xx/USB_CDC/Makefile +++ b/testhal/STM32F1xx/USB_CDC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32F1xx/USB_MSC/Makefile b/testhal/STM32F1xx/USB_MSC/Makefile index 651b7b346..7c5126ccd 100644 --- a/testhal/STM32F1xx/USB_MSC/Makefile +++ b/testhal/STM32F1xx/USB_MSC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32L1xx/ADC/Makefile b/testhal/STM32L1xx/ADC/Makefile index 9209b441d..dbe1c0f78 100644 --- a/testhal/STM32L1xx/ADC/Makefile +++ b/testhal/STM32L1xx/ADC/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32L1xx/EXT/Makefile b/testhal/STM32L1xx/EXT/Makefile index 9209b441d..dbe1c0f78 100644 --- a/testhal/STM32L1xx/EXT/Makefile +++ b/testhal/STM32L1xx/EXT/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32L1xx/GPT/Makefile b/testhal/STM32L1xx/GPT/Makefile index 9209b441d..dbe1c0f78 100644 --- a/testhal/STM32L1xx/GPT/Makefile +++ b/testhal/STM32L1xx/GPT/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32L1xx/IRQ_STORM/Makefile b/testhal/STM32L1xx/IRQ_STORM/Makefile index 9209b441d..dbe1c0f78 100644 --- a/testhal/STM32L1xx/IRQ_STORM/Makefile +++ b/testhal/STM32L1xx/IRQ_STORM/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32L1xx/PWM-ICU/Makefile b/testhal/STM32L1xx/PWM-ICU/Makefile index 9209b441d..dbe1c0f78 100644 --- a/testhal/STM32L1xx/PWM-ICU/Makefile +++ b/testhal/STM32L1xx/PWM-ICU/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32L1xx/SPI/Makefile b/testhal/STM32L1xx/SPI/Makefile index 9209b441d..dbe1c0f78 100644 --- a/testhal/STM32L1xx/SPI/Makefile +++ b/testhal/STM32L1xx/SPI/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/testhal/STM32L1xx/UART/Makefile b/testhal/STM32L1xx/UART/Makefile index 9209b441d..dbe1c0f78 100644 --- a/testhal/STM32L1xx/UART/Makefile +++ b/testhal/STM32L1xx/UART/Makefile @@ -23,9 +23,9 @@ ifeq ($(USE_THUMB),) USE_THUMB = yes endif -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no endif # diff --git a/todo.txt b/todo.txt index 51f3c6795..25809a9a1 100644 --- a/todo.txt +++ b/todo.txt @@ -6,6 +6,7 @@ X = In progress, some work done. N = Decided against. Current Pipeline (2.3.x): +* Improved Makefile system. - USB driver enhancements. - USB and USB_SERIAL APIs reclassification. - Incorporate the USB bus attach/detach handling in usbStart()/usbStop(). @@ -35,7 +36,6 @@ X Implement the "transmission end" serial driver event on those platforms with different subsystems and not just the kernel. - Reduce number of demos globally, add demos to a repository or on web site. Required in order to reduce support effort. -- Improved Makefile system. - MAC driver for STM32F107. - FatFs wrapper. - New device driver models: Clock, Systick, RTC, WDG, DAC, Power Monitor. -- cgit v1.2.3 From 7e567dedc7a496257a00660a14cf3dfbc571a59c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 10:33:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3429 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/DMAv1/stm32_dma.c | 497 ------------------------------- os/hal/platforms/STM32/DMAv1/stm32_dma.h | 330 -------------------- os/hal/platforms/STM32F1xx/platform.mk | 4 +- os/hal/platforms/STM32F1xx/stm32_dma.c | 497 +++++++++++++++++++++++++++++++ os/hal/platforms/STM32F1xx/stm32_dma.h | 330 ++++++++++++++++++++ 5 files changed, 829 insertions(+), 829 deletions(-) delete mode 100644 os/hal/platforms/STM32/DMAv1/stm32_dma.c delete mode 100644 os/hal/platforms/STM32/DMAv1/stm32_dma.h create mode 100644 os/hal/platforms/STM32F1xx/stm32_dma.c create mode 100644 os/hal/platforms/STM32F1xx/stm32_dma.h diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.c b/os/hal/platforms/STM32/DMAv1/stm32_dma.c deleted file mode 100644 index 84e372c26..000000000 --- a/os/hal/platforms/STM32/DMAv1/stm32_dma.c +++ /dev/null @@ -1,497 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file DMAv1/stm32_dma.c - * @brief DMA helper driver code. - * - * @addtogroup STM32_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * IRSs when allocating streams. - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK 0x0000007F - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK 0x00000F80 - -/** - * @brief Post-reset value of the stream CCR register. - */ -#define STM32_DMA_CCR_RESET_VALUE 0x00000000 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, - {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, - {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, - {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, - {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, - {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, - {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) - {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, - {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, - {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, -#if defined(STM32F10X_CL) || defined(__DOXYGEN__) - {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, - {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, -#else /* !STM32F10X_CL */ - {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn}, - {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn}, -#endif /* !STM32F10X_CL */ -#endif /* STM32_HAS_DMA2 */ -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ - void *dma_param; /**< @brief DMA callback parameter. */ -} dma_isr_redir_t; - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/** - * @brief DMA IRQ redirectors. - */ -static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 stream 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->IFCR = STM32_DMA_ISR_MASK << 0; - if (dma_isr_redir[0].dma_func) - dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA1->IFCR = STM32_DMA_ISR_MASK << 4; - if (dma_isr_redir[1].dma_func) - dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA1->IFCR = STM32_DMA_ISR_MASK << 8; - if (dma_isr_redir[2].dma_func) - dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA1->IFCR = STM32_DMA_ISR_MASK << 12; - if (dma_isr_redir[3].dma_func) - dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA1->IFCR = STM32_DMA_ISR_MASK << 16; - if (dma_isr_redir[4].dma_func) - dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 6 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; - DMA1->IFCR = STM32_DMA_ISR_MASK << 20; - if (dma_isr_redir[5].dma_func) - dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 7 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; - DMA1->IFCR = STM32_DMA_ISR_MASK << 24; - if (dma_isr_redir[6].dma_func) - dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; - DMA2->IFCR = STM32_DMA_ISR_MASK << 0; - if (dma_isr_redir[7].dma_func) - dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; - DMA2->IFCR = STM32_DMA_ISR_MASK << 4; - if (dma_isr_redir[8].dma_func) - dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; - DMA2->IFCR = STM32_DMA_ISR_MASK << 8; - if (dma_isr_redir[9].dma_func) - dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -#if defined(STM32F10X_CL) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; - DMA2->IFCR = STM32_DMA_ISR_MASK << 12; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; - DMA2->IFCR = STM32_DMA_ISR_MASK << 16; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} -#else /* !STM32F10X_CL */ -/** - * @brief DMA2 streams 4 and 5 shared interrupt handler. - * @note This IRQ is shared between DMA2 channels 4 and 5 so it is a - * bit less efficient because an extra check. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - /* Check on channel 4.*/ - flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA2->IFCR = STM32_DMA_ISR_MASK << 12; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - } - - /* Check on channel 5.*/ - flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; - if (flags & STM32_DMA_ISR_MASK) { - DMA2->IFCR = STM32_DMA_ISR_MASK << 16; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - } - - CH_IRQ_EPILOGUE(); -} -#endif /* !STM32F10X_CL */ -#endif /* STM32_HAS_DMA2 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dma_streams_mask = 0; - for (i = 0; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].channel->CCR = 0; - dma_isr_redir[i].dma_func = NULL; - } - DMA1->IFCR = 0xFFFFFFFF; -#if STM32_HAS_DMA2 - DMA2->IFCR = 0xFFFFFFFF; -#endif -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval FALSE no error, stream taken. - * @retval TRUE error, stream already taken. - * - * @special - */ -bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - chDbgCheck(dmastp != NULL, "dmaAllocate"); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) - return TRUE; - - /* Marks the stream as allocated.*/ - dma_isr_redir[dmastp->selfindex].dma_func = func; - dma_isr_redir[dmastp->selfindex].dma_param = param; - dma_streams_mask |= (1 << dmastp->selfindex); - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) - rccEnableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) - rccEnableDMA2(FALSE); -#endif - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmaStreamClearInterrupt(dmastp); - dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; - - /* Enables the associated IRQ vector if a callback is defined.*/ - if (func != NULL) - NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); - - return FALSE; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - chDbgCheck(dmastp != NULL, "dmaRelease"); - - /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "dmaRelease(), #1", "not allocated"); - - /* Disables the associated IRQ vector.*/ - NVICDisableVector(dmastp->vector); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1 << dmastp->selfindex); - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) - rccDisableDMA1(FALSE); -#if STM32_HAS_DMA2 - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) - rccDisableDMA2(FALSE); -#endif -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.h b/os/hal/platforms/STM32/DMAv1/stm32_dma.h deleted file mode 100644 index f209898d4..000000000 --- a/os/hal/platforms/STM32/DMAv1/stm32_dma.h +++ /dev/null @@ -1,330 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file DMAv1/stm32_dma.h - * @brief DMA helper driver header. - * @note This file requires definitions from the ST header files - * stm32f10x.h or stm32l1xx.h. - * @note This driver uses the new naming convention used for the STM32F2xx - * so the "DMA channels" are referred as "DMA streams". - * - * @addtogroup STM32_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Total number of DMA streams. - * @note This is the total number of streams among all the DMA units. - */ -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -#define STM32_DMA_STREAMS 12 -#else -#define STM32_DMA_STREAMS 7 -#endif - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x0F - -/** - * @name DMA streams identifiers - * @{ - */ -#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0]) -#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1]) -#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2]) -#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3]) -#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4]) -#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5]) -#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6]) -#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[7]) -#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[8]) -#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[9]) -#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[10]) -#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[11]) -/** @} */ - -/** - * @name CR register constants common to all DMA types - */ -#define STM32_DMA_CR_EN DMA_CCR1_EN -#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE -#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE -#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE -#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) -#define STM32_DMA_CR_DIR_P2M 0 -#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR -#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM -#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC -#define STM32_DMA_CR_PINC DMA_CCR1_PINC -#define STM32_DMA_CR_MINC DMA_CCR1_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0 -#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0 -#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 -#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL -#define STM32_DMA_CR_PL(n) ((n) << 12) -/** @} */ - -/** - * @name CR register constants only found in enhanced DMA - */ -#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ -#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - */ -#define STM32_DMA_ISR_FEIF 0 -#define STM32_DMA_ISR_DMEIF 0 -#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 -#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 -#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ - volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ - uint8_t ishift; /**< @brief Bits offset in xIFCR - register. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the ISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CPAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->channel->CPAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the CMAR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->channel->CMAR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->channel->CNDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register - * - * @special - */ -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->channel->CCR = (uint32_t)(mode); \ -} - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmastp) { \ - (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ -} - -/** - * @brief Starts a memory to memory operation using the specified stream. - * @note The default transfer data mode is "byte to byte" but it can be - * changed by specifying extra options in the @p mode parameter. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value - * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN - * . - * @param[in] src source address - * @param[in] dst destination address - * @param[in] n number of data units to copy - */ -#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ - dmaStreamSetPeripheral(dmastp, src); \ - dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamGetTransactionSize(dmastp, n); \ - dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ -} - -/** - * @brief Polled wait for DMA transfer end. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post After use the stream can be released using @p dmaStreamRelease(). - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - */ -#define dmaWaitCompletion(dmastp) \ - while (((dmastp)->channel->CNDTR > 0) && \ - ((dmastp)->channel->CCR & STM32_DMA_CR_EN)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk index a73f1b4f3..5e42d1335 100644 --- a/os/hal/platforms/STM32F1xx/platform.mk +++ b/os/hal/platforms/STM32F1xx/platform.mk @@ -1,5 +1,6 @@ # List of all the STM32F1xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ @@ -13,7 +14,6 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.c b/os/hal/platforms/STM32F1xx/stm32_dma.c new file mode 100644 index 000000000..84e372c26 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/stm32_dma.c @@ -0,0 +1,497 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file DMAv1/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * IRSs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x0000007F + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x00000F80 + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, + {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, + {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, + {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, + {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, + {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, + {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn}, +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) + {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn}, + {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn}, + {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn}, +#if defined(STM32F10X_CL) || defined(__DOXYGEN__) + {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn}, + {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn}, +#else /* !STM32F10X_CL */ + {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn}, + {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn}, +#endif /* !STM32F10X_CL */ +#endif /* STM32_HAS_DMA2 */ +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 20; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 24; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +#if defined(STM32F10X_CL) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} +#else /* !STM32F10X_CL */ +/** + * @brief DMA2 streams 4 and 5 shared interrupt handler. + * @note This IRQ is shared between DMA2 channels 4 and 5 so it is a + * bit less efficient because an extra check. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + /* Check on channel 4.*/ + flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA2->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + } + + /* Check on channel 5.*/ + flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; + if (flags & STM32_DMA_ISR_MASK) { + DMA2->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* !STM32F10X_CL */ +#endif /* STM32_HAS_DMA2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->IFCR = 0xFFFFFFFF; +#if STM32_HAS_DMA2 + DMA2->IFCR = 0xFFFFFFFF; +#endif +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) + rccEnableDMA2(FALSE); +#endif + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmaStreamClearInterrupt(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + NVICDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); +#if STM32_HAS_DMA2 + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) + rccDisableDMA2(FALSE); +#endif +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h new file mode 100644 index 000000000..f209898d4 --- /dev/null +++ b/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -0,0 +1,330 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file DMAv1/stm32_dma.h + * @brief DMA helper driver header. + * @note This file requires definitions from the ST header files + * stm32f10x.h or stm32l1xx.h. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +#define STM32_DMA_STREAMS 12 +#else +#define STM32_DMA_STREAMS 7 +#endif + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0F + +/** + * @name DMA streams identifiers + * @{ + */ +#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0]) +#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1]) +#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2]) +#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3]) +#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4]) +#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5]) +#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6]) +#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[7]) +#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[8]) +#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[9]) +#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[10]) +#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[11]) +/** @} */ + +/** + * @name CR register constants common to all DMA types + */ +#define STM32_DMA_CR_EN DMA_CCR1_EN +#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC +#define STM32_DMA_CR_PINC DMA_CCR1_PINC +#define STM32_DMA_CR_MINC DMA_CCR1_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 +#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL +#define STM32_DMA_CR_PL(n) ((n) << 12) +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + */ +#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + */ +#define STM32_DMA_ISR_FEIF 0 +#define STM32_DMA_ISR_DMEIF 0 +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamGetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) \ + while (((dmastp)->channel->CNDTR > 0) && \ + ((dmastp)->channel->CCR & STM32_DMA_CR_EN)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ -- cgit v1.2.3 From c5086c0b0c99d87f9f8b3142b8e084c84123a23e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 10:34:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3430 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/DMAv2/stm32_dma.c | 541 ------------------------------- os/hal/platforms/STM32/DMAv2/stm32_dma.h | 327 ------------------- os/hal/platforms/STM32F2xx/platform.mk | 3 +- os/hal/platforms/STM32F2xx/stm32_dma.c | 541 +++++++++++++++++++++++++++++++ os/hal/platforms/STM32F2xx/stm32_dma.h | 327 +++++++++++++++++++ 5 files changed, 869 insertions(+), 870 deletions(-) delete mode 100644 os/hal/platforms/STM32/DMAv2/stm32_dma.c delete mode 100644 os/hal/platforms/STM32/DMAv2/stm32_dma.h create mode 100644 os/hal/platforms/STM32F2xx/stm32_dma.c create mode 100644 os/hal/platforms/STM32F2xx/stm32_dma.h diff --git a/os/hal/platforms/STM32/DMAv2/stm32_dma.c b/os/hal/platforms/STM32/DMAv2/stm32_dma.c deleted file mode 100644 index 70f412083..000000000 --- a/os/hal/platforms/STM32/DMAv2/stm32_dma.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file DMAv2/stm32_dma.c - * @brief Enhanced DMA helper driver code. - * - * @addtogroup STM32_DMA - * @details DMA sharing helper driver. In the STM32 the DMA streams are a - * shared resource, this driver allows to allocate and free DMA - * streams at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * IRSs when allocating streams. - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Mask of the DMA1 streams in @p dma_streams_mask. - */ -#define STM32_DMA1_STREAMS_MASK 0x000000FF - -/** - * @brief Mask of the DMA2 streams in @p dma_streams_mask. - */ -#define STM32_DMA2_STREAMS_MASK 0x0000FF00 - -/** - * @brief Post-reset value of the stream CR register. - */ -#define STM32_DMA_CR_RESET_VALUE 0x00000000 - -/** - * @brief Post-reset value of the stream FCR register. - */ -#define STM32_DMA_FCR_RESET_VALUE 0x00000021 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief DMA streams descriptors. - * @details This table keeps the association between an unique stream - * identifier and the involved physical registers. - * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc. - */ -const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {0, DMA1, DMA1_Stream0, &DMA1->LIFCR, 0}, - {1, DMA1, DMA1_Stream1, &DMA1->LIFCR, 6}, - {2, DMA1, DMA1_Stream2, &DMA1->LIFCR, 16}, - {3, DMA1, DMA1_Stream3, &DMA1->LIFCR, 22}, - {4, DMA1, DMA1_Stream4, &DMA1->HIFCR, 0}, - {5, DMA1, DMA1_Stream5, &DMA1->HIFCR, 6}, - {6, DMA1, DMA1_Stream6, &DMA1->HIFCR, 16}, - {7, DMA1, DMA1_Stream7, &DMA1->HIFCR, 22}, - {8, DMA2, DMA2_Stream0, &DMA2->LIFCR, 0}, - {9, DMA2, DMA2_Stream1, &DMA2->LIFCR, 6}, - {10, DMA2, DMA2_Stream2, &DMA2->LIFCR, 16}, - {11, DMA2, DMA2_Stream3, &DMA2->LIFCR, 22}, - {12, DMA2, DMA2_Stream4, &DMA2->HIFCR, 0}, - {13, DMA2, DMA2_Stream5, &DMA2->HIFCR, 6}, - {14, DMA2, DMA2_Stream6, &DMA2->HIFCR, 16}, - {15, DMA2, DMA2_Stream7, &DMA2->HIFCR, 22}, -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dma_func; - void *dma_param; -} dma_isr_redir_t; - -/** - * @brief Mask of the allocated streams. - */ -static uint32_t dma_streams_mask; - -/** - * @brief DMA IRQ redirectors. - */ -static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 stream 0 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = STM32_DMA_ISR_MASK << 0; - if (dma_isr_redir[0].dma_func) - dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = STM32_DMA_ISR_MASK << 6; - if (dma_isr_redir[1].dma_func) - dma_isr_redir[1].dma_func(dma_isr_redir[0].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = STM32_DMA_ISR_MASK << 16; - if (dma_isr_redir[2].dma_func) - dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK; - DMA1->LIFCR = STM32_DMA_ISR_MASK << 22; - if (dma_isr_redir[3].dma_func) - dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = STM32_DMA_ISR_MASK << 0; - if (dma_isr_redir[4].dma_func) - dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = STM32_DMA_ISR_MASK << 6; - if (dma_isr_redir[5].dma_func) - dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 6 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = STM32_DMA_ISR_MASK << 16; - if (dma_isr_redir[6].dma_func) - dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 stream 7 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK; - DMA1->HIFCR = STM32_DMA_ISR_MASK << 22; - if (dma_isr_redir[7].dma_func) - dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 0 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = STM32_DMA_ISR_MASK << 0; - if (dma_isr_redir[8].dma_func) - dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = STM32_DMA_ISR_MASK << 6; - if (dma_isr_redir[9].dma_func) - dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = STM32_DMA_ISR_MASK << 16; - if (dma_isr_redir[10].dma_func) - dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK; - DMA2->LIFCR = STM32_DMA_ISR_MASK << 22; - if (dma_isr_redir[11].dma_func) - dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = STM32_DMA_ISR_MASK << 0; - if (dma_isr_redir[12].dma_func) - dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = STM32_DMA_ISR_MASK << 6; - if (dma_isr_redir[13].dma_func) - dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 6 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = STM32_DMA_ISR_MASK << 16; - if (dma_isr_redir[14].dma_func) - dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 stream 7 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) { - uint32_t flags; - - CH_IRQ_PROLOGUE(); - - flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK; - DMA2->HIFCR = STM32_DMA_ISR_MASK << 22; - if (dma_isr_redir[15].dma_func) - dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags); - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dma_streams_mask = 0; - for (i = 0; i < STM32_DMA_STREAMS; i++) { - _stm32_dma_streams[i].stream->CR = 0; - dma_isr_redir[i].dma_func = NULL; - } - DMA1->LIFCR = 0xFFFFFFFF; - DMA1->HIFCR = 0xFFFFFFFF; - DMA2->LIFCR = 0xFFFFFFFF; - DMA2->HIFCR = 0xFFFFFFFF; -} - -/** - * @brief Allocates a DMA stream. - * @details The stream is allocated and, if required, the DMA clock enabled. - * The function also enables the IRQ vector associated to the stream - * and initializes its priority. - * @pre The stream must not be already in use or an error is returned. - * @post The stream is allocated and the default ISR handler redirected - * to the specified function. - * @post The stream ISR vector is enabled and its priority configured. - * @post The stream must be freed using @p dmaStreamRelease() before it can - * be reused with another peripheral. - * @post The stream is in its post-reset state. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] priority IRQ priority mask for the DMA stream - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval FALSE no error, stream taken. - * @retval TRUE error, stream already taken. - * - * @special - */ -bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - - chDbgCheck(dmastp != NULL, "dmaAllocate"); - - /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & dmastp->mask) != 0) - return TRUE; - - /* Marks the stream as allocated.*/ - dma_isr_redir[dmastp->selfindex].dma_func = func; - dma_isr_redir[dmastp->selfindex].dma_param = param; - dma_streams_mask |= (1 << dmastp->selfindex); - - /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) { - RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; - RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA1LPEN; - } - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) { - RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; - RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA2LPEN; - } - - /* Putting the stream in a safe state.*/ - dmaStreamDisable(dmastp); - dmaStreamClearInterrupt(dmastp); - dmastp->channel->CR = STM32_DMA_CR_RESET_VALUE; - dmastp->channel->FCR = STM32_DMA_FCR_RESET_VALUE; - - /* Enables the associated IRQ vector if a callback is defined.*/ - if (func != NULL) - NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); - - return FALSE; -} - -/** - * @brief Releases a DMA stream. - * @details The stream is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated stream is an illegal operation - * and is trapped if assertions are enabled. - * @pre The stream must have been allocated using @p dmaStreamAllocate(). - * @post The stream is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - - chDbgCheck(dmastp != NULL, "dmaRelease"); - - /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & dmastp->mask) != 0, - "dmaRelease(), #1", "not allocated"); - - /* Disables the associated IRQ vector.*/ - NVICDisableVector(dmastp->vector); - - /* Marks the stream as not allocated.*/ - dma_streams_mask &= ~(1 << dmastp->selfindex); - - /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) { - RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA1EN; - RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA1LPEN; - } - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) { - RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2EN; - RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA2LPEN; - } -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/os/hal/platforms/STM32/DMAv2/stm32_dma.h b/os/hal/platforms/STM32/DMAv2/stm32_dma.h deleted file mode 100644 index af18497fc..000000000 --- a/os/hal/platforms/STM32/DMAv2/stm32_dma.h +++ /dev/null @@ -1,327 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file DMAv2/stm32_dma.h - * @brief Enhanced-DMA helper driver header. - * @note This file requires definitions from the ST STM32F2xx header file - * stm32f2xx.h. - * - * @addtogroup STM32_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Total number of DMA streams. - * @note This is the total number of streams among all the DMA units. - */ -#define STM32_DMA_STREAMS 16 - -/** - * @brief Mask of the ISR bits passed to the DMA callback functions. - */ -#define STM32_DMA_ISR_MASK 0x3D - -/** - * @name DMA streams identifiers - * @{ - */ -#define STM32_DMA1_STREAM0 (&_stm32_dma_streams[0]) -#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[1]) -#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[2]) -#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[3]) -#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[4]) -#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[5]) -#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[6]) -#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[7]) -#define STM32_DMA2_STREAM0 (&_stm32_dma_streams[8]) -#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[9]) -#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[10]) -#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[11]) -#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[12]) -#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[13]) -#define STM32_DMA2_STREAM6 (&_stm32_dma_streams[14]) -#define STM32_DMA2_STREAM7 (&_stm32_dma_streams[15]) -/** @} */ - -/** - * @name CR register constants common to all DMA types - */ -#define STM32_DMA_CR_EN DMA_SxCR_EN -#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE -#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE -#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE -#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR -#define STM32_DMA_CR_DIR_P2M 0 -#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0 -#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1 -#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC -#define STM32_DMA_CR_PINC DMA_SxCR_PINC -#define STM32_DMA_CR_MINC DMA_SxCR_MINC -#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE -#define STM32_DMA_CR_PSIZE_BYTE 0 -#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0 -#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1 -#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE -#define STM32_DMA_CR_MSIZE_BYTE 0 -#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0 -#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1 -#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL -#define STM32_DMA_CR_PL(n) ((n) << 16) -/** @} */ - -/** - * @name CR register constants only found in STM32F2xx - */ -#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE -#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL -#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS -#define STM32_DMA_CR_DBM DMA_SxCR_DBM -#define STM32_DMA_CR_CT DMA_SxCR_CT -#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST -#define STM32_DMA_CR_PBURST_SINGLE 0 -#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0 -#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1 -#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) -#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST -#define STM32_DMA_CR_MBURST_SINGLE 0 -#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0 -#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1 -#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) -#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL -#define STM32_DMA_CR_CHSEL(n) ((n) << 25) -/** @} */ - -/** - * @name FCR register constants only found in STM32F2xx - */ -#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE -#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS -#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS -#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH -#define STM32_DMA_FCR_FTH_1Q 0 -#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0 -#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1 -#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1) -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - */ -#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0 -#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0 -#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0 -#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0 -#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA stream descriptor structure. - */ -typedef struct { - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ - volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ - uint8_t ishift; /**< @brief Bits offset in xIFCR - register. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ -} stm32_dma_stream_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the xISR register, the bits - * are aligned to bit zero - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Associates a peripheral data register to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the PAR register - * - * @special - */ -#define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->stream->PAR = (uint32_t)(addr); \ -} - -/** - * @brief Associates a memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the M0AR register - * - * @special - */ -#define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->stream->M0AR = (uint32_t)(addr); \ -} - -/** - * @brief Associates an alternate memory destination to a DMA stream. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] addr value to be written in the M1AR register - * - * @special - */ -#define dmaStreamSetMemory1(dmastp, addr) { \ - (dmastp)->stream->M1AR = (uint32_t)(addr); \ -} - -/** - * @brief Sets the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] size value to be written in the CNDTR register - * - * @special - */ -#define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->stream->NDTR = (uint32_t)(size); \ -} - -/** - * @brief Returns the number of transfers to be performed. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @return The number of transfers to be performed. - * - * @special - */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR)) - -/** - * @brief Programs the stream mode settings. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the CR register - * - * @special - */ -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->stream->CR = (uint32_t)(mode); \ -} - -/** - * @brief Programs the stream FIFO settings. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * @param[in] mode value to be written in the FCR register - * - * @special - */ -#define dmaStreamSetFIFO(dmastp, mode) { \ - (dmastp)->stream->FCR = (uint32_t)(mode); \ -} - -/** - * @brief DMA stream enable. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmachp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamEnable(dmachp) { \ - (dmastp)->stream->CR |= STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream disable. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \ -} - -/** - * @brief DMA stream interrupt sources clear. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmastp pointer to a stm32_dma_stream_t structure - * - * @special - */ -#define dmaStreamClearInterrupt(dmastp) { \ - *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); - void dmaStreamRelease(const stm32_dma_stream_t *dmastp); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32F2xx/platform.mk b/os/hal/platforms/STM32F2xx/platform.mk index c1502009f..64365e897 100644 --- a/os/hal/platforms/STM32F2xx/platform.mk +++ b/os/hal/platforms/STM32F2xx/platform.mk @@ -9,5 +9,4 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/hal_lld.c \ # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F2xx \ ${CHIBIOS}/os/hal/platforms/STM32 \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ - ${CHIBIOS}/os/hal/platforms/STM32/DMAv2 + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 diff --git a/os/hal/platforms/STM32F2xx/stm32_dma.c b/os/hal/platforms/STM32F2xx/stm32_dma.c new file mode 100644 index 000000000..70f412083 --- /dev/null +++ b/os/hal/platforms/STM32F2xx/stm32_dma.c @@ -0,0 +1,541 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file DMAv2/stm32_dma.c + * @brief Enhanced DMA helper driver code. + * + * @addtogroup STM32_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * IRSs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x000000FF + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x0000FF00 + +/** + * @brief Post-reset value of the stream CR register. + */ +#define STM32_DMA_CR_RESET_VALUE 0x00000000 + +/** + * @brief Post-reset value of the stream FCR register. + */ +#define STM32_DMA_FCR_RESET_VALUE 0x00000021 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {0, DMA1, DMA1_Stream0, &DMA1->LIFCR, 0}, + {1, DMA1, DMA1_Stream1, &DMA1->LIFCR, 6}, + {2, DMA1, DMA1_Stream2, &DMA1->LIFCR, 16}, + {3, DMA1, DMA1_Stream3, &DMA1->LIFCR, 22}, + {4, DMA1, DMA1_Stream4, &DMA1->HIFCR, 0}, + {5, DMA1, DMA1_Stream5, &DMA1->HIFCR, 6}, + {6, DMA1, DMA1_Stream6, &DMA1->HIFCR, 16}, + {7, DMA1, DMA1_Stream7, &DMA1->HIFCR, 22}, + {8, DMA2, DMA2_Stream0, &DMA2->LIFCR, 0}, + {9, DMA2, DMA2_Stream1, &DMA2->LIFCR, 6}, + {10, DMA2, DMA2_Stream2, &DMA2->LIFCR, 16}, + {11, DMA2, DMA2_Stream3, &DMA2->LIFCR, 22}, + {12, DMA2, DMA2_Stream4, &DMA2->HIFCR, 0}, + {13, DMA2, DMA2_Stream5, &DMA2->HIFCR, 6}, + {14, DMA2, DMA2_Stream6, &DMA2->HIFCR, 16}, + {15, DMA2, DMA2_Stream7, &DMA2->HIFCR, 22}, +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; + void *dma_param; +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[12].dma_func) + dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[13].dma_func) + dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[14].dma_func) + dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[15].dma_func) + dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].stream->CR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->LIFCR = 0xFFFFFFFF; + DMA1->HIFCR = 0xFFFFFFFF; + DMA2->LIFCR = 0xFFFFFFFF; + DMA2->HIFCR = 0xFFFFFFFF; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & dmastp->mask) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) { + RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; + RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA1LPEN; + } + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) { + RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; + RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA2LPEN; + } + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmaStreamClearInterrupt(dmastp); + dmastp->channel->CR = STM32_DMA_CR_RESET_VALUE; + dmastp->channel->FCR = STM32_DMA_FCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & dmastp->mask) != 0, + "dmaRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + NVICDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) { + RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA1EN; + RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA1LPEN; + } + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) { + RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2EN; + RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA2LPEN; + } +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32F2xx/stm32_dma.h b/os/hal/platforms/STM32F2xx/stm32_dma.h new file mode 100644 index 000000000..af18497fc --- /dev/null +++ b/os/hal/platforms/STM32F2xx/stm32_dma.h @@ -0,0 +1,327 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file DMAv2/stm32_dma.h + * @brief Enhanced-DMA helper driver header. + * @note This file requires definitions from the ST STM32F2xx header file + * stm32f2xx.h. + * + * @addtogroup STM32_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS 16 + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x3D + +/** + * @name DMA streams identifiers + * @{ + */ +#define STM32_DMA1_STREAM0 (&_stm32_dma_streams[0]) +#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[1]) +#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[2]) +#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[3]) +#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[4]) +#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[5]) +#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[6]) +#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[7]) +#define STM32_DMA2_STREAM0 (&_stm32_dma_streams[8]) +#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[9]) +#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[10]) +#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[11]) +#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[12]) +#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[13]) +#define STM32_DMA2_STREAM6 (&_stm32_dma_streams[14]) +#define STM32_DMA2_STREAM7 (&_stm32_dma_streams[15]) +/** @} */ + +/** + * @name CR register constants common to all DMA types + */ +#define STM32_DMA_CR_EN DMA_SxCR_EN +#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE +#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE +#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE +#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0 +#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1 +#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC +#define STM32_DMA_CR_PINC DMA_SxCR_PINC +#define STM32_DMA_CR_MINC DMA_SxCR_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1 +#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL +#define STM32_DMA_CR_PL(n) ((n) << 16) +/** @} */ + +/** + * @name CR register constants only found in STM32F2xx + */ +#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE +#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL +#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS +#define STM32_DMA_CR_DBM DMA_SxCR_DBM +#define STM32_DMA_CR_CT DMA_SxCR_CT +#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST +#define STM32_DMA_CR_PBURST_SINGLE 0 +#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0 +#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1 +#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) +#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST +#define STM32_DMA_CR_MBURST_SINGLE 0 +#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0 +#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1 +#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) +#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL +#define STM32_DMA_CR_CHSEL(n) ((n) << 25) +/** @} */ + +/** + * @name FCR register constants only found in STM32F2xx + */ +#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE +#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS +#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS +#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH +#define STM32_DMA_FCR_FTH_1Q 0 +#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0 +#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1 +#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1) +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + */ +#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0 +#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0 +#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0 +#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0 +#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the xISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the PAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->stream->PAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M0AR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->stream->M0AR = (uint32_t)(addr); \ +} + +/** + * @brief Associates an alternate memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M1AR register + * + * @special + */ +#define dmaStreamSetMemory1(dmastp, addr) { \ + (dmastp)->stream->M1AR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->stream->NDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->stream->CR = (uint32_t)(mode); \ +} + +/** + * @brief Programs the stream FIFO settings. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the FCR register + * + * @special + */ +#define dmaStreamSetFIFO(dmastp, mode) { \ + (dmastp)->stream->FCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmachp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmachp) { \ + (dmastp)->stream->CR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ -- cgit v1.2.3 -- cgit v1.2.3 From 8cc4b7f2e82a9a498ad97fb3ba45626a5b745bf9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 10:48:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3432 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/platform.mk | 1 - os/hal/platforms/STM32F1xx/stm32_dma.c | 4 +- os/hal/platforms/STM32F1xx/stm32_dma.h | 7 +- os/hal/platforms/STM32L1xx/platform.mk | 4 +- os/hal/platforms/STM32L1xx/stm32_dma.c | 349 +++++++++++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/stm32_dma.h | 320 ++++++++++++++++++++++++++++++ readme.txt | 2 +- 7 files changed, 677 insertions(+), 10 deletions(-) create mode 100644 os/hal/platforms/STM32L1xx/stm32_dma.c create mode 100644 os/hal/platforms/STM32L1xx/stm32_dma.h diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk index 5e42d1335..33579609c 100644 --- a/os/hal/platforms/STM32F1xx/platform.mk +++ b/os/hal/platforms/STM32F1xx/platform.mk @@ -21,6 +21,5 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \ PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \ ${CHIBIOS}/os/hal/platforms/STM32 \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/DMAv1 \ ${CHIBIOS}/os/hal/platforms/STM32/USBv1 \ ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.c b/os/hal/platforms/STM32F1xx/stm32_dma.c index 84e372c26..7fd1e39ee 100644 --- a/os/hal/platforms/STM32F1xx/stm32_dma.c +++ b/os/hal/platforms/STM32F1xx/stm32_dma.c @@ -19,10 +19,10 @@ */ /** - * @file DMAv1/stm32_dma.c + * @file STM32F1xx/stm32_dma.c * @brief DMA helper driver code. * - * @addtogroup STM32_DMA + * @addtogroup STM32F1xx_DMA * @details DMA sharing helper driver. In the STM32 the DMA streams are a * shared resource, this driver allows to allocate and free DMA * streams at runtime in order to allow all the other device diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h index f209898d4..bacd0a809 100644 --- a/os/hal/platforms/STM32F1xx/stm32_dma.h +++ b/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -19,14 +19,13 @@ */ /** - * @file DMAv1/stm32_dma.h + * @file STM32F1xx/stm32_dma.h * @brief DMA helper driver header. - * @note This file requires definitions from the ST header files - * stm32f10x.h or stm32l1xx.h. + * @note This file requires definitions from the ST header file stm32f10x.h. * @note This driver uses the new naming convention used for the STM32F2xx * so the "DMA channels" are referred as "DMA streams". * - * @addtogroup STM32_DMA + * @addtogroup STM32F1xx_DMA * @{ */ diff --git a/os/hal/platforms/STM32L1xx/platform.mk b/os/hal/platforms/STM32L1xx/platform.mk index 45e937ee5..301187e71 100644 --- a/os/hal/platforms/STM32L1xx/platform.mk +++ b/os/hal/platforms/STM32L1xx/platform.mk @@ -1,5 +1,6 @@ # List of all the STM32L1xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ @@ -9,7 +10,6 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/DMAv1/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c # Required include directories diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.c b/os/hal/platforms/STM32L1xx/stm32_dma.c new file mode 100644 index 000000000..e49c419d9 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/stm32_dma.c @@ -0,0 +1,349 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32L1xx/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32L1xx_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * IRSs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x0000007F + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x00000F80 + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn}, + {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn}, + {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn}, + {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn}, + {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn}, + {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn}, + {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn} +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 4; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 8; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 12; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 20; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; + DMA1->IFCR = STM32_DMA_ISR_MASK << 24; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->IFCR = 0xFFFFFFFF; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmaStreamClearInterrupt(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + NVICDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h new file mode 100644 index 000000000..cada5de38 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/stm32_dma.h @@ -0,0 +1,320 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32L1xx/stm32_dma.h + * @brief DMA helper driver header. + * @note This file requires definitions from the ST header file stm32f10x.h. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32L1xx_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS 7 + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0F + +/** + * @name DMA streams identifiers + * @{ + */ +#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0]) +#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1]) +#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2]) +#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3]) +#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4]) +#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5]) +#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6]) +/** @} */ + +/** + * @name CR register constants common to all DMA types + */ +#define STM32_DMA_CR_EN DMA_CCR1_EN +#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC +#define STM32_DMA_CR_PINC DMA_CCR1_PINC +#define STM32_DMA_CR_MINC DMA_CCR1_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 +#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL +#define STM32_DMA_CR_PL(n) ((n) << 12) +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + */ +#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ +#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + */ +#define STM32_DMA_ISR_FEIF 0 +#define STM32_DMA_ISR_DMEIF 0 +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamGetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) \ + while (((dmastp)->channel->CNDTR > 0) && \ + ((dmastp)->channel->CCR & STM32_DMA_CR_EN)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/readme.txt b/readme.txt index ed4ea9a95..c736185f6 100644 --- a/readme.txt +++ b/readme.txt @@ -80,7 +80,7 @@ - NEW: Implemented new makefile system for ARM GCC ports, now objects, listings and out files are generated into a "build" directory and not together with sources. Also implemented a simplified output log mode. - Now makefiles and load stript files are requirements and trigger a + Now makefiles and load script files are requirements and trigger a rebuild if touched. *** 2.3.3 *** -- cgit v1.2.3 From 05f792e54ea17171380538bf95e062ad6f37196c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 10:49:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3433 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/stm32_dma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h index cada5de38..e23980f9f 100644 --- a/os/hal/platforms/STM32L1xx/stm32_dma.h +++ b/os/hal/platforms/STM32L1xx/stm32_dma.h @@ -21,7 +21,7 @@ /** * @file STM32L1xx/stm32_dma.h * @brief DMA helper driver header. - * @note This file requires definitions from the ST header file stm32f10x.h. + * @note This file requires definitions from the ST header file stm32l1xx.h. * @note This driver uses the new naming convention used for the STM32F2xx * so the "DMA channels" are referred as "DMA streams". * -- cgit v1.2.3 From 560ce194e054c011f05ebf92e6e5e1c8aa51d119 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 10:50:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3434 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/readme.txt b/readme.txt index c736185f6..92591c6f6 100644 --- a/readme.txt +++ b/readme.txt @@ -82,6 +82,8 @@ together with sources. Also implemented a simplified output log mode. Now makefiles and load script files are requirements and trigger a rebuild if touched. +- CHANGE: Moved the STM32 DMA helper driver files under the sub-family + specific directory because documentation issues. *** 2.3.3 *** - FIX: Fixed uninitialized variable in STM32 PWM and ICU drivers (bug 3413558). -- cgit v1.2.3 From ef48678d56dbfcf5ab29ba69b6b28119d126d641 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 10:55:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3435 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/readme.txt b/readme.txt index 92591c6f6..6d84090d6 100644 --- a/readme.txt +++ b/readme.txt @@ -82,8 +82,8 @@ together with sources. Also implemented a simplified output log mode. Now makefiles and load script files are requirements and trigger a rebuild if touched. -- CHANGE: Moved the STM32 DMA helper driver files under the sub-family - specific directory because documentation issues. +- CHANGE: Moved the STM32 DMA helper drivers files under the sub-family + specific directories because documentation issues. *** 2.3.3 *** - FIX: Fixed uninitialized variable in STM32 PWM and ICU drivers (bug 3413558). -- cgit v1.2.3 From 3c26a6f1586fb23d44958a8038310b40bcd0c5cf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 13:07:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3436 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/ports/GCC/ARM/rules.mk | 4 ++-- os/ports/GCC/ARMCMx/rules.mk | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/os/ports/GCC/ARM/rules.mk b/os/ports/GCC/ARM/rules.mk index e63e7c373..18503fed4 100644 --- a/os/ports/GCC/ARM/rules.mk +++ b/os/ports/GCC/ARM/rules.mk @@ -25,8 +25,8 @@ else ACSRC += $(CSRC) ACPPSRC += $(CPPSRC) endif -ASRC = $(ACSRC) $(ACPPSRC) -TSRC = $(TCSRC) $(TCPPSRC) +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) SRCPATHS = $(sort $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) # Various directories diff --git a/os/ports/GCC/ARMCMx/rules.mk b/os/ports/GCC/ARMCMx/rules.mk index 1fc867931..e40892fa9 100644 --- a/os/ports/GCC/ARMCMx/rules.mk +++ b/os/ports/GCC/ARMCMx/rules.mk @@ -25,8 +25,8 @@ else ACSRC += $(CSRC) ACPPSRC += $(CPPSRC) endif -ASRC = $(ACSRC) $(ACPPSRC) -TSRC = $(TCSRC) $(TCPPSRC) +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) SRCPATHS = $(sort $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) # Various directories -- cgit v1.2.3 From ef826d2d5c93731b9f6243ccb1ad38edd7d972be Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 13:11:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3437 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/reports/STM32F103-72-GCC.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/reports/STM32F103-72-GCC.txt b/docs/reports/STM32F103-72-GCC.txt index f0bcdafa5..0ef3cdd00 100644 --- a/docs/reports/STM32F103-72-GCC.txt +++ b/docs/reports/STM32F103-72-GCC.txt @@ -6,7 +6,7 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) *** ChibiOS/RT test suite *** *** Kernel: 2.3.3unstable -*** Compiled: Oct 2 2011 - 13:53:22 +*** Compiled: Oct 8 2011 - 15:05:49 *** Compiler: GCC 4.6.0 *** Architecture: ARMv7-M *** Core Variant: Cortex-M3 -- cgit v1.2.3 From b8aac8295e455e123ce1337b760e349d47cb2ede Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 14:23:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3438 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/Doxyfile_chm | 2 +- docs/Doxyfile_html | 2 +- docs/reports/STM32L152-32-GCC.txt | 30 +++++++++++++++++------------- os/kernel/include/ch.h | 4 ++-- readme.txt | 4 ++-- 5 files changed, 23 insertions(+), 19 deletions(-) diff --git a/docs/Doxyfile_chm b/docs/Doxyfile_chm index 7bd911db7..dd7717de8 100644 --- a/docs/Doxyfile_chm +++ b/docs/Doxyfile_chm @@ -31,7 +31,7 @@ PROJECT_NAME = ChibiOS/RT # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = 2.3.3 +PROJECT_NUMBER = 2.3.4 # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer diff --git a/docs/Doxyfile_html b/docs/Doxyfile_html index 73981e6dd..f66d3afd2 100644 --- a/docs/Doxyfile_html +++ b/docs/Doxyfile_html @@ -31,7 +31,7 @@ PROJECT_NAME = ChibiOS/RT # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = 2.3.3 +PROJECT_NUMBER = 2.3.4 # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer diff --git a/docs/reports/STM32L152-32-GCC.txt b/docs/reports/STM32L152-32-GCC.txt index 3c9370693..8c9b5e380 100644 --- a/docs/reports/STM32L152-32-GCC.txt +++ b/docs/reports/STM32L152-32-GCC.txt @@ -5,7 +5,11 @@ Settings: SYSCLK=48, ACR=0x11 (1 wait state) *** ChibiOS/RT test suite *** -*** Kernel: 2.3.3unstable +*** Kern +*** ChibiOS/RT test suite +*** +*** Kernel: 2.3.4unstable +*** Compiled: Oct 8 2011 - 16:20:37 *** Compiler: GCC 4.6.0 *** Architecture: ARMv7-M *** Core Variant: Cortex-M3 @@ -99,51 +103,51 @@ Settings: SYSCLK=48, ACR=0x11 (1 wait state) --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.1 (Benchmark, messages #1) ---- Score : 131582 msgs/S, 263164 ctxswc/S +--- Score : 131586 msgs/S, 263172 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.2 (Benchmark, messages #2) ---- Score : 107944 msgs/S, 215888 ctxswc/S +--- Score : 107947 msgs/S, 215894 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.3 (Benchmark, messages #3) ---- Score : 107944 msgs/S, 215888 ctxswc/S +--- Score : 107947 msgs/S, 215894 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.4 (Benchmark, context switch) ---- Score : 454112 ctxswc/S +--- Score : 454128 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 80216 threads/S +--- Score : 79818 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 114552 threads/S +--- Score : 114145 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 33101 reschedules/S, 198606 ctxswc/S +--- Score : 33102 reschedules/S, 198612 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 229080 ctxswc/S +--- Score : 229096 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 350672 bytes/S +--- Score : 350684 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 344308 timers/S +--- Score : 364000 timers/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 468312 wait+signal/S +--- Score : 468332 wait+signal/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 309196 lock+unlock/S +--- Score : 309208 lock+unlock/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.13 (Benchmark, RAM footprint) diff --git a/os/kernel/include/ch.h b/os/kernel/include/ch.h index 35b01af2c..e751e0fc5 100644 --- a/os/kernel/include/ch.h +++ b/os/kernel/include/ch.h @@ -40,7 +40,7 @@ /** * @brief Kernel version string. */ -#define CH_KERNEL_VERSION "2.3.3unstable" +#define CH_KERNEL_VERSION "2.3.4unstable" /** * @name Kernel version @@ -59,7 +59,7 @@ /** * @brief Kernel version patch number. */ -#define CH_KERNEL_PATCH 3 +#define CH_KERNEL_PATCH 4 /** @} */ /* diff --git a/readme.txt b/readme.txt index 6d84090d6..58316233c 100644 --- a/readme.txt +++ b/readme.txt @@ -78,8 +78,8 @@ - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). - NEW: Added memory copy functionality to the STM32 DMA driver. - NEW: Implemented new makefile system for ARM GCC ports, now objects, - listings and out files are generated into a "build" directory and not - together with sources. Also implemented a simplified output log mode. + listings and output files are generated into a "build" directory and not + together with sources, also implemented a simplified output log mode. Now makefiles and load script files are requirements and trigger a rebuild if touched. - CHANGE: Moved the STM32 DMA helper drivers files under the sub-family -- cgit v1.2.3 From eea23b22826e76dba443a12c651d5490a0314471 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Oct 2011 16:56:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3439 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_AVR_MT_128/board.c | 49 +++++++++++++--------- demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h | 7 ++++ demos/ARM7-AT91SAM7S-GCC/halconf.h | 7 ++++ demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h | 7 ++++ demos/ARM7-AT91SAM7X-GCC/halconf.h | 7 ++++ demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 7 ++++ demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 7 ++++ demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 7 ++++ demos/ARM7-LPC214x-G++/halconf.h | 7 ++++ demos/ARM7-LPC214x-GCC/halconf.h | 7 ++++ demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h | 7 ++++ demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h | 7 ++++ demos/ARMCM3-STM32F100-DISCOVERY/halconf.h | 7 ++++ demos/ARMCM3-STM32F103-FATFS/halconf.h | 7 ++++ demos/ARMCM3-STM32F103-G++/halconf.h | 7 ++++ demos/ARMCM3-STM32F103/halconf.h | 7 ++++ demos/ARMCM3-STM32F103ZG-FATFS/halconf.h | 7 ++++ demos/ARMCM3-STM32F107/halconf.h | 7 ++++ demos/ARMCM3-STM32L152-DISCOVERY/halconf.h | 7 ++++ demos/AVR-AT90CANx-GCC/halconf.h | 9 +++- demos/AVR-ATmega128-GCC/halconf.h | 9 +++- demos/MSP430-MSP430x1611-GCC/halconf.h | 7 ++++ demos/PPC-SPC563-GCC/halconf.h | 7 ++++ demos/Posix-GCC/halconf.h | 7 ++++ demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h | 7 ++++ demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h | 7 ++++ demos/STM8S-STM8S208-RC/halconf.h | 7 ++++ demos/Win32-MinGW/halconf.h | 7 ++++ os/hal/templates/halconf.h | 7 ++++ test/coverage/halconf.h | 7 ++++ testhal/LPC11xx/IRQ_STORM/halconf.h | 7 ++++ testhal/LPC13xx/IRQ_STORM/halconf.h | 7 ++++ testhal/STM32F1xx/ADC/halconf.h | 7 ++++ testhal/STM32F1xx/CAN/halconf.h | 7 ++++ testhal/STM32F1xx/EXT/halconf.h | 7 ++++ testhal/STM32F1xx/EXT_WAKEUP/halconf.h | 7 ++++ testhal/STM32F1xx/GPT/halconf.h | 7 ++++ testhal/STM32F1xx/I2C/halconf.h | 7 ++++ testhal/STM32F1xx/IRQ_STORM/halconf.h | 7 ++++ testhal/STM32F1xx/MAC/halconf.h | 7 ++++ testhal/STM32F1xx/PWM-ICU/halconf.h | 7 ++++ testhal/STM32F1xx/RTC/halconf.h | 14 +++---- testhal/STM32F1xx/SDC/halconf.h | 7 ++++ testhal/STM32F1xx/SPI/halconf.h | 7 ++++ testhal/STM32F1xx/UART/halconf.h | 7 ++++ testhal/STM32F1xx/USB_CDC/halconf.h | 7 ++++ testhal/STM32F1xx/USB_MSC/halconf.h | 7 ++++ testhal/STM32L1xx/ADC/halconf.h | 7 ++++ testhal/STM32L1xx/EXT/halconf.h | 7 ++++ testhal/STM32L1xx/GPT/halconf.h | 7 ++++ testhal/STM32L1xx/IRQ_STORM/halconf.h | 7 ++++ testhal/STM32L1xx/PWM-ICU/halconf.h | 7 ++++ testhal/STM32L1xx/SPI/halconf.h | 7 ++++ testhal/STM32L1xx/UART/halconf.h | 7 ++++ testhal/STM8S/SPI/demo/halconf.h | 7 ++++ 55 files changed, 410 insertions(+), 28 deletions(-) diff --git a/boards/OLIMEX_AVR_MT_128/board.c b/boards/OLIMEX_AVR_MT_128/board.c index b1fa460a9..c7e74e2d4 100644 --- a/boards/OLIMEX_AVR_MT_128/board.c +++ b/boards/OLIMEX_AVR_MT_128/board.c @@ -21,6 +21,35 @@ #include "ch.h" #include "hal.h" +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ +#if defined(PORTA) + {VAL_PORTA, VAL_DDRA}, +#endif +#if defined(PORTA) + {VAL_PORTB, VAL_DDRB}, +#endif +#if defined(PORTA) + {VAL_PORTC, VAL_DDRC}, +#endif +#if defined(PORTA) + {VAL_PORTD, VAL_DDRD}, +#endif +#if defined(PORTA) + {VAL_PORTE, VAL_DDRE}, +#endif +}; +#endif /* HAL_USE_PAL */ + +/** + * @brief Timer0 interrupt handler. + */ CH_IRQ_HANDLER(TIMER0_COMP_vect) { CH_IRQ_PROLOGUE(); @@ -32,29 +61,11 @@ CH_IRQ_HANDLER(TIMER0_COMP_vect) { CH_IRQ_EPILOGUE(); } -/* +/** * Board-specific initialization code. */ void boardInit(void) { - /* - * I/O ports setup. - */ - DDRA = VAL_DDRA; - PORTA = VAL_PORTA; - DDRB = VAL_DDRB; - PORTB = VAL_PORTB; - DDRC = VAL_DDRC; - PORTC = VAL_PORTC; - DDRD = VAL_DDRD; - PORTD = VAL_PORTD; - DDRE = VAL_DDRE; - PORTE = VAL_PORTE; - DDRF = VAL_DDRF; - PORTF = VAL_PORTF; - DDRG = VAL_DDRG; - PORTG = VAL_PORTG; - /* * External interrupts setup, all disabled initially. */ diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h index 5f2bc4485..443a3f2be 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARM7-AT91SAM7S-GCC/halconf.h b/demos/ARM7-AT91SAM7S-GCC/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/ARM7-AT91SAM7S-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h index 560a77dbe..bf6440204 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index f1d93c6f2..7d774fb20 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index f1d93c6f2..7d774fb20 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index 560a77dbe..bf6440204 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h index 560a77dbe..bf6440204 100644 --- a/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h index 560a77dbe..bf6440204 100644 --- a/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h index e8acd1f13..2c109a7ef 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM TRUE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARMCM3-STM32F103-FATFS/halconf.h b/demos/ARMCM3-STM32F103-FATFS/halconf.h index 560a77dbe..bf6440204 100644 --- a/demos/ARMCM3-STM32F103-FATFS/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARMCM3-STM32F103-G++/halconf.h b/demos/ARMCM3-STM32F103-G++/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/ARMCM3-STM32F103-G++/halconf.h +++ b/demos/ARMCM3-STM32F103-G++/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARMCM3-STM32F103/halconf.h b/demos/ARMCM3-STM32F103/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/ARMCM3-STM32F103/halconf.h +++ b/demos/ARMCM3-STM32F103/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h index 9aa7cd21e..978dbc65c 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h +++ b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARMCM3-STM32F107/halconf.h b/demos/ARMCM3-STM32F107/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/ARMCM3-STM32F107/halconf.h +++ b/demos/ARMCM3-STM32F107/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h index e8acd1f13..2c109a7ef 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM TRUE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index 8ec0c2a35..b4fb49092 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -38,7 +38,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL FALSE +#define HAL_USE_PAL TRUE #endif /** @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index 8ec0c2a35..b4fb49092 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -38,7 +38,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL FALSE +#define HAL_USE_PAL TRUE #endif /** @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h index aca6c2f61..b3d9443c2 100644 --- a/demos/PPC-SPC563-GCC/halconf.h +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h index aa145ef4d..682089a94 100644 --- a/demos/Posix-GCC/halconf.h +++ b/demos/Posix-GCC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h index b9bee3656..b4fb49092 100644 --- a/demos/STM8S-STM8S208-RC/halconf.h +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index aa145ef4d..682089a94 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/os/hal/templates/halconf.h b/os/hal/templates/halconf.h index 2e28bea73..9a0d3c7d7 100644 --- a/os/hal/templates/halconf.h +++ b/os/hal/templates/halconf.h @@ -108,6 +108,13 @@ #define HAL_USE_PWM TRUE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/test/coverage/halconf.h b/test/coverage/halconf.h index 95b25b63e..50f223ef8 100644 --- a/test/coverage/halconf.h +++ b/test/coverage/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/LPC11xx/IRQ_STORM/halconf.h b/testhal/LPC11xx/IRQ_STORM/halconf.h index f5e7cc1ed..f9a1b78f6 100644 --- a/testhal/LPC11xx/IRQ_STORM/halconf.h +++ b/testhal/LPC11xx/IRQ_STORM/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/LPC13xx/IRQ_STORM/halconf.h b/testhal/LPC13xx/IRQ_STORM/halconf.h index f5e7cc1ed..f9a1b78f6 100644 --- a/testhal/LPC13xx/IRQ_STORM/halconf.h +++ b/testhal/LPC13xx/IRQ_STORM/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/ADC/halconf.h b/testhal/STM32F1xx/ADC/halconf.h index 62cc1e67d..b1de4bf39 100644 --- a/testhal/STM32F1xx/ADC/halconf.h +++ b/testhal/STM32F1xx/ADC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/CAN/halconf.h b/testhal/STM32F1xx/CAN/halconf.h index f73d58cf1..03b395896 100644 --- a/testhal/STM32F1xx/CAN/halconf.h +++ b/testhal/STM32F1xx/CAN/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/EXT/halconf.h b/testhal/STM32F1xx/EXT/halconf.h index d7df1593a..775428e22 100644 --- a/testhal/STM32F1xx/EXT/halconf.h +++ b/testhal/STM32F1xx/EXT/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h index ad81d2c24..e77cc2ae7 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/GPT/halconf.h b/testhal/STM32F1xx/GPT/halconf.h index ff9202a66..3be209376 100644 --- a/testhal/STM32F1xx/GPT/halconf.h +++ b/testhal/STM32F1xx/GPT/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/I2C/halconf.h b/testhal/STM32F1xx/I2C/halconf.h index 834d54572..31d581932 100644 --- a/testhal/STM32F1xx/I2C/halconf.h +++ b/testhal/STM32F1xx/I2C/halconf.h @@ -103,6 +103,13 @@ #define HAL_USE_PWM TRUE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/IRQ_STORM/halconf.h b/testhal/STM32F1xx/IRQ_STORM/halconf.h index f5e7cc1ed..f9a1b78f6 100644 --- a/testhal/STM32F1xx/IRQ_STORM/halconf.h +++ b/testhal/STM32F1xx/IRQ_STORM/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/MAC/halconf.h b/testhal/STM32F1xx/MAC/halconf.h index 0b8b13660..8ccf4de5c 100644 --- a/testhal/STM32F1xx/MAC/halconf.h +++ b/testhal/STM32F1xx/MAC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/PWM-ICU/halconf.h b/testhal/STM32F1xx/PWM-ICU/halconf.h index e5eeb8b7a..5d3985cdd 100644 --- a/testhal/STM32F1xx/PWM-ICU/halconf.h +++ b/testhal/STM32F1xx/PWM-ICU/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM TRUE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h index 4932b25f4..12944d159 100644 --- a/testhal/STM32F1xx/RTC/halconf.h +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -103,6 +103,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + /** * @brief Enables the SDC subsystem. */ @@ -145,13 +152,6 @@ #define HAL_USE_USB FALSE #endif -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC TRUE -#endif - /*===========================================================================*/ /* ADC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32F1xx/SDC/halconf.h b/testhal/STM32F1xx/SDC/halconf.h index 9aa7cd21e..978dbc65c 100644 --- a/testhal/STM32F1xx/SDC/halconf.h +++ b/testhal/STM32F1xx/SDC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/SPI/halconf.h b/testhal/STM32F1xx/SPI/halconf.h index a825e65c5..b3bbd85fd 100644 --- a/testhal/STM32F1xx/SPI/halconf.h +++ b/testhal/STM32F1xx/SPI/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/UART/halconf.h b/testhal/STM32F1xx/UART/halconf.h index 2dd31e012..8a458d702 100644 --- a/testhal/STM32F1xx/UART/halconf.h +++ b/testhal/STM32F1xx/UART/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/USB_CDC/halconf.h b/testhal/STM32F1xx/USB_CDC/halconf.h index c502005f2..cfe13f216 100644 --- a/testhal/STM32F1xx/USB_CDC/halconf.h +++ b/testhal/STM32F1xx/USB_CDC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32F1xx/USB_MSC/halconf.h b/testhal/STM32F1xx/USB_MSC/halconf.h index f772d653a..726ec0a55 100644 --- a/testhal/STM32F1xx/USB_MSC/halconf.h +++ b/testhal/STM32F1xx/USB_MSC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32L1xx/ADC/halconf.h b/testhal/STM32L1xx/ADC/halconf.h index 62cc1e67d..b1de4bf39 100644 --- a/testhal/STM32L1xx/ADC/halconf.h +++ b/testhal/STM32L1xx/ADC/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32L1xx/EXT/halconf.h b/testhal/STM32L1xx/EXT/halconf.h index d7df1593a..775428e22 100644 --- a/testhal/STM32L1xx/EXT/halconf.h +++ b/testhal/STM32L1xx/EXT/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32L1xx/GPT/halconf.h b/testhal/STM32L1xx/GPT/halconf.h index ff9202a66..3be209376 100644 --- a/testhal/STM32L1xx/GPT/halconf.h +++ b/testhal/STM32L1xx/GPT/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32L1xx/IRQ_STORM/halconf.h b/testhal/STM32L1xx/IRQ_STORM/halconf.h index f5e7cc1ed..f9a1b78f6 100644 --- a/testhal/STM32L1xx/IRQ_STORM/halconf.h +++ b/testhal/STM32L1xx/IRQ_STORM/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32L1xx/PWM-ICU/halconf.h b/testhal/STM32L1xx/PWM-ICU/halconf.h index e5eeb8b7a..5d3985cdd 100644 --- a/testhal/STM32L1xx/PWM-ICU/halconf.h +++ b/testhal/STM32L1xx/PWM-ICU/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM TRUE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32L1xx/SPI/halconf.h b/testhal/STM32L1xx/SPI/halconf.h index a825e65c5..b3bbd85fd 100644 --- a/testhal/STM32L1xx/SPI/halconf.h +++ b/testhal/STM32L1xx/SPI/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM32L1xx/UART/halconf.h b/testhal/STM32L1xx/UART/halconf.h index 2dd31e012..8a458d702 100644 --- a/testhal/STM32L1xx/UART/halconf.h +++ b/testhal/STM32L1xx/UART/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ diff --git a/testhal/STM8S/SPI/demo/halconf.h b/testhal/STM8S/SPI/demo/halconf.h index af1c8e1a4..b2567cb8f 100644 --- a/testhal/STM8S/SPI/demo/halconf.h +++ b/testhal/STM8S/SPI/demo/halconf.h @@ -104,6 +104,13 @@ #define HAL_USE_PWM FALSE #endif +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + /** * @brief Enables the SDC subsystem. */ -- cgit v1.2.3 From 977abf0c51adfac84351ac5c9d93edf4719fd094 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 9 Oct 2011 16:32:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3440 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_AVR_MT_128/board.h | 35 ++++++++++++++++++----------------- demos/AVR-ATmega128-GCC/lcd.c | 26 ++++++++++++++++---------- demos/AVR-ATmega128-GCC/main.c | 6 +++--- 3 files changed, 37 insertions(+), 30 deletions(-) diff --git a/boards/OLIMEX_AVR_MT_128/board.h b/boards/OLIMEX_AVR_MT_128/board.h index dfe6828bb..4dc68db92 100644 --- a/boards/OLIMEX_AVR_MT_128/board.h +++ b/boards/OLIMEX_AVR_MT_128/board.h @@ -93,23 +93,24 @@ #define VAL_DDRG 0x00 #define VAL_PORTG 0x07 -#define PORTA_BUTTON1 (1 << 0) -#define PORTA_BUTTON2 (1 << 1) -#define PORTA_BUTTON3 (1 << 2) -#define PORTA_BUTTON4 (1 << 3) -#define PORTA_BUTTON5 (1 << 4) -#define PORTA_DALLAS (1 << 5) -#define PORTA_RELAY (1 << 6) - -#define PORTC_44780_RS (1 << 0) -#define PORTC_44780_RW (1 << 1) -#define PORTC_44780_E (1 << 2) -#define PORTC_44780_D4 (1 << 4) -#define PORTC_44780_D5 (1 << 5) -#define PORTC_44780_D6 (1 << 6) -#define PORTC_44780_D7 (1 << 7) -#define PORTC_44780_DATA (PORTC_44780_D4 | PORTC_44780_D5 | \ - PORTC_44780_D6 | PORTC_44780_D7) + +#define PORTA_BUTTON1 0 +#define PORTA_BUTTON2 1 +#define PORTA_BUTTON3 2 +#define PORTA_BUTTON4 3 +#define PORTA_BUTTON5 4 +#define PORTA_DALLAS 5 +#define PORTA_RELAY 6 + +#define PORTC_44780_RS_MASK (1 << 0) +#define PORTC_44780_RW_MASK (1 << 1) +#define PORTC_44780_E_MASK (1 << 2) +#define PORTC_44780_D4_MASK (1 << 4) +#define PORTC_44780_D5_MASK (1 << 5) +#define PORTC_44780_D6_MASK (1 << 6) +#define PORTC_44780_D7_MASK (1 << 7) +#define PORTC_44780_DATA_MASK (PORTC_44780_D4_MASK | PORTC_44780_D5_MASK | \ + PORTC_44780_D6_MASK | PORTC_44780_D7_MASK) #define PORTE_BUZZ1 (1 << 4) #define PORTE_BUZZ2 (1 << 5) diff --git a/demos/AVR-ATmega128-GCC/lcd.c b/demos/AVR-ATmega128-GCC/lcd.c index 5ef8fca02..cd8aa5006 100644 --- a/demos/AVR-ATmega128-GCC/lcd.c +++ b/demos/AVR-ATmega128-GCC/lcd.c @@ -25,10 +25,10 @@ static void e_pulse(void) { volatile uint8_t i; - PORTC |= PORTC_44780_E; + PORTC |= PORTC_44780_E_MASK; for (i = 0; i < ELOOPVALUE; i++); ; - PORTC &= ~PORTC_44780_E; + PORTC &= ~PORTC_44780_E_MASK; } static void wait_not_busy(void) { @@ -41,8 +41,9 @@ static void wait_not_busy(void) { */ void lcdInit(void) { - PORTC = (PORTC & ~(PORTC_44780_DATA | PORTC_44780_RS | PORTC_44780_E | PORTC_44780_RW)) | - (LCD_CMD_INIT8 & PORTC_44780_DATA); + PORTC = (PORTC & ~(PORTC_44780_DATA_MASK | PORTC_44780_RS_MASK | + PORTC_44780_E_MASK | PORTC_44780_RW_MASK)) | + (LCD_CMD_INIT8 & PORTC_44780_DATA_MASK); chThdSleep(50); e_pulse(); chThdSleep(10); @@ -50,8 +51,9 @@ void lcdInit(void) { chThdSleep(2); e_pulse(); wait_not_busy(); - PORTC = (PORTC & ~(PORTC_44780_DATA | PORTC_44780_RS | PORTC_44780_E | PORTC_44780_RW)) | - (LCD_CMD_INIT4 & PORTC_44780_DATA); + PORTC = (PORTC & ~(PORTC_44780_DATA_MASK | PORTC_44780_RS_MASK | + PORTC_44780_E_MASK | PORTC_44780_RW_MASK)) | + (LCD_CMD_INIT4 & PORTC_44780_DATA_MASK); e_pulse(); lcdCmd(LCD_CMD_INIT4); lcdCmd(LCD_SET_DM | LCD_DM_DISPLAY_ON); @@ -64,9 +66,11 @@ void lcdInit(void) { void lcdCmd(uint8_t cmd) { wait_not_busy(); - PORTC = (PORTC | PORTC_44780_DATA) & (cmd | (0x0F & ~PORTC_44780_RS)); + PORTC = (PORTC | PORTC_44780_DATA_MASK) & (cmd | + (0x0F & ~PORTC_44780_RS_MASK)); e_pulse(); - PORTC = (PORTC | PORTC_44780_DATA) & ((cmd << 4) | (0x0F & ~PORTC_44780_RS)); + PORTC = (PORTC | PORTC_44780_DATA_MASK) & ((cmd << 4) | + (0x0F & ~PORTC_44780_RS_MASK)); e_pulse(); } @@ -78,9 +82,11 @@ void lcdPutc(char c) { wait_not_busy(); b = c | 0x0F; - PORTC = (PORTC | PORTC_44780_DATA | PORTC_44780_RS) & (c | 0x0F); + PORTC = (PORTC | PORTC_44780_DATA_MASK | PORTC_44780_RS_MASK) & + (c | 0x0F); e_pulse(); - PORTC = (PORTC | PORTC_44780_DATA | PORTC_44780_RS) & ((c << 4) | 0x0F); + PORTC = (PORTC | PORTC_44780_DATA_MASK | PORTC_44780_RS_MASK) & + ((c << 4) | 0x0F); e_pulse(); } diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index 0b26a9641..cd982d1b9 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -28,8 +28,8 @@ static WORKING_AREA(waThread1, 32); static msg_t Thread1(void *arg) { while (TRUE) { - if (!(PINA & PORTA_BUTTON2)) - PORTA ^= PORTA_RELAY; + if (!palReadPad(IOPORT1, PORTA_BUTTON2)) + palTogglePad(IOPORT1, PORTA_RELAY); chThdSleepMilliseconds(1000); } return 0; @@ -38,7 +38,7 @@ static msg_t Thread1(void *arg) { static void TimerHandler(eventid_t id) { msg_t TestThread(void *p); - if (!(PINA & PORTA_BUTTON1)) + if (!palReadPad(IOPORT1, PORTA_BUTTON1)) TestThread(&SD2); } -- cgit v1.2.3 From 36d1e0978ac7cce6074470ac5a09d14b9986f922 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 10 Oct 2011 18:08:37 +0000 Subject: Finalized AVR PAL driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3441 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_AVR_CAN/board.c | 44 +++++++++++++++++++++++++----------------- boards/OLIMEX_AVR_CAN/board.h | 4 ++-- demos/AVR-AT90CANx-GCC/main.c | 32 ++++++++---------------------- demos/AVR-ATmega128-GCC/main.c | 30 ++++++---------------------- docs/reports/ATmega128-16.txt | 34 +++++++++++++++++--------------- os/hal/platforms/AVR/pal_lld.c | 4 ---- readme.txt | 1 + 7 files changed, 61 insertions(+), 88 deletions(-) diff --git a/boards/OLIMEX_AVR_CAN/board.c b/boards/OLIMEX_AVR_CAN/board.c index de1af241c..cd84a8086 100644 --- a/boards/OLIMEX_AVR_CAN/board.c +++ b/boards/OLIMEX_AVR_CAN/board.c @@ -21,6 +21,32 @@ #include "ch.h" #include "hal.h" +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ +#if defined(PORTA) + {VAL_PORTA, VAL_DDRA}, +#endif +#if defined(PORTA) + {VAL_PORTB, VAL_DDRB}, +#endif +#if defined(PORTA) + {VAL_PORTC, VAL_DDRC}, +#endif +#if defined(PORTA) + {VAL_PORTD, VAL_DDRD}, +#endif +#if defined(PORTA) + {VAL_PORTE, VAL_DDRE}, +#endif +}; +#endif /* HAL_USE_PAL */ + CH_IRQ_HANDLER(TIMER0_COMP_vect) { CH_IRQ_PROLOGUE(); @@ -37,24 +63,6 @@ CH_IRQ_HANDLER(TIMER0_COMP_vect) { */ void boardInit(void) { - /* - * I/O ports setup. - */ - DDRA = VAL_DDRA; - PORTA = VAL_PORTA; - DDRB = VAL_DDRB; - PORTB = VAL_PORTB; - DDRC = VAL_DDRC; - PORTC = VAL_PORTC; - DDRD = VAL_DDRD; - PORTD = VAL_PORTD; - DDRE = VAL_DDRE; - PORTE = VAL_PORTE; - DDRF = VAL_DDRF; - PORTF = VAL_PORTF; - DDRG = VAL_DDRG; - PORTG = VAL_PORTG; - /* * External interrupts setup, all disabled initially. */ diff --git a/boards/OLIMEX_AVR_CAN/board.h b/boards/OLIMEX_AVR_CAN/board.h index b1d6038c3..c4db2338a 100644 --- a/boards/OLIMEX_AVR_CAN/board.h +++ b/boards/OLIMEX_AVR_CAN/board.h @@ -87,8 +87,8 @@ #define VAL_DDRG 0x00 #define VAL_PORTG 0x07 -#define PORTE_LED (1 << 4) -#define PORTE_BUTTON (1 << 5) +#define PORTE_LED 4 +#define PORTE_BUTTON 5 #if !defined(_FROM_ASM_) #ifdef __cplusplus diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index d039c6cf6..50d43a7f9 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -20,34 +20,22 @@ #include "ch.h" #include "hal.h" -#include "evtimer.h" +#include "test.h" static WORKING_AREA(waThread1, 32); static msg_t Thread1(void *arg) { while (TRUE) { - PORTE ^= PORTE_LED; - chThdSleepMilliseconds(500); + palTogglePad(IOPORT5, PORTE_LED); + chThdSleepMilliseconds(500); } return 0; } -static void TimerHandler(eventid_t id) { - msg_t TestThread(void *p); - - if (!(PORTE & PORTE_BUTTON)) - TestThread(&SD2); -} - /* * Application entry point. */ int main(void) { - static EvTimer evt; - static evhandler_t handlers[1] = { - TimerHandler - }; - static EventListener el0; /* * System initializations. @@ -64,20 +52,16 @@ int main(void) { */ sdStart(&SD2, NULL); - /* - * Event Timer initialization. - */ - evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - /* * Starts the LED blinker thread. */ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - while(TRUE) - chEvtDispatch(handlers, chEvtWaitOne(ALL_EVENTS)); + while(TRUE) { + if (!palReadPad(IOPORT5, PORTE_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } return 0; } diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index cd982d1b9..36b482c4b 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -20,7 +20,7 @@ #include "ch.h" #include "hal.h" -#include "evtimer.h" +#include "test.h" #include "lcd.h" @@ -35,22 +35,10 @@ static msg_t Thread1(void *arg) { return 0; } -static void TimerHandler(eventid_t id) { - msg_t TestThread(void *p); - - if (!palReadPad(IOPORT1, PORTA_BUTTON1)) - TestThread(&SD2); -} - /* * Application entry point. */ int main(void) { - static EvTimer evt; - static evhandler_t handlers[1] = { - TimerHandler - }; - static EventListener el0; /* * System initializations. @@ -76,20 +64,14 @@ int main(void) { lcdPuts(LCD_LINE1, " ChibiOS/RT "); lcdPuts(LCD_LINE2, " Hello World! "); - /* - * Event Timer initialization. - */ - evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - /* * Starts the LED blinker thread. */ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - while(TRUE) - chEvtDispatch(handlers, chEvtWaitOne(ALL_EVENTS)); - - return 0; + while(TRUE) { + if (!palReadPad(IOPORT1, PORTA_BUTTON1)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } } diff --git a/docs/reports/ATmega128-16.txt b/docs/reports/ATmega128-16.txt index 2317da5c7..8b2c21f4a 100644 --- a/docs/reports/ATmega128-16.txt +++ b/docs/reports/ATmega128-16.txt @@ -5,10 +5,12 @@ Settings: F_CPU=16000000 *** ChibiOS/RT test suite *** -*** Kernel: 2.1.6unstable -*** GCC Version: 4.3.0 +*** Kernel: 2.3.4unstable +*** Compiled: Oct 9 2011 - 10:47:27 +*** Compiler: GCC 4.3.0 *** Architecture: AVR *** Core Variant: MegaAVR +*** Port Info: None *** Platform: ATmega128 *** Test Board: Olimex AVR-MT-128 @@ -83,31 +85,31 @@ Settings: F_CPU=16000000 --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.1 (Benchmark, messages #1) ---- Score : 31125 msgs/S, 62250 ctxswc/S +--- Score : 31561 msgs/S, 63122 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.2 (Benchmark, messages #2) ---- Score : 24979 msgs/S, 49958 ctxswc/S +--- Score : 24980 msgs/S, 49960 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.3 (Benchmark, messages #3) ---- Score : 24979 msgs/S, 49958 ctxswc/S +--- Score : 24980 msgs/S, 49960 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.4 (Benchmark, context switch) ---- Score : 89904 ctxswc/S +--- Score : 88896 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 21054 threads/S +--- Score : 19766 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 27121 threads/S +--- Score : 25179 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 7970 reschedules/S, 47820 ctxswc/S +--- Score : 7891 reschedules/S, 47346 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.8 (Benchmark, round robin context switching) @@ -115,31 +117,31 @@ Settings: F_CPU=16000000 --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 80180 bytes/S +--- Score : 96364 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 81522 timers/S +--- Score : 85724 timers/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 227560 wait+signal/S +--- Score : 227568 wait+signal/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 116720 lock+unlock/S +--- Score : 116724 lock+unlock/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 230 bytes ---- Thread: 29 bytes +--- System: 234 bytes +--- Thread: 31 bytes --- Timer : 10 bytes --- Semaph: 5 bytes --- EventS: 2 bytes --- EventL: 5 bytes --- Mutex : 8 bytes --- CondV.: 4 bytes ---- Queue : 15 bytes +--- Queue : 16 bytes --- MailB.: 18 bytes --- Result: SUCCESS ---------------------------------------------------------------------------- diff --git a/os/hal/platforms/AVR/pal_lld.c b/os/hal/platforms/AVR/pal_lld.c index 4bfd7bd04..2f3174934 100644 --- a/os/hal/platforms/AVR/pal_lld.c +++ b/os/hal/platforms/AVR/pal_lld.c @@ -103,8 +103,6 @@ void _pal_lld_init(const PALConfig *config) { * with pull-up by default. * * @notapi - * - * TODO: check PAL_MODE_UNCONNECTED mode recommended for AVR */ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, @@ -113,8 +111,6 @@ void _pal_lld_setgroupmode(ioportid_t port, switch (mode) { case PAL_MODE_RESET: case PAL_MODE_INPUT: - port->dir &= ~mask; - break; case PAL_MODE_INPUT_ANALOG: port->dir &= ~mask; port->out &= ~mask; diff --git a/readme.txt b/readme.txt index 58316233c..3b365809d 100644 --- a/readme.txt +++ b/readme.txt @@ -82,6 +82,7 @@ together with sources, also implemented a simplified output log mode. Now makefiles and load script files are requirements and trigger a rebuild if touched. +- NEW: Updated AVR demos to use the new PAL driver. - CHANGE: Moved the STM32 DMA helper drivers files under the sub-family specific directories because documentation issues. -- cgit v1.2.3 From 3ce8ccb68a6de3b053f0e5fd685725c0904597d9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 15 Oct 2011 06:37:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3442 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_AVR_CAN/board.c | 8 ++++---- boards/OLIMEX_AVR_MT_128/board.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/boards/OLIMEX_AVR_CAN/board.c b/boards/OLIMEX_AVR_CAN/board.c index cd84a8086..4e808d501 100644 --- a/boards/OLIMEX_AVR_CAN/board.c +++ b/boards/OLIMEX_AVR_CAN/board.c @@ -32,16 +32,16 @@ const PALConfig pal_default_config = #if defined(PORTA) {VAL_PORTA, VAL_DDRA}, #endif -#if defined(PORTA) +#if defined(PORTB) {VAL_PORTB, VAL_DDRB}, #endif -#if defined(PORTA) +#if defined(PORTC) {VAL_PORTC, VAL_DDRC}, #endif -#if defined(PORTA) +#if defined(PORTD) {VAL_PORTD, VAL_DDRD}, #endif -#if defined(PORTA) +#if defined(PORTE) {VAL_PORTE, VAL_DDRE}, #endif }; diff --git a/boards/OLIMEX_AVR_MT_128/board.c b/boards/OLIMEX_AVR_MT_128/board.c index c7e74e2d4..90b0f7306 100644 --- a/boards/OLIMEX_AVR_MT_128/board.c +++ b/boards/OLIMEX_AVR_MT_128/board.c @@ -32,16 +32,16 @@ const PALConfig pal_default_config = #if defined(PORTA) {VAL_PORTA, VAL_DDRA}, #endif -#if defined(PORTA) +#if defined(PORTB) {VAL_PORTB, VAL_DDRB}, #endif -#if defined(PORTA) +#if defined(PORTC) {VAL_PORTC, VAL_DDRC}, #endif -#if defined(PORTA) +#if defined(PORTD) {VAL_PORTD, VAL_DDRD}, #endif -#if defined(PORTA) +#if defined(PORTE) {VAL_PORTE, VAL_DDRE}, #endif }; -- cgit v1.2.3 From ade734b003ec8f45e365816c60a1689dd3454146 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 15 Oct 2011 07:10:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3443 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_AVR_CAN/board.c | 6 +++++ boards/OLIMEX_AVR_MT_128/board.c | 6 +++++ os/hal/platforms/AVR/pal_lld.c | 10 +++++++++ os/hal/platforms/AVR/pal_lld.h | 34 ++++++++++++++++++++++++---- os/hal/platforms/AVR/platform.dox | 47 ++++++++++++++++++++++++++++++++++----- 5 files changed, 93 insertions(+), 10 deletions(-) diff --git a/boards/OLIMEX_AVR_CAN/board.c b/boards/OLIMEX_AVR_CAN/board.c index 4e808d501..e22d72d48 100644 --- a/boards/OLIMEX_AVR_CAN/board.c +++ b/boards/OLIMEX_AVR_CAN/board.c @@ -44,6 +44,12 @@ const PALConfig pal_default_config = #if defined(PORTE) {VAL_PORTE, VAL_DDRE}, #endif +#if defined(PORTF) + {VAL_PORTF, VAL_DDRF}, +#endif +#if defined(PORTG) + {VAL_PORTG, VAL_DDRG}, +#endif }; #endif /* HAL_USE_PAL */ diff --git a/boards/OLIMEX_AVR_MT_128/board.c b/boards/OLIMEX_AVR_MT_128/board.c index 90b0f7306..c3f97cfff 100644 --- a/boards/OLIMEX_AVR_MT_128/board.c +++ b/boards/OLIMEX_AVR_MT_128/board.c @@ -44,6 +44,12 @@ const PALConfig pal_default_config = #if defined(PORTE) {VAL_PORTE, VAL_DDRE}, #endif +#if defined(PORTF) + {VAL_PORTF, VAL_DDRF}, +#endif +#if defined(PORTG) + {VAL_PORTG, VAL_DDRG}, +#endif }; #endif /* HAL_USE_PAL */ diff --git a/os/hal/platforms/AVR/pal_lld.c b/os/hal/platforms/AVR/pal_lld.c index 2f3174934..0676047ac 100644 --- a/os/hal/platforms/AVR/pal_lld.c +++ b/os/hal/platforms/AVR/pal_lld.c @@ -85,6 +85,16 @@ void _pal_lld_init(const PALConfig *config) { PORTE = config->porte.out; DDRE = config->porte.dir; #endif + +#if defined(PORTF) || defined(__DOXYGEN__) + PORTF = config->portf.out; + DDRF = config->portf.dir; +#endif + +#if defined(PORTG) || defined(__DOXYGEN__) + PORTG = config->portg.out; + DDRG = config->portg.dir; +#endif } /** diff --git a/os/hal/platforms/AVR/pal_lld.h b/os/hal/platforms/AVR/pal_lld.h index a2d1f8714..fe64029d0 100644 --- a/os/hal/platforms/AVR/pal_lld.h +++ b/os/hal/platforms/AVR/pal_lld.h @@ -43,24 +43,30 @@ /*===========================================================================*/ /** - * @brief Width, in bits, of an I/O port. + * @brief Width, in bits, of an I/O port. */ #define PAL_IOPORTS_WIDTH 8 /** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. */ #define PAL_WHOLE_PORT ((ioportmask_t)0xFF) /** - * @brief AVR setup registers. + * @brief AVR setup registers. */ typedef struct { uint8_t out; uint8_t dir; } avr_gpio_setup_t; +/** + * @brief AVR registers block. + * @note On some devices registers do not follow this layout on some + * ports, the ports with abnormal layout cannot be used through + * the PAL driver. Example: PORT F on Mega128. + */ typedef struct { volatile uint8_t in; volatile uint8_t dir; @@ -90,6 +96,12 @@ typedef struct { #if defined(PORTE) || defined(__DOXYGEN__) avr_gpio_setup_t porte; #endif +#if defined(PORTF) || defined(__DOXYGEN__) + avr_gpio_setup_t portf; +#endif +#if defined(PORTG) || defined(__DOXYGEN__) + avr_gpio_setup_t portg; +#endif } PALConfig; /** @@ -149,6 +161,20 @@ typedef avr_gpio_registers_t *ioportid_t; #define IOPORT5 ((volatile avr_gpio_registers_t *)&PINE) #endif +#if defined(PORTF) || defined(__DOXYGEN__) +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 ((volatile avr_gpio_registers_t *)&PINF) +#endif + +#if defined(PORTG) || defined(__DOXYGEN__) +/** + * @brief GPIO port G identifier. + */ +#define IOPORT7 ((volatile avr_gpio_registers_t *)&PING) +#endif + /*===========================================================================*/ /* Implementation, some of the following macros could be implemented as */ /* functions, if so please put them in pal_lld.c. */ diff --git a/os/hal/platforms/AVR/platform.dox b/os/hal/platforms/AVR/platform.dox index 2ac2256b9..a004113b0 100644 --- a/os/hal/platforms/AVR/platform.dox +++ b/os/hal/platforms/AVR/platform.dox @@ -37,14 +37,49 @@ /** * @defgroup AVR_PAL AVR PAL Support - * @details The AVR PAL driver uses the GPIO peripherals. + * @details The AVR PAL driver uses the PORT peripherals. * * @section avr_pal_1 Supported HW resources - * - GPIOA. - * - GPIOB. - * - GPIOC. - * - GPIOD. - * - GPIOE. + * - PORTA. + * - PORTB. + * - PORTC. + * - PORTD. + * - PORTE. + * - PORTF. + * - PORTG. + * . + * @section avr_pal_2 AVR PAL driver implementation features + * The AVR PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset functions. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section avr_pal_3 Supported PAL setup modes + * The AVR PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section avr_pal_4 Suboptimal behavior + * The AVR PORT is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * - Group set+reset function is not atomic. + * - Writing on pads/groups/ports programmed as input with pull-up + * resistor changes the resistor setting because the output latch is + * used for resistor selection. + * - The PORT registers layout on some devices is not regular (it does + * not have contiguous PIN, DDR, PORT registers in this order), such + * ports cannot be accessed using the PAL driver. For example, PORT F + * on ATmega128. Verify the user manual of your device. * . * @ingroup AVR_DRIVERS */ -- cgit v1.2.3 From 889cd1ace2dc720546fb509d94783a6e46f842ee Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 15 Oct 2011 11:05:21 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3444 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp | 6 +- docs/reports/STM32L152-32-IAR.txt | 167 ++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+), 3 deletions(-) create mode 100644 docs/reports/STM32L152-32-IAR.txt diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp index c70831761..2ebd37623 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp +++ b/demos/ARMCM3-STM32L152-DISCOVERY/iar/ch.ewp @@ -87,7 +87,7 @@ diff --git a/demos/ARMCM3-STM32F107/keil/ch.uvproj b/demos/ARMCM3-STM32F107/keil/ch.uvproj index 3600bb519..c68d0291f 100644 --- a/demos/ARMCM3-STM32F107/keil/ch.uvproj +++ b/demos/ARMCM3-STM32F107/keil/ch.uvproj @@ -876,16 +876,6 @@ 1 ..\..\..\os\hal\platforms\STM32\serial_lld.c - - stm32_dma.h - 5 - ..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.h - - - stm32_dma.c - 1 - ..\..\..\os\hal\platforms\STM32\DMAv1\stm32_dma.c - pal_lld.h 5 @@ -931,6 +921,16 @@ 5 ..\..\..\os\hal\platforms\STM32F1xx\stm32_rcc.h + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.c + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32F1xx\stm32_dma.h + diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/keil/ch.uvproj b/demos/ARMCM3-STM32L152-DISCOVERY/keil/ch.uvproj new file mode 100644 index 000000000..1e43a6c18 --- /dev/null +++ b/demos/ARMCM3-STM32L152-DISCOVERY/keil/ch.uvproj @@ -0,0 +1,980 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32L152RB + STMicroelectronics + IRAM(0x20000000-0x20003FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + "STARTUP\ST\STM32L1xx\startup_stm32l1xx_md.s" ("STM32L15xx Medium density Startup Code") + ULP2CM3(-O207 -S8 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000) + 5248 + stm32l1xx.h + + + + + + + + + + SFD\ST\STM32L15x\STM32L15x.sfr + 0 + + + + ST\STM32L1xx\ + ST\STM32L1xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x20004000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32\GPIOv2;..\..\..\os\hal\platforms\STM32L1xx;..\..\..\boards\ST_STM32L_DISCOVERY;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\ST_STM32L_DISCOVERY;..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\ST_STM32L_DISCOVERY\board.c + + + board.h + 5 + ..\..\..\boards\ST_STM32L_DISCOVERY\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + nvic.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + nvic.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.h + + + cmparams.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx\cmparams.h + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\STM32L1xx\vectors.s + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + + + platform + + + adc_lld.c + 1 + ..\..\..\os\hal\platforms\STM32L1xx\adc_lld.c + + + adc_lld.h + 5 + ..\..\..\os\hal\platforms\STM32L1xx\adc_lld.h + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32L1xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32L1xx\hal_lld.h + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + pwm_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + pwm_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\serial_lld.c + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\spi_lld.h + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\spi_lld.c + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\serial_lld.h + + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.c + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32L1xx\stm32_dma.h + + + stm32_rcc.h + 5 + ..\..\..\os\hal\platforms\STM32L1xx\stm32_rcc.h + + + stm32l1xx.h + 5 + ..\..\..\os\hal\platforms\STM32L1xx\stm32l1xx.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + + + + + + diff --git a/docs/reports/STM32F100-24-RVCT.txt b/docs/reports/STM32F100-24-RVCT.txt index 29fcd3156..cde37b57c 100644 --- a/docs/reports/STM32F100-24-RVCT.txt +++ b/docs/reports/STM32F100-24-RVCT.txt @@ -1,14 +1,17 @@ *************************************************************************** Options: -O3 -Otime --apcs=interwork Settings: SYSCLK=24, ACR=0x10 (no wait states) -Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation]. +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. *************************************************************************** *** ChibiOS/RT test suite *** -*** Kernel: 2.1.7unstable +*** Kernel: 2.3.4unstable +*** Compiled: Oct 15 2011 - 14:58:38 +*** Compiler: RVCT *** Architecture: ARMv7-M *** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode *** Platform: STM32 Value Line Medium Density *** Test Board: ST STM32VL-Discovery @@ -98,56 +101,56 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation]. --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.1 (Benchmark, messages #1) ---- Score : 99090 msgs/S, 198180 ctxswc/S +--- Score : 101071 msgs/S, 202142 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.2 (Benchmark, messages #2) ---- Score : 86522 msgs/S, 173044 ctxswc/S +--- Score : 86737 msgs/S, 173474 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.3 (Benchmark, messages #3) ---- Score : 86522 msgs/S, 173044 ctxswc/S +--- Score : 86737 msgs/S, 173474 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.4 (Benchmark, context switch) ---- Score : 343016 ctxswc/S +--- Score : 340176 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 65072 threads/S +--- Score : 63779 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 91152 threads/S +--- Score : 91045 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 29264 reschedules/S, 175584 ctxswc/S +--- Score : 29194 reschedules/S, 175164 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 202360 ctxswc/S +--- Score : 203860 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 228520 bytes/S +--- Score : 255612 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 294828 timers/S +--- Score : 311804 timers/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 454856 wait+signal/S +--- Score : 454332 wait+signal/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 277668 lock+unlock/S +--- Score : 274152 lock+unlock/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 360 bytes ---- Thread: 68 bytes +--- System: 376 bytes +--- Thread: 72 bytes --- Timer : 20 bytes --- Semaph: 12 bytes --- EventS: 4 bytes diff --git a/docs/reports/STM32L152-32-RVCT.txt b/docs/reports/STM32L152-32-RVCT.txt new file mode 100644 index 000000000..aadaddb7b --- /dev/null +++ b/docs/reports/STM32L152-32-RVCT.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: SYSCLK=24, ACR=0x10 (no wait states) +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.3.4unstable +*** Compiled: Oct 15 2011 - 15:19:16 +*** Compiler: RVCT +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32L Ultra Low Power Medium Density +*** Test Board: ST STM32L-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 123437 msgs/S, 246874 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 106869 msgs/S, 213738 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 106869 msgs/S, 213738 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 425360 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 78833 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 111359 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 35464 reschedules/S, 212784 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 243100 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 312000 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 361876 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 530708 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 324940 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/readme.txt b/readme.txt index 3b365809d..e6a0d72d8 100644 --- a/readme.txt +++ b/readme.txt @@ -83,6 +83,7 @@ Now makefiles and load script files are requirements and trigger a rebuild if touched. - NEW: Updated AVR demos to use the new PAL driver. +- NEW: Added Keil build files to the STM32L-Discovery demo. - CHANGE: Moved the STM32 DMA helper drivers files under the sub-family specific directories because documentation issues. -- cgit v1.2.3 From 78325ebdf2db30514e6b61e25b0c1894a8e29b79 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 15 Oct 2011 17:29:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3448 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/reports/STM32F103-72-GCC.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/reports/STM32F103-72-GCC.txt b/docs/reports/STM32F103-72-GCC.txt index 0ef3cdd00..b6f829154 100644 --- a/docs/reports/STM32F103-72-GCC.txt +++ b/docs/reports/STM32F103-72-GCC.txt @@ -5,8 +5,8 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) *** ChibiOS/RT test suite *** -*** Kernel: 2.3.3unstable -*** Compiled: Oct 8 2011 - 15:05:49 +*** Kernel: 2.3.4unstable +*** Compiled: Oct 15 2011 - 19:06:16 *** Compiler: GCC 4.6.0 *** Architecture: ARMv7-M *** Core Variant: Cortex-M3 @@ -128,7 +128,7 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 468656 ctxswc/S +--- Score : 468652 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) -- cgit v1.2.3 From 309b1e411426e8d36d9a552ef2870da3db912a80 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 23 Oct 2011 11:39:45 +0000 Subject: Improvements to the USB driver, first phase. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3449 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/main.c | 18 +---- demos/ARM7-AT91SAM7X-FATFS-GCC/main.c | 18 +---- demos/ARMCM3-STM32F103-FATFS/main.c | 18 +---- demos/ARMCM3-STM32F103ZG-FATFS/main.c | 18 +---- demos/PPC-SPC563-GCC/main.c | 18 +---- demos/Posix-GCC/main.c | 18 +---- demos/Win32-MinGW/main.c | 18 +---- os/hal/include/usb.h | 86 +++++++++++++++++---- os/hal/platforms/STM32/USBv1/usb_lld.c | 133 ++++++++++++++------------------- os/hal/platforms/STM32/USBv1/usb_lld.h | 20 ++--- os/hal/src/serial_usb.c | 91 +++++++++++++--------- os/hal/src/usb.c | 107 ++++++-------------------- os/kernel/include/chthreads.h | 10 +++ os/kernel/src/chqueues.c | 23 +++--- readme.txt | 8 ++ testhal/STM32F1xx/USB_CDC/main.c | 17 +---- 16 files changed, 254 insertions(+), 367 deletions(-) diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c index c525cdc54..582135cca 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c @@ -129,23 +129,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { } static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSGQ", - "SNDMSG", - "WTMSG", - "WTQUEUE", - "FINAL" - }; + static const char *states[] = {THD_STATE_NAMES}; Thread *tp; (void)argv; diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c index d761f2b2d..f9a53ae24 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c @@ -129,23 +129,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { } static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSGQ", - "SNDMSG", - "WTMSG", - "WTQUEUE", - "FINAL" - }; + static const char *states[] = {THD_STATE_NAMES}; Thread *tp; (void)argv; diff --git a/demos/ARMCM3-STM32F103-FATFS/main.c b/demos/ARMCM3-STM32F103-FATFS/main.c index a2bc4cf03..a41ea239d 100644 --- a/demos/ARMCM3-STM32F103-FATFS/main.c +++ b/demos/ARMCM3-STM32F103-FATFS/main.c @@ -117,23 +117,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { } static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSGQ", - "SNDMSG", - "WTMSG", - "WTQUEUE", - "FINAL" - }; + static const char *states[] = {THD_STATE_NAMES}; Thread *tp; (void)argv; diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/main.c b/demos/ARMCM3-STM32F103ZG-FATFS/main.c index 258b1f007..0b9020dcf 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/main.c +++ b/demos/ARMCM3-STM32F103ZG-FATFS/main.c @@ -194,23 +194,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { } static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSGQ", - "SNDMSG", - "WTMSG", - "WTQUEUE", - "FINAL" - }; + static const char *states[] = {THD_STATE_NAMES}; Thread *tp; (void)argv; diff --git a/demos/PPC-SPC563-GCC/main.c b/demos/PPC-SPC563-GCC/main.c index aa1b9fd7e..24b831770 100644 --- a/demos/PPC-SPC563-GCC/main.c +++ b/demos/PPC-SPC563-GCC/main.c @@ -44,23 +44,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { } static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSGQ", - "SNDMSG", - "WTMSG", - "WTQUEUE", - "FINAL" - }; + static const char *states[] = {THD_STATE_NAMES}; Thread *tp; (void)argv; diff --git a/demos/Posix-GCC/main.c b/demos/Posix-GCC/main.c index 543386a85..4904edec0 100644 --- a/demos/Posix-GCC/main.c +++ b/demos/Posix-GCC/main.c @@ -51,23 +51,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { } static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSGQ", - "SNDMSG", - "WTMSG", - "WTQUEUE", - "FINAL" - }; + static const char *states[] = {THD_STATE_NAMES}; Thread *tp; (void)argv; diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index a735dfa0c..d4cc554ce 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -49,23 +49,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { } static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSGQ", - "SNDMSG", - "WTMSG", - "WTQUEUE", - "FINAL" - }; + static const char *states[] = {THD_STATE_NAMES}; Thread *tp; (void)argv; diff --git a/os/hal/include/usb.h b/os/hal/include/usb.h index 884b11e8d..18842abd3 100644 --- a/os/hal/include/usb.h +++ b/os/hal/include/usb.h @@ -172,11 +172,6 @@ USB_DESC_BYTE(bInterval) /** @} */ -/** - * @brief Returned by some functions to report a busy endpoint. - */ -#define USB_ENDPOINT_BUSY ((size_t)0xFFFFFFFF) - /** * @name Endpoint types and settings * @{ @@ -362,6 +357,75 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, */ #define usbGetReceiveStatusI(usbp, ep) ((usbp)->receiving & (1 << (ep))) +/** + * @brief Reads from a dedicated packet buffer. + * @pre In order to use this function he endpoint must have been + * initialized in packet mode. + * @note This function can be invoked both in thread and IRQ context. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * @return The received packet size regardless the specified + * @p n parameter. + * @retval 0 Zero size packet received. + * + * @special + */ +#define usbReadPacketBuffer(usbp, ep, buf, n) \ + usb_lld_read_packet_buffer(usbp, ep, buf, n) + +/** + * @brief Writes to a dedicated packet buffer. + * @pre In order to use this function he endpoint must have been + * initialized in packet mode. + * @note This function can be invoked both in thread and IRQ context. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @special + */ +#define usbWritePacketBuffer(usbp, ep, buf, n) \ + usb_lld_write_packet_buffer(usbp, ep, buf, n) + +/** + * @brief Prepares for a receive transaction on an OUT endpoint. + * @pre In order to use this function he endpoint must have been + * initialized in transaction mode. + * @post The endpoint is ready for @p usbStartReceiveI(). + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the received data + * @param[in] n maximum number of bytes to copy + * + * @special + */ +#define usbPrepareReceive(usbp, ep, buf, n) \ + usb_lld_prepare_receive(usbp, ep, buf, n) + +/** + * @brief Prepares for a transmit transaction on an IN endpoint. + * @pre In order to use this function he endpoint must have been + * initialized in transaction mode. + * @post The endpoint is ready for @p usbStartTransmitI(). + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the data to be transmitted + * @param[in] n maximum number of bytes to copy + * + * @special + */ +#define usbPrepareTransmit(usbp, ep, buf, n) \ + usb_lld_prepare_transmit(usbp, ep, buf, n) + /** * @brief Returns the exact size of a receive transaction. * @details The received size can be different from the size specified in @@ -417,7 +481,7 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, * callback in order to read the received setup packet. * @pre In order to use this function the endpoint must have been * initialized as a control endpoint. - * @post The endpoint is ready to accept another packet. + * @note This function can be invoked both in thread and IRQ context. * * @param[in] usbp pointer to the @p USBDriver object * @param[in] ep endpoint number @@ -511,14 +575,8 @@ extern "C" { const USBEndpointConfig *epcp); void usbDisableEndpointsI(USBDriver *usbp); void usbReadSetupI(USBDriver *usbp, usbep_t ep, uint8_t *buf); - size_t usbReadPacketI(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n); - size_t usbWritePacketI(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n); - bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n); - bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n); + bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep); + bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep); bool_t usbStallReceiveI(USBDriver *usbp, usbep_t ep); bool_t usbStallTransmitI(USBDriver *usbp, usbep_t ep); void _usb_reset(USBDriver *usbp); diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.c b/os/hal/platforms/STM32/USBv1/usb_lld.c index 01bc50090..253f45197 100644 --- a/os/hal/platforms/STM32/USBv1/usb_lld.c +++ b/os/hal/platforms/STM32/USBv1/usb_lld.c @@ -109,58 +109,6 @@ static uint32_t pm_alloc(USBDriver *usbp, size_t size) { return next; } -/** - * @brief Copies a packet from memory into a packet buffer. - * - * @param[in] ep endpoint number - * @param[in] buf buffer where to fetch the endpoint data - * @param[in] n maximum number of bytes to copy - */ -static void write_packet(usbep_t ep, const uint8_t *buf, size_t n){ - uint32_t *pmap; - stm32_usb_descriptor_t *udp; - size_t count; - - udp = USB_GET_DESCRIPTOR(ep); - pmap = USB_ADDR2PTR(udp->TXADDR); - udp->TXCOUNT = n; - count = (n + 1) / 2; - while (count) { - *pmap++ = *(uint16_t *)buf; - buf += 2; - count--; - } - EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID); -} - -/** - * @brief Copies a packet from a packet buffer into memory. - * - * @param[in] ep endpoint number - * @param[in] buf buffer where to copy the endpoint data - * @param[in] n maximum number of bytes to copy - * @return The packet size. - * @retval 0 Special case, zero sized packet. - */ -static size_t read_packet(usbep_t ep, uint8_t *buf, size_t n){ - uint32_t *pmap; - stm32_usb_descriptor_t *udp; - size_t count; - - udp = USB_GET_DESCRIPTOR(ep); - pmap = USB_ADDR2PTR(udp->RXADDR); - count = udp->RXCOUNT & RXCOUNT_COUNT_MASK; - if (n > count) - n = count; - count = (n + 1) / 2; - while (count) { - *(uint16_t *)buf = (uint16_t)*pmap++; - buf += 2; - count--; - } - return n; -} - /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -257,7 +205,8 @@ CH_IRQ_HANDLER(Vector90) { n = epcp->in_maxsize; else n = epcp->in_state->txsize; - write_packet(ep, epcp->in_state->txbuf, n); + usb_lld_write_packet_buffer(usbp, ep, epcp->in_state->txbuf, n); + usb_lld_start_in(usbp, ep); } else { /* Transfer completed, invokes the callback.*/ @@ -279,7 +228,10 @@ CH_IRQ_HANDLER(Vector90) { } else { /* Transaction mode.*/ - n = read_packet(ep, epcp->out_state->rxbuf, epcp->out_state->rxsize); + n = usb_lld_read_packet_buffer(usbp, ep, + epcp->out_state->rxbuf, + epcp->out_state->rxsize); + usb_lld_start_out(usbp, ep); epcp->out_state->rxbuf += n; epcp->out_state->rxcnt += n; epcp->out_state->rxsize -= n; @@ -569,14 +521,13 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { *(uint16_t *)buf = (uint16_t)*pmap++; buf += 2; } - EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); } /** - * @brief Reads a packet from the dedicated packet buffer. + * @brief Reads from a dedicated packet buffer. * @pre In order to use this function he endpoint must have been * initialized in packet mode. - * @post The endpoint is ready to accept another packet. + * @note This function can be invoked both in thread and IRQ context. * * @param[in] usbp pointer to the @p USBDriver object * @param[in] ep endpoint number @@ -589,8 +540,8 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { * * @notapi */ -size_t usb_lld_read_packet(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n) { +size_t usb_lld_read_packet_buffer(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n) { uint32_t *pmap; stm32_usb_descriptor_t *udp; size_t count; @@ -607,15 +558,14 @@ size_t usb_lld_read_packet(USBDriver *usbp, usbep_t ep, buf += 2; n--; } - EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); return count; } /** - * @brief Writes a packet to the dedicated packet buffer. + * @brief Writes to a dedicated packet buffer. * @pre In order to use this function he endpoint must have been * initialized in packet mode. - * @post The endpoint is ready to transmit the packet. + * @note This function can be invoked both in thread and IRQ context. * * @param[in] usbp pointer to the @p USBDriver object * @param[in] ep endpoint number @@ -625,8 +575,8 @@ size_t usb_lld_read_packet(USBDriver *usbp, usbep_t ep, * * @notapi */ -void usb_lld_write_packet(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n) { +void usb_lld_write_packet_buffer(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n) { uint32_t *pmap; stm32_usb_descriptor_t *udp; @@ -640,21 +590,20 @@ void usb_lld_write_packet(USBDriver *usbp, usbep_t ep, buf += 2; n--; } - EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID); } /** - * @brief Starts a receive operation on an OUT endpoint. + * @brief Prepares for a receive operation. * * @param[in] usbp pointer to the @p USBDriver object * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the endpoint data - * @param[in] n maximum number of bytes to copy in the buffer + * @param[out] buf buffer where to copy the received data + * @param[in] n maximum number of bytes to copy * * @notapi */ -void usb_lld_start_out(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n) { +void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n) { USBOutEndpointState *osp = usbp->epc[ep]->out_state; osp->rxbuf = buf; @@ -665,21 +614,20 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep, else osp->rxpkts = (uint16_t)((n + usbp->epc[ep]->out_maxsize - 1) / usbp->epc[ep]->out_maxsize); - EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); } /** - * @brief Starts a transmit operation on an IN endpoint. + * @brief Prepares for a transmit operation. * * @param[in] usbp pointer to the @p USBDriver object * @param[in] ep endpoint number - * @param[in] buf buffer where to fetch the endpoint data + * @param[in] buf buffer where to fetch the data to be transmitted * @param[in] n maximum number of bytes to copy * * @notapi */ -void usb_lld_start_in(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n) { +void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n) { USBInEndpointState *isp = usbp->epc[ep]->in_state; isp->txbuf = buf; @@ -687,7 +635,39 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep, isp->txcnt = 0; if (n > (size_t)usbp->epc[ep]->in_maxsize) n = (size_t)usbp->epc[ep]->in_maxsize; - write_packet(ep, buf, n); + usb_lld_write_packet_buffer(usbp, ep, buf, n); +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_RX(ep, EPR_STAT_RX_VALID); +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[in] buf buffer where to fetch the endpoint data + * @param[in] n maximum number of bytes to copy + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { + + (void)usbp; + + EPR_SET_STAT_TX(ep, EPR_STAT_TX_VALID); } /** @@ -701,6 +681,7 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep, void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { (void)usbp; + EPR_SET_STAT_RX(ep, EPR_STAT_RX_STALL); } diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.h b/os/hal/platforms/STM32/USBv1/usb_lld.h index 47160af56..0ee9fd6c2 100644 --- a/os/hal/platforms/STM32/USBv1/usb_lld.h +++ b/os/hal/platforms/STM32/USBv1/usb_lld.h @@ -375,16 +375,18 @@ extern "C" { usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); - size_t usb_lld_read_packet(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n); - void usb_lld_write_packet(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n); - void usb_lld_start_out(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n); - void usb_lld_start_in(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n); - void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + size_t usb_lld_read_packet_buffer(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n); + void usb_lld_write_packet_buffer(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n); + void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n); + void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep); void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); #ifdef __cplusplus diff --git a/os/hal/src/serial_usb.c b/os/hal/src/serial_usb.c index 16822502a..ea434b197 100644 --- a/os/hal/src/serial_usb.c +++ b/os/hal/src/serial_usb.c @@ -118,21 +118,26 @@ static const struct SerialUSBDriverVMT vmt = { */ static void inotify(GenericQueue *qp) { SerialUSBDriver *sdup = (SerialUSBDriver *)qp->q_wrptr; - size_t n; /* Writes to the input queue can only happen when the queue has been emptied, then a whole packet is loaded in the queue.*/ - if (chIQIsEmptyI(&sdup->iqueue)) { - - n = usbReadPacketI(sdup->config->usbp, USB_CDC_DATA_AVAILABLE_EP, - sdup->iqueue.q_buffer, SERIAL_USB_BUFFERS_SIZE); - if (n != USB_ENDPOINT_BUSY) { - chIOAddFlagsI(sdup, IO_INPUT_AVAILABLE); - sdup->iqueue.q_rdptr = sdup->iqueue.q_buffer; - sdup->iqueue.q_counter = n; - while (notempty(&sdup->iqueue.q_waiting)) - chSchReadyI(fifo_remove(&sdup->iqueue.q_waiting))->p_u.rdymsg = Q_OK; - } + if (!usbGetReceiveStatusI(sdup->config->usbp, USB_CDC_DATA_AVAILABLE_EP) && + chIQIsEmptyI(&sdup->iqueue)) { + chSysUnlock(); + + /* Unlocked to make the potentially long read operation preemptable.*/ + size_t n = usbReadPacketBuffer(sdup->config->usbp, + USB_CDC_DATA_AVAILABLE_EP, + sdup->iqueue.q_buffer, + SERIAL_USB_BUFFERS_SIZE); + + chSysLock(); + usbStartReceiveI(sdup->config->usbp, USB_CDC_DATA_AVAILABLE_EP); + chIOAddFlagsI(sdup, IO_INPUT_AVAILABLE); + sdup->iqueue.q_rdptr = sdup->iqueue.q_buffer; + sdup->iqueue.q_counter = n; + while (notempty(&sdup->iqueue.q_waiting)) + chSchReadyI(fifo_remove(&sdup->iqueue.q_waiting))->p_u.rdymsg = Q_OK; } } @@ -141,14 +146,20 @@ static void inotify(GenericQueue *qp) { */ static void onotify(GenericQueue *qp) { SerialUSBDriver *sdup = (SerialUSBDriver *)qp->q_rdptr; - size_t w, n; + size_t n; /* If there is any data in the output queue then it is sent within a single packet and the queue is emptied.*/ n = chOQGetFullI(&sdup->oqueue); - w = usbWritePacketI(sdup->config->usbp, USB_CDC_DATA_REQUEST_EP, - sdup->oqueue.q_buffer, n); - if (w != USB_ENDPOINT_BUSY) { + if (!usbGetTransmitStatusI(sdup->config->usbp, USB_CDC_DATA_REQUEST_EP)) { + chSysUnlock(); + + /* Unlocked to make the potentially long write operation preemptable.*/ + usbWritePacketBuffer(sdup->config->usbp, USB_CDC_DATA_REQUEST_EP, + sdup->oqueue.q_buffer, n); + + chSysLock(); + usbStartTransmitI(sdup->config->usbp, USB_CDC_DATA_REQUEST_EP); chIOAddFlagsI(sdup, IO_OUTPUT_EMPTY); sdup->oqueue.q_wrptr = sdup->oqueue.q_buffer; sdup->oqueue.q_counter = chQSizeI(&sdup->oqueue); @@ -285,21 +296,27 @@ bool_t sduRequestsHook(USBDriver *usbp) { */ void sduDataTransmitted(USBDriver *usbp, usbep_t ep) { SerialUSBDriver *sdup = usbp->param; - size_t n, w; + size_t n; chSysLockFromIsr(); /* If there is any data in the output queue then it is sent within a single packet and the queue is emptied.*/ n = chOQGetFullI(&sdup->oqueue); if (n > 0) { - w = usbWritePacketI(usbp, ep, sdup->oqueue.q_buffer, n); - if (w != USB_ENDPOINT_BUSY) { - chIOAddFlagsI(sdup, IO_OUTPUT_EMPTY); - sdup->oqueue.q_wrptr = sdup->oqueue.q_buffer; - sdup->oqueue.q_counter = chQSizeI(&sdup->oqueue); - while (notempty(&sdup->oqueue.q_waiting)) - chSchReadyI(fifo_remove(&sdup->oqueue.q_waiting))->p_u.rdymsg = Q_OK; - } + /* The endpoint cannot be busy, we are in the context of the callback, + so it is safe to transmit without a check.*/ + chSysUnlockFromIsr(); + + /* Unlocked to make the potentially long write operation preemptable.*/ + usbWritePacketBuffer(usbp, ep, sdup->oqueue.q_buffer, n); + + chSysLockFromIsr(); + usbStartTransmitI(usbp, ep); + chIOAddFlagsI(sdup, IO_OUTPUT_EMPTY); + sdup->oqueue.q_wrptr = sdup->oqueue.q_buffer; + sdup->oqueue.q_counter = chQSizeI(&sdup->oqueue); + while (notempty(&sdup->oqueue.q_waiting)) + chSchReadyI(fifo_remove(&sdup->oqueue.q_waiting))->p_u.rdymsg = Q_OK; } chSysUnlockFromIsr(); } @@ -319,17 +336,23 @@ void sduDataReceived(USBDriver *usbp, usbep_t ep) { /* Writes to the input queue can only happen when the queue has been emptied, then a whole packet is loaded in the queue.*/ if (chIQIsEmptyI(&sdup->iqueue)) { + /* The endpoint cannot be busy, we are in the context of the callback, + so a packet is in the buffer for sure.*/ size_t n; - n = usbReadPacketI(usbp, ep, sdup->iqueue.q_buffer, - SERIAL_USB_BUFFERS_SIZE); - if (n != USB_ENDPOINT_BUSY) { - chIOAddFlagsI(sdup, IO_INPUT_AVAILABLE); - sdup->iqueue.q_rdptr = sdup->iqueue.q_buffer; - sdup->iqueue.q_counter = n; - while (notempty(&sdup->iqueue.q_waiting)) - chSchReadyI(fifo_remove(&sdup->iqueue.q_waiting))->p_u.rdymsg = Q_OK; - } + chSysUnlockFromIsr(); + + /* Unlocked to make the potentially long write operation preemptable.*/ + n = usbReadPacketBuffer(usbp, ep, sdup->iqueue.q_buffer, + SERIAL_USB_BUFFERS_SIZE); + + chSysLockFromIsr(); + usbStartReceiveI(usbp, ep); + chIOAddFlagsI(sdup, IO_INPUT_AVAILABLE); + sdup->iqueue.q_rdptr = sdup->iqueue.q_buffer; + sdup->iqueue.q_counter = n; + while (notempty(&sdup->iqueue.q_waiting)) + chSchReadyI(fifo_remove(&sdup->iqueue.q_waiting))->p_u.rdymsg = Q_OK; } chSysUnlockFromIsr(); } diff --git a/os/hal/src/usb.c b/os/hal/src/usb.c index 44a772ab1..30919580c 100644 --- a/os/hal/src/usb.c +++ b/os/hal/src/usb.c @@ -309,7 +309,7 @@ void usbInitEndpointI(USBDriver *usbp, usbep_t ep, chDbgCheck((usbp != NULL) && (epcp != NULL), "usbInitEndpointI"); chDbgAssert(usbp->state == USB_ACTIVE, "usbEnableEndpointI(), #1", "invalid state"); - chDbgAssert(usbp->epc[ep] != NULL, + chDbgAssert(usbp->epc[ep] == NULL, "usbEnableEndpointI(), #2", "already initialized"); /* Logically enabling the endpoint in the USBDriver structure.*/ @@ -351,127 +351,55 @@ void usbDisableEndpointsI(USBDriver *usbp) { usb_lld_disable_endpoints(usbp); } -/** - * @brief Reads a packet from the dedicated packet buffer. - * @pre In order to use this function he endpoint must have been - * initialized in packet mode. - * @post The endpoint is ready to accept another packet. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the packet data - * @param[in] n maximum number of bytes to copy. This value must - * not exceed the maximum packet size for this endpoint. - * @return The received packet size regardless the specified - * @p n parameter. - * @retval USB_ENDPOINT_BUSY Endpoint busy receiving. - * @retval 0 Zero size packet received. - * - * @iclass - */ -size_t usbReadPacketI(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n) { - - chDbgCheckClassI(); - chDbgCheck((usbp != NULL) && (buf != NULL), "usbReadPacketI"); - - if (usbGetReceiveStatusI(usbp, ep)) - return USB_ENDPOINT_BUSY; - - usbp->receiving |= (1 << ep); - return usb_lld_read_packet(usbp, ep, buf, n);; -} - -/** - * @brief Writes a packet to the dedicated packet buffer. - * @pre In order to use this function he endpoint must have been - * initialized in packet mode. - * @post The endpoint is ready to transmit the packet. - * - * @param[in] usbp pointer to the @p USBDriver object - * @param[in] ep endpoint number - * @param[in] buf buffer where to fetch the packet data - * @param[in] n maximum number of bytes to copy. This value must - * not exceed the maximum packet size for this endpoint. - * @return The operation status. - * @retval USB_ENDPOINT_BUSY Endpoint busy transmitting. - * @retval 0 Operation complete. - * - * @iclass - */ -size_t usbWritePacketI(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n) { - - chDbgCheckClassI(); - chDbgCheck((usbp != NULL) && (buf != NULL), "usbWritePacketI"); - - if (usbGetTransmitStatusI(usbp, ep)) - return USB_ENDPOINT_BUSY; - - usbp->transmitting |= (1 << ep); - usb_lld_write_packet(usbp, ep, buf, n); - return 0; -} - /** * @brief Starts a receive transaction on an OUT endpoint. - * @pre In order to use this function he endpoint must have been - * initialized in transaction mode. * @post The endpoint callback is invoked when the transfer has been * completed. * * @param[in] usbp pointer to the @p USBDriver object * @param[in] ep endpoint number - * @param[out] buf buffer where to copy the received data - * @param[in] n maximum number of bytes to copy * @return The operation status. * @retval FALSE Operation started successfully. * @retval TRUE Endpoint busy, operation not started. * * @iclass */ -bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep, - uint8_t *buf, size_t n) { +bool_t usbStartReceiveI(USBDriver *usbp, usbep_t ep) { chDbgCheckClassI(); - chDbgCheck((usbp != NULL) && (buf != NULL), "usbStartReceiveI"); + chDbgCheck(usbp != NULL, "usbStartReceiveI"); if (usbGetReceiveStatusI(usbp, ep)) return TRUE; usbp->receiving |= (1 << ep); - usb_lld_start_out(usbp, ep, buf, n); + usb_lld_start_out(usbp, ep); return FALSE; } /** * @brief Starts a transmit transaction on an IN endpoint. - * @pre In order to use this function he endpoint must have been - * initialized in transaction mode. * @post The endpoint callback is invoked when the transfer has been * completed. * * @param[in] usbp pointer to the @p USBDriver object * @param[in] ep endpoint number - * @param[in] buf buffer where to fetch the data to be transmitted - * @param[in] n maximum number of bytes to copy * @return The operation status. * @retval FALSE Operation started successfully. * @retval TRUE Endpoint busy, operation not started. * * @iclass */ -bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep, - const uint8_t *buf, size_t n) { +bool_t usbStartTransmitI(USBDriver *usbp, usbep_t ep) { chDbgCheckClassI(); - chDbgCheck((usbp != NULL) && (buf != NULL), "usbStartTransmitI"); + chDbgCheck(usbp != NULL, "usbStartTransmitI"); if (usbGetTransmitStatusI(usbp, ep)) return TRUE; usbp->transmitting |= (1 << ep); - usb_lld_start_in(usbp, ep, buf, n); + usb_lld_start_in(usbp, ep); return FALSE; } @@ -597,13 +525,15 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) { if (usbp->ep0n > 0) { /* Starts the transmit phase.*/ usbp->ep0state = USB_EP0_TX; - usb_lld_start_in(usbp, 0, usbp->ep0next, usbp->ep0n); + usb_lld_prepare_transmit(usbp, 0, usbp->ep0next, usbp->ep0n); + usb_lld_start_in(usbp, 0); } else { /* No transmission phase, directly receiving the zero sized status packet.*/ usbp->ep0state = USB_EP0_WAITING_STS; - usb_lld_start_out(usbp, 0, NULL, 0); + usb_lld_prepare_receive(usbp, 0, NULL, 0); + usb_lld_start_out(usbp, 0); } } else { @@ -611,13 +541,15 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) { if (usbp->ep0n > 0) { /* Starts the receive phase.*/ usbp->ep0state = USB_EP0_RX; - usb_lld_start_out(usbp, 0, usbp->ep0next, usbp->ep0n); + usb_lld_prepare_receive(usbp, 0, usbp->ep0next, usbp->ep0n); + usb_lld_start_out(usbp, 0); } else { /* No receive phase, directly sending the zero sized status packet.*/ usbp->ep0state = USB_EP0_SENDING_STS; - usb_lld_start_in(usbp, 0, NULL, 0); + usb_lld_prepare_transmit(usbp, 0, NULL, 0); + usb_lld_start_in(usbp, 0); } } } @@ -644,13 +576,15 @@ void _usb_ep0in(USBDriver *usbp, usbep_t ep) { transmitted.*/ if ((usbp->ep0n < max) && ((usbp->ep0n % usbp->epc[0]->in_maxsize) == 0)) { - usb_lld_start_in(usbp, 0, NULL, 0); + usb_lld_prepare_transmit(usbp, 0, NULL, 0); + usb_lld_start_in(usbp, 0); return; } /* Transmit phase over, receiving the zero sized status packet.*/ usbp->ep0state = USB_EP0_WAITING_STS; - usb_lld_start_out(usbp, 0, NULL, 0); + usb_lld_prepare_receive(usbp, 0, NULL, 0); + usb_lld_start_out(usbp, 0); return; case USB_EP0_SENDING_STS: /* Status packet sent, invoking the callback if defined.*/ @@ -687,7 +621,8 @@ void _usb_ep0out(USBDriver *usbp, usbep_t ep) { case USB_EP0_RX: /* Receive phase over, sending the zero sized status packet.*/ usbp->ep0state = USB_EP0_SENDING_STS; - usb_lld_start_in(usbp, 0, NULL, 0); + usb_lld_prepare_transmit(usbp, 0, NULL, 0); + usb_lld_start_in(usbp, 0); return; case USB_EP0_WAITING_STS: /* Status packet received, it must be zero sized, invoking the callback diff --git a/os/kernel/include/chthreads.h b/os/kernel/include/chthreads.h index 582b4e1e1..5848d5643 100644 --- a/os/kernel/include/chthreads.h +++ b/os/kernel/include/chthreads.h @@ -51,6 +51,16 @@ #define THD_STATE_WTMSG 12 /**< @brief Waiting for a message. */ #define THD_STATE_WTQUEUE 13 /**< @brief Waiting on an I/O queue. */ #define THD_STATE_FINAL 14 /**< @brief Thread terminated. */ + +/** + * @brief Thread states as array of strings. + * @details Each element in an array initialized with this macro can be + * indexed using the numeric thread state values. + */ +#define THD_STATE_NAMES \ + "READY", "CURRENT", "SUSPENDED", "WTSEM", "WTMTX", "WTCOND", "SLEEPING", \ + "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", "SNDMSG", "WTMSG", "WTQUEUE", \ + "FINAL" /** @} */ /** diff --git a/os/kernel/src/chqueues.c b/os/kernel/src/chqueues.c index cf3d21732..b32ccf803 100644 --- a/os/kernel/src/chqueues.c +++ b/os/kernel/src/chqueues.c @@ -152,9 +152,8 @@ msg_t chIQPutI(InputQueue *iqp, uint8_t b) { * @details This function reads a byte value from an input queue. If the queue * is empty then the calling thread is suspended until a byte arrives * in the queue or a timeout occurs. - * @note The callback is invoked if the queue is empty before entering the - * @p THD_STATE_WTQUEUE state in order to solicit the low level to - * start queue filling. + * @note The callback is invoked before reading the character from the + * buffer or before entering the state @p THD_STATE_WTQUEUE. * * @param[in] iqp pointer to an @p InputQueue structure * @param[in] time the number of ticks before the operation timeouts, @@ -172,12 +171,11 @@ msg_t chIQGetTimeout(InputQueue *iqp, systime_t time) { uint8_t b; chSysLock(); + if (iqp->q_notify) + iqp->q_notify(iqp); + while (chIQIsEmptyI(iqp)) { msg_t msg; - - if (iqp->q_notify) - iqp->q_notify(iqp); - if ((msg = qwait((GenericQueue *)iqp, time)) < Q_OK) { chSysUnlock(); return msg; @@ -201,9 +199,8 @@ msg_t chIQGetTimeout(InputQueue *iqp, systime_t time) { * been reset. * @note The function is not atomic, if you need atomicity it is suggested * to use a semaphore or a mutex for mutual exclusion. - * @note The callback is invoked if the queue is empty before entering the - * @p THD_STATE_WTQUEUE state in order to solicit the low level to - * start queue filling. + * @note The callback is invoked before reading each character from the + * buffer or before entering the state @p THD_STATE_WTQUEUE. * * @param[in] iqp pointer to an @p InputQueue structure * @param[out] bp pointer to the data buffer @@ -227,10 +224,10 @@ size_t chIQReadTimeout(InputQueue *iqp, uint8_t *bp, chSysLock(); while (TRUE) { - while (chIQIsEmptyI(iqp)) { - if (nfy) - nfy(iqp); + if (nfy) + nfy(iqp); + while (chIQIsEmptyI(iqp)) { if (qwait((GenericQueue *)iqp, time) != Q_OK) { chSysUnlock(); return r; diff --git a/readme.txt b/readme.txt index e6a0d72d8..2b4eb54ed 100644 --- a/readme.txt +++ b/readme.txt @@ -76,6 +76,11 @@ *** 2.3.4 *** - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). +- NEW: Updated USB driver model and STM32 implementation. Updated the + SERIAL_USB driver to match the new API. Fixed several problems in + both drivers. +- NEW: Added a macro THD_STATE_NAMES to chthreads.h. This macro is an + initializer for string arrays containing thread state names. - NEW: Added memory copy functionality to the STM32 DMA driver. - NEW: Implemented new makefile system for ARM GCC ports, now objects, listings and output files are generated into a "build" directory and not @@ -84,6 +89,9 @@ rebuild if touched. - NEW: Updated AVR demos to use the new PAL driver. - NEW: Added Keil build files to the STM32L-Discovery demo. +- CHANGE: Now the callback associated to input queues is invoked before + reading each character. Previously it was invoked only before going + to sleep into the THD_STATE_WTQUEUE state. - CHANGE: Moved the STM32 DMA helper drivers files under the sub-family specific directories because documentation issues. diff --git a/testhal/STM32F1xx/USB_CDC/main.c b/testhal/STM32F1xx/USB_CDC/main.c index 601b6ce0b..2c46eb11b 100644 --- a/testhal/STM32F1xx/USB_CDC/main.c +++ b/testhal/STM32F1xx/USB_CDC/main.c @@ -332,22 +332,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { } static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { - static const char *states[] = { - "READY", - "CURRENT", - "SUSPENDED", - "WTSEM", - "WTMTX", - "WTCOND", - "SLEEPING", - "WTEXIT", - "WTOREVT", - "WTANDEVT", - "SNDMSGQ", - "SNDMSG", - "WTMSG", - "FINAL" - }; + static const char *states[] = {THD_STATE_NAMES}; Thread *tp; (void)argv; -- cgit v1.2.3 From 53df7ed814f665ebeef75b379941f9c0cebcba55 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 23 Oct 2011 11:51:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3450 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/dox/usb.dox | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/os/hal/dox/usb.dox b/os/hal/dox/usb.dox index 62b3aaf12..5778cc1a7 100644 --- a/os/hal/dox/usb.dox +++ b/os/hal/dox/usb.dox @@ -132,9 +132,9 @@ receiving [label="EP_BUSY\nReceiving Packet"]; idle [label="EP_IDLE\nPacket in Buffer"]; - disabled -> receiving [label="\usbInitEndpointI()"]; + disabled -> receiving [label="\nusbInitEndpointI()"]; receiving -> idle [label="\npacket received\n>out_cb<"]; - idle -> receiving [label="\nusbReadPacketI()"]; + idle -> receiving [label="\nusbReadPacketBuffer()\nusbStartReceiveI()"]; receiving -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; } @@ -152,8 +152,8 @@ transmitting [label="EP_BUSY\nSending Packet"]; idle [label="EP_IDLE\nBuffer Empty"]; - disabled -> idle [label="\usbInitEndpointI()"]; - idle -> transmitting [label="\nusbWritePacketI()"]; + disabled -> idle [label="\nusbInitEndpointI()"]; + idle -> transmitting [label="\nusbWritePacketBuffer()\nusbStartTransmitI()"]; transmitting -> idle [label="\npacket sent\n>in_cb<"]; transmitting -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; idle -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; @@ -176,8 +176,8 @@ receiving [label="EP_BUSY\nReceiving"]; idle [label="EP_IDLE\nReady"]; - disabled -> idle [label="\usbInitEndpointI()"]; - idle -> receiving [label="\usbStartReceiveI()"]; + disabled -> idle [label="\nusbInitEndpointI()"]; + idle -> receiving [label="\nusbPrepareReceive()\nusbStartReceiveI()"]; receiving -> receiving [label="\nmore packets"]; receiving -> idle [label="\nreception end\n>out_cb<"]; receiving -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; @@ -198,7 +198,7 @@ idle [label="EP_IDLE\nReady"]; disabled -> idle [label="\usbInitEndpointI()"]; - idle -> transmitting [label="\nusbStartTransmitI()"]; + idle -> transmitting [label="\nusbPrepareTransmit()\nusbStartTransmitI()"]; transmitting -> transmitting [label="\nmore packets"]; transmitting -> idle [label="\ntransmission end\n>in_cb<"]; transmitting -> disabled [label="\nUSB RESET\nusbDisableEndpointsI()"]; -- cgit v1.2.3 From 2f572f109a463e7faa46ed544c91198e72e63343 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 23 Oct 2011 12:21:44 +0000 Subject: USB enhancements, phase two. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3451 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_STM32_P103/board.h | 10 ++++++++++ os/hal/include/usb.h | 10 ++++++++++ os/various/shell.c | 2 +- readme.txt | 12 +++++++++--- testhal/STM32F1xx/USB_CDC/main.c | 1 + 5 files changed, 31 insertions(+), 4 deletions(-) diff --git a/boards/OLIMEX_STM32_P103/board.h b/boards/OLIMEX_STM32_P103/board.h index 337fc8ca0..699e9ad46 100644 --- a/boards/OLIMEX_STM32_P103/board.h +++ b/boards/OLIMEX_STM32_P103/board.h @@ -135,6 +135,16 @@ #define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ #define VAL_GPIOEODR 0xFFFFFFFF +/* + * USB bus activation macro, required by the USB driver. + */ +#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC) + +/* + * USB bus de-activation macro, required by the USB driver. + */ +#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC) + #if !defined(_FROM_ASM_) #ifdef __cplusplus extern "C" { diff --git a/os/hal/include/usb.h b/os/hal/include/usb.h index 18842abd3..bc4418f6b 100644 --- a/os/hal/include/usb.h +++ b/os/hal/include/usb.h @@ -321,6 +321,16 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, * @name Macro Functions * @{ */ +/** + * @brief Connects the USB device. + */ +#define usbConnectBus(usbp) usb_lld_connect_bus(usbp) + +/** + * @brief Disconnect the USB device. + */ +#define usbDisconnectBus(usbp) usb_lld_disconnect_bus(usbp) + /** * @brief Returns the current frame number. * diff --git a/os/various/shell.c b/os/various/shell.c index a99f2657c..4c84a7b51 100644 --- a/os/various/shell.c +++ b/os/various/shell.c @@ -204,7 +204,7 @@ static msg_t shell_thread(void *p) { there is not a chSysUnlock() because the thread terminates upon return.*/ chSysLock(); chEvtBroadcastI(&shell_terminated); - return msg; + chThdExitS(msg); } /** diff --git a/readme.txt b/readme.txt index 2b4eb54ed..4b15c2dca 100644 --- a/readme.txt +++ b/readme.txt @@ -76,9 +76,15 @@ *** 2.3.4 *** - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). -- NEW: Updated USB driver model and STM32 implementation. Updated the - SERIAL_USB driver to match the new API. Fixed several problems in - both drivers. +- NEW: Updated USB driver model and STM32 implementation and fixed several + problems. + - Changed the API to move buffer copy operations out of critical zones. + - Added usbConnectBus() and usbDisconnectBus() functions. + - Fixed problems with incorrect assertions. +- NEW Updated the SERIAL_USB driver to match the new USB API, also fixed + some problems. + - Fixed incorrect use of input queues, the change required a change in + input queues too. - NEW: Added a macro THD_STATE_NAMES to chthreads.h. This macro is an initializer for string arrays containing thread state names. - NEW: Added memory copy functionality to the STM32 DMA driver. diff --git a/testhal/STM32F1xx/USB_CDC/main.c b/testhal/STM32F1xx/USB_CDC/main.c index 2c46eb11b..9e05edbdb 100644 --- a/testhal/STM32F1xx/USB_CDC/main.c +++ b/testhal/STM32F1xx/USB_CDC/main.c @@ -421,6 +421,7 @@ int main(void) { */ sduObjectInit(&SDU1); sduStart(&SDU1, &serusbcfg); + usbConnectBus(serusbcfg.usbp); palClearPad(GPIOC, GPIOC_USB_DISC); /* -- cgit v1.2.3 From befe9632df5540514af04a9e7a084a50778873e8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 25 Oct 2011 19:56:00 +0000 Subject: Fixed a small documentation error in port_unlock() implementations. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3452 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/kernel/templates/chcore.c | 2 +- os/ports/GCC/ARM/chcore.h | 2 +- os/ports/GCC/ARMCMx/chcore_v6m.h | 2 +- os/ports/GCC/ARMCMx/chcore_v7m.h | 2 +- os/ports/GCC/AVR/chcore.h | 2 +- os/ports/GCC/MSP430/chcore.h | 2 +- os/ports/IAR/ARMCMx/chcore_v6m.h | 2 +- os/ports/IAR/ARMCMx/chcore_v7m.h | 2 +- os/ports/RVCT/ARMCMx/chcore_v6m.h | 2 +- os/ports/RVCT/ARMCMx/chcore_v7m.h | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/os/kernel/templates/chcore.c b/os/kernel/templates/chcore.c index 74281f759..25a3b42a0 100644 --- a/os/kernel/templates/chcore.c +++ b/os/kernel/templates/chcore.c @@ -50,7 +50,7 @@ void port_lock(void) { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform more + * @details Usually this function just enables interrupts but may perform more * actions. */ void port_unlock(void) { diff --git a/os/ports/GCC/ARM/chcore.h b/os/ports/GCC/ARM/chcore.h index f23048e4c..1e9877c61 100644 --- a/os/ports/GCC/ARM/chcore.h +++ b/os/ports/GCC/ARM/chcore.h @@ -347,7 +347,7 @@ struct context { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform + * @details Usually this function just enables interrupts but may perform * more actions. * @note In this port it enables both the IRQ and FIQ sources. */ diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h index b98be1166..71fffdac8 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.h +++ b/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -176,7 +176,7 @@ struct intctx { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform + * @details Usually this function just enables interrupts but may perform * more actions. */ #define port_unlock() asm volatile ("cpsie i" : : : "memory") diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index 3710c2edf..a2427c27e 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -224,7 +224,7 @@ struct intctx { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform + * @details Usually this function just enables interrupts but may perform * more actions. * @note In this port this it lowers the base priority to user level. */ diff --git a/os/ports/GCC/AVR/chcore.h b/os/ports/GCC/AVR/chcore.h index 282ec5a16..88001a73d 100644 --- a/os/ports/GCC/AVR/chcore.h +++ b/os/ports/GCC/AVR/chcore.h @@ -248,7 +248,7 @@ struct context { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform more + * @details Usually this function just enables interrupts but may perform more * actions. * @note Implemented as global interrupt enable. */ diff --git a/os/ports/GCC/MSP430/chcore.h b/os/ports/GCC/MSP430/chcore.h index c969a6b16..e31a23307 100644 --- a/os/ports/GCC/MSP430/chcore.h +++ b/os/ports/GCC/MSP430/chcore.h @@ -217,7 +217,7 @@ struct context { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform more + * @details Usually this function just enables interrupts but may perform more * actions. * @note Implemented as global interrupt enable. */ diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h index 0480451c0..a7e59e8fd 100644 --- a/os/ports/IAR/ARMCMx/chcore_v6m.h +++ b/os/ports/IAR/ARMCMx/chcore_v6m.h @@ -174,7 +174,7 @@ struct intctx { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform + * @details Usually this function just enables interrupts but may perform * more actions. */ #define port_unlock() __enable_interrupt() diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.h b/os/ports/IAR/ARMCMx/chcore_v7m.h index 086a99d39..ee077749c 100644 --- a/os/ports/IAR/ARMCMx/chcore_v7m.h +++ b/os/ports/IAR/ARMCMx/chcore_v7m.h @@ -215,7 +215,7 @@ struct intctx { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform + * @details Usually this function just enables interrupts but may perform * more actions. * @note In this port this it lowers the base priority to user level. */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h index bdeec1674..a2598f03a 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v6m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h @@ -174,7 +174,7 @@ struct intctx { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform + * @details Usually this function just enables interrupts but may perform * more actions. */ #define port_unlock() __enable_irq() diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h index 17447476f..ef04fa15e 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v7m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -218,7 +218,7 @@ struct intctx { /** * @brief Kernel-unlock action. - * @details Usually this function just disables interrupts but may perform + * @details Usually this function just enables interrupts but may perform * more actions. * @note In this port this it lowers the base priority to user level. */ -- cgit v1.2.3 From 267e558ee47441126a6e54312a3529a8c4564f76 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 26 Oct 2011 17:49:51 +0000 Subject: I2C. Fixed warning. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3453 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 317fc57dd..a0914e819 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -277,8 +277,9 @@ void _i2c_ev7_master_rec_byte_qued(I2CDriver *i2cp){ rxBuffp++; (i2cp->rxbytes)--; } - else + else{ _i2c_unhandled_case(i2cp); + } break; default: -- cgit v1.2.3 From 71ff7f78d21d33ad39ecbbe356adca26d86de87b Mon Sep 17 00:00:00 2001 From: barthess Date: Thu, 27 Oct 2011 08:00:32 +0000 Subject: I2C. Dead code removing. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3454 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.h | 1 - 1 file changed, 1 deletion(-) diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index 548b5418e..b66ba5d6a 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -164,7 +164,6 @@ typedef struct { i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode duty cycle */ uint8_t own_addr_7; /**< @brief Specifies the first device 7-bit own address. */ uint16_t own_addr_10; /**< @brief Specifies the second part of device own address in 10-bit mode. Set to NULL if not used. */ - uint16_t ack; /**< @brief Enables or disables the acknowledgment. */ uint8_t nbit_own_addr; /**< @brief Specifies if 7-bit or 10-bit address is acknowledged */ } I2CConfig; -- cgit v1.2.3 From 113f63e33f8a1ebd0e5d8689ee4183f1d3b2ba47 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 30 Oct 2011 07:45:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3455 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/USBv1/stm32_usb.h | 16 ++++++++++++---- os/hal/platforms/STM32/USBv1/usb_lld.c | 14 +++++++------- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/os/hal/platforms/STM32/USBv1/stm32_usb.h b/os/hal/platforms/STM32/USBv1/stm32_usb.h index 7ba03350a..d5701c192 100644 --- a/os/hal/platforms/STM32/USBv1/stm32_usb.h +++ b/os/hal/platforms/STM32/USBv1/stm32_usb.h @@ -80,17 +80,25 @@ typedef struct { */ volatile uint32_t TXADDR; /** - * @brief TX counter register. + * @brief TX counter register 0. */ - volatile uint32_t TXCOUNT; + volatile uint16_t TXCOUNT0; + /** + * @brief TX counter register 1. + */ + volatile uint16_t TXCOUNT1; /** * @brief RX buffer offset register. */ volatile uint32_t RXADDR; /** - * @brief RX counter register. + * @brief RX counter register 0. + */ + volatile uint16_t RXCOUNT0; + /** + * @brief RX counter register 1. */ - volatile uint32_t RXCOUNT; + volatile uint16_t RXCOUNT1; } stm32_usb_descriptor_t; /** diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.c b/os/hal/platforms/STM32/USBv1/usb_lld.c index 253f45197..b81766f6d 100644 --- a/os/hal/platforms/STM32/USBv1/usb_lld.c +++ b/os/hal/platforms/STM32/USBv1/usb_lld.c @@ -195,7 +195,7 @@ CH_IRQ_HANDLER(Vector90) { } else { /* Transaction mode.*/ - n = USB_GET_DESCRIPTOR(ep)->TXCOUNT; + n = (size_t)USB_GET_DESCRIPTOR(ep)->TXCOUNT0; epcp->in_state->txbuf += n; epcp->in_state->txcnt += n; epcp->in_state->txsize -= n; @@ -419,10 +419,10 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { else nblocks = ((((epcp->out_maxsize - 1) | 1) + 1) / 2) << 10; dp = USB_GET_DESCRIPTOR(ep); - dp->TXCOUNT = 0; - dp->RXCOUNT = nblocks; - dp->TXADDR = pm_alloc(usbp, epcp->in_maxsize); - dp->RXADDR = pm_alloc(usbp, epcp->out_maxsize); + dp->TXCOUNT0 = 0; + dp->RXCOUNT0 = nblocks; + dp->TXADDR = pm_alloc(usbp, epcp->in_maxsize); + dp->RXADDR = pm_alloc(usbp, epcp->out_maxsize); } /** @@ -549,7 +549,7 @@ size_t usb_lld_read_packet_buffer(USBDriver *usbp, usbep_t ep, (void)usbp; udp = USB_GET_DESCRIPTOR(ep); pmap = USB_ADDR2PTR(udp->RXADDR); - count = udp->RXCOUNT & RXCOUNT_COUNT_MASK; + count = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK; if (n > count) n = count; n = (n + 1) / 2; @@ -583,7 +583,7 @@ void usb_lld_write_packet_buffer(USBDriver *usbp, usbep_t ep, (void)usbp; udp = USB_GET_DESCRIPTOR(ep); pmap = USB_ADDR2PTR(udp->TXADDR); - udp->TXCOUNT = n; + udp->TXCOUNT0 = (uint16_t)n; n = (n + 1) / 2; while (n > 0) { *pmap++ = *(uint16_t *)buf; -- cgit v1.2.3 From 2e4d6bc9abce18f10967536c2c2b2512593b6421 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 30 Oct 2011 08:03:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3456 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/USBv1/stm32_usb.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/os/hal/platforms/STM32/USBv1/stm32_usb.h b/os/hal/platforms/STM32/USBv1/stm32_usb.h index d5701c192..b06e8d887 100644 --- a/os/hal/platforms/STM32/USBv1/stm32_usb.h +++ b/os/hal/platforms/STM32/USBv1/stm32_usb.h @@ -140,6 +140,7 @@ typedef struct { #define EPR_STAT_TX_NAK 0x0020 #define EPR_STAT_TX_VALID 0x0030 #define EPR_DTOG_TX 0x0040 +#define EPR_SWBUF_RX 0x0040 #define EPR_CTR_TX 0x0080 #define EPR_EP_KIND 0x0100 #define EPR_EP_TYPE_MASK 0x0600 @@ -154,6 +155,7 @@ typedef struct { #define EPR_STAT_RX_NAK 0x2000 #define EPR_STAT_RX_VALID 0x3000 #define EPR_DTOG_RX 0x4000 +#define EPR_SWBUF_TX 0x4000 #define EPR_CTR_RX 0x8000 #define CNTR_FRES 0x0001 -- cgit v1.2.3 From 8912d9fea23f516281c150fb5f3a101f4338a37d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 30 Oct 2011 10:09:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3457 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/AT91SAM7/ext_lld.c | 238 ++++++++++++++++++++++++++++++++ os/hal/platforms/AT91SAM7/ext_lld.h | 249 ++++++++++++++++++++++++++++++++++ os/hal/platforms/AT91SAM7/platform.mk | 1 + readme.txt | 2 + 4 files changed, 490 insertions(+) create mode 100644 os/hal/platforms/AT91SAM7/ext_lld.c create mode 100644 os/hal/platforms/AT91SAM7/ext_lld.h diff --git a/os/hal/platforms/AT91SAM7/ext_lld.c b/os/hal/platforms/AT91SAM7/ext_lld.c new file mode 100644 index 000000000..2dbfc1562 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/ext_lld.c @@ -0,0 +1,238 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio, + 2011 Florian Goebe, Chair for Computer Science 11, + RWTH Aachen University + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + */ + +/** + * @file STM32/ext_lld.c + * @brief STM32 EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTDA driver identifier. + */ +EXTDriver EXTDA; + +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) +/** + * @brief EXTDB driver identifier. + */ +EXTDriver EXTDB; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Handles external interrupts. + * + * @param[in] extp pointer to the driver that received the interrupt + */ +static void ext_lld_serveInterrupt(EXTDriver *extp) { + uint32_t irqFlags; + uint32_t ch; + + chSysLockFromIsr(); + + /* Read flags of pending PIO interrupts.*/ + irqFlags = extp->pio->PIO_ISR; + + /* Call callback function for any pending interrupt.*/ + for(ch = 0; ch < 32; ch++) { + + /* Check if the channel is activated and if its IRQ flag is set.*/ + if((extp->config->channels[ch].mode & + EXT_CH_MODE_ENABLED & EXT_CH_MODE_EDGES_MASK) + && ((1 << ch) & irqFlags)) { + (extp->config->channels[ch].cb)(extp, ch); + } + } + + chSysUnlockFromIsr(); + + AT91C_BASE_AIC->AIC_EOICR = 0; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTIA_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + ext_lld_serveInterrupt(&EXTDA); + + CH_IRQ_EPILOGUE(); +} + +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(EXTIB_IRQHandler) { + CH_IRQ_PROLOGUE(); + + ext_lld_serveInterrupt(&EXTDB); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) { + + /* Driver initialization.*/ + extObjectInit(&EXTDA); + + /* Set PIO base addresses.*/ + EXTDA.pio = AT91C_BASE_PIOA; + + /* Set peripheral IDs.*/ + EXTDA.pid = AT91C_ID_PIOA; + +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) + /* Aame for PIOB.*/ + extObjectInit(&EXTDB); + EXTDB.pio = AT91C_BASE_PIOB; + EXTDB.pid = AT91C_ID_PIOB; +#endif +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) { + uint16_t ch; + uint32_t ier = 0; + const EXTConfig *config = extp->config; + + switch(extp->pid) { + case AT91C_ID_PIOA: + AIC_ConfigureIT(AT91C_ID_PIOA, SAM7_computeSMR(config->mode, + config->priority), + EXTIA_IRQHandler); + break; +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) + case AT91C_ID_PIOB: + AIC_ConfigureIT(AT91C_ID_PIOB, SAM7_computeSMR(config->mode, + config->priority), + EXTIB_IRQHandler); + break; +#endif + } + + /* Enable and Disable channels with respect to config.*/ + for(ch = 0; ch < EXT_MAX_CHANNELS; ch++) { + ier |= (config->channels[ch].mode & EXT_CH_MODE_EDGES_MASK & EXT_CH_MODE_ENABLED ? 1 : 0) << ch; + } + extp->pio->PIO_IER = ier; + extp->pio->PIO_IDR = ~ier; + + /* Enable interrupt on corresponding PIO port in AIC.*/ + AIC_EnableIT(extp->pid); +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) { + + /* Disable interrupt on corresponding PIO port in AIC.*/ + AIC_DisableIT(extp->pid); +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + + extp->pio->PIO_IER = (1 << channel); +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + + extp->pio->PIO_IDR = (1 << channel); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/ext_lld.h b/os/hal/platforms/AT91SAM7/ext_lld.h new file mode 100644 index 000000000..4c8442481 --- /dev/null +++ b/os/hal/platforms/AT91SAM7/ext_lld.h @@ -0,0 +1,249 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio, + 2011 Florian Goebe, Chair for Computer Science 11, + RWTH Aachen University + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file AT91SAM7/ext_lld.h + * @brief AT91SAM7 EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Pointer to the SAM7 AIC register block. + */ +#define SAM7_EXT_AIC ((AT91PS_AIC *)AT91C_BASE_AIC) + +/** + * @brief Number of channels within one ext driver. + */ +#define EXT_MAX_CHANNELS 32 + +/** + * @brief Mask of priority bits in interrupt mode register. + */ +#define SAM7_EXT_PRIORITY_MASK 0x00000007 + +/** + * @brief Shifter for priority bits in interrupt mode register. + */ +#define SAM7_EXT_PRIORITY_SHIFTER 0 + +/** + * @brief Shifter for mode bits in interrupt mode register. + */ +#define SAM7_EXT_MODE_SHIFTER 5 + +/* + * On the SAM7 architecture, a single channel can only be enables or disabled + * Hence, undefine the other channel mode constants + */ +#ifdef EXT_CH_MODE_RISING_EDGE +#undef EXT_CH_MODE_RISING_EDGE +#endif + +#ifdef EXT_CH_MODE_FALLING_EDGE +#undef EXT_CH_MODE_FALLING_EDGE +#endif + +#ifdef EXT_CH_MODE_BOTH_EDGES +#undef EXT_CH_MODE_BOTH_EDGES +#endif + +/** + * @name EXT channels mode + * @{ + */ +#define EXT_CH_MODE_ENABLED 1 /**< @brief Channel is enabled. */ +/** @} */ + +/** + * @name EXT drivers mode + * @{ + */ +/** + * @brief Mask for modes. + */ +#define SAM7_EXT_MODE_MASK AT91C_AIC_SRCTYPE +/** + * @brief Falling edge callback. + */ +#define SAM7_EXT_MODE_FALLING_EDGE AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE +/** + * @brief Rising edge callback. + */ +#define SAM7_EXT_MODE_RISING_EDGE AT91C_AIC_SRCTYPE_POSITIVE_EDGE +/** + * @brief High-level callback. + */ +#define SAM7_EXT_MODE_HIGH_LEVEL AT91C_AIC_SRCTYPE_HIGH_LEVEL +/** + * @brief Low-level callback. + */ +#define SAM7_EXT_MODE_LOW_LEVEL AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL +/** @} */ + +/** + * @name EXT drivers priorities + * @{ + */ +#define SAM7_EXT_PRIOR_HIGHEST AT91C_AIC_PRIOR_HIGHEST +#define SAM7_EXT_PRIOR_LOWEST AT91C_AIC_PRIOR_LOWEST +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + * @details In the STM32 implementation a @p NULL callback pointer is + * valid and configures the channel as an event sources instead + * of an interrupt source. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ + + /** + * @brief interrupt mode. + */ + uint32_t mode; + + /** + * @brief interrupt priority. + */ + uint32_t priority; +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the corresponding PIO registers block. + */ + AT91PS_PIO pio; + /** + * @brief peripheral ID of the corresponding PIO block. + */ + uint32_t pid; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Computes the content for the interrupt source mode register. + */ +#define SAM7_computeSMR(mode, prio) ( \ + ((mode & SAM7_EXT_MODE_MASK) << SAM7_EXT_MODE_SHIFTER) | \ + ((prio & SAM7_EXT_PRIORITY_MASK) << SAM7_EXT_PRIORITY_SHIFTER) \ +) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTDA; +#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \ + (SAM7_PLATFORM == SAM7X512) +extern EXTDriver EXTDB; +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/AT91SAM7/platform.mk b/os/hal/platforms/AT91SAM7/platform.mk index 9a5bba436..83b53491a 100644 --- a/os/hal/platforms/AT91SAM7/platform.mk +++ b/os/hal/platforms/AT91SAM7/platform.mk @@ -1,6 +1,7 @@ # List of all the AT91SAM7 platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AT91SAM7/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/AT91SAM7/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/AT91SAM7/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/AT91SAM7/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/AT91SAM7/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/AT91SAM7/mac_lld.c \ diff --git a/readme.txt b/readme.txt index 4b15c2dca..937ec5b82 100644 --- a/readme.txt +++ b/readme.txt @@ -76,6 +76,8 @@ *** 2.3.4 *** - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). +- NEW: Added EXT driver implementation for AT91SAM7x contributed by Florian. + (TODO: Test application missing). - NEW: Updated USB driver model and STM32 implementation and fixed several problems. - Changed the API to move buffer copy operations out of critical zones. -- cgit v1.2.3 From a54d331c93e98f75a2784adf48e61dcd81b792bb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 30 Oct 2011 20:57:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3458 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/USBv1/usb_lld.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.c b/os/hal/platforms/STM32/USBv1/usb_lld.c index b81766f6d..e148a6fea 100644 --- a/os/hal/platforms/STM32/USBv1/usb_lld.c +++ b/os/hal/platforms/STM32/USBv1/usb_lld.c @@ -696,6 +696,7 @@ void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { (void)usbp; + EPR_SET_STAT_TX(ep, EPR_STAT_TX_STALL); } -- cgit v1.2.3 From 656ec7b1fbd543c5c32a9eee3292cdf2f70701f8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 1 Nov 2011 10:16:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3459 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/USBv1/stm32_usb.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/os/hal/platforms/STM32/USBv1/stm32_usb.h b/os/hal/platforms/STM32/USBv1/stm32_usb.h index b06e8d887..435224033 100644 --- a/os/hal/platforms/STM32/USBv1/stm32_usb.h +++ b/os/hal/platforms/STM32/USBv1/stm32_usb.h @@ -78,7 +78,7 @@ typedef struct { /** * @brief TX buffer offset register. */ - volatile uint32_t TXADDR; + volatile uint32_t TXADDR0; /** * @brief TX counter register 0. */ @@ -90,7 +90,7 @@ typedef struct { /** * @brief RX buffer offset register. */ - volatile uint32_t RXADDR; + volatile uint32_t RXADDR0; /** * @brief RX counter register 0. */ @@ -101,6 +101,14 @@ typedef struct { volatile uint16_t RXCOUNT1; } stm32_usb_descriptor_t; +/** + * @name Register aliases + * @{ + */ +#define RXADDR1 TXADDR0 +#define TXADDR1 RXADDR0 +/** @} */ + /** * @brief USB registers block numeric address. */ @@ -140,9 +148,11 @@ typedef struct { #define EPR_STAT_TX_NAK 0x0020 #define EPR_STAT_TX_VALID 0x0030 #define EPR_DTOG_TX 0x0040 -#define EPR_SWBUF_RX 0x0040 +#define EPR_SWBUF_RX EPR_DTOG_TX #define EPR_CTR_TX 0x0080 #define EPR_EP_KIND 0x0100 +#define EPR_EP_DBL_BUF EPR_EP_KIND +#define EPR_EP_STATUS_OUT EPR_EP_KIND #define EPR_EP_TYPE_MASK 0x0600 #define EPR_EP_TYPE_BULK 0x0000 #define EPR_EP_TYPE_CONTROL 0x0200 @@ -155,7 +165,7 @@ typedef struct { #define EPR_STAT_RX_NAK 0x2000 #define EPR_STAT_RX_VALID 0x3000 #define EPR_DTOG_RX 0x4000 -#define EPR_SWBUF_TX 0x4000 +#define EPR_SWBUF_TX EPR_DTOG_RX #define EPR_CTR_RX 0x8000 #define CNTR_FRES 0x0001 -- cgit v1.2.3 From dc71ea034dc35f6a394a71831c95a73cd2ae06e7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 2 Nov 2011 17:36:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3460 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32F4_DISCOVERY/board.c | 55 + boards/ST_STM32F4_DISCOVERY/board.h | 447 ++ boards/ST_STM32F4_DISCOVERY/board.mk | 5 + boards/ST_STM32L_DISCOVERY/board.h | 21 +- os/hal/platforms/STM32F4xx/hal_lld.c | 164 + os/hal/platforms/STM32F4xx/hal_lld.h | 955 +++++ os/hal/platforms/STM32F4xx/platform.mk | 9 + os/hal/platforms/STM32F4xx/stm32_dma.c | 541 +++ os/hal/platforms/STM32F4xx/stm32_dma.h | 327 ++ os/hal/platforms/STM32F4xx/stm32f4xx.h | 7000 ++++++++++++++++++++++++++++++++ 10 files changed, 9506 insertions(+), 18 deletions(-) create mode 100644 boards/ST_STM32F4_DISCOVERY/board.c create mode 100644 boards/ST_STM32F4_DISCOVERY/board.h create mode 100644 boards/ST_STM32F4_DISCOVERY/board.mk create mode 100644 os/hal/platforms/STM32F4xx/hal_lld.c create mode 100644 os/hal/platforms/STM32F4xx/hal_lld.h create mode 100644 os/hal/platforms/STM32F4xx/platform.mk create mode 100644 os/hal/platforms/STM32F4xx/stm32_dma.c create mode 100644 os/hal/platforms/STM32F4xx/stm32_dma.h create mode 100644 os/hal/platforms/STM32F4xx/stm32f4xx.h diff --git a/boards/ST_STM32F4_DISCOVERY/board.c b/boards/ST_STM32F4_DISCOVERY/board.c new file mode 100644 index 000000000..4a93dada2 --- /dev/null +++ b/boards/ST_STM32F4_DISCOVERY/board.c @@ -0,0 +1,55 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH} +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/ST_STM32F4_DISCOVERY/board.h b/boards/ST_STM32F4_DISCOVERY/board.h new file mode 100644 index 000000000..b3d2f23e7 --- /dev/null +++ b/boards/ST_STM32F4_DISCOVERY/board.h @@ -0,0 +1,447 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F4-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F4_DISCOVERY +#define BOARD_NAME "ST STM32F4-Discovery" + +/* + * Board frequencies. + * NOTE: The LSE crystal is not fitted by default on the board. + */ +#define STM32_LSECLK 0 +#define STM32_HSECLK 8000000 + +/* + * MCU type as defined in the ST header file stm32l1xx.h. + */ +#define STM32F4XX + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_LRCK 4 +#define GPIOA_SPC 5 +#define GPIOA_SDO 6 +#define GPIOA_SDA_SDI_SDO 7 +#define GPIOA_VBUS_FS 9 +#define GPIOA_OTG_FS_ID 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 + +#define GPIOB_SWO 3 +#define GPIOB_SCL 6 +#define GPIOB_SDA 9 +#define GPIOB_SCK 10 + +#define GPIOC_OTG_FS_POWER_ON 0 +#define GPIOC_DOUT 3 +#define GPIOC_MCLK 7 +#define GPIOC_SCLK 10 +#define GPIOC_SDIN 12 + +#define GPIOD_RESET 4 +#define GPIOD_OVER_CURRENT 5 +#define GPIOD_LED4 12 /* Green LED. */ +#define GPIOD_LED3 13 /* Orange LED. */ +#define GPIOD_LED5 14 /* Red LED. */ +#define GPIOD_LED6 15 /* Blue LED. */ + +#define GPIOE_INT1 0 +#define GPIOE_INT2 1 +#define GPIOE_CS_SPI 3 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v)U << ((n % 8) * 4)) + +/* + * Port A setup. + * All input with pull-up except: + * PA0 - GPIOA_BUTTON (input floating). + * PA4 - GPIOA_LRCK (alternate 6). + * PA5 - GPIOA_SPC (alternate 5). + * PA6 - GPIOA_SDO (alternate 5). + * PA7 - GPIOA_SDI (alternate 5). + * PA9 - GPIOA_VBUS_FS (input floating). + * PA10 - GPIOA_OTG_FS_ID (alternate 10). + * PA11 - GPIOA_OTG_FS_DM (alternate 10). + * PA12 - GPIOA_OTG_FS_DP (alternate 10). + * PA13 - GPIOA_SWDIO (alternate 0). + * PA14 - GPIOA_SWCLK (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_ALTERNATE(GPIOA_LRCK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPC) | \ + PIN_MODE_ALTERNATE(GPIOA_SDO) | \ + PIN_MODE_ALTERNATE(GPIOA_SDI) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOA_OTYPER 0x00000000 +#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOA_PUPDR (PIN_PUDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUDR_PULLUP(1) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_PULLUP(3) | \ + PIN_PUDR_FLOATING(GPIOA_LRCK) | \ + PIN_PUDR_FLOATING(GPIOA_SPC) | \ + PIN_PUDR_FLOATING(GPIOA_SDO) | \ + PIN_PUDR_FLOATING(GPIOA_SDI) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_FLOATING(GPIOA_VBUS_FS) | \ + PIN_PUDR_FLOATING(GPIOA_OTG_FS_ID) | \ + PIN_PUDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUDR_PULLUP(15)) +#define VAL_GPIOA_ODR 0xFFFFFFFF +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(4, 6) | \ + PIN_AFIO_AF(5, 5) | \ + PIN_AFIO_AF(6, 5) | \ + PIN_AFIO_AF(7, 5)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(10, 10) | \ + PIN_AFIO_AF(11, 10) | \ + PIN_AFIO_AF(12, 10) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0)) + +/* + * Port B setup. + * All input with pull-up except: + * PB3 - GPIOB_SWO (alternate 0). + * PB6 - GPIOB_SCL (alternate 4). + * PB9 - GPIOB_SDA (alternate 4). + * PB10 - GPIOB_SCK (alternate 5). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_ALTERNATE(GPIOB_SCL) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_ALTERNATE(GPIOB_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_SCK) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_SDA)) +#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLUP(0) | \ + PIN_PUDR_PULLUP(1) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_FLOATING(GPIOB_SWO) | \ + PIN_PUDR_PULLUP(4) | \ + PIN_PUDR_PULLUP(5) | \ + PIN_PUDR_FLOATING(GPIOB_SCL) | \ + PIN_PUDR_PULLUP(7) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_FLOATING(GPIOB_SDA) | \ + PIN_PUDR_FLOATING(GPIOB_SCK | \ + PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_PULLUP(12) | \ + PIN_PUDR_PULLUP(13) | \ + PIN_PUDR_PULLUP(14) | \ + PIN_PUDR_PULLUP(15)) +#define VAL_GPIOB_ODR 0xFFFFFFFF +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(6, 4)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(9, 4) | \ + PIN_AFIO_AF(10, 5)) + +/* + * Port C setup. + * All input with pull-up except: + * PC0 - GPIOC_OTG_FS_POWER_ON (output push-pull). + * PC3 - GPIOC_DOUT (alternate 5). + * PC7 - GPIOC_MCLK (alternate 6). + * PC10 - GPIOC_SCLK (alternate 6). + * PC12 - GPIOC_SDIN (alternate 6). + */ +#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_ALTERNATE(GPIOC_DOUT) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_ALTERNATE(GPIOC_MCLK) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_ALTERNATE(GPIOC_SCLK) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIN)) \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOC_OTYPER 0x00000000 +#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOC_PUPDR (PIN_PUDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ + PIN_PUDR_PULLUP(1) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_FLOATING(GPIOC_DOUT)) | \ + PIN_PUDR_PULLUP(4) | \ + PIN_PUDR_PULLUP(5) | \ + PIN_PUDR_PULLUP(6) | \ + PIN_PUDR_FLOATING(GPIOC_MCLK)) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_PULLUP(9) | \ + PIN_PUDR_FLOATING(GPIOC_SCLK)) | \ + PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_FLOATING(GPIOC_SDIN)) | \ + PIN_PUDR_PULLUP(13) | \ + PIN_PUDR_PULLUP(14) | \ + PIN_PUDR_PULLUP(15)) +#define VAL_GPIOC_ODR 0xFFFFFFFF +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(3, 5) | \ + PIN_AFIO_AF(7, 6)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(10, 6) | \ + PIN_AFIO_AF(12, 6)) + +/* + * Port D setup. + * All input with pull-up except: + * PD4 - GPIOD_RESET (output push-pull). + * PD5 - GPIOD_OVER_CURRENT (input floating). + * PD12 - GPIOD_LED4 (output push-pull). + * PD13 - GPIOD_LED3 (output push-pull). + * PD14 - GPIOD_LED5 (output push-pull). + * PD15 - GPIOD_LED6 (output push-pull). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_OUTPUT(GPIOD_RESET) | \ + PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(GPIOD_LED4) | \ + PIN_MODE_INPUT(GPIOD_LED3) | \ + PIN_MODE_INPUT(GPIOD_LED5) | \ + PIN_MODE_INPUT(GPIOD_LED6)) +#define VAL_GPIOD_OTYPER 0x00000000 +#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(0) | \ + PIN_PUDR_PULLUP(1) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_PULLUP(3) | \ + PIN_PUDR_FLOATING(GPIOD_RESET) | \ + PIN_PUDR_FLOATING(GPIOD_OVER_CURRENT) |\ + PIN_PUDR_PULLUP(6) | \ + PIN_PUDR_PULLUP(7) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_PULLUP(9) | \ + PIN_PUDR_PULLUP(10) | \ + PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_FLOATING(GPIOD_LED4) | \ + PIN_PUDR_FLOATING(GPIOD_LED3) | \ + PIN_PUDR_FLOATING(GPIOD_LED5) | \ + PIN_PUDR_FLOATING(GPIOD_LED6)) +#define VAL_GPIOD_ODR 0x0FFFFFCF +#define VAL_GPIOD_AFRL 0x00000000 +#define VAL_GPIOD_AFRH 0x00000000 + +/* + * Port E setup. + * All input with pull-up except: + * PE0 - GPIOE_INT1 (input floating). + * PE1 - GPIOE_INT2 (input floating). + * PE3 - GPIOE_CS_SPI (output push-pull). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \ + PIN_MODE_INPUT(GPIOE_INT2) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(GPIOE_CS_SPI) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOE_OTYPER 0x00000000 +#define VAL_GPIOE_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOE_PUPDR (PIN_PUDR_FLOATING(0GPIOE_INT1) | \ + PIN_PUDR_FLOATING(GPIOE_INT2) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_FLOATING(GPIOE_CS_SPI) | \ + PIN_PUDR_PULLUP(4) | \ + PIN_PUDR_PULLUP(5) | \ + PIN_PUDR_PULLUP(6) | \ + PIN_PUDR_PULLUP(7) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_PULLUP(9) | \ + PIN_PUDR_PULLUP(10) | \ + PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_PULLUP(12) | \ + PIN_PUDR_PULLUP(13) | \ + PIN_PUDR_PULLUP(14) | \ + PIN_PUDR_PULLUP(15)) +#define VAL_GPIOE_ODR 0xFFFFFFFF +#define VAL_GPIOE_AFRL 0x00000000 +#define VAL_GPIOE_AFRH 0x00000000 + +/* + * Port F setup. + * All input with pull-up. + */ +#define VAL_GPIOF_MODER 0x00000000 +#define VAL_GPIOF_OTYPER 0x00000000 +#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOF_PUPDR 0xFFFFFFFF +#define VAL_GPIOF_ODR 0xFFFFFFFF +#define VAL_GPIOF_AFRL 0x00000000 +#define VAL_GPIOF_AFRH 0x00000000 + +/* + * Port G setup. + * All input with pull-up. + */ +#define VAL_GPIOG_MODER 0x00000000 +#define VAL_GPIOG_OTYPER 0x00000000 +#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOG_PUPDR 0xFFFFFFFF +#define VAL_GPIOG_ODR 0xFFFFFFFF +#define VAL_GPIOG_AFRL 0x00000000 +#define VAL_GPIOG_AFRH 0x00000000 + +/* + * Port H setup. + * All input with pull-up except: + * PH0 - GPIOH_OSC_IN (input floating). + * PH1 - GPIOH_OSC_OUT (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOH_OTYPER 0x00000000 +#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOH_PUPDR (PIN_PUDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUDR_PULLUP(2) | \ + PIN_PUDR_PULLUP(3) | \ + PIN_PUDR_PULLUP(4) | \ + PIN_PUDR_PULLUP(5) | \ + PIN_PUDR_PULLUP(6) | \ + PIN_PUDR_PULLUP(7) | \ + PIN_PUDR_PULLUP(8) | \ + PIN_PUDR_PULLUP(9) | \ + PIN_PUDR_PULLUP(10) | \ + PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_PULLUP(12) | \ + PIN_PUDR_PULLUP(13) | \ + PIN_PUDR_PULLUP(14) | \ + PIN_PUDR_PULLUP(15)) +#define VAL_GPIOH_ODR 0xFFFFFFFF +#define VAL_GPIOH_AFRL 0x00000000 +#define VAL_GPIOH_AFRH 0x00000000 + +/* + * Port I setup. + * All input with pull-up. + */ +#define VAL_GPIOI_MODER 0x00000000 +#define VAL_GPIOI_OTYPER 0x00000000 +#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOI_PUPDR 0xFFFFFFFF +#define VAL_GPIOI_ODR 0xFFFFFFFF +#define VAL_GPIOI_AFRL 0x00000000 +#define VAL_GPIOI_AFRH 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM32F4_DISCOVERY/board.mk b/boards/ST_STM32F4_DISCOVERY/board.mk new file mode 100644 index 000000000..eb47aa2af --- /dev/null +++ b/boards/ST_STM32F4_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY diff --git a/boards/ST_STM32L_DISCOVERY/board.h b/boards/ST_STM32L_DISCOVERY/board.h index f91998a59..6326c5e4d 100644 --- a/boards/ST_STM32L_DISCOVERY/board.h +++ b/boards/ST_STM32L_DISCOVERY/board.h @@ -22,13 +22,13 @@ #define _BOARD_H_ /* - * Setup for STMicroelectronics STM32VL-Discovery board. + * Setup for STMicroelectronics STM32L-Discovery board. */ /* * Board identifier. */ -#define BOARD_ST_STM32VL_DISCOVERY +#define BOARD_ST_STM32L_DISCOVERY #define BOARD_NAME "ST STM32L-Discovery" /* @@ -69,22 +69,7 @@ #define PIN_PUDR_FLOATING(n) (0U << ((n) * 2)) #define PIN_PUDR_PULLUP(n) (1U << ((n) * 2)) #define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2)) -#define PIN_AFIO_AF0(n) (0U << ((n % 8) * 4)) -#define PIN_AFIO_AF1(n) (1U << ((n % 8) * 4)) -#define PIN_AFIO_AF2(n) (2U << ((n % 8) * 4)) -#define PIN_AFIO_AF3(n) (3U << ((n % 8) * 4)) -#define PIN_AFIO_AF4(n) (4U << ((n % 8) * 4)) -#define PIN_AFIO_AF5(n) (5U << ((n % 8) * 4)) -#define PIN_AFIO_AF6(n) (6U << ((n % 8) * 4)) -#define PIN_AFIO_AF7(n) (7U << ((n % 8) * 4)) -#define PIN_AFIO_AF8(n) (8U << ((n % 8) * 4)) -#define PIN_AFIO_AF9(n) (9U << ((n % 8) * 4)) -#define PIN_AFIO_AF10(n) (10U << ((n % 8) * 4)) -#define PIN_AFIO_AF11(n) (11U << ((n % 8) * 4)) -#define PIN_AFIO_AF12(n) (12U << ((n % 8) * 4)) -#define PIN_AFIO_AF13(n) (13U << ((n % 8) * 4)) -#define PIN_AFIO_AF14(n) (14U << ((n % 8) * 4)) -#define PIN_AFIO_AF15(n) (15U << ((n % 8) * 4)) +#define PIN_AFIO_AF(n, v) ((v)U << ((n % 8) * 4)) /* * Port A setup. diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c new file mode 100644 index 000000000..74afa4bdb --- /dev/null +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -0,0 +1,164 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F4xx/hal_lld.c + * @brief STM32F4xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#define AIRCR_VECTKEY 0x05FA0000 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals.*/ +// RCC->APB1RSTR = 0xFFFFFFFF; +// RCC->APB2RSTR = 0xFFFFFFFF; +// RCC->APB1RSTR = 0; +// RCC->APB2RSTR = 0; + + /* SysTick initialization using the system clock.*/ + SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + + +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif +} + +/** + * @brief STM32F2xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +#if defined(STM32F2XX) || defined(__DOXYGEN__) +/** + * @brief Clocks and internal voltage initialization. + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* PWR clock enable.*/ + RCC->APB1ENR = RCC_APB1ENR_PWREN; + + /* Initial clocks setup and wait for HSI stabilization, the MSI clock is + always enabled because it is the fallback clock when PLL the fails.*/ + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0) + ; /* Waits until HSI is stable. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ + RCC->CR |= RCC_CR_HSEON; + while ((RCC->CR & RCC_CR_HSERDY) == 0) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_LSE_ENABLED + /* LSE activation, have to unlock the register.*/ + if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) { + PWR->CR |= PWR_CR_DBP; + RCC->BDCR |= RCC_BDCR_LSEON; + PWR->CR &= ~PWR_CR_DBP; + } + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; /* Waits until PLL is stable. */ +#endif + +#if STM32_ACTIVATE_PLLI2S + /* PLLI2S activation.*/ + RCC->PLLI2SCFGR = STM32_PLI2SR_VALUE | STM32_PLLI2SN_VALUE; + RCC->CR |= RCC_CR_PLLI2SON; + while (!(RCC->CR & RCC_CR_PLLI2SRDY)) + ; /* Waits until PLLI2S is stable. */ +#endif + + /* Other clock-related settings (dividers, MCO etc).*/ + RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | + STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; + + /* Flash setup. */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from MSI. */ +#if (STM32_SW != STM32_SW_HSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* STM32_NO_INIT */ +} +#else +void stm32_clock_init(void) {} +#endif + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h new file mode 100644 index 000000000..1371f0e8e --- /dev/null +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -0,0 +1,955 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F4xx/hal_lld.h + * @brief STM32F4xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_HSECLK. + * . + * One of the following macros must also be defined: + * - STM32F4XX for High-performance STM32 F-4 devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm32f4xx.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "STM32F2 High performance" + +#define STM32_HSICLK 16000000 /**< High speed internal clock. */ +#define STM32_LSICLK 38000 /**< Low speed internal clock. */ + +/* RCC_PLLCFGR register bits definitions.*/ +#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ +#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ +#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ +#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ +#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ + +/* RCC_CFGR register bits definitions.*/ +#define STM32_SW_MASK (3 << 0) /**< SW mask. */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */ +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ +#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ +#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */ + +#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */ + +#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */ +#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */ +#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ + +#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ +#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ +#define STM32_MCO1PRE_DIV2 (1 << 24) /**< MCO1 divided by 2. */ +#define STM32_MCO1PRE_DIV3 (2 << 24) /**< MCO1 divided by 3. */ +#define STM32_MCO1PRE_DIV4 (3 << 24) /**< MCO1 divided by 4. */ +#define STM32_MCO1PRE_DIV5 (4 << 24) /**< MCO1 divided by 5. */ + +#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */ +#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */ +#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */ +#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */ +#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ +#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ + +#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */ +#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */ +#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */ + +/* RCC_PLLI2SCFGR register bits definitions.*/ +#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */ +#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ + +/* STM32F2xx capabilities.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE + +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE + +#define STM32_HAS_DAC TRUE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +#define STM32_HAS_ETH TRUE + +#define STM32_EXTI_NUM_CHANNELS 23 + +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI TRUE + +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE + +#define STM32_HAS_RTC TRUE + +#define STM32_HAS_SDIO TRUE + +#define STM32_HAS_SPI1 TRUE +#define STM32_HAS_SPI2 TRUE +#define STM32_HAS_SPI3 TRUE + +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 TRUE +#define STM32_HAS_TIM13 TRUE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 TRUE + +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 TRUE + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ + +#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ +#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line + detect. */ +#define TAMPER_IRQHandler Vector48 /**< Tamper. */ +#define RTC_IRQHandler Vector4C /**< RTC. */ +#define FLASH_IRQHandler Vector50 /**< Flash. */ +#define RCC_IRQHandler Vector54 /**< RCC. */ +#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ +#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ +#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ +#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ +#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ +#define DMA1_Stream0_IRQHandler Vector6C /**< DMA1 Stream 0. */ +#define DMA1_Stream1_IRQHandler Vector70 /**< DMA1 Stream 1. */ +#define DMA1_Stream2_IRQHandler Vector74 /**< DMA1 Stream 2. */ +#define DMA1_Stream3_IRQHandler Vector78 /**< DMA1 Stream 3. */ +#define DMA1_Stream4_IRQHandler Vector7C /**< DMA1 Stream 4. */ +#define DMA1_Stream5_IRQHandler Vector80 /**< DMA1 Stream 5. */ +#define DMA1_Stream6_IRQHandler Vector84 /**< DMA1 Stream 6. */ +#define ADC1_2_3_IRQHandler Vector88 /**< ADC1, ADC2 and ADC3. */ +#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ +#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ +#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ +#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ +#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ +#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ +#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ +#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and + Commutation. */ +#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ +#define TIM2_IRQHandler VectorB0 /**< TIM2. */ +#define TIM3_IRQHandler VectorB4 /**< TIM3. */ +#define TIM4_IRQHandler VectorB8 /**< TIM4. */ +#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ +#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ +#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ +#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ +#define SPI1_IRQHandler VectorCC /**< SPI1. */ +#define SPI2_IRQHandler VectorD0 /**< SPI2. */ +#define USART1_IRQHandler VectorD4 /**< USART1. */ +#define USART2_IRQHandler VectorD8 /**< USART2. */ +#define USART3_IRQHandler VectorDC /**< USART3. */ +#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ +#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarm through EXTI + line. */ +#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through + EXTI line. */ +#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ +#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ +#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and + Commutation. */ +#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ +#define DMA1_Stream7_IRQHandler VectorFC /**< DMA1 Stream 7. */ +#define FSMC_IRQHandler Vector100 /**< FSMC. */ +#define TIM5_IRQHandler Vector108 /**< TIM5. */ +#define SPI3_IRQHandler Vector10C /**< SPI3. */ +#define UART4_IRQHandler Vector110 /**< UART4. */ +#define UART5_IRQHandler Vector114 /**< UART5. */ +#define TIM6_IRQHandler Vector118 /**< TIM6. */ +#define TIM7_IRQHandler Vector11C /**< TIM7. */ +#define DMA2_Stream0_IRQHandler Vector120 /**< DMA2 Stream0. */ +#define DMA2_Stream1_IRQHandler Vector124 /**< DMA2 Stream1. */ +#define DMA2_Stream2_IRQHandler Vector128 /**< DMA2 Stream2. */ +#define DMA2_Stream3_IRQHandler Vector12C /**< DMA2 Stream3. */ +#define DMA2_Stream4_IRQHandler Vector130 /**< DMA2 Stream4. */ +#define ETH_IRQHandler Vector134 /**< Ethernet. */ +#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through + EXTI line. */ +#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ +#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ +#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ +#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ +#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ +#define DMA2_Stream5_IRQHandler Vector150 /**< DMA2 Stream5. */ +#define DMA2_Stream6_IRQHandler Vector154 /**< DMA2 Stream6. */ +#define DMA2_Stream7_IRQHandler Vector158 /**< DMA2 Stream7. */ +#define USART6_IRQHandler Vector15C /**< USART6. */ +#define I2C3_EV_IRQHandler Vector160 /**< I2C3 Event. */ +#define I2C3_ER_IRQHandler Vector164 /**< I2C3 Error. */ +#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/ +#define OTG_HS_EP1_IN_IRQHandler Vector16C /**< USB OTG HS End Point 1 In. */ +#define OTG_HS_WKUP_IRQHandler Vector170 /**< USB OTG HS Wakeup through + EXTI line. */ +#define OTG_HS_IRQHandler Vector174 /**< USB OTG HS. */ +#define DCMI_IRQHandler Vector178 /**< DCMI. */ +#define CRYP_IRQHandler Vector17C /**< CRYP. */ +#define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED FALSE +#endif + +/** + * @brief ADC clock setting. + */ +#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_ADC_CLOCK_ENABLED TRUE +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_USB_CLOCK_ENABLED TRUE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 32MHz system clock from + * the internal 16MHz HSI clock. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 120MHz system clock from + * the external 25MHz HSE clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief PLLM divider value. + * @note The allowed values are 2..63. + * @note The default value is calculated for a 120MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLM_VALUE 25 +#endif + +/** + * @brief PLLN multiplier value. + * @note The allowed values are 192..432. + * @note The default value is calculated for a 120MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLN_VALUE 240 +#endif + +/** + * @brief PLLP multiplier value. + * @note The allowed values are DIV2, DIV4, DIV6, DIV8. + * @note The default value is calculated for a 120MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLP_VALUE 2 +#endif + +/** + * @brief PLLQ multiplier value. + * @note The allowed values are 4..15. + * @note The default value is calculated for a 120MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLQ_VALUE 5 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 120MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief RTC prescaler value. + */ +#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__) +#define STM32_RTCPRE_VALUE 25 +#endif + +/** + * @brief MC01 clock source value. + * @note The default value outputs HSI clock on MC01 pin. + */ +#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__) +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#endif + +/** + * @brief MC01 prescaler value. + * @note The default value outputs HSI clock on MC01 pin. + */ +#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__) +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#endif + +/** + * @brief MC02 clock source value. + * @note The default value outputs SYSCLK / 5 on MC02 pin. + */ +#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__) +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#endif + +/** + * @brief MC02 prescaler value. + * @note The default value outputs SYSCLK / 5 on MC02 pin. + */ +#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#endif + +/** + * @brief PLLI2SN multiplier value. + * @note The allowed values are 192..432. + * @note The default value is calculated for a 48000 I2S clock with + * I2SDIV = 12 and I2SODD = 1. + */ +#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SN_VALUE 384 +#endif + +/** + * @brief PLLI2SR multiplier value. + * @note The allowed values are 2..7. + * @note The default value is calculated for a 48000 I2S clock with + * I2SDIV = 12 and I2SODD = 1. + */ +#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLI2SLP_VALUE 5 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Maximum HSECLK. + */ +#define STM32_HSECLK_MAX 32000000 + +/** + * @brief Maximum SYSCLK. + */ +#define STM32_SYSCLK_MAX 120000000 + +/** + * @brief Maximum frequency thresholds and wait states for flash access. + * @note The values are valid for 2.7V to 3.6V supply range. + */ +#define STM32_0WS_THRESHOLD 30000000 +#define STM32_1WS_THRESHOLD 60000000 +#define STM32_2WS_THRESHOLD 90000000 +#define STM32_3WS_THRESHOLD 0 +#define STM32_4WS_THRESHOLD 0 +#define STM32_5WS_THRESHOLD 0 +#define STM32_6WS_THRESHOLD 0 +#define STM32_7WS_THRESHOLD 0 + +/* HSI related checks.*/ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ +#if STM32_ADC_CLOCK_ENABLED || \ + (STM32_SW == STM32_SW_HSI) || \ + ((STM32_SW == STM32_SW_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) || \ + (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "required HSI clock is not enabled" +#endif +#endif /* !STM32_HSI_ENABLED */ + +/* HSE related checks.*/ +#if STM32_HSE_ENABLED +#if STM32_HSECLK == 0 +#error "impossible to activate HSE" +#endif +#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)" +#endif +#else /* !STM32_HSE_ENABLED */ +#if (STM32_SW == STM32_SW_HSE) || \ + ((STM32_SW == STM32_SW_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \ + ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ + (STM_RTC_SOURCE == STM32_RTCSEL_HSEDIV) +#error "required HSE clock is not enabled" +#endif +#endif /* !STM32_HSE_ENABLED */ + +/* LSI related checks.*/ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ +#if STM_RTCCLK == STM32_LSICLK +#error "required LSI clock is not enabled" +#endif +#endif /* !STM32_LSI_ENABLED */ + +/* LSE related checks.*/ +#if STM32_LSE_ENABLED +#if (STM32_LSECLK == 0) +#error "impossible to activate LSE" +#endif +#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000) +#error "STM32_LSECLK outside acceptable range (1...1000KHz)" +#endif +#else /* !#if STM32_LSE_ENABLED */ +#if STM_RTCCLK == STM32_LSECLK +#error "required LSE clock is not enabled" +#endif +#endif /* !#if STM32_LSE_ENABLED */ + +/* PLL related checks.*/ +#if STM32_USB_CLOCK_ENABLED || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \ + (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/** + * @brief STM32_PLLM field. + */ +#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ + defined(__DOXYGEN__) +#define STM32_PLLM STM32_PLLM_VALUE +#else +#error "invalid STM32_PLLM_VALUE value specified" +#endif + +/** + * @brief STM32_PLLN field. + */ +#if ((STM32_PLLN_VALUE >= 192) && (STM32_PLLN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLN (STM32_PLLN_VALUE << 6) +#else +#error "invalid STM32_PLLN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLP field. + */ +#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLP (0 << 16) +#elif STM32_PLLP_VALUE == 4 +#define STM32_PLLP (1 << 16) +#elif STM32_PLLP_VALUE == 6 +#define STM32_PLLP (2 << 16) +#elif STM32_PLLP_VALUE == 8 +#define STM32_PLLP (3 << 16) +#else +#error "invalid STM32_PLLP_VALUE value specified" +#endif + +/** + * @brief STM32_PLLQ field. + */ +#if ((STM32_PLLQ_VALUE >= 4) && (STM32_PLLQ_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define STM32_PLLQ (STM32_PLLQ_VALUE << 24) +#else +#error "invalid STM32_PLLQ_VALUE value specified" +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN STM32_HSECLK +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN STM32_HSICLK +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* PLL input frequency range check.*/ +#if (STM32_PLLCLKIN < 4000000) || (STM32_PLLCLKIN > 26000000) +#error "STM32_PLLCLKIN outside acceptable range (4...26MHz)" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLVCO ((STM32_PLLCLKIN / STM32_PLLM_VALUE) * \ + STM32_PLLN_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLVCO < 192000000) || (STM32_PLLVCO > 432000000) +#error STM32_PLLVCO +#error "STM32_PLLVCO outside acceptable range (192...432MHz)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) + +/* PLL output frequency range check.*/ +#if (STM32_PLLCLKOUT < 24000000) || (STM32_PLLCLKOUT > 120000000) +#error "STM32_PLLCLKOUT outside acceptable range (24...120MHz)" +#endif + +/** + * @brief System clock source. + */ +#if STM32_NO_INIT || defined(__DOXYGEN__) +#define STM32_SYSCLK 96000000 +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK +#elif (STM32_SW == STM32_SW_PLL) +#define STM32_SYSCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* AHB frequency check.*/ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* APB1 frequency check.*/ +#if STM32_PCLK2 > STM32_SYSCLK_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* APB2 frequency check.*/ +#if STM32_PCLK2 > STM32_SYSCLK_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief RTC frequency. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief MCO1 divider clock. + */ +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__) +#define STM_MCO1DIVCLK STM32_HSICLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE +#define STM_MCO1DIVCLK STM32_LSECLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE +#define STM_MCO1DIVCLK STM32_HSECLK +#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL +#define STM_MCO1DIVCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_MCO1SEL value specified" +#endif + +/** + * @brief MCO1 output pin clock. + */ +#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__) +#define STM_MCO1CLK STM_MCO1DIVCLK +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2 +#define STM_MCO1CLK (STM_MCO1DIVCLK / 2) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3 +#define STM_MCO1CLK (STM_MCO1DIVCLK / 3) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4 +#define STM_MCO1CLK (STM_MCO1DIVCLK / 4) +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5 +#define STM_MCO1CLK (STM_MCO1DIVCLK / 5) +#else +#error "invalid STM32_MCO1PRE value specified" +#endif + +/** + * @brief MCO2 divider clock. + */ +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__) +#define STM_MCO2DIVCLK STM32_HSECLK +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL +#define STM_MCO2DIVCLK STM32_PLLCLKOUT +#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK +#define STM_MCO2DIVCLK STM32_SYSCLK +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S +#define STM_MCO2DIVCLK STM32_PLLI2S + +#else +#error "invalid STM32_MCO2SEL value specified" +#endif + +/** + * @brief MCO2 output pin clock. + */ +#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__) +#define STM_MCO2CLK STM_MCO2DIVCLK +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2 +#define STM_MCO2CLK (STM_MCO2DIVCLK / 2) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3 +#define STM_MCO2CLK (STM_MCO2DIVCLK / 3) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4 +#define STM_MCO2CLK (STM_MCO2DIVCLK / 4) +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5 +#define STM_MCO2CLK (STM_MCO2DIVCLK / 5) +#else +#error "invalid STM32_MCO2PRE value specified" +#endif + +/** + * @brief HSE divider toward RTC clock. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (HSECLK / STM32_RTCPRE_VALUE) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM_RTCCLK 0 +#elif STM32_RTCSEL == STM32_RTCSEL_LSE +#define STM_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM_RTCCLK STM32_HSEDIVCLK +#else +#error "invalid STM32_RTCSEL value specified" +#endif + +/** + * @brief ADC frequency. + */ +#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADCPRE value specified" +#endif + +/* ADC frequency check.*/ +#if STM32_ADCCLK > 30000000 +#error "STM32_ADCCLK exceeding maximum frequency (30MHz)" +#endif + +/** + * @brief OTG frequency. + */ +#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__) +#define STM32_OTGFSCLK (STM32_PLLVCO / 3) +#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2) +#define STM32_OTGFSCLK (STM32_PLLVCO / 2) +#else +#error "invalid STM32_OTGFSPRE value specified" +#endif + +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000000 +#elif STM32_HCLK <= STM32_1WS_THRESHOLD +#define STM32_FLASHBITS 0x00000001 +#elif STM32_HCLK <= STM32_2WS_THRESHOLD +#define STM32_FLASHBITS 0x00000002 +#elif STM32_HCLK <= STM32_3WS_THRESHOLD +#define STM32_FLASHBITS 0x00000003 +#elif STM32_HCLK <= STM32_4WS_THRESHOLD +#define STM32_FLASHBITS 0x00000004 +#elif STM32_HCLK <= STM32_5WS_THRESHOLD +#define STM32_FLASHBITS 0x00000005 +#elif STM32_HCLK <= STM32_6WS_THRESHOLD +#define STM32_FLASHBITS 0x00000006 +#else +#define STM32_FLASHBITS 0x00000007 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* STM32 DMA support code.*/ +//#include "stm32_dma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk new file mode 100644 index 000000000..36d555536 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/platform.mk @@ -0,0 +1,9 @@ +# List of all the STM32L1xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \ + ${CHIBIOS}/os/hal/platforms/STM32 \ + ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.c b/os/hal/platforms/STM32F4xx/stm32_dma.c new file mode 100644 index 000000000..e35d93543 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/stm32_dma.c @@ -0,0 +1,541 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F4xx/stm32_dma.c + * @brief Enhanced DMA helper driver code. + * + * @addtogroup STM32_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * IRSs when allocating streams. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK 0x000000FF + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK 0x0000FF00 + +/** + * @brief Post-reset value of the stream CR register. + */ +#define STM32_DMA_CR_RESET_VALUE 0x00000000 + +/** + * @brief Post-reset value of the stream FCR register. + */ +#define STM32_DMA_FCR_RESET_VALUE 0x00000021 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {0, DMA1, DMA1_Stream0, &DMA1->LIFCR, 0}, + {1, DMA1, DMA1_Stream1, &DMA1->LIFCR, 6}, + {2, DMA1, DMA1_Stream2, &DMA1->LIFCR, 16}, + {3, DMA1, DMA1_Stream3, &DMA1->LIFCR, 22}, + {4, DMA1, DMA1_Stream4, &DMA1->HIFCR, 0}, + {5, DMA1, DMA1_Stream5, &DMA1->HIFCR, 6}, + {6, DMA1, DMA1_Stream6, &DMA1->HIFCR, 16}, + {7, DMA1, DMA1_Stream7, &DMA1->HIFCR, 22}, + {8, DMA2, DMA2_Stream0, &DMA2->LIFCR, 0}, + {9, DMA2, DMA2_Stream1, &DMA2->LIFCR, 6}, + {10, DMA2, DMA2_Stream2, &DMA2->LIFCR, 16}, + {11, DMA2, DMA2_Stream3, &DMA2->LIFCR, 22}, + {12, DMA2, DMA2_Stream4, &DMA2->HIFCR, 0}, + {13, DMA2, DMA2_Stream5, &DMA2->HIFCR, 6}, + {14, DMA2, DMA2_Stream6, &DMA2->HIFCR, 16}, + {15, DMA2, DMA2_Stream7, &DMA2->HIFCR, 22}, +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dma_func; + void *dma_param; +} dma_isr_redir_t; + +/** + * @brief Mask of the allocated streams. + */ +static uint32_t dma_streams_mask; + +/** + * @brief DMA IRQ redirectors. + */ +static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[0].dma_func) + dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[1].dma_func) + dma_isr_redir[1].dma_func(dma_isr_redir[0].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[2].dma_func) + dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[3].dma_func) + dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[4].dma_func) + dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[5].dma_func) + dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[6].dma_func) + dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA1->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[7].dma_func) + dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 0 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[8].dma_func) + dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[9].dma_func) + dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[10].dma_func) + dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->LIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[11].dma_func) + dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 0; + if (dma_isr_redir[12].dma_func) + dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 6; + if (dma_isr_redir[13].dma_func) + dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 16; + if (dma_isr_redir[14].dma_func) + dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 stream 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) { + uint32_t flags; + + CH_IRQ_PROLOGUE(); + + flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK; + DMA2->HIFCR = STM32_DMA_ISR_MASK << 22; + if (dma_isr_redir[15].dma_func) + dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags); + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma_streams_mask = 0; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].stream->CR = 0; + dma_isr_redir[i].dma_func = NULL; + } + DMA1->LIFCR = 0xFFFFFFFF; + DMA1->HIFCR = 0xFFFFFFFF; + DMA2->LIFCR = 0xFFFFFFFF; + DMA2->HIFCR = 0xFFFFFFFF; +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] priority IRQ priority mask for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE no error, stream taken. + * @retval TRUE error, stream already taken. + * + * @special + */ +bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + chDbgCheck(dmastp != NULL, "dmaAllocate"); + + /* Checks if the stream is already taken.*/ + if ((dma_streams_mask & dmastp->mask) != 0) + return TRUE; + + /* Marks the stream as allocated.*/ + dma_isr_redir[dmastp->selfindex].dma_func = func; + dma_isr_redir[dmastp->selfindex].dma_param = param; + dma_streams_mask |= (1 << dmastp->selfindex); + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) { + RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; + RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA1LPEN; + } + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) { + RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; + RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA2LPEN; + } + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmaStreamClearInterrupt(dmastp); + dmastp->channel->CR = STM32_DMA_CR_RESET_VALUE; + dmastp->channel->FCR = STM32_DMA_FCR_RESET_VALUE; + + /* Enables the associated IRQ vector if a callback is defined.*/ + if (func != NULL) + NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + + return FALSE; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + chDbgCheck(dmastp != NULL, "dmaRelease"); + + /* Check if the streams is not taken.*/ + chDbgAssert((dma_streams_mask & dmastp->mask) != 0, + "dmaRelease(), #1", "not allocated"); + + /* Disables the associated IRQ vector.*/ + NVICDisableVector(dmastp->vector); + + /* Marks the stream as not allocated.*/ + dma_streams_mask &= ~(1 << dmastp->selfindex); + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) { + RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA1EN; + RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA1LPEN; + } + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) { + RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2EN; + RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA2LPEN; + } +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h new file mode 100644 index 000000000..a1266fec4 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/stm32_dma.h @@ -0,0 +1,327 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F4xx/stm32_dma.h + * @brief Enhanced-DMA helper driver header. + * @note This file requires definitions from the ST STM32F2xx header file + * stm32f2xx.h. + * + * @addtogroup STM32_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Total number of DMA streams. + * @note This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS 16 + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x3D + +/** + * @name DMA streams identifiers + * @{ + */ +#define STM32_DMA1_STREAM0 (&_stm32_dma_streams[0]) +#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[1]) +#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[2]) +#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[3]) +#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[4]) +#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[5]) +#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[6]) +#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[7]) +#define STM32_DMA2_STREAM0 (&_stm32_dma_streams[8]) +#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[9]) +#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[10]) +#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[11]) +#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[12]) +#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[13]) +#define STM32_DMA2_STREAM6 (&_stm32_dma_streams[14]) +#define STM32_DMA2_STREAM7 (&_stm32_dma_streams[15]) +/** @} */ + +/** + * @name CR register constants common to all DMA types + */ +#define STM32_DMA_CR_EN DMA_SxCR_EN +#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE +#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE +#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE +#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR +#define STM32_DMA_CR_DIR_P2M 0 +#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0 +#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1 +#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC +#define STM32_DMA_CR_PINC DMA_SxCR_PINC +#define STM32_DMA_CR_MINC DMA_SxCR_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0 +#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0 +#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1 +#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL +#define STM32_DMA_CR_PL(n) ((n) << 16) +/** @} */ + +/** + * @name CR register constants only found in STM32F2xx + */ +#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE +#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL +#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS +#define STM32_DMA_CR_DBM DMA_SxCR_DBM +#define STM32_DMA_CR_CT DMA_SxCR_CT +#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST +#define STM32_DMA_CR_PBURST_SINGLE 0 +#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0 +#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1 +#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) +#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST +#define STM32_DMA_CR_MBURST_SINGLE 0 +#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0 +#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1 +#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) +#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL +#define STM32_DMA_CR_CHSEL(n) ((n) << 25) +/** @} */ + +/** + * @name FCR register constants only found in STM32F2xx + */ +#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE +#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS +#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS +#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH +#define STM32_DMA_FCR_FTH_1Q 0 +#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0 +#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1 +#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1) +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + */ +#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0 +#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0 +#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0 +#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0 +#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA stream descriptor structure. + */ +typedef struct { + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ + uint8_t ishift; /**< @brief Bits offset in xIFCR + register. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the xISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the PAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->stream->PAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M0AR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->stream->M0AR = (uint32_t)(addr); \ +} + +/** + * @brief Associates an alternate memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the M1AR register + * + * @special + */ +#define dmaStreamSetMemory1(dmastp, addr) { \ + (dmastp)->stream->M1AR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->stream->NDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->stream->CR = (uint32_t)(mode); \ +} + +/** + * @brief Programs the stream FIFO settings. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the FCR register + * + * @special + */ +#define dmaStreamSetFIFO(dmastp, mode) { \ + (dmastp)->stream->FCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmachp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmachp) { \ + (dmastp)->stream->CR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/stm32f4xx.h b/os/hal/platforms/STM32F4xx/stm32f4xx.h new file mode 100644 index 000000000..60dc0622a --- /dev/null +++ b/os/hal/platforms/STM32F4xx/stm32f4xx.h @@ -0,0 +1,7000 @@ +/** + ****************************************************************************** + * @file stm32f4xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 30-September-2011 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F4xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F4XX) + #define STM32F4XX +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F4XX) + #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F4XX Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F4XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; + +/** + * @} + */ + + /* CHIBIOS FIX */ +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +/*#include "system_stm32f4xx.h"*/ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + uint16_t RESERVED11; /*!< Reserved, 0x46 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED12; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED13; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED14; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ +} HASH_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*! Date: Wed, 2 Nov 2011 20:39:26 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3461 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile | 5 +++++ demos/ARM7-AT91SAM7S-GCC/Makefile | 5 +++++ demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile | 5 +++++ demos/ARM7-AT91SAM7X-GCC/Makefile | 5 +++++ demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 5 +++++ demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 5 +++++ demos/ARM7-LPC214x-FATFS-GCC/Makefile | 5 +++++ demos/ARM7-LPC214x-G++/Makefile | 5 +++++ demos/ARM7-LPC214x-GCC/Makefile | 5 +++++ demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile | 5 +++++ demos/ARMCM3-GENERIC-KERNEL/Makefile | 5 +++++ demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile | 5 +++++ demos/ARMCM3-STM32F100-DISCOVERY/Makefile | 5 +++++ demos/ARMCM3-STM32F103-FATFS/Makefile | 5 +++++ demos/ARMCM3-STM32F103-G++/Makefile | 5 +++++ demos/ARMCM3-STM32F103/Makefile | 5 +++++ demos/ARMCM3-STM32F103ZG-FATFS/Makefile | 5 +++++ demos/ARMCM3-STM32F107/Makefile | 5 +++++ demos/ARMCM3-STM32L152-DISCOVERY/Makefile | 5 +++++ demos/MSP430-MSP430x1611-GCC/Makefile | 5 +++++ demos/PPC-SPC563-GCC/Makefile | 5 +++++ os/ports/GCC/ARM/rules.mk | 3 ++- os/ports/GCC/ARMCMx/rules.mk | 3 ++- os/ports/GCC/MSP430/rules.mk | 3 ++- os/ports/GCC/PPC/rules.mk | 3 ++- testhal/LPC11xx/IRQ_STORM/Makefile | 5 +++++ testhal/LPC13xx/IRQ_STORM/Makefile | 5 +++++ testhal/STM32F1xx/ADC/Makefile | 5 +++++ testhal/STM32F1xx/CAN/Makefile | 5 +++++ testhal/STM32F1xx/EXT/Makefile | 5 +++++ testhal/STM32F1xx/EXT_WAKEUP/Makefile | 5 +++++ testhal/STM32F1xx/GPT/Makefile | 5 +++++ testhal/STM32F1xx/I2C/Makefile | 7 ++++++- testhal/STM32F1xx/IRQ_STORM/Makefile | 5 +++++ testhal/STM32F1xx/MAC/Makefile | 5 +++++ testhal/STM32F1xx/PWM-ICU/Makefile | 5 +++++ testhal/STM32F1xx/RTC/Makefile | 5 +++++ testhal/STM32F1xx/SDC/Makefile | 5 +++++ testhal/STM32F1xx/SPI/Makefile | 5 +++++ testhal/STM32F1xx/UART/Makefile | 5 +++++ testhal/STM32F1xx/USB_CDC/Makefile | 5 +++++ testhal/STM32F1xx/USB_MSC/Makefile | 5 +++++ testhal/STM32L1xx/ADC/Makefile | 5 +++++ testhal/STM32L1xx/EXT/Makefile | 5 +++++ testhal/STM32L1xx/GPT/Makefile | 5 +++++ testhal/STM32L1xx/IRQ_STORM/Makefile | 5 +++++ testhal/STM32L1xx/PWM-ICU/Makefile | 5 +++++ testhal/STM32L1xx/SPI/Makefile | 5 +++++ testhal/STM32L1xx/UART/Makefile | 5 +++++ 49 files changed, 234 insertions(+), 5 deletions(-) diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile index adc817ee5..fd0e38598 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARM7-AT91SAM7S-GCC/Makefile b/demos/ARM7-AT91SAM7S-GCC/Makefile index 4b9b64dac..6c93f9d39 100644 --- a/demos/ARM7-AT91SAM7S-GCC/Makefile +++ b/demos/ARM7-AT91SAM7S-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile index fa7345ac3..09ac4e822 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 02aef99ab..02da69ba2 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index 1ec4e05ff..81e62fe24 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile index 5ce1c763c..09d89a9aa 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARM7-LPC214x-FATFS-GCC/Makefile b/demos/ARM7-LPC214x-FATFS-GCC/Makefile index 79373b307..a768f7ca5 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/Makefile +++ b/demos/ARM7-LPC214x-FATFS-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 58fda12e8..67b294b7c 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti -fno-exceptions diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 521670bde..6be46ea25 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile b/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile index 780883687..9919f1519 100644 --- a/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARMCM3-GENERIC-KERNEL/Makefile b/demos/ARMCM3-GENERIC-KERNEL/Makefile index 18ba489eb..13e548692 100644 --- a/demos/ARMCM3-GENERIC-KERNEL/Makefile +++ b/demos/ARMCM3-GENERIC-KERNEL/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile b/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile index e54b4243c..9b6daf3c0 100644 --- a/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/Makefile b/demos/ARMCM3-STM32F100-DISCOVERY/Makefile index 9d97a1866..1438aabd2 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/Makefile +++ b/demos/ARMCM3-STM32F100-DISCOVERY/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARMCM3-STM32F103-FATFS/Makefile b/demos/ARMCM3-STM32F103-FATFS/Makefile index 9aeb9d4e4..b75514038 100644 --- a/demos/ARMCM3-STM32F103-FATFS/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARMCM3-STM32F103-G++/Makefile b/demos/ARMCM3-STM32F103-G++/Makefile index 6a7b3f97e..7fa37b7b0 100644 --- a/demos/ARMCM3-STM32F103-G++/Makefile +++ b/demos/ARMCM3-STM32F103-G++/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti -fno-exceptions diff --git a/demos/ARMCM3-STM32F103/Makefile b/demos/ARMCM3-STM32F103/Makefile index 7d9fd52f6..f9c6ec62a 100644 --- a/demos/ARMCM3-STM32F103/Makefile +++ b/demos/ARMCM3-STM32F103/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/Makefile b/demos/ARMCM3-STM32F103ZG-FATFS/Makefile index 52fb87144..cf05df7c9 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/Makefile +++ b/demos/ARMCM3-STM32F103ZG-FATFS/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARMCM3-STM32F107/Makefile b/demos/ARMCM3-STM32F107/Makefile index 17d3bc855..75521eb30 100644 --- a/demos/ARMCM3-STM32F107/Makefile +++ b/demos/ARMCM3-STM32F107/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/Makefile b/demos/ARMCM3-STM32L152-DISCOVERY/Makefile index 35f22d9d6..dc82a2f04 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/Makefile +++ b/demos/ARMCM3-STM32L152-DISCOVERY/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 647080524..2d5568fd7 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/demos/PPC-SPC563-GCC/Makefile b/demos/PPC-SPC563-GCC/Makefile index 01b7a6f93..d771d2eb9 100644 --- a/demos/PPC-SPC563-GCC/Makefile +++ b/demos/PPC-SPC563-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/os/ports/GCC/ARM/rules.mk b/os/ports/GCC/ARM/rules.mk index 18503fed4..94840e7f3 100644 --- a/os/ports/GCC/ARM/rules.mk +++ b/os/ports/GCC/ARM/rules.mk @@ -12,6 +12,7 @@ OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ # Automatic compiler options OPT = $(USE_OPT) +COPT = $(USE_COPT) CPPOPT = $(USE_CPPOPT) ifeq ($(USE_LINK_GC),yes) OPT += -ffunction-sections -fdata-sections @@ -56,7 +57,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) ifeq ($(USE_LINK_GC),yes) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) diff --git a/os/ports/GCC/ARMCMx/rules.mk b/os/ports/GCC/ARMCMx/rules.mk index e40892fa9..cda8ceda2 100644 --- a/os/ports/GCC/ARMCMx/rules.mk +++ b/os/ports/GCC/ARMCMx/rules.mk @@ -12,6 +12,7 @@ OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ # Automatic compiler options OPT = $(USE_OPT) +COPT = $(USE_COPT) CPPOPT = $(USE_CPPOPT) ifeq ($(USE_LINK_GC),yes) OPT += -ffunction-sections -fdata-sections @@ -56,7 +57,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) ifeq ($(USE_LINK_GC),yes) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) diff --git a/os/ports/GCC/MSP430/rules.mk b/os/ports/GCC/MSP430/rules.mk index 181feba88..81eb443eb 100644 --- a/os/ports/GCC/MSP430/rules.mk +++ b/os/ports/GCC/MSP430/rules.mk @@ -2,6 +2,7 @@ # Automatic compiler options OPT = $(USE_OPT) +COPT = $(USE_COPT) CPPOPT = $(USE_CPPOPT) ifeq ($(USE_CURRP_CACHING),yes) OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' @@ -33,7 +34,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mmcu=$(MCU) ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) ifeq ($(LINK_GC),yes) LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) else diff --git a/os/ports/GCC/PPC/rules.mk b/os/ports/GCC/PPC/rules.mk index 4e45135d4..b5f5060ef 100644 --- a/os/ports/GCC/PPC/rules.mk +++ b/os/ports/GCC/PPC/rules.mk @@ -2,6 +2,7 @@ # Automatic compiler options OPT = $(USE_OPT) +COPT = $(USE_COPT) CPPOPT = $(USE_CPPOPT) ifeq ($(USE_CURRP_CACHING),yes) OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' @@ -33,7 +34,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(CWARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) ifeq ($(LINK_GC),yes) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) else diff --git a/testhal/LPC11xx/IRQ_STORM/Makefile b/testhal/LPC11xx/IRQ_STORM/Makefile index d81cc6208..2dd75ef71 100644 --- a/testhal/LPC11xx/IRQ_STORM/Makefile +++ b/testhal/LPC11xx/IRQ_STORM/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/LPC13xx/IRQ_STORM/Makefile b/testhal/LPC13xx/IRQ_STORM/Makefile index ce797ce3e..081579754 100644 --- a/testhal/LPC13xx/IRQ_STORM/Makefile +++ b/testhal/LPC13xx/IRQ_STORM/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/ADC/Makefile b/testhal/STM32F1xx/ADC/Makefile index a225f325c..0f7e20317 100644 --- a/testhal/STM32F1xx/ADC/Makefile +++ b/testhal/STM32F1xx/ADC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/CAN/Makefile b/testhal/STM32F1xx/CAN/Makefile index a225f325c..0f7e20317 100644 --- a/testhal/STM32F1xx/CAN/Makefile +++ b/testhal/STM32F1xx/CAN/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/EXT/Makefile b/testhal/STM32F1xx/EXT/Makefile index ef8dc610b..190662d49 100644 --- a/testhal/STM32F1xx/EXT/Makefile +++ b/testhal/STM32F1xx/EXT/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/EXT_WAKEUP/Makefile b/testhal/STM32F1xx/EXT_WAKEUP/Makefile index f81417481..be2ae829f 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/Makefile +++ b/testhal/STM32F1xx/EXT_WAKEUP/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/GPT/Makefile b/testhal/STM32F1xx/GPT/Makefile index a225f325c..0f7e20317 100644 --- a/testhal/STM32F1xx/GPT/Makefile +++ b/testhal/STM32F1xx/GPT/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/I2C/Makefile b/testhal/STM32F1xx/I2C/Makefile index 8bbb71015..dc2441200 100644 --- a/testhal/STM32F1xx/I2C/Makefile +++ b/testhal/STM32F1xx/I2C/Makefile @@ -9,6 +9,11 @@ ifeq ($(USE_OPT),) #USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -Wall -Wextra endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti @@ -122,7 +127,7 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ # Compiler settings # -# -lm äîáàâëåí èìåííî çäåñü, ïîòîìó ÷òî áîëüøå íåêóäà +# -lm �������� ������ �����, ������ ��� ������ ������ MCU = cortex-m3 #TRGT = arm-elf- diff --git a/testhal/STM32F1xx/IRQ_STORM/Makefile b/testhal/STM32F1xx/IRQ_STORM/Makefile index a225f325c..0f7e20317 100644 --- a/testhal/STM32F1xx/IRQ_STORM/Makefile +++ b/testhal/STM32F1xx/IRQ_STORM/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/MAC/Makefile b/testhal/STM32F1xx/MAC/Makefile index f493e4a2d..626ff0b9d 100644 --- a/testhal/STM32F1xx/MAC/Makefile +++ b/testhal/STM32F1xx/MAC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/PWM-ICU/Makefile b/testhal/STM32F1xx/PWM-ICU/Makefile index a225f325c..0f7e20317 100644 --- a/testhal/STM32F1xx/PWM-ICU/Makefile +++ b/testhal/STM32F1xx/PWM-ICU/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/RTC/Makefile b/testhal/STM32F1xx/RTC/Makefile index fa40730f9..e0c032c91 100644 --- a/testhal/STM32F1xx/RTC/Makefile +++ b/testhal/STM32F1xx/RTC/Makefile @@ -19,6 +19,11 @@ ifeq ($(USE_OPT),) #USE_OPT = -Os -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/SDC/Makefile b/testhal/STM32F1xx/SDC/Makefile index f1195d4b0..4e25ee845 100644 --- a/testhal/STM32F1xx/SDC/Makefile +++ b/testhal/STM32F1xx/SDC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/SPI/Makefile b/testhal/STM32F1xx/SPI/Makefile index a225f325c..0f7e20317 100644 --- a/testhal/STM32F1xx/SPI/Makefile +++ b/testhal/STM32F1xx/SPI/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/UART/Makefile b/testhal/STM32F1xx/UART/Makefile index a225f325c..0f7e20317 100644 --- a/testhal/STM32F1xx/UART/Makefile +++ b/testhal/STM32F1xx/UART/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/USB_CDC/Makefile b/testhal/STM32F1xx/USB_CDC/Makefile index ee6f94363..0c781d14c 100644 --- a/testhal/STM32F1xx/USB_CDC/Makefile +++ b/testhal/STM32F1xx/USB_CDC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32F1xx/USB_MSC/Makefile b/testhal/STM32F1xx/USB_MSC/Makefile index 7c5126ccd..1f76375fe 100644 --- a/testhal/STM32F1xx/USB_MSC/Makefile +++ b/testhal/STM32F1xx/USB_MSC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32L1xx/ADC/Makefile b/testhal/STM32L1xx/ADC/Makefile index dbe1c0f78..0d3a8e2b2 100644 --- a/testhal/STM32L1xx/ADC/Makefile +++ b/testhal/STM32L1xx/ADC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32L1xx/EXT/Makefile b/testhal/STM32L1xx/EXT/Makefile index dbe1c0f78..0d3a8e2b2 100644 --- a/testhal/STM32L1xx/EXT/Makefile +++ b/testhal/STM32L1xx/EXT/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32L1xx/GPT/Makefile b/testhal/STM32L1xx/GPT/Makefile index dbe1c0f78..0d3a8e2b2 100644 --- a/testhal/STM32L1xx/GPT/Makefile +++ b/testhal/STM32L1xx/GPT/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32L1xx/IRQ_STORM/Makefile b/testhal/STM32L1xx/IRQ_STORM/Makefile index dbe1c0f78..0d3a8e2b2 100644 --- a/testhal/STM32L1xx/IRQ_STORM/Makefile +++ b/testhal/STM32L1xx/IRQ_STORM/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32L1xx/PWM-ICU/Makefile b/testhal/STM32L1xx/PWM-ICU/Makefile index dbe1c0f78..0d3a8e2b2 100644 --- a/testhal/STM32L1xx/PWM-ICU/Makefile +++ b/testhal/STM32L1xx/PWM-ICU/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32L1xx/SPI/Makefile b/testhal/STM32L1xx/SPI/Makefile index dbe1c0f78..0d3a8e2b2 100644 --- a/testhal/STM32L1xx/SPI/Makefile +++ b/testhal/STM32L1xx/SPI/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti diff --git a/testhal/STM32L1xx/UART/Makefile b/testhal/STM32L1xx/UART/Makefile index dbe1c0f78..0d3a8e2b2 100644 --- a/testhal/STM32L1xx/UART/Makefile +++ b/testhal/STM32L1xx/UART/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) USE_CPPOPT = -fno-rtti -- cgit v1.2.3 From 6d159cc390ec49136915ed124750a1c2f26b8f47 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 3 Nov 2011 18:02:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3462 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/hal_lld.h | 503 +------------------------ os/hal/platforms/STM32F1xx/hal_lld_f100.h | 185 ++++++++- os/hal/platforms/STM32F1xx/hal_lld_f103.h | 340 ++++++++++++++++- os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 107 +++++- os/hal/platforms/STM32F4xx/hal_lld.h | 86 +++-- os/hal/platforms/STM32L1xx/hal_lld.h | 59 ++- readme.txt | 6 +- 7 files changed, 746 insertions(+), 540 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index da9e610fd..9b87b0a85 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -55,509 +55,26 @@ /* Derived constants and error checks. */ /*===========================================================================*/ +#if defined(__DOXYGEN__) /** - * @brief Platform name. + * @name Platform identification + * @{ */ -#if defined(__DOXYGEN__) #define PLATFORM_NAME "STM32" +/** @} */ -#elif defined(STM32F10X_LD_VL) -/* - * Capability flags for Value Line Low Density devices. - */ -#define PLATFORM_NAME "STM32 Value Line Low Density" -#include "hal_lld_f100.h" - -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE - -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE - -#define STM32_HAS_DAC TRUE - -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -#define STM32_HAS_ETH FALSE - -#define STM32_EXTI_NUM_CHANNELS 19 - -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE - -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 FALSE - -#define STM32_HAS_RTC TRUE - -#define STM32_HAS_SDIO FALSE - -#define STM32_HAS_SPI1 TRUE -#define STM32_HAS_SPI2 FALSE -#define STM32_HAS_SPI3 FALSE - -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE - -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_USART6 FALSE - -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE - -#elif defined(STM32F10X_MD_VL) -/* - * Capability flags for Value Line Medium Density devices. - */ -#define PLATFORM_NAME "STM32 Value Line Medium Density" +#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) || defined(__DOXYGEN__) #include "hal_lld_f100.h" -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE - -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE - -#define STM32_HAS_DAC TRUE - -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -#define STM32_HAS_ETH FALSE - -#define STM32_EXTI_NUM_CHANNELS 19 - -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE - -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE - -#define STM32_HAS_RTC TRUE - -#define STM32_HAS_SDIO FALSE - -#define STM32_HAS_SPI1 TRUE -#define STM32_HAS_SPI2 TRUE -#define STM32_HAS_SPI3 FALSE - -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE - -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_USART6 FALSE - -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE - -#elif defined(STM32F10X_LD) -/* - * Capability flags for Performance Line Low Density devices. - */ -#define PLATFORM_NAME "STM32 Performance Line Low Density" -#include "hal_lld_f103.h" - -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE - -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE - -#define STM32_HAS_DAC FALSE - -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -#define STM32_HAS_ETH FALSE - -#define STM32_EXTI_NUM_CHANNELS 19 - -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE - -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 FALSE - -#define STM32_HAS_RTC TRUE - -#define STM32_HAS_SDIO FALSE - -#define STM32_HAS_SPI1 TRUE -#define STM32_HAS_SPI2 FALSE -#define STM32_HAS_SPI3 FALSE - -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE - -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_USART6 FALSE - -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE - -#elif defined(STM32F10X_MD) -/* - * Capability flags for Performance Line Medium Density devices. - */ -#define PLATFORM_NAME "STM32 Performance Line Medium Density" -#include "hal_lld_f103.h" - -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE - -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE - -#define STM32_HAS_DAC FALSE - -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -#define STM32_HAS_ETH FALSE - -#define STM32_EXTI_NUM_CHANNELS 19 - -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE - -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE - -#define STM32_HAS_RTC TRUE - -#define STM32_HAS_SDIO FALSE - -#define STM32_HAS_SPI1 TRUE -#define STM32_HAS_SPI2 TRUE -#define STM32_HAS_SPI3 FALSE - -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE - -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE -#define STM32_HAS_USART6 FALSE - -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE - -#elif defined(STM32F10X_HD) -/* - * Capability flags for Performance Line High Density devices. - */ -#define PLATFORM_NAME "STM32 Performance Line High Density" -#include "hal_lld_f103.h" - -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE - -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE - -#define STM32_HAS_DAC TRUE - -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -#define STM32_HAS_ETH FALSE - -#define STM32_EXTI_NUM_CHANNELS 19 - -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE - -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE - -#define STM32_HAS_RTC TRUE - -#define STM32_HAS_SDIO TRUE - -#define STM32_HAS_SPI1 TRUE -#define STM32_HAS_SPI2 TRUE -#define STM32_HAS_SPI3 TRUE - -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 TRUE -#define STM32_HAS_TIM9 TRUE -#define STM32_HAS_TIM10 TRUE -#define STM32_HAS_TIM11 TRUE -#define STM32_HAS_TIM12 TRUE -#define STM32_HAS_TIM13 TRUE -#define STM32_HAS_TIM14 TRUE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE - -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 TRUE -#define STM32_HAS_UART5 TRUE -#define STM32_HAS_USART6 FALSE - -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE - -#elif defined(STM32F10X_XL) -/* - * Capability flags for Performance Line eXtra Density devices. - */ -#define PLATFORM_NAME "STM32 Performance Line eXtra Density" +#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ + defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ + defined(__DOXYGEN__) #include "hal_lld_f103.h" -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE - -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE - -#define STM32_HAS_DAC TRUE - -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -#define STM32_HAS_ETH FALSE - -#define STM32_EXTI_NUM_CHANNELS 19 - -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE - -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE - -#define STM32_HAS_RTC TRUE - -#define STM32_HAS_SDIO TRUE - -#define STM32_HAS_SPI1 TRUE -#define STM32_HAS_SPI2 TRUE -#define STM32_HAS_SPI3 TRUE - -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 TRUE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE - -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 TRUE -#define STM32_HAS_UART5 TRUE -#define STM32_HAS_USART6 FALSE - -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE - -#elif defined(STM32F10X_CL) -/* - * Capability flags for Connectivity Line devices. - */ -#define PLATFORM_NAME "STM32 Connectivity Line" +#elif defined(STM32F10X_CL) || defined(__DOXYGEN__) #include "hal_lld_f105_f107.h" -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE - -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE - -#define STM32_HAS_DAC TRUE - -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -#define STM32_HAS_ETH TRUE - -#define STM32_EXTI_NUM_CHANNELS 20 - -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE - -#define STM32_HAS_I2C1 TRUE -#define STM32_HAS_I2C2 TRUE - -#define STM32_HAS_RTC TRUE - -#define STM32_HAS_SDIO FALSE - -#define STM32_HAS_SPI1 TRUE -#define STM32_HAS_SPI2 TRUE -#define STM32_HAS_SPI3 TRUE - -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE - -#define STM32_HAS_USART1 TRUE -#define STM32_HAS_USART2 TRUE -#define STM32_HAS_USART3 TRUE -#define STM32_HAS_UART4 TRUE -#define STM32_HAS_UART5 TRUE -#define STM32_HAS_USART6 FALSE - -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 TRUE - #else #error "unspecified, unsupported or invalid STM32 platform" #endif diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 012cf0c11..864be581e 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -40,10 +40,35 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @name Platform identification + * @{ + */ +#if defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32 Value Line" + +#elif defined(STM32F10X_LD_VL) +#define PLATFORM_NAME "STM32 Value Line Low Density" + +#elif defined(STM32F10X_MD_VL) +#define PLATFORM_NAME "STM32 Value Line Medium Density" +#else +#error "unsupported STM32 Value Line member" +#endif +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ #define STM32_HSICLK 8000000 /**< High speed internal clock. */ #define STM32_LSICLK 40000 /**< Low speed internal clock. */ +/** @} */ -/* RCC_CFGR register bits definitions.*/ +/** + * @name RCC_CFGR register bits definitions + * @{ + */ #define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ #define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ #define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ @@ -92,11 +117,168 @@ #define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ #define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) +/** + * @name STM32F100 LD capabilities + * @{ + */ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE + +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE + +#define STM32_HAS_DAC TRUE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +#define STM32_HAS_ETH FALSE + +#define STM32_EXTI_NUM_CHANNELS 19 + +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C3 FALSE + +#define STM32_HAS_RTC TRUE + +#define STM32_HAS_SDIO FALSE + +#define STM32_HAS_SPI1 TRUE +#define STM32_HAS_SPI2 FALSE +#define STM32_HAS_SPI3 FALSE + +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE + +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE + +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_LD_VL) */ + +#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__) +/** + * @name STM32F100 MD capabilities + * @{ + */ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE + +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE + +#define STM32_HAS_DAC TRUE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +#define STM32_HAS_ETH FALSE + +#define STM32_EXTI_NUM_CHANNELS 19 + +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 FALSE + +#define STM32_HAS_RTC TRUE + +#define STM32_HAS_SDIO FALSE + +#define STM32_HAS_SPI1 TRUE +#define STM32_HAS_SPI2 TRUE +#define STM32_HAS_SPI3 FALSE + +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE + +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE + +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_MD_VL) */ /*===========================================================================*/ /* Platform specific friendly IRQ names. */ /*===========================================================================*/ +/** + * @name IRQ VECTOR names + * @{ + */ #define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ #define PVD_IRQHandler Vector44 /**< PVD through EXTI Line detect. */ @@ -149,6 +331,7 @@ #define TIM12_IRQHandler VectorEC /**< TIM12. */ #define TIM13_IRQHandler VectorF0 /**< TIM13. */ #define TIM14_IRQHandler VectorF4 /**< TIM14. */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 7f493ee01..7c04b7d38 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -40,10 +40,42 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @name Platform identification + * @{ + */ +#if defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32 Performance Line" + +#elif defined(STM32F10X_LD) +#define PLATFORM_NAME "STM32 Performance Line Low Density" + +#elif defined(STM32F10X_MD) +#define PLATFORM_NAME "STM32 Performance Line Medium Density" + +#elif defined(STM32F10X_HD) +#define PLATFORM_NAME "STM32 Performance Line High Density" + +#elif defined(STM32F10X_XL) +#define PLATFORM_NAME "STM32 Performance Line eXtra Density" + +#else +#error "unsupported STM32 Performance Line member" +#endif +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ #define STM32_HSICLK 8000000 /**< High speed internal clock. */ #define STM32_LSICLK 40000 /**< Low speed internal clock. */ +/** @} */ -/* RCC_CFGR register bits definitions.*/ +/** + * @name RCC_CFGR register bits definitions + * @{ + */ #define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ #define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ #define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ @@ -95,11 +127,316 @@ #define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ #define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +#if defined(STM32F10X_LD) || defined(__DOXYGEN__) +/** + * @name STM32F103 LD capabilities + * @{ + */ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE + +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE + +#define STM32_HAS_DAC FALSE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +#define STM32_HAS_ETH FALSE + +#define STM32_EXTI_NUM_CHANNELS 19 + +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C3 FALSE + +#define STM32_HAS_RTC TRUE + +#define STM32_HAS_SDIO FALSE + +#define STM32_HAS_SPI1 TRUE +#define STM32_HAS_SPI2 FALSE +#define STM32_HAS_SPI3 FALSE + +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE + +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_LD) */ + +#if defined(STM32F10X_MD) || defined(__DOXYGEN__) +/** + * @name STM32F103 MD capabilities + * @{ + */ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE + +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE + +#define STM32_HAS_DAC FALSE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +#define STM32_HAS_ETH FALSE + +#define STM32_EXTI_NUM_CHANNELS 19 + +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 FALSE + +#define STM32_HAS_RTC TRUE + +#define STM32_HAS_SDIO FALSE + +#define STM32_HAS_SPI1 TRUE +#define STM32_HAS_SPI2 TRUE +#define STM32_HAS_SPI3 FALSE + +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE + +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_MD) */ + +#if defined(STM32F10X_HD) || defined(__DOXYGEN__) +/** + * @name STM32F103 HD capabilities + * @{ + */ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE + +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE + +#define STM32_HAS_DAC TRUE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +#define STM32_HAS_ETH FALSE + +#define STM32_EXTI_NUM_CHANNELS 19 + +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 FALSE + +#define STM32_HAS_RTC TRUE + +#define STM32_HAS_SDIO TRUE + +#define STM32_HAS_SPI1 TRUE +#define STM32_HAS_SPI2 TRUE +#define STM32_HAS_SPI3 TRUE + +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 TRUE +#define STM32_HAS_TIM10 TRUE +#define STM32_HAS_TIM11 TRUE +#define STM32_HAS_TIM12 TRUE +#define STM32_HAS_TIM13 TRUE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 FALSE + +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_HD) */ + +#if defined(STM32F10X_XL) || defined(__DOXYGEN__) +/** + * @name STM32F103 XL capabilities + * @{ + */ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE + +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE + +#define STM32_HAS_DAC TRUE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +#define STM32_HAS_ETH FALSE + +#define STM32_EXTI_NUM_CHANNELS 19 + +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 FALSE + +#define STM32_HAS_RTC TRUE + +#define STM32_HAS_SDIO TRUE + +#define STM32_HAS_SPI1 TRUE +#define STM32_HAS_SPI2 TRUE +#define STM32_HAS_SPI3 TRUE + +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 TRUE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 FALSE + +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ +#endif /* defined(STM32F10X_XL) */ /*===========================================================================*/ /* Platform specific friendly IRQ names. */ /*===========================================================================*/ +/** + * @name IRQ VECTOR names + * @{ + */ #define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ #define PVD_IRQHandler Vector44 /**< PVD through EXTI Line detect. */ @@ -165,6 +502,7 @@ #define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ #define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ #define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 25e28c62d..e4361c77f 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -40,10 +40,25 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "STM32 Connectivity Line" +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ #define STM32_HSICLK 8000000 /**< High speed internal clock. */ #define STM32_LSICLK 40000 /**< Low speed internal clock. */ +/** @} */ -/* RCC_CFGR register bits definitions.*/ +/** + * @name RCC_CFGR register bits definitions + * @{ + */ #define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ #define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ #define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ @@ -97,15 +112,100 @@ #define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ #define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock. */ +/** @} */ -/* RCC_CFGR2 register bits definitions.*/ +/** + * @name RCC_CFGR2 register bits definitions + * @{ + */ #define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */ #define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F105/F107 CL capabilities + * @{ + */ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE + +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE + +#define STM32_HAS_DAC TRUE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +#define STM32_HAS_ETH TRUE + +#define STM32_EXTI_NUM_CHANNELS 20 + +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 FALSE + +#define STM32_HAS_RTC TRUE + +#define STM32_HAS_SDIO FALSE + +#define STM32_HAS_SPI1 TRUE +#define STM32_HAS_SPI2 TRUE +#define STM32_HAS_SPI3 TRUE + +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 TRUE +#define STM32_HAS_TIM5 TRUE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE + +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 FALSE + +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 TRUE +#define STM32_HAS_OTG2 FALSE +/** @} */ /*===========================================================================*/ /* Platform specific friendly IRQ names. */ /*===========================================================================*/ +/** + * @name IRQ VECTOR names + * @{ + */ #define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ #define PVD_IRQHandler Vector44 /**< PVD through EXTI Line detect. */ @@ -172,7 +272,8 @@ #define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ #define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ #define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ - +/** @} */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 1371f0e8e..1b6882511 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -44,14 +44,24 @@ /*===========================================================================*/ /** - * @brief Platform name. + * @name Platform identification + * @{ */ #define PLATFORM_NAME "STM32F2 High performance" +/** @} */ +/** + * @name Internal clock sources + * @{ + */ #define STM32_HSICLK 16000000 /**< High speed internal clock. */ #define STM32_LSICLK 38000 /**< Low speed internal clock. */ +/** @} */ -/* RCC_PLLCFGR register bits definitions.*/ +/** + * @name RCC_PLLCFGR register bits definitions + * @{ + */ #define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ #define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ #define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ @@ -60,8 +70,12 @@ #define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ #define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ +/** @} */ -/* RCC_CFGR register bits definitions.*/ +/** + * @name RCC_CFGR register bits definitions + * @{ + */ #define STM32_SW_MASK (3 << 0) /**< SW mask. */ #define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ #define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ @@ -120,11 +134,22 @@ #define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */ #define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */ -/* RCC_PLLI2SCFGR register bits definitions.*/ +/** + * @name RCC_PLLI2SCFGR register bits definitions + * @{ + */ #define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */ #define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ -/* STM32F2xx capabilities.*/ +/** + * @name STM32F4xx capabilities + * @{ + */ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE #define STM32_HAS_ADC3 TRUE @@ -153,6 +178,7 @@ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 TRUE #define STM32_HAS_RTC TRUE @@ -189,11 +215,17 @@ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 TRUE +#define STM32_HAS_OTG2 TRUE +/** @} */ /*===========================================================================*/ /* Platform specific friendly IRQ names. */ /*===========================================================================*/ +/** + * @name IRQ VECTOR names + * @{ + */ #define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ #define PVD_IRQHandler Vector44 /**< PVD through EXTI Line detect. */ @@ -281,6 +313,8 @@ #define DCMI_IRQHandler Vector178 /**< DCMI. */ #define CRYP_IRQHandler Vector17C /**< CRYP. */ #define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */ +#define FPU_IRQHandler Vector184 /**< Floating Point Unit. */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -321,26 +355,12 @@ #define STM32_LSE_ENABLED FALSE #endif -/** - * @brief ADC clock setting. - */ -#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__) -#define STM32_ADC_CLOCK_ENABLED TRUE -#endif - -/** - * @brief USB clock setting. - */ -#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__) -#define STM32_USB_CLOCK_ENABLED TRUE -#endif - /** * @brief Main clock source selection. * @note If the selected clock source is not the PLL then the PLL is not * initialized and started. - * @note The default value is calculated for a 32MHz system clock from - * the internal 16MHz HSI clock. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. */ #if !defined(STM32_SW) || defined(__DOXYGEN__) #define STM32_SW STM32_SW_PLL @@ -350,8 +370,8 @@ * @brief Clock source for the PLL. * @note This setting has only effect if the PLL is selected as the * system clock source. - * @note The default value is calculated for a 120MHz system clock from - * the external 25MHz HSE clock. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. */ #if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) #define STM32_PLLSRC STM32_PLLSRC_HSE @@ -360,8 +380,8 @@ /** * @brief PLLM divider value. * @note The allowed values are 2..63. - * @note The default value is calculated for a 120MHz system clock from - * an external 25MHz HSE clock. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. */ #if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) #define STM32_PLLM_VALUE 25 @@ -370,8 +390,8 @@ /** * @brief PLLN multiplier value. * @note The allowed values are 192..432. - * @note The default value is calculated for a 120MHz system clock from - * an external 25MHz HSE clock. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. */ #if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) #define STM32_PLLN_VALUE 240 @@ -380,8 +400,8 @@ /** * @brief PLLP multiplier value. * @note The allowed values are DIV2, DIV4, DIV6, DIV8. - * @note The default value is calculated for a 120MHz system clock from - * an external 25MHz HSE clock. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. */ #if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) #define STM32_PLLP_VALUE 2 @@ -390,8 +410,8 @@ /** * @brief PLLQ multiplier value. * @note The allowed values are 4..15. - * @note The default value is calculated for a 120MHz system clock from - * an external 25MHz HSE clock. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. */ #if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) #define STM32_PLLQ_VALUE 5 @@ -399,8 +419,8 @@ /** * @brief AHB prescaler value. - * @note The default value is calculated for a 120MHz system clock from - * an external 25MHz HSE clock. + * @note The default value is calculated for a 168MHz system clock from + * an external 8MHz HSE clock. */ #if !defined(STM32_HPRE) || defined(__DOXYGEN__) #define STM32_HPRE STM32_HPRE_DIV1 diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 6efee2ca7..7ad613b5f 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -50,27 +50,45 @@ /*===========================================================================*/ /** - * @brief Platform name. + * @name Platform identification + * @{ */ #define PLATFORM_NAME "STM32L Ultra Low Power Medium Density" +/** @} */ +/** + * @name Internal clock sources + * @{ + */ #define STM32_HSICLK 16000000 /**< High speed internal clock. */ #define STM32_LSICLK 38000 /**< Low speed internal clock. */ +/** @} */ -/* PWR_CR register bits definitions.*/ +/** + * @name PWR_CR register bits definitions + * @{ + */ #define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */ #define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */ #define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ #define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */ +/** @} */ -/* RCC_CR register bits definitions.*/ +/** + * @name RCC_CR register bits definitions + * @{ + */ #define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */ #define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */ #define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */ #define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */ #define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */ +/** @} */ -/* RCC_CFGR register bits definitions.*/ +/** + * @name RCC_CFGR register bits definitions + * @{ + */ #define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */ #define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */ #define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */ @@ -115,8 +133,12 @@ #define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 1. */ #define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 1. */ #define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 1. */ +/** @} */ -/* RCC_ICSCR register bits definitions.*/ +/** + * @name RCC_ICSCR register bits definitions + * @{ + */ #define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */ #define STM32_MSIRANGE_64K (0 << 13) /**< 64KHz nominal. */ #define STM32_MSIRANGE_128K (1 << 13) /**< 128KHz nominal. */ @@ -125,15 +147,27 @@ #define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */ #define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */ #define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */ +/** @} */ -/* RCC_CSR register bits definitions.*/ +/** + * @name RCC_CSR register bits definitions + * @{ + */ #define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */ #define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */ #define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */ #define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */ #define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */ +/** @} */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ -/* STM32L1xx capabilities.*/ +/** + * @name STM32L1xx capabilities + * @{ + */ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE @@ -158,9 +192,11 @@ #define STM32_HAS_GPIOF FALSE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI FALSE #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 FALSE #define STM32_HAS_RTC TRUE @@ -197,9 +233,16 @@ #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ + +/*===========================================================================*/ +/* Platform specific friendly IRQ names. */ +/*===========================================================================*/ /** - * @name Platform specific friendly IRQ names + * @name IRQ VECTOR names + * @{ */ #define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ #define PVD_IRQHandler Vector44 /**< PVD through EXTI Line diff --git a/readme.txt b/readme.txt index 937ec5b82..ffce54fea 100644 --- a/readme.txt +++ b/readme.txt @@ -76,7 +76,11 @@ *** 2.3.4 *** - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). -- NEW: Added EXT driver implementation for AT91SAM7x contributed by Florian. +- NEW: Reorganized the STM32F1xx hal_lld_xxx.h files in order to distribute + the capability macros into the appropriate file (previously those were all + in the common hal_lld.h). +- NEW: Added USE_COPT setting to all makefiles, contributed by Mabl. +- NEW: Added EXT driver implementation for AT91SAM7x, contributed by Florian. (TODO: Test application missing). - NEW: Updated USB driver model and STM32 implementation and fixed several problems. -- cgit v1.2.3 From c90189fc103322b3f2ea85bc59a50d92cc9f2913 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 3 Nov 2011 18:06:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3463 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/USBv1/usb_lld.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.c b/os/hal/platforms/STM32/USBv1/usb_lld.c index e148a6fea..3ecf738da 100644 --- a/os/hal/platforms/STM32/USBv1/usb_lld.c +++ b/os/hal/platforms/STM32/USBv1/usb_lld.c @@ -421,8 +421,8 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { dp = USB_GET_DESCRIPTOR(ep); dp->TXCOUNT0 = 0; dp->RXCOUNT0 = nblocks; - dp->TXADDR = pm_alloc(usbp, epcp->in_maxsize); - dp->RXADDR = pm_alloc(usbp, epcp->out_maxsize); + dp->TXADDR0 = pm_alloc(usbp, epcp->in_maxsize); + dp->RXADDR0 = pm_alloc(usbp, epcp->out_maxsize); } /** @@ -516,7 +516,7 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { (void)usbp; udp = USB_GET_DESCRIPTOR(ep); - pmap = USB_ADDR2PTR(udp->RXADDR); + pmap = USB_ADDR2PTR(udp->RXADDR0); for (n = 0; n < 4; n++) { *(uint16_t *)buf = (uint16_t)*pmap++; buf += 2; @@ -548,7 +548,7 @@ size_t usb_lld_read_packet_buffer(USBDriver *usbp, usbep_t ep, (void)usbp; udp = USB_GET_DESCRIPTOR(ep); - pmap = USB_ADDR2PTR(udp->RXADDR); + pmap = USB_ADDR2PTR(udp->RXADDR0); count = (size_t)udp->RXCOUNT0 & RXCOUNT_COUNT_MASK; if (n > count) n = count; @@ -582,7 +582,7 @@ void usb_lld_write_packet_buffer(USBDriver *usbp, usbep_t ep, (void)usbp; udp = USB_GET_DESCRIPTOR(ep); - pmap = USB_ADDR2PTR(udp->TXADDR); + pmap = USB_ADDR2PTR(udp->TXADDR0); udp->TXCOUNT0 = (uint16_t)n; n = (n + 1) / 2; while (n > 0) { -- cgit v1.2.3 From 7a9ba73df808b2ea3b410a7d1f75293115881c90 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 3 Nov 2011 18:07:58 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3464 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/various/shell.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os/various/shell.c b/os/various/shell.c index 4c84a7b51..94aeb5045 100644 --- a/os/various/shell.c +++ b/os/various/shell.c @@ -205,6 +205,7 @@ static msg_t shell_thread(void *p) { chSysLock(); chEvtBroadcastI(&shell_terminated); chThdExitS(msg); + return 0; /* Never executed.*/ } /** -- cgit v1.2.3 From bf185be2602528df7dd0f388b350cb71a378a1ce Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 3 Nov 2011 21:58:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3465 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32F4_DISCOVERY/board.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/boards/ST_STM32F4_DISCOVERY/board.h b/boards/ST_STM32F4_DISCOVERY/board.h index b3d2f23e7..30742b9af 100644 --- a/boards/ST_STM32F4_DISCOVERY/board.h +++ b/boards/ST_STM32F4_DISCOVERY/board.h @@ -233,7 +233,7 @@ PIN_MODE_INPUT(9) | \ PIN_MODE_ALTERNATE(GPIOC_SCLK) | \ PIN_MODE_INPUT(11) | \ - PIN_MODE_ALTERNATE(GPIOC_SDIN)) \ + PIN_MODE_ALTERNATE(GPIOC_SDIN) | \ PIN_MODE_INPUT(13) | \ PIN_MODE_INPUT(14) | \ PIN_MODE_INPUT(15)) @@ -242,16 +242,16 @@ #define VAL_GPIOC_PUPDR (PIN_PUDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ PIN_PUDR_PULLUP(1) | \ PIN_PUDR_PULLUP(2) | \ - PIN_PUDR_FLOATING(GPIOC_DOUT)) | \ + PIN_PUDR_FLOATING(GPIOC_DOUT) | \ PIN_PUDR_PULLUP(4) | \ PIN_PUDR_PULLUP(5) | \ PIN_PUDR_PULLUP(6) | \ - PIN_PUDR_FLOATING(GPIOC_MCLK)) | \ + PIN_PUDR_FLOATING(GPIOC_MCLK) | \ PIN_PUDR_PULLUP(8) | \ PIN_PUDR_PULLUP(9) | \ - PIN_PUDR_FLOATING(GPIOC_SCLK)) | \ + PIN_PUDR_FLOATING(GPIOC_SCLK) | \ PIN_PUDR_PULLUP(11) | \ - PIN_PUDR_FLOATING(GPIOC_SDIN)) | \ + PIN_PUDR_FLOATING(GPIOC_SDIN) | \ PIN_PUDR_PULLUP(13) | \ PIN_PUDR_PULLUP(14) | \ PIN_PUDR_PULLUP(15)) -- cgit v1.2.3 From ba89f675a2affeaa66f06c31085ecc95b88e25df Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 4 Nov 2011 20:20:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3466 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32F4_DISCOVERY/board.h | 6 + os/hal/platforms/STM32F1xx/hal_lld_f100.h | 6 +- os/hal/platforms/STM32F1xx/hal_lld_f103.h | 10 +- os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 2 +- os/hal/platforms/STM32F4xx/hal_lld.h | 149 ++++++++++++++++++++----- os/hal/platforms/STM32L1xx/hal_lld.h | 2 +- 6 files changed, 135 insertions(+), 40 deletions(-) diff --git a/boards/ST_STM32F4_DISCOVERY/board.h b/boards/ST_STM32F4_DISCOVERY/board.h index 30742b9af..00940a684 100644 --- a/boards/ST_STM32F4_DISCOVERY/board.h +++ b/boards/ST_STM32F4_DISCOVERY/board.h @@ -38,6 +38,12 @@ #define STM32_LSECLK 0 #define STM32_HSECLK 8000000 +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300 + /* * MCU type as defined in the ST header file stm32l1xx.h. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 864be581e..cdad07bc5 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -45,13 +45,13 @@ * @{ */ #if defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32 Value Line" +#define PLATFORM_NAME "STM32F1 Value Line" #elif defined(STM32F10X_LD_VL) -#define PLATFORM_NAME "STM32 Value Line Low Density" +#define PLATFORM_NAME "STM32F1 Value Line Low Density" #elif defined(STM32F10X_MD_VL) -#define PLATFORM_NAME "STM32 Value Line Medium Density" +#define PLATFORM_NAME "STM32F1 Value Line Medium Density" #else #error "unsupported STM32 Value Line member" #endif diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 7c04b7d38..92144b5dc 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -45,19 +45,19 @@ * @{ */ #if defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32 Performance Line" +#define PLATFORM_NAME "STM32F1 Performance Line" #elif defined(STM32F10X_LD) -#define PLATFORM_NAME "STM32 Performance Line Low Density" +#define PLATFORM_NAME "STM32F1 Performance Line Low Density" #elif defined(STM32F10X_MD) -#define PLATFORM_NAME "STM32 Performance Line Medium Density" +#define PLATFORM_NAME "STM32F1 Performance Line Medium Density" #elif defined(STM32F10X_HD) -#define PLATFORM_NAME "STM32 Performance Line High Density" +#define PLATFORM_NAME "STM32F1 Performance Line High Density" #elif defined(STM32F10X_XL) -#define PLATFORM_NAME "STM32 Performance Line eXtra Density" +#define PLATFORM_NAME "STM32F1 Performance Line eXtra Density" #else #error "unsupported STM32 Performance Line member" diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index e4361c77f..52de807d2 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -44,7 +44,7 @@ * @name Platform identification * @{ */ -#define PLATFORM_NAME "STM32 Connectivity Line" +#define PLATFORM_NAME "STM32F1 Connectivity Line" /** @} */ /** diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 1b6882511..38581b6bd 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -25,6 +25,7 @@ * @p board.h file: * - STM32_LSECLK. * - STM32_HSECLK. + * - STM32_VDD (as hundredths of Volt). * . * One of the following macros must also be defined: * - STM32F4XX for High-performance STM32 F-4 devices. @@ -47,7 +48,7 @@ * @name Platform identification * @{ */ -#define PLATFORM_NAME "STM32F2 High performance" +#define PLATFORM_NAME "STM32F4 High Performance & DSP" /** @} */ /** @@ -58,6 +59,15 @@ #define STM32_LSICLK 38000 /**< Low speed internal clock. */ /** @} */ +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */ +#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */ +#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */ +/** @} */ + /** * @name RCC_PLLCFGR register bits definitions * @{ @@ -114,6 +124,10 @@ #define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ #define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ +#define STM32_I2CSRC_MASK (1 << 23) /**< I2CSRC mask. */ +#define STM32_I2CSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ +#define STM32_I2CSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ + #define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ #define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ #define STM32_MCO1PRE_DIV2 (1 << 24) /**< MCO1 divided by 2. */ @@ -327,6 +341,16 @@ #define STM32_NO_INIT FALSE #endif +/** + * @brief Core voltage selection. + * @note This setting affects all the performance and clock related + * settings, the maximum performance is only obtainable selecting + * the maximum voltage. + */ +#if !defined(STM32_VOS) || defined(__DOXYGEN__) +#define STM32_VOS STM32_VOS_HIGH +#endif + /** * @brief Enables or disables the HSI clock source. */ @@ -367,7 +391,7 @@ #endif /** - * @brief Clock source for the PLL. + * @brief Clock source for the PLLs. * @note This setting has only effect if the PLL is selected as the * system clock source. * @note The default value is calculated for a 168MHz system clock from @@ -384,7 +408,7 @@ * an external 8MHz HSE clock. */ #if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLM_VALUE 25 +#define STM32_PLLM_VALUE 8 #endif /** @@ -394,17 +418,17 @@ * an external 8MHz HSE clock. */ #if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLN_VALUE 240 +#define STM32_PLLN_VALUE 336 #endif /** - * @brief PLLP multiplier value. - * @note The allowed values are DIV2, DIV4, DIV6, DIV8. + * @brief PLLP divider value. + * @note The allowed values are 2, 4, 6, 8. * @note The default value is calculated for a 168MHz system clock from * an external 8MHz HSE clock. */ #if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLP_VALUE 2 +#define STM32_PLLP_VALUE 2 #endif /** @@ -414,7 +438,7 @@ * an external 8MHz HSE clock. */ #if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLQ_VALUE 5 +#define STM32_PLLQ_VALUE 7 #endif /** @@ -444,7 +468,7 @@ * @brief RTC prescaler value. */ #if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__) -#define STM32_RTCPRE_VALUE 25 +#define STM32_RTCPRE_VALUE 8 #endif /** @@ -479,24 +503,35 @@ #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #endif + +/** + * @brief Enables or disables the I2S clock source. + */ +#if !defined(STM32_I2S_ENABLED) || defined(__DOXYGEN__) +#define STM32_I2S_ENABLED FALSE +#endif + +/** + * @brief I2S clock source. + */ +#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) +#define STM32_I2SSRC STM32_I2CSRC_PLLI2S +#endif + /** * @brief PLLI2SN multiplier value. * @note The allowed values are 192..432. - * @note The default value is calculated for a 48000 I2S clock with - * I2SDIV = 12 and I2SODD = 1. */ #if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLI2SN_VALUE 384 +#define STM32_PLLI2SN_VALUE 192 #endif /** * @brief PLLI2SR multiplier value. * @note The allowed values are 2..7. - * @note The default value is calculated for a 48000 I2S clock with - * I2SDIV = 12 and I2SODD = 1. */ -#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__) -#define STM32_PLI2SLP_VALUE 5 +#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SR_VALUE 5 #endif /*===========================================================================*/ @@ -506,47 +541,101 @@ /** * @brief Maximum HSECLK. */ -#define STM32_HSECLK_MAX 32000000 +#define STM32_HSECLK_MAX 26000000 + +/** + * @brief Minimum HSECLK. + */ +#define STM32_HSECLK_MIN 1000000 /** * @brief Maximum SYSCLK. + * @note It is a function of the core voltage setting. */ -#define STM32_SYSCLK_MAX 120000000 +#if (STM32_VOS == STM32_VOS_HIGH) || defined(__DOXYGEN__) +#define STM32_SYSCLK_MAX 168000000 +#else +#define STM32_SYSCLK_MAX 144000000 +#endif /** * @brief Maximum frequency thresholds and wait states for flash access. * @note The values are valid for 2.7V to 3.6V supply range. */ +#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) #define STM32_0WS_THRESHOLD 30000000 #define STM32_1WS_THRESHOLD 60000000 #define STM32_2WS_THRESHOLD 90000000 -#define STM32_3WS_THRESHOLD 0 -#define STM32_4WS_THRESHOLD 0 -#define STM32_5WS_THRESHOLD 0 +#define STM32_3WS_THRESHOLD 120000000 +#define STM32_4WS_THRESHOLD 150000000 +#define STM32_5WS_THRESHOLD 168000000 #define STM32_6WS_THRESHOLD 0 #define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 240) && (STM32_VDD < 270) +#define STM32_0WS_THRESHOLD 24000000 +#define STM32_1WS_THRESHOLD 48000000 +#define STM32_2WS_THRESHOLD 72000000 +#define STM32_3WS_THRESHOLD 96000000 +#define STM32_4WS_THRESHOLD 120000000 +#define STM32_5WS_THRESHOLD 144000000 +#define STM32_6WS_THRESHOLD 168000000 +#define STM32_7WS_THRESHOLD 0 +#elif (STM32_VDD >= 210) && (STM32_VDD < 240) +#define STM32_0WS_THRESHOLD 18000000 +#define STM32_1WS_THRESHOLD 36000000 +#define STM32_2WS_THRESHOLD 54000000 +#define STM32_3WS_THRESHOLD 72000000 +#define STM32_4WS_THRESHOLD 90000000 +#define STM32_5WS_THRESHOLD 108000000 +#define STM32_6WS_THRESHOLD 120000000 +#define STM32_7WS_THRESHOLD 138000000 +#elif (STM32_VDD >= 180) && (STM32_VDD < 210) +#define STM32_0WS_THRESHOLD 16000000 +#define STM32_1WS_THRESHOLD 32000000 +#define STM32_2WS_THRESHOLD 48000000 +#define STM32_3WS_THRESHOLD 64000000 +#define STM32_4WS_THRESHOLD 80000000 +#define STM32_5WS_THRESHOLD 96000000 +#define STM32_6WS_THRESHOLD 112000000 +#define STM32_7WS_THRESHOLD 128000000 +#else +#error "invalid VDD voltage specified" +#endif /* HSI related checks.*/ #if STM32_HSI_ENABLED #else /* !STM32_HSI_ENABLED */ -#if STM32_ADC_CLOCK_ENABLED || \ - (STM32_SW == STM32_SW_HSI) || \ - ((STM32_SW == STM32_SW_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSI)) || \ - (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \ + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \ ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ (STM32_PLLSRC == STM32_PLLSRC_HSI)) -#error "required HSI clock is not enabled" +#error "HSI not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSI) || \ + ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCO2SEL" #endif + +#if STM32_I2S_ENABLED && \ + (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_I2S_ENABLED and STM32_I2SSRC" +#endif + #endif /* !STM32_HSI_ENABLED */ /* HSE related checks.*/ #if STM32_HSE_ENABLED #if STM32_HSECLK == 0 #error "impossible to activate HSE" -#endif -#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX) -#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)" +#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" #endif #else /* !STM32_HSE_ENABLED */ #if (STM32_SW == STM32_SW_HSE) || \ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 7ad613b5f..09bd9bf78 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -53,7 +53,7 @@ * @name Platform identification * @{ */ -#define PLATFORM_NAME "STM32L Ultra Low Power Medium Density" +#define PLATFORM_NAME "STM32L1 Ultra Low Power Medium Density" /** @} */ /** -- cgit v1.2.3 From 5649691bf9e05cd64fa244de733497f7dbc4efae Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Nov 2011 08:14:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3467 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/hal_lld.h | 284 ++++++++++++++++++++++++----------- os/hal/platforms/STM32L1xx/hal_lld.h | 53 +++++-- 2 files changed, 233 insertions(+), 104 deletions(-) diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 38581b6bd..6fc67e39e 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -51,6 +51,71 @@ #define PLATFORM_NAME "STM32F4 High Performance & DSP" /** @} */ +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 26000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 1000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 1000 + +/** + * @brief Maximum PLL input clock frequency. + */ +#define STM32_PLLIN_MAX 2000000 + +/** + * @brief Maximum PLL input clock frequency. + */ +#define STM32_PLLIN_MIN 950000 + +/** + * @brief Maximum PLLCLKOUT clock frequency. + */ +#define STM32_PLLVCO_MAX 432000000 + +/** + * @brief Maximum PLLCLKOUT clock frequency. + */ +#define STM32_PLLVCO_MIN 192000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 168000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 24000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 42000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 84000000 +/** @} */ + /** * @name Internal clock sources * @{ @@ -156,6 +221,17 @@ #define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ /** @} */ +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ +/** @} */ + /*===========================================================================*/ /* Platform capabilities. */ /*===========================================================================*/ @@ -379,6 +455,20 @@ #define STM32_LSE_ENABLED FALSE #endif +/** + * @brief USB clock setting. + */ +#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_USB_CLOCK_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the I2S clock source. + */ +#if !defined(STM32_I2S_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_I2S_CLOCK_ENABLED FALSE +#endif + /** * @brief Main clock source selection. * @note If the selected clock source is not the PLL then the PLL is not @@ -465,9 +555,16 @@ #endif /** - * @brief RTC prescaler value. + * @brief RTC source clock. */ -#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__) +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSE +#endif + +/** + * @brief RTC HSE prescaler value. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) #define STM32_RTCPRE_VALUE 8 #endif @@ -503,12 +600,11 @@ #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #endif - /** * @brief Enables or disables the I2S clock source. */ -#if !defined(STM32_I2S_ENABLED) || defined(__DOXYGEN__) -#define STM32_I2S_ENABLED FALSE +#if !defined(STM32_I2S_CLOCK_ENABLED) || defined(__DOXYGEN__) +#define STM32_I2S_CLOCK_ENABLED FALSE #endif /** @@ -538,16 +634,6 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -/** - * @brief Maximum HSECLK. - */ -#define STM32_HSECLK_MAX 26000000 - -/** - * @brief Minimum HSECLK. - */ -#define STM32_HSECLK_MIN 1000000 - /** * @brief Maximum SYSCLK. * @note It is a function of the core voltage setting. @@ -602,10 +688,16 @@ #error "invalid VDD voltage specified" #endif -/* HSI related checks.*/ +/* + * HSI related checks. + */ #if STM32_HSI_ENABLED #else /* !STM32_HSI_ENABLED */ +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + #if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) #error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" #endif @@ -622,59 +714,95 @@ #error "HSI not enabled, required by STM32_MCO2SEL" #endif -#if STM32_I2S_ENABLED && \ +#if STM32_I2S_CLOCK_ENABLED && \ (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \ (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_I2S_ENABLED and STM32_I2SSRC" +#error "HSI not enabled, required by STM32_I2S_CLOCK_ENABLED and STM32_I2SSRC" #endif #endif /* !STM32_HSI_ENABLED */ -/* HSE related checks.*/ +/* + * HSE related checks. + */ #if STM32_HSE_ENABLED + #if STM32_HSECLK == 0 -#error "impossible to activate HSE" +#error "HSE frequency not defined" #elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" #endif + #else /* !STM32_HSE_ENABLED */ -#if (STM32_SW == STM32_SW_HSE) || \ - ((STM32_SW == STM32_SW_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ - (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \ ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ - (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \ ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ - (STM32_PLLSRC == STM32_PLLSRC_HSE)) || \ - (STM_RTC_SOURCE == STM32_RTCSEL_HSEDIV) -#error "required HSE clock is not enabled" + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO2SEL" #endif + +#if STM32_I2S_CLOCK_ENABLED && \ + (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_I2S_CLOCK_ENABLED and STM32_I2SSRC" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + #endif /* !STM32_HSE_ENABLED */ -/* LSI related checks.*/ +/* + * LSI related checks. + */ #if STM32_LSI_ENABLED #else /* !STM32_LSI_ENABLED */ -#if STM_RTCCLK == STM32_LSICLK + +#if STM32_RTCSEL == STM32_RTCSEL_LSI #error "required LSI clock is not enabled" #endif + #endif /* !STM32_LSI_ENABLED */ -/* LSE related checks.*/ +/* + * LSE related checks. + */ #if STM32_LSE_ENABLED + #if (STM32_LSECLK == 0) -#error "impossible to activate LSE" +#error "LSE frequency not defined" #endif -#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000) -#error "STM32_LSECLK outside acceptable range (1...1000KHz)" + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" #endif + #else /* !#if STM32_LSE_ENABLED */ -#if STM_RTCCLK == STM32_LSECLK -#error "required LSE clock is not enabled" + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" #endif + #endif /* !#if STM32_LSE_ENABLED */ -/* PLL related checks.*/ +/* + * PLL related checks. + */ #if STM32_USB_CLOCK_ENABLED || \ (STM32_SW == STM32_SW_PLL) || \ (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \ @@ -693,7 +821,7 @@ */ #if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ defined(__DOXYGEN__) -#define STM32_PLLM STM32_PLLM_VALUE +#define STM32_PLLM (STM32_PLLM_VALUE << 0) #else #error "invalid STM32_PLLM_VALUE value specified" #endif @@ -737,28 +865,29 @@ * @brief PLL input clock frequency. */ #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLCLKIN STM32_HSECLK +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) #elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN STM32_HSICLK +#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) #else #error "invalid STM32_PLLSRC value specified" #endif /* PLL input frequency range check.*/ -#if (STM32_PLLCLKIN < 4000000) || (STM32_PLLCLKIN > 26000000) -#error "STM32_PLLCLKIN outside acceptable range (4...26MHz)" +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" #endif /** * @brief PLL VCO frequency. */ -#define STM32_PLLVCO ((STM32_PLLCLKIN / STM32_PLLM_VALUE) * \ - STM32_PLLN_VALUE) +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) -/* PLL output frequency range check.*/ -#if (STM32_PLLVCO < 192000000) || (STM32_PLLVCO > 432000000) +/* + * PLL output frequency range check. + */ +#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) #error STM32_PLLVCO -#error "STM32_PLLVCO outside acceptable range (192...432MHz)" +#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" #endif /** @@ -767,15 +896,15 @@ #define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) /* PLL output frequency range check.*/ -#if (STM32_PLLCLKOUT < 24000000) || (STM32_PLLCLKOUT > 120000000) -#error "STM32_PLLCLKOUT outside acceptable range (24...120MHz)" +#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" #endif /** * @brief System clock source. */ #if STM32_NO_INIT || defined(__DOXYGEN__) -#define STM32_SYSCLK 96000000 +#define STM32_SYSCLK STM32_HSICLK #elif (STM32_SW == STM32_SW_HSI) #define STM32_SYSCLK STM32_HSICLK #elif (STM32_SW == STM32_SW_HSE) @@ -816,7 +945,9 @@ #error "invalid STM32_HPRE value specified" #endif -/* AHB frequency check.*/ +/* + * AHB frequency check. + */ #if STM32_HCLK > STM32_SYSCLK_MAX #error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" #endif @@ -838,9 +969,11 @@ #error "invalid STM32_PPRE1 value specified" #endif -/* APB1 frequency check.*/ -#if STM32_PCLK2 > STM32_SYSCLK_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_SYSCLK_MAX)" +/* + * APB1 frequency check. + */ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" #endif /** @@ -860,9 +993,11 @@ #error "invalid STM32_PPRE2 value specified" #endif -/* APB2 frequency check.*/ -#if STM32_PCLK2 > STM32_SYSCLK_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)" +/* + * APB2 frequency check. + */ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" #endif /** @@ -918,7 +1053,6 @@ #define STM_MCO2DIVCLK STM32_SYSCLK #elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S #define STM_MCO2DIVCLK STM32_PLLI2S - #else #error "invalid STM32_MCO2SEL value specified" #endif @@ -943,9 +1077,9 @@ /** * @brief HSE divider toward RTC clock. */ -#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ defined(__DOXYGEN__) -#define STM32_HSEDIVCLK (HSECLK / STM32_RTCPRE_VALUE) +#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE) #else #error "invalid STM32_RTCPRE value specified" #endif @@ -965,36 +1099,10 @@ #error "invalid STM32_RTCSEL value specified" #endif -/** - * @brief ADC frequency. - */ -#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) -#define STM32_ADCCLK (STM32_PCLK2 / 2) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_PCLK2 / 4) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV6 -#define STM32_ADCCLK (STM32_PCLK2 / 6) -#elif STM32_ADCPRE == STM32_ADCPRE_DIV8 -#define STM32_ADCCLK (STM32_PCLK2 / 8) -#else -#error "invalid STM32_ADCPRE value specified" -#endif - -/* ADC frequency check.*/ -#if STM32_ADCCLK > 30000000 -#error "STM32_ADCCLK exceeding maximum frequency (30MHz)" -#endif - /** * @brief OTG frequency. */ -#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__) -#define STM32_OTGFSCLK (STM32_PLLVCO / 3) -#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2) -#define STM32_OTGFSCLK (STM32_PLLVCO / 2) -#else -#error "invalid STM32_OTGFSPRE value specified" -#endif +#define STM32_OTGFSCLK (STM32_PLLVCO / STM32_PLLQ_VALUE) /** * @brief Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock. diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 09bd9bf78..9ca34fb7c 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -464,19 +464,34 @@ /* Voltage related limits.*/ #if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__) /** - * @brief Maximum HSECLK at current voltage setting. + * @brief Maximum HSE clock frequency at current voltage setting. */ #define STM32_HSECLK_MAX 32000000 /** - * @brief Maximum SYSCLK at current voltage setting. + * @brief Maximum SYSCLK clock frequency at current voltage setting. */ #define STM32_SYSCLK_MAX 32000000 /** - * @brief Maximum PLLCLKOUT at current voltage setting. + * @brief Maximum VCO clock frequency at current voltage setting. */ -#define STM32_PLLCLKOUT_MAX 96000000 +#define STM32_PLLVCO_MAX 96000000 + +/** + * @brief Minimum VCO clock frequency at current voltage setting. + */ +#define STM32_PLLVCO_MIN 6000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX 32000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX 32000000 /** * @brief Maximum frequency not requiring a wait state for flash accesses. @@ -491,13 +506,19 @@ #elif STM32_VOS == STM32_VOS_1P5 #define STM32_HSECLK_MAX 16000000 #define STM32_SYSCLK_MAX 16000000 -#define STM32_PLLCLKOUT_MAX 48000000 +#define STM32_PLLVCO_MAX 48000000 +#define STM32_PLLVCO_MIN 6000000 +#define STM32_PCLK1_MAX 16000000 +#define STM32_PCLK2_MAX 16000000 #define STM32_0WS_THRESHOLD 8000000 #define STM32_HSI_AVAILABLE TRUE #elif STM32_VOS == STM32_VOS_1P2 #define STM32_HSECLK_MAX 4000000 #define STM32_SYSCLK_MAX 4000000 -#define STM32_PLLCLKOUT_MAX 24000000 +#define STM32_PLLVCO_MAX 24000000 +#define STM32_PLLVCO_MIN 6000000 +#define STM32_PCLK1_MAX 4000000 +#define STM32_PCLK2_MAX 4000000 #define STM32_0WS_THRESHOLD 2000000 #define STM32_HSI_AVAILABLE FALSE #else @@ -636,8 +657,8 @@ #define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) /* PLL output frequency range check.*/ -#if (STM32_PLLVCO < 6000000) || (STM32_PLLVCO > 96000000) -#error "STM32_PLLVCO outside acceptable range (6...96MHz)" +#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" #endif /** @@ -742,8 +763,8 @@ #endif /* APB1 frequency check.*/ -#if STM32_PCLK2 > STM32_SYSCLK_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_SYSCLK_MAX)" +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" #endif /** @@ -764,8 +785,8 @@ #endif /* APB2 frequency check.*/ -#if STM32_PCLK2 > STM32_SYSCLK_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)" +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" #endif /** @@ -810,13 +831,13 @@ * @brief HSE divider toward RTC clock. */ #if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__) -#define STM32_HSEDIVCLK (HSECLK / 2) +#define STM32_HSEDIVCLK (STM32_HSECLK / 2) #elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__) -#define STM32_HSEDIVCLK (HSECLK / 4) +#define STM32_HSEDIVCLK (STM32_HSECLK / 4) #elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__) -#define STM32_HSEDIVCLK (HSECLK / 8) +#define STM32_HSEDIVCLK (STM32_HSECLK / 8) #elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__) -#define STM32_HSEDIVCLK (HSECLK / 16) +#define STM32_HSEDIVCLK (STM32_HSECLK / 16) #else #error "invalid STM32_RTCPRE value specified" #endif -- cgit v1.2.3 From 1297070fa9afcb4895b459bf798822e72bb42ea1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Nov 2011 09:53:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3468 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/hal_lld.h | 187 ++++++++++++++++++++++------------- 1 file changed, 120 insertions(+), 67 deletions(-) diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 6fc67e39e..337b67b55 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -76,22 +76,22 @@ #define STM32_LSECLK_MIN 1000 /** - * @brief Maximum PLL input clock frequency. + * @brief Maximum PLLs input clock frequency. */ #define STM32_PLLIN_MAX 2000000 /** - * @brief Maximum PLL input clock frequency. + * @brief Maximum PLLs input clock frequency. */ #define STM32_PLLIN_MIN 950000 /** - * @brief Maximum PLLCLKOUT clock frequency. + * @brief Maximum PLLs VCO clock frequency. */ #define STM32_PLLVCO_MAX 432000000 /** - * @brief Maximum PLLCLKOUT clock frequency. + * @brief Maximum PLLs VCO clock frequency. */ #define STM32_PLLVCO_MIN 192000000 @@ -114,6 +114,11 @@ * @brief Maximum APB2 clock frequency. */ #define STM32_PCLK2_MAX 84000000 + +/** + * @brief Maximum SPI/I2S clock frequency. + */ +#define STM32_SPII2S_MAX 37500000 /** @} */ /** @@ -458,15 +463,8 @@ /** * @brief USB clock setting. */ -#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__) -#define STM32_USB_CLOCK_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the I2S clock source. - */ -#if !defined(STM32_I2S_CLOCK_ENABLED) || defined(__DOXYGEN__) -#define STM32_I2S_CLOCK_ENABLED FALSE +#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__) +#define STM32_CLOCK48_REQUIRED TRUE #endif /** @@ -600,18 +598,11 @@ #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #endif -/** - * @brief Enables or disables the I2S clock source. - */ -#if !defined(STM32_I2S_CLOCK_ENABLED) || defined(__DOXYGEN__) -#define STM32_I2S_CLOCK_ENABLED FALSE -#endif - /** * @brief I2S clock source. */ #if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) -#define STM32_I2SSRC STM32_I2CSRC_PLLI2S +#define STM32_I2SSRC STM32_I2CSRC_CKIN #endif /** @@ -714,10 +705,9 @@ #error "HSI not enabled, required by STM32_MCO2SEL" #endif -#if STM32_I2S_CLOCK_ENABLED && \ - (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \ +#if (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \ (STM32_PLLSRC == STM32_PLLSRC_HSI) -#error "HSI not enabled, required by STM32_I2S_CLOCK_ENABLED and STM32_I2SSRC" +#error "HSI not enabled, required by STM32_I2SSRC" #endif #endif /* !STM32_HSI_ENABLED */ @@ -755,10 +745,9 @@ #error "HSE not enabled, required by STM32_MCO2SEL" #endif -#if STM32_I2S_CLOCK_ENABLED && \ - (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \ +#if (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \ (STM32_PLLSRC == STM32_PLLSRC_HSE) -#error "HSE not enabled, required by STM32_I2S_CLOCK_ENABLED and STM32_I2SSRC" +#error "HSE not enabled, required by STM32_I2SSRC" #endif #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV @@ -800,10 +789,38 @@ #endif /* !#if STM32_LSE_ENABLED */ +/** + * @brief STM32_PLLM field. + */ +#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ + defined(__DOXYGEN__) +#define STM32_PLLM (STM32_PLLM_VALUE << 0) +#else +#error "invalid STM32_PLLM_VALUE value specified" +#endif + +/** + * @brief PLLs input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) +#else +#error "invalid STM32_PLLSRC value specified" +#endif + /* - * PLL related checks. + * PLLs input frequency range check. */ -#if STM32_USB_CLOCK_ENABLED || \ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/* + * PLL enable check. + */ +#if STM32_CLOCK48_REQUIRED || \ (STM32_SW == STM32_SW_PLL) || \ (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \ (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \ @@ -816,16 +833,6 @@ #define STM32_ACTIVATE_PLL FALSE #endif -/** - * @brief STM32_PLLM field. - */ -#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ - defined(__DOXYGEN__) -#define STM32_PLLM (STM32_PLLM_VALUE << 0) -#else -#error "invalid STM32_PLLM_VALUE value specified" -#endif - /** * @brief STM32_PLLN field. */ @@ -854,39 +861,22 @@ /** * @brief STM32_PLLQ field. */ -#if ((STM32_PLLQ_VALUE >= 4) && (STM32_PLLQ_VALUE <= 15)) || \ +#if ((STM32_PLLQ_VALUE >= 4) && (STM32_PLLQ_VALUE <= 15)) || \ defined(__DOXYGEN__) #define STM32_PLLQ (STM32_PLLQ_VALUE << 24) #else #error "invalid STM32_PLLQ_VALUE value specified" #endif -/** - * @brief PLL input clock frequency. - */ -#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) -#elif STM32_PLLSRC == STM32_PLLSRC_HSI -#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) -#else -#error "invalid STM32_PLLSRC value specified" -#endif - -/* PLL input frequency range check.*/ -#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) -#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" -#endif - /** * @brief PLL VCO frequency. */ -#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) /* - * PLL output frequency range check. + * PLL VCO frequency range check. */ #if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) -#error STM32_PLLVCO #error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" #endif @@ -895,7 +885,9 @@ */ #define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) -/* PLL output frequency range check.*/ +/* + * PLL output frequency range check. + */ #if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX) #error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" #endif @@ -1000,14 +992,61 @@ #error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" #endif +/* + * PLLI2S enable check. + */ +#if (STM32_I2CSRC == STM32_I2CSRC_PLLI2S) || defined(__DOXYGEN__) /** - * @brief RTC frequency. + * @brief PLL activation flag. */ -#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ +#define STM32_ACTIVATE_PLLI2S TRUE +#else +#define STM32_ACTIVATE_PLLI2S FALSE +#endif + +/** + * @brief STM32_PLLI2SN field. + */ +#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \ defined(__DOXYGEN__) -#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) +#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) #else -#error "invalid STM32_RTCPRE value specified" +#error "invalid STM32_PLLI2SN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLI2SR field. + */ +#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28) +#else +#error "invalid STM32_PLLI2SR_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE) + +/* + * PLLI2S VCO frequency range check. + */ +#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ + (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLLI2S output clock frequency. + */ +#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR) + +/* + * PLLI2S output frequency range check. + */ +#if STM32_PLLI2SCLKOUT > STM32_SPII2S_MAX +#error "STM32_PLLI2SCLKOUT outside acceptable range (STM32_SPII2S_MAX)" #endif /** @@ -1084,6 +1123,16 @@ #error "invalid STM32_RTCPRE value specified" #endif +/** + * @brief RTC HSE divider setting. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + /** * @brief RTC clock. */ @@ -1100,9 +1149,13 @@ #endif /** - * @brief OTG frequency. + * @brief 48MHz frequency. */ -#define STM32_OTGFSCLK (STM32_PLLVCO / STM32_PLLQ_VALUE) +#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__) +#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) +#else +#define STM32_PLL48CLK 0 +#endif /** * @brief Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock. @@ -1156,7 +1209,7 @@ /*===========================================================================*/ /* STM32 DMA support code.*/ -//#include "stm32_dma.h" +#include "stm32_dma.h" #ifdef __cplusplus extern "C" { -- cgit v1.2.3 From d5fa815855e904a5928441a45a37b798a0d618e9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Nov 2011 10:58:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3469 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/stm32_rcc.h | 2 +- os/hal/platforms/STM32F4xx/hal_lld.c | 13 +- os/hal/platforms/STM32F4xx/stm32_rcc.h | 887 +++++++++++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/stm32_rcc.h | 2 +- 4 files changed, 895 insertions(+), 9 deletions(-) create mode 100644 os/hal/platforms/STM32F4xx/stm32_rcc.h diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h index 2a5daaadd..aa55d4fca 100644 --- a/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -373,7 +373,7 @@ /** @} */ /** - * @brief I2c peripherals specific RCC operations + * @brief I2C peripherals specific RCC operations * @{ */ /** diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c index 74afa4bdb..ae399242b 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.c +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -58,11 +58,12 @@ */ void hal_lld_init(void) { - /* Reset of all peripherals.*/ -// RCC->APB1RSTR = 0xFFFFFFFF; -// RCC->APB2RSTR = 0xFFFFFFFF; -// RCC->APB1RSTR = 0; -// RCC->APB2RSTR = 0; + /* Reset of all peripherals. AHB3 is not reseted because it could have + been initialized in the board initialization file (board.c).*/ + rccResetAHB1(!0); + rccResetAHB2(!0); + rccResetAPB1(!RCC_APB1RSTR_PWRRST); + rccResetAPB2(!RCC_APB2RSTR_SYSCFGRST); /* SysTick initialization using the system clock.*/ SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; @@ -71,8 +72,6 @@ void hal_lld_init(void) { SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk; - - #if defined(STM32_DMA_REQUIRED) dmaInit(); #endif diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h new file mode 100644 index 000000000..3a10e57b2 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -0,0 +1,887 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F4xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f4xx.h. + * + * @addtogroup STM32F4xx_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ + if (lp) \ + RCC->APB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ + if (lp) \ + RCC->APB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ + if (lp) \ + RCC->APB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB1(mask, lp) { \ + RCC->AHB1ENR |= (mask); \ + if (lp) \ + RCC->AHB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB1(mask, lp) { \ + RCC->AHB1ENR &= ~(mask); \ + if (lp) \ + RCC->AHB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * + * @api + */ +#define rccResetAHB1(mask) { \ + RCC->AHB1RSTR |= (mask); \ + RCC->AHB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB2(mask, lp) { \ + RCC->AHB2ENR |= (mask); \ + if (lp) \ + RCC->AHB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB2(mask, lp) { \ + RCC->AHB2ENR &= ~(mask); \ + if (lp) \ + RCC->AHB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * + * @api + */ +#define rccResetAHB2(mask) { \ + RCC->AHB2RSTR |= (mask); \ + RCC->AHB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB3(mask, lp) { \ + RCC->AHB3ENR |= (mask); \ + if (lp) \ + RCC->AHB3LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB3(mask, lp) { \ + RCC->AHB3ENR &= ~(mask); \ + if (lp) \ + RCC->AHB3LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * + * @api + */ +#define rccResetAHB3(mask) { \ + RCC->AHB3RSTR |= (mask); \ + RCC->AHB3RSTR = 0; \ +} +/** @} */ + +/** + * @brief ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) + +/** + * @brief Enables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Disables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Resets the ADC2 peripheral. + * + * @api + */ +#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST) + +/** + * @brief Enables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Disables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Resets the ADC3 peripheral. + * + * @api + */ +#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST) +/** @} */ + +/** + * @brief DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB(RCC_AHB1RSTR_DMA1RST) + +/** + * @brief Enables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Resets the DMA2 peripheral. + * + * @api + */ +#define rccResetDMA2() rccResetAHB(RCC_AHB1RSTR_DMA2RST) +/** @} */ + +/** + * @brief I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) + +/** + * @brief Enables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Disables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Resets the I2C3 peripheral. + * + * @api + */ +#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST) +/** @} */ + +/** + * @brief SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +/** @} */ + +/** + * @brief TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Disables the TIM5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Resets the TIM5 peripheral. + * + * @api + */ +#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) +/** @} */ + +/** + * @brief USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) + +/** + * @brief Enables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Disables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Enables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) + +/** + * @brief Resets the USART6 peripheral. + * + * @api + */ +#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/platforms/STM32L1xx/stm32_rcc.h index e2460a41f..9ffcc07b4 100644 --- a/os/hal/platforms/STM32L1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32L1xx/stm32_rcc.h @@ -237,7 +237,7 @@ /** @} */ /** - * @brief I2c peripherals specific RCC operations + * @brief I2C peripherals specific RCC operations * @{ */ /** -- cgit v1.2.3 From e5e6b2c513a5338a8b79c745eb841e1d3e063bc9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Nov 2011 13:56:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3470 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32L152-DISCOVERY/readme.txt | 2 +- os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h | 57 +++++ os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld | 146 ++++++++++++ os/ports/GCC/ARMCMx/STM32F4xx/port.mk | 14 ++ os/ports/GCC/ARMCMx/STM32F4xx/vectors.c | 283 ++++++++++++++++++++++++ 5 files changed, 501 insertions(+), 1 deletion(-) create mode 100644 os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h create mode 100644 os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld create mode 100644 os/ports/GCC/ARMCMx/STM32F4xx/port.mk create mode 100644 os/ports/GCC/ARMCMx/STM32F4xx/vectors.c diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt b/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt index 7f19c0889..a79e306a4 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt +++ b/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo runs on an ST STM32VL-Discovery board. +The demo runs on an ST STM32L-Discovery board. ** The Demo ** diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h new file mode 100644 index 000000000..e5d942d61 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h @@ -0,0 +1,57 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F1xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F1xx. + * + * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32F1xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld new file mode 100644 index 000000000..0476b0bf1 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F407xG.ld @@ -0,0 +1,146 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F407xG memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 1M + ram : org = 0x20000000, len = 112k + ethram : org = 0x2001C000, len = 16k + ccmram : org = 0x10000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/port.mk b/os/ports/GCC/ARMCMx/STM32F4xx/port.mk new file mode 100644 index 000000000..072e2d363 --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/port.mk @@ -0,0 +1,14 @@ +# List of the ChibiOS/RT Cortex-M3 STM32 port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F4xx/ld diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c b/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c new file mode 100644 index 000000000..6ee8bb23e --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/vectors.c @@ -0,0 +1,283 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/STM32F4xx/vectors.c + * @brief Interrupt vectors for the STM32F4xx family. + * + * @defgroup ARMCMx_STM32F4xx_VECTORS STM32F4xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the STM32F4xx family. + * @{ + */ + +#include "ch.h" + +#if !defined(__DOXYGEN__) +extern void __main_stack_end__(void); +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void MemManageVector(void); +extern void BusFaultVector(void); +extern void UsageFaultVector(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void DebugMonitorVector(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +extern void VectorC0(void); +extern void VectorC4(void); +extern void VectorC8(void); +extern void VectorCC(void); +extern void VectorD0(void); +extern void VectorD4(void); +extern void VectorD8(void); +extern void VectorDC(void); +extern void VectorE0(void); +extern void VectorE4(void); +extern void VectorE8(void); +extern void VectorEC(void); +extern void VectorF0(void); +extern void VectorF4(void); +extern void VectorF8(void); +extern void VectorFC(void); +extern void Vector100(void); +extern void Vector104(void); +extern void Vector108(void); +extern void Vector10C(void); +extern void Vector110(void); +extern void Vector114(void); +extern void Vector118(void); +extern void Vector11C(void); +extern void Vector120(void); +extern void Vector124(void); +extern void Vector128(void); +extern void Vector12C(void); +extern void Vector130(void); +extern void Vector134(void); +extern void Vector138(void); +extern void Vector13C(void); +extern void Vector140(void); +extern void Vector144(void); +extern void Vector148(void); +extern void Vector14C(void); +extern void Vector150(void); +extern void Vector154(void); +extern void Vector158(void); +extern void Vector15C(void); +extern void Vector160(void); +extern void Vector164(void); +extern void Vector168(void); +extern void Vector16C(void); +extern void Vector170(void); +extern void Vector174(void); +extern void Vector178(void); +extern void Vector17C(void); +extern void Vector180(void); +extern void Vector184(void); +#endif + +/** + * @brief STM32 vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +void (*_vectors[])(void) = { + __main_stack_end__, ResetHandler, NMIVector, HardFaultVector, + MemManageVector, BusFaultVector, UsageFaultVector, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + DebugMonitorVector, Vector34, PendSVVector, SysTickVector, + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC, + VectorC0, VectorC4, VectorC8, VectorCC, + VectorD0, VectorD4, VectorD8, VectorDC, + VectorE0, VectorE4, VectorE8, VectorEC, + VectorF0, VectorF4, VectorF8, VectorFC, + Vector100, Vector104, Vector108, Vector10C, + Vector110, Vector114, Vector118, Vector11C, + Vector120, Vector124, Vector128, Vector12C, + Vector130, Vector134, Vector138, Vector13C, + Vector140, Vector144, Vector148, Vector14C, + Vector150, Vector154, Vector158, Vector15C, + Vector160, Vector164, Vector168, Vector16C, + Vector170, Vector174, Vector178, Vector17C, + Vector180, Vector184 +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + asm volatile ( + ".weak NMIVector \nNMIVector: \n\t" + ".weak HardFaultVector \nHardFaultVector: \n\t" + ".weak MemManageVector \nMemManageVector: \n\t" + ".weak BusFaultVector \nBusFaultVector: \n\t" + ".weak UsageFaultVector \nUsageFaultVector: \n\t" + ".weak Vector1C \nVector1C: \n\t" + ".weak Vector20 \nVector20: \n\t" + ".weak Vector24 \nVector24: \n\t" + ".weak Vector28 \nVector28: \n\t" + ".weak SVCallVector \nSVCallVector: \n\t" + ".weak DebugMonitorVector \nDebugMonitorVector: \n\t" + ".weak Vector34 \nVector34: \n\t" + ".weak PendSVVector \nPendSVVector: \n\t" + ".weak SysTickVector \nSysTickVector: \n\t" + ".weak Vector40 \nVector40: \n\t" + ".weak Vector44 \nVector44: \n\t" + ".weak Vector48 \nVector48: \n\t" + ".weak Vector4C \nVector4C: \n\t" + ".weak Vector50 \nVector50: \n\t" + ".weak Vector54 \nVector54: \n\t" + ".weak Vector58 \nVector58: \n\t" + ".weak Vector5C \nVector5C: \n\t" + ".weak Vector60 \nVector60: \n\t" + ".weak Vector64 \nVector64: \n\t" + ".weak Vector68 \nVector68: \n\t" + ".weak Vector6C \nVector6C: \n\t" + ".weak Vector70 \nVector70: \n\t" + ".weak Vector74 \nVector74: \n\t" + ".weak Vector78 \nVector78: \n\t" + ".weak Vector7C \nVector7C: \n\t" + ".weak Vector80 \nVector80: \n\t" + ".weak Vector84 \nVector84: \n\t" + ".weak Vector88 \nVector88: \n\t" + ".weak Vector8C \nVector8C: \n\t" + ".weak Vector90 \nVector90: \n\t" + ".weak Vector94 \nVector94: \n\t" + ".weak Vector98 \nVector98: \n\t" + ".weak Vector9C \nVector9C: \n\t" + ".weak VectorA0 \nVectorA0: \n\t" + ".weak VectorA4 \nVectorA4: \n\t" + ".weak VectorA8 \nVectorA8: \n\t" + ".weak VectorAC \nVectorAC: \n\t" + ".weak VectorB0 \nVectorB0: \n\t" + ".weak VectorB4 \nVectorB4: \n\t" + ".weak VectorB8 \nVectorB8: \n\t" + ".weak VectorBC \nVectorBC: \n\t" + ".weak VectorC0 \nVectorC0: \n\t" + ".weak VectorC4 \nVectorC4: \n\t" + ".weak VectorC8 \nVectorC8: \n\t" + ".weak VectorCC \nVectorCC: \n\t" + ".weak VectorD0 \nVectorD0: \n\t" + ".weak VectorD4 \nVectorD4: \n\t" + ".weak VectorD8 \nVectorD8: \n\t" + ".weak VectorDC \nVectorDC: \n\t" + ".weak VectorE0 \nVectorE0: \n\t" + ".weak VectorE4 \nVectorE4: \n\t" + ".weak VectorE8 \nVectorE8: \n\t" + ".weak VectorEC \nVectorEC: \n\t" + ".weak VectorF0 \nVectorF0: \n\t" + ".weak VectorF4 \nVectorF4: \n\t" + ".weak VectorF8 \nVectorF8: \n\t" + ".weak VectorFC \nVectorFC: \n\t" + ".weak Vector100 \nVector100: \n\t" + ".weak Vector104 \nVector104: \n\t" + ".weak Vector108 \nVector108: \n\t" + ".weak Vector10C \nVector10C: \n\t" + ".weak Vector110 \nVector110: \n\t" + ".weak Vector114 \nVector114: \n\t" + ".weak Vector118 \nVector118: \n\t" + ".weak Vector11C \nVector11C: \n\t" + ".weak Vector120 \nVector120: \n\t" + ".weak Vector124 \nVector124: \n\t" + ".weak Vector128 \nVector128: \n\t" + ".weak Vector12C \nVector12C: \n\t" + ".weak Vector130 \nVector130: \n\t" + ".weak Vector134 \nVector134: \n\t" + ".weak Vector138 \nVector138: \n\t" + ".weak Vector13C \nVector13C: \n\t" + ".weak Vector140 \nVector140: \n\t" + ".weak Vector144 \nVector144: \n\t" + ".weak Vector148 \nVector148: \n\t" + ".weak Vector14C \nVector14C: \n\t" + ".weak Vector150 \nVector150: \n\t" + ".weak Vector154 \nVector154: \n\t" + ".weak Vector158 \nVector158: \n\t" + ".weak Vector15C \nVector15C: \n\t" + ".weak Vector160 \nVector160: \n\t" + ".weak Vector164 \nVector164: \n\t" + ".weak Vector168 \nVector168: \n\t" + ".weak Vector16C \nVector16C: \n\t" + ".weak Vector170 \nVector170: \n\t" + ".weak Vector174 \nVector174: \n\t" + ".weak Vector178 \nVector178: \n\t" + ".weak Vector17C \nVector17C: \n\t" + ".weak Vector180 \nVector180: \n\t" + ".weak Vector184 \nVector184: \n\t" + ); + + while (TRUE) + ; +} + +/** @} */ -- cgit v1.2.3 From 4895ea3f4ea3c80f9e2648c71d566da69388b4ff Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Nov 2011 13:57:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3471 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h index e5d942d61..96ea09ff8 100644 --- a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h @@ -19,13 +19,13 @@ */ /** - * @file GCC/ARMCMx/STM32F1xx/cmparams.h - * @brief ARM Cortex-M3 parameters for the STM32F1xx. + * @file GCC/ARMCMx/STM32F4xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F4xx. * - * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters + * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters * @ingroup ARMCMx_SPECIFIC * @details This file contains the Cortex-M3 specific parameters for the - * STM32F1xx platform. + * STM32F4xx platform. * @{ */ -- cgit v1.2.3 From cdf83ce254198264167a1102c9c615b141b3c1dd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Nov 2011 14:40:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3472 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32F4_DISCOVERY/board.c | 5 +- boards/ST_STM32F4_DISCOVERY/board.h | 8 +- demos/ARMCM3-STM32F407-DISCOVERY/Makefile | 209 ++++++++ demos/ARMCM3-STM32F407-DISCOVERY/chconf.h | 535 +++++++++++++++++++++ demos/ARMCM3-STM32F407-DISCOVERY/halconf.h | 335 +++++++++++++ demos/ARMCM3-STM32F407-DISCOVERY/main.c | 254 ++++++++++ demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h | 189 ++++++++ demos/ARMCM3-STM32F407-DISCOVERY/readme.txt | 31 ++ os/hal/platforms/STM32/GPIOv2/pal_lld.c | 9 +- os/hal/platforms/STM32F4xx/hal_lld.h | 7 +- os/hal/platforms/STM32F4xx/stm32_dma.h | 2 +- os/hal/platforms/STM32F4xx/stm32f4xx.h | 4 +- os/hal/platforms/STM32L1xx/stm32l1xx.h | 2 + os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h | 3 + 14 files changed, 1582 insertions(+), 11 deletions(-) create mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/Makefile create mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/chconf.h create mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/halconf.h create mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/main.c create mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h create mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/readme.txt diff --git a/boards/ST_STM32F4_DISCOVERY/board.c b/boards/ST_STM32F4_DISCOVERY/board.c index 4a93dada2..efb8ef566 100644 --- a/boards/ST_STM32F4_DISCOVERY/board.c +++ b/boards/ST_STM32F4_DISCOVERY/board.c @@ -34,7 +34,10 @@ const PALConfig pal_default_config = {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH} + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} }; #endif diff --git a/boards/ST_STM32F4_DISCOVERY/board.h b/boards/ST_STM32F4_DISCOVERY/board.h index 00940a684..cd1b64552 100644 --- a/boards/ST_STM32F4_DISCOVERY/board.h +++ b/boards/ST_STM32F4_DISCOVERY/board.h @@ -56,7 +56,7 @@ #define GPIOA_LRCK 4 #define GPIOA_SPC 5 #define GPIOA_SDO 6 -#define GPIOA_SDA_SDI_SDO 7 +#define GPIOA_SDI 7 #define GPIOA_VBUS_FS 9 #define GPIOA_OTG_FS_ID 10 #define GPIOA_OTG_FS_DM 11 @@ -107,7 +107,7 @@ #define PIN_PUDR_FLOATING(n) (0U << ((n) * 2)) #define PIN_PUDR_PULLUP(n) (1U << ((n) * 2)) #define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2)) -#define PIN_AFIO_AF(n, v) ((v)U << ((n % 8) * 4)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) /* * Port A setup. @@ -206,7 +206,7 @@ PIN_PUDR_PULLUP(7) | \ PIN_PUDR_PULLUP(8) | \ PIN_PUDR_FLOATING(GPIOB_SDA) | \ - PIN_PUDR_FLOATING(GPIOB_SCK | \ + PIN_PUDR_FLOATING(GPIOB_SCK) | \ PIN_PUDR_PULLUP(11) | \ PIN_PUDR_PULLUP(12) | \ PIN_PUDR_PULLUP(13) | \ @@ -340,7 +340,7 @@ PIN_MODE_INPUT(15)) #define VAL_GPIOE_OTYPER 0x00000000 #define VAL_GPIOE_OSPEEDR 0xFFFFFFFF -#define VAL_GPIOE_PUPDR (PIN_PUDR_FLOATING(0GPIOE_INT1) | \ +#define VAL_GPIOE_PUPDR (PIN_PUDR_FLOATING(GPIOE_INT1) | \ PIN_PUDR_FLOATING(GPIOE_INT2) | \ PIN_PUDR_PULLUP(2) | \ PIN_PUDR_FLOATING(GPIOE_CS_SPI) | \ diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/Makefile b/demos/ARMCM3-STM32F407-DISCOVERY/Makefile new file mode 100644 index 000000000..28a823c16 --- /dev/null +++ b/demos/ARMCM3-STM32F407-DISCOVERY/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/chconf.h b/demos/ARMCM3-STM32F407-DISCOVERY/chconf.h new file mode 100644 index 000000000..9dd831c96 --- /dev/null +++ b/demos/ARMCM3-STM32F407-DISCOVERY/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/halconf.h b/demos/ARMCM3-STM32F407-DISCOVERY/halconf.h new file mode 100644 index 000000000..b4fb49092 --- /dev/null +++ b/demos/ARMCM3-STM32F407-DISCOVERY/halconf.h @@ -0,0 +1,335 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/main.c b/demos/ARMCM3-STM32F407-DISCOVERY/main.c new file mode 100644 index 000000000..07e158077 --- /dev/null +++ b/demos/ARMCM3-STM32F407-DISCOVERY/main.c @@ -0,0 +1,254 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#if 0 +static void pwmpcb(PWMDriver *pwmp); +static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); +static void spicb(SPIDriver *spip); + +/* Total number of channels to be sampled by a single ADC operation.*/ +#define ADC_GRP1_NUM_CHANNELS 2 + +/* Depth of the conversion buffer, channels are sampled four times each.*/ +#define ADC_GRP1_BUF_DEPTH 4 + +/* + * ADC samples buffer. + */ +static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; + +/* + * ADC conversion group. + * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. + * Channels: IN10 (48 cycles sample time) + * Sensor (192 cycles sample time) + */ +static const ADCConversionGroup adcgrpcfg = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + adccb, + NULL, + /* HW dependent part.*/ + 0, + 0, + 0, + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192), + 0, + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, + 0, + 0, + ADC_SQR5_SQ2_N(ADC_CHANNEL_IN10) | ADC_SQR5_SQ1_N(ADC_CHANNEL_SENSOR) +}; + +/* + * PWM configuration structure. + * Cyclic callback enabled, channels 3 and 4 enabled without callbacks, + * the active state is a logic one. + */ +static PWMConfig pwmcfg = { + 10000, /* 10KHz PWM clock frequency. */ + 10000, /* PWM period 1S (in ticks). */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + /* HW dependent part.*/ + 0 +}; + +/* + * SPI configuration structure. + * Maximum speed (12MHz), CPHA=0, CPOL=0, 16bits frames, MSb transmitted first. + * The slave select line is the pin GPIOA_SPI1NSS on the port GPIOA. + */ +static const SPIConfig spicfg = { + spicb, + /* HW dependent part.*/ + GPIOB, + 12, + SPI_CR1_DFF +}; + +/* + * PWM cyclic callback. + * A new ADC conversion is started. + */ +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + + /* Starts an asynchronous ADC conversion operation, the conversion + will be executed in parallel to the current PWM cycle and will + terminate before the next PWM cycle.*/ + chSysLockFromIsr(); + adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + chSysUnlockFromIsr(); +} + +/* + * ADC end conversion callback. + * The PWM channels are reprogrammed using the latest ADC samples. + * The latest samples are transmitted into a single SPI transaction. + */ +void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void) buffer; (void) n; + /* Note, only in the ADC_COMPLETE state because the ADC driver fires an + intermediate callback when the buffer is half full.*/ + if (adcp->state == ADC_COMPLETE) { + adcsample_t avg_ch1, avg_ch2; + + /* Calculates the average values from the ADC samples.*/ + avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; + avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; + + chSysLockFromIsr(); + + /* Changes the channels pulse width, the change will be effective + starting from the next cycle.*/ + pwmEnableChannelI(&PWMD4, 0, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch1)); + pwmEnableChannelI(&PWMD4, 1, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); + + /* SPI slave selection and transmission start.*/ + spiSelectI(&SPID2); + spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); + + chSysUnlockFromIsr(); + } +} + +/* + * SPI end transfer callback. + */ +static void spicb(SPIDriver *spip) { + + /* On transfer end just releases the slave select line.*/ + chSysLockFromIsr(); + spiUnselectI(spip); + chSysUnlockFromIsr(); +} +#endif + +/* + * This is a periodic thread that does absolutely nothing except increasing + * a seconds counter. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + static uint32_t seconds_counter; + + (void)arg; + chRegSetThreadName("counter"); + while (TRUE) { + chThdSleepMilliseconds(1000); + seconds_counter++; + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + * PA9 and PA10 are routed to USART1. + */ +// sdStart(&SD1, NULL); +// palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); +// palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); + + /* + * If the user button is pressed after the reset then the test suite is + * executed immediately before activating the various device drivers in + * order to not alter the benchmark scores. + */ +// if (palReadPad(GPIOA, GPIOA_BUTTON)) +// TestThread(&SD1); + + /* + * Initializes the SPI driver 2. The SPI2 signals are routed as follow: + * PB12 - NSS. + * PB13 - SCK. + * PB14 - MISO. + * PB15 - MOSI. + */ +#if 0 + spiStart(&SPID2, &spicfg); + palSetPad(GPIOB, 12); + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* NSS. */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ + + /* + * Initializes the ADC driver 1 and enable the thermal sensor. + * The pin PC0 on the port GPIOC is programmed as analog input. + */ + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); + + /* + * Initializes the PWM driver 4, routes the TIM4 outputs to the board LEDs. + */ + pwmStart(&PWMD4, &pwmcfg); + palSetPadMode(GPIOB, GPIOB_LED4, PAL_MODE_ALTERNATE(2)); + palSetPadMode(GPIOB, GPIOB_LED3, PAL_MODE_ALTERNATE(2)); +#endif + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state, when the button is + * pressed the test procedure is launched with output on the serial + * driver 1. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..2324fc0c1 --- /dev/null +++ b/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h @@ -0,0 +1,189 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_HIGH +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2CSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt b/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt new file mode 100644 index 000000000..61e619628 --- /dev/null +++ b/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F100xB. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F4-Discovery board. + +** The Demo ** + +The demo shows how to use the ADC, PWM and SPI drivers using asynchronous +APIs. The ADC samples two channels (temperature sensor and PC0) and modulates +the PWM using the sampled values. The sample data is also transmitted using +the SPI port 1. +By pressing the button located on the board the test procedure is activated +with output on the serial port COM1 (USART1). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/os/hal/platforms/STM32/GPIOv2/pal_lld.c index bde24db25..affdaaedb 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.c +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.c @@ -40,7 +40,14 @@ RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ - RCC_AHB1ENR_GPIOIEN) + RCC_AHB1ENR_GPIOIEN) +#define AHB1_LPEN_MASK AHB1_EN_MASK +#elif defined(STM32F4XX) +#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ + RCC_AHB1ENR_GPIOIEN) #define AHB1_LPEN_MASK AHB1_EN_MASK #else #error "missing or usupported platform for GPIOv2 PAL driver" diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 337b67b55..ca46e5287 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -781,13 +781,13 @@ #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" #endif -#else /* !#if STM32_LSE_ENABLED */ +#else /* !STM32_LSE_ENABLED */ #if STM32_RTCSEL == STM32_RTCSEL_LSE #error "LSE not enabled, required by STM32_RTCSEL" #endif -#endif /* !#if STM32_LSE_ENABLED */ +#endif /* !STM32_LSE_ENABLED */ /** * @brief STM32_PLLM field. @@ -1208,8 +1208,9 @@ /* External declarations. */ /*===========================================================================*/ -/* STM32 DMA support code.*/ +/* STM32 DMA and RCC helpers.*/ #include "stm32_dma.h" +#include "stm32_rcc.h" #ifdef __cplusplus extern "C" { diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h index a1266fec4..327b1bc55 100644 --- a/os/hal/platforms/STM32F4xx/stm32_dma.h +++ b/os/hal/platforms/STM32F4xx/stm32_dma.h @@ -155,7 +155,7 @@ * @brief STM32 DMA stream descriptor structure. */ typedef struct { - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + DMA_Stream_TypeDef *stream; /**< @brief Associated DMA channel. */ volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ uint8_t ishift; /**< @brief Bits offset in xIFCR register. */ diff --git a/os/hal/platforms/STM32F4xx/stm32f4xx.h b/os/hal/platforms/STM32F4xx/stm32f4xx.h index 60dc0622a..ccc1a3565 100644 --- a/os/hal/platforms/STM32F4xx/stm32f4xx.h +++ b/os/hal/platforms/STM32F4xx/stm32f4xx.h @@ -646,7 +646,8 @@ typedef struct /** * @brief General Purpose I/O */ - +/* CHIBIOS FIX */ +#if 0 typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ @@ -660,6 +661,7 @@ typedef struct __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; +#endif /** * @brief System configuration controller diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h index 48be82360..9723158c8 100644 --- a/os/hal/platforms/STM32L1xx/stm32l1xx.h +++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h @@ -411,6 +411,7 @@ typedef struct /** * @brief General Purpose IO */ +/* CHIBIOS FIX */ #if 0 typedef struct { @@ -429,6 +430,7 @@ typedef struct __IO uint32_t AFR[2]; } GPIO_TypeDef; #endif +#endif /** * @brief SysTem Configuration diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h b/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h index c999b1c83..ecf22a6bf 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h @@ -586,6 +586,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fps { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#else +/* CHIBIOS FIX */ + (void)fpscr; #endif } -- cgit v1.2.3 From 4f783ee161926a018c71a303dc3106ca36fb1079 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 6 Nov 2011 08:36:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3473 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp | 2256 +++++++++++++++++++++++++++ demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww | 10 + demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf | 39 + os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h | 57 + os/ports/IAR/ARMCMx/STM32F4xx/vectors.s | 337 ++++ 5 files changed, 2699 insertions(+) create mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp create mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww create mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf create mode 100644 os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h create mode 100644 os/ports/IAR/ARMCMx/STM32F4xx/vectors.s diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp b/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp new file mode 100644 index 000000000..cf9763bbe --- /dev/null +++ b/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp @@ -0,0 +1,2256 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 13 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.c + + + $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32f4xx.h + + + + port + + STM32F4xx + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww b/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf b/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf new file mode 100644 index 000000000..c0a51f44c --- /dev/null +++ b/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h new file mode 100644 index 000000000..733c952d5 --- /dev/null +++ b/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h @@ -0,0 +1,57 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/STM32F4xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F4xx. + * + * @defgroup IAR_ARMCMx_STM32F4xx STM32F4xx Specific Parameters + * @ingroup IAR_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32F4xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s b/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s new file mode 100644 index 000000000..a24773b42 --- /dev/null +++ b/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s @@ -0,0 +1,337 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + + MODULE ?vectors + + AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE + PRESERVE8 + + SECTION IRQSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(3) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA + +__vector_table: + DCD SFE(IRQSTACK) + DCD __iar_program_start + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C + DCD Vector150 + DCD Vector154 + DCD Vector158 + DCD Vector15C + DCD Vector160 + DCD Vector164 + DCD Vector168 + DCD Vector16C + DCD Vector170 + DCD Vector174 + DCD Vector178 + DCD Vector17C + DCD Vector180 + DCD Vector184 + +/* + * Default interrupt handlers. + */ + PUBWEAK NMIVector + PUBWEAK HardFaultVector + PUBWEAK MemManageVector + PUBWEAK BusFaultVector + PUBWEAK UsageFaultVector + PUBWEAK Vector1C + PUBWEAK Vector20 + PUBWEAK Vector24 + PUBWEAK Vector28 + PUBWEAK SVCallVector + PUBWEAK DebugMonitorVector + PUBWEAK Vector34 + PUBWEAK PendSVVector + PUBWEAK SysTickVector + PUBWEAK Vector40 + PUBWEAK Vector44 + PUBWEAK Vector48 + PUBWEAK Vector4C + PUBWEAK Vector50 + PUBWEAK Vector54 + PUBWEAK Vector58 + PUBWEAK Vector5C + PUBWEAK Vector60 + PUBWEAK Vector64 + PUBWEAK Vector68 + PUBWEAK Vector6C + PUBWEAK Vector70 + PUBWEAK Vector74 + PUBWEAK Vector78 + PUBWEAK Vector7C + PUBWEAK Vector80 + PUBWEAK Vector84 + PUBWEAK Vector88 + PUBWEAK Vector8C + PUBWEAK Vector90 + PUBWEAK Vector94 + PUBWEAK Vector98 + PUBWEAK Vector9C + PUBWEAK VectorA0 + PUBWEAK VectorA4 + PUBWEAK VectorA8 + PUBWEAK VectorAC + PUBWEAK VectorB0 + PUBWEAK VectorB4 + PUBWEAK VectorB8 + PUBWEAK VectorBC + PUBWEAK VectorC0 + PUBWEAK VectorC4 + PUBWEAK VectorC8 + PUBWEAK VectorCC + PUBWEAK VectorD0 + PUBWEAK VectorD4 + PUBWEAK VectorD8 + PUBWEAK VectorDC + PUBWEAK VectorE0 + PUBWEAK VectorE4 + PUBWEAK VectorE8 + PUBWEAK VectorEC + PUBWEAK VectorF0 + PUBWEAK VectorF4 + PUBWEAK VectorF8 + PUBWEAK VectorFC + PUBWEAK Vector100 + PUBWEAK Vector104 + PUBWEAK Vector108 + PUBWEAK Vector10C + PUBWEAK Vector110 + PUBWEAK Vector114 + PUBWEAK Vector118 + PUBWEAK Vector11C + PUBWEAK Vector120 + PUBWEAK Vector124 + PUBWEAK Vector128 + PUBWEAK Vector12C + PUBWEAK Vector130 + PUBWEAK Vector134 + PUBWEAK Vector138 + PUBWEAK Vector13C + PUBWEAK Vector140 + PUBWEAK Vector144 + PUBWEAK Vector148 + PUBWEAK Vector14C + PUBWEAK Vector150 + PUBWEAK Vector154 + PUBWEAK Vector158 + PUBWEAK Vector15C + PUBWEAK Vector160 + PUBWEAK Vector164 + PUBWEAK Vector168 + PUBWEAK Vector16C + PUBWEAK Vector170 + PUBWEAK Vector174 + PUBWEAK Vector178 + PUBWEAK Vector17C + PUBWEAK Vector180 + PUBWEAK Vector184 + PUBLIC _unhandled_exception + + SECTION .text:CODE:REORDER(1) + THUMB + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C +Vector150 +Vector154 +Vector158 +Vector15C +Vector160 +Vector164 +Vector168 +Vector16C +Vector170 +Vector174 +Vector178 +Vector17C +Vector180 +Vector184 +_unhandled_exception + b _unhandled_exception + + END -- cgit v1.2.3 From 9e51498e1196b28e5c073a7505df2ae08f05b59a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 6 Nov 2011 09:39:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3474 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32F4_DISCOVERY/board.h | 10 +++++----- demos/ARMCM3-STM32F407-DISCOVERY/main.c | 14 ++++++++++++++ os/hal/platforms/STM32/GPIOv2/pal_lld.c | 2 +- os/hal/platforms/STM32F4xx/hal_lld.c | 15 ++++----------- 4 files changed, 24 insertions(+), 17 deletions(-) diff --git a/boards/ST_STM32F4_DISCOVERY/board.h b/boards/ST_STM32F4_DISCOVERY/board.h index cd1b64552..227f96ce9 100644 --- a/boards/ST_STM32F4_DISCOVERY/board.h +++ b/boards/ST_STM32F4_DISCOVERY/board.h @@ -289,10 +289,10 @@ PIN_MODE_INPUT(9) | \ PIN_MODE_INPUT(10) | \ PIN_MODE_INPUT(11) | \ - PIN_MODE_INPUT(GPIOD_LED4) | \ - PIN_MODE_INPUT(GPIOD_LED3) | \ - PIN_MODE_INPUT(GPIOD_LED5) | \ - PIN_MODE_INPUT(GPIOD_LED6)) + PIN_MODE_OUTPUT(GPIOD_LED4) | \ + PIN_MODE_OUTPUT(GPIOD_LED3) | \ + PIN_MODE_OUTPUT(GPIOD_LED5) | \ + PIN_MODE_OUTPUT(GPIOD_LED6)) #define VAL_GPIOD_OTYPER 0x00000000 #define VAL_GPIOD_OSPEEDR 0xFFFFFFFF #define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(0) | \ @@ -311,7 +311,7 @@ PIN_PUDR_FLOATING(GPIOD_LED3) | \ PIN_PUDR_FLOATING(GPIOD_LED5) | \ PIN_PUDR_FLOATING(GPIOD_LED6)) -#define VAL_GPIOD_ODR 0x0FFFFFCF +#define VAL_GPIOD_ODR 0x00000FCF #define VAL_GPIOD_AFRL 0x00000000 #define VAL_GPIOD_AFRH 0x00000000 diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/main.c b/demos/ARMCM3-STM32F407-DISCOVERY/main.c index 07e158077..eb2653f32 100644 --- a/demos/ARMCM3-STM32F407-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32F407-DISCOVERY/main.c @@ -159,6 +159,7 @@ static void spicb(SPIDriver *spip) { * a seconds counter. */ static WORKING_AREA(waThread1, 128); +#if 0 static msg_t Thread1(void *arg) { static uint32_t seconds_counter; @@ -169,6 +170,19 @@ static msg_t Thread1(void *arg) { seconds_counter++; } } +#else +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOD, GPIOD_LED5); + chThdSleepMilliseconds(500); + palClearPad(GPIOD, GPIOD_LED5); + chThdSleepMilliseconds(500); + } +} +#endif /* * Application entry point. diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/os/hal/platforms/STM32/GPIOv2/pal_lld.c index affdaaedb..728523719 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.c +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.c @@ -99,7 +99,7 @@ void _pal_lld_init(const PALConfig *config) { */ #if defined(STM32L1XX_MD) rccEnableAHB(AHB_EN_MASK, TRUE); -#elif defined(STM32F2XX) +#elif defined(STM32F2XX) || defined(STM32F4XX) RCC->AHB1ENR |= AHB1_EN_MASK; RCC->AHB1LPENR |= AHB1_LPEN_MASK; #endif diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c index ae399242b..bd88ad2da 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.c +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -84,10 +84,6 @@ void hal_lld_init(void) { * * @special */ -#if defined(STM32F2XX) || defined(__DOXYGEN__) -/** - * @brief Clocks and internal voltage initialization. - */ void stm32_clock_init(void) { #if !STM32_NO_INIT @@ -135,7 +131,7 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_PLLI2S /* PLLI2S activation.*/ - RCC->PLLI2SCFGR = STM32_PLI2SR_VALUE | STM32_PLLI2SN_VALUE; + RCC->PLLI2SCFGR = STM32_PLLI2SR_VALUE | STM32_PLLI2SN_VALUE; RCC->CR |= RCC_CR_PLLI2SON; while (!(RCC->CR & RCC_CR_PLLI2SRDY)) ; /* Waits until PLLI2S is stable. */ @@ -145,19 +141,16 @@ void stm32_clock_init(void) { RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; - /* Flash setup. */ + /* Flash setup.*/ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | STM32_FLASHBITS; - /* Switching to the configured clock source if it is different from MSI. */ + /* Switching to the configured clock source if it is different from MSI.*/ #if (STM32_SW != STM32_SW_HSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) ; #endif #endif /* STM32_NO_INIT */ } -#else -void stm32_clock_init(void) {} -#endif /** @} */ -- cgit v1.2.3 From 2848e99c07e4174412dd0879046b9c3f82961695 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 6 Nov 2011 12:25:34 +0000 Subject: STM32F4 support working, most device drivers still to test, report added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3475 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F407-DISCOVERY/main.c | 14 +-- demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h | 4 +- docs/reports/STM32F407-168-GCC.txt | 164 +++++++++++++++++++++++++++++ os/hal/platforms/STM32/serial_lld.c | 4 + os/hal/platforms/STM32F4xx/hal_lld.c | 3 +- 5 files changed, 179 insertions(+), 10 deletions(-) create mode 100644 docs/reports/STM32F407-168-GCC.txt diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/main.c b/demos/ARMCM3-STM32F407-DISCOVERY/main.c index eb2653f32..cc12871d4 100644 --- a/demos/ARMCM3-STM32F407-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32F407-DISCOVERY/main.c @@ -201,19 +201,19 @@ int main(void) { /* * Activates the serial driver 1 using the driver default configuration. - * PA9 and PA10 are routed to USART1. + * PA2(TX) and PA3(RX) are routed to USART1. */ -// sdStart(&SD1, NULL); -// palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); -// palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); + sdStart(&SD2, NULL); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); /* * If the user button is pressed after the reset then the test suite is * executed immediately before activating the various device drivers in * order to not alter the benchmark scores. */ -// if (palReadPad(GPIOA, GPIOA_BUTTON)) -// TestThread(&SD1); + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD2); /* * Initializes the SPI driver 2. The SPI2 signals are routed as follow: @@ -262,7 +262,7 @@ int main(void) { */ while (TRUE) { if (palReadPad(GPIOA, GPIOA_BUTTON)) - TestThread(&SD1); + TestThread(&SD2); chThdSleepMilliseconds(500); } } diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h index 2324fc0c1..2da3961ed 100644 --- a/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h @@ -141,8 +141,8 @@ /* * SERIAL driver system settings. */ -#define STM32_SERIAL_USE_USART1 TRUE -#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE diff --git a/docs/reports/STM32F407-168-GCC.txt b/docs/reports/STM32F407-168-GCC.txt new file mode 100644 index 000000000..9b2702146 --- /dev/null +++ b/docs/reports/STM32F407-168-GCC.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=168, ACR=0x705 (5 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.3.4unstable +*** Compiled: Nov 6 2011 - 12:43:29 +*** Compiler: GCC 4.6.0 +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F4 High Performance & DSP +*** Test Board: ST STM32F4-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 756090 msgs/S, 1512180 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 621671 msgs/S, 1243342 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 621671 msgs/S, 1243342 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 2567560 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 452437 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 638228 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 192887 reschedules/S, 1157322 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 1367420 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1844568 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 2151998 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 2685712 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1886020 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/os/hal/platforms/STM32/serial_lld.c b/os/hal/platforms/STM32/serial_lld.c index ce412dedb..d9d0836fd 100644 --- a/os/hal/platforms/STM32/serial_lld.c +++ b/os/hal/platforms/STM32/serial_lld.c @@ -90,7 +90,11 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) { /* * Baud rate setting. */ +#if STM32_HAS_USART6 + if ((sdp->usart == USART1) || (sdp->usart == USART6)) +#else if (sdp->usart == USART1) +#endif u->BRR = STM32_PCLK2 / config->sc_speed; else u->BRR = STM32_PCLK1 / config->sc_speed; diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c index bd88ad2da..5033c41c8 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.c +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -142,7 +142,8 @@ void stm32_clock_init(void) { STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; /* Flash setup.*/ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | STM32_FLASHBITS; + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | + STM32_FLASHBITS; /* Switching to the configured clock source if it is different from MSI.*/ #if (STM32_SW != STM32_SW_HSI) -- cgit v1.2.3 From bfcc14cb5cb5fdce3d3cb1ae29e250be4252da80 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 6 Nov 2011 14:56:31 +0000 Subject: Added support for USART6 to STM32 serial driver, fixed bug 3434094. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3477 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h | 2 ++ os/hal/platforms/STM32/serial_lld.c | 50 +++++++++++++++++++++++++++++- os/hal/platforms/STM32/serial_lld.h | 33 +++++++++++++++++--- readme.txt | 6 +++- 4 files changed, 84 insertions(+), 7 deletions(-) diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h index 2da3961ed..058cc7a76 100644 --- a/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h @@ -146,11 +146,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/os/hal/platforms/STM32/serial_lld.c b/os/hal/platforms/STM32/serial_lld.c index d9d0836fd..c5dda231b 100644 --- a/os/hal/platforms/STM32/serial_lld.c +++ b/os/hal/platforms/STM32/serial_lld.c @@ -60,6 +60,11 @@ SerialDriver SD4; SerialDriver SD5; #endif +/** @brief USART6 serial driver identifier.*/ +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +SerialDriver SD6; +#endif + /*===========================================================================*/ /* Driver local variables. */ /*===========================================================================*/ @@ -127,7 +132,7 @@ static void usart_deinit(USART_TypeDef *u) { #if STM32_SERIAL_USE_USART1 || STM32_SERIAL_USE_USART2 || \ STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \ - USE_STM32_USART5 + STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 /** * @brief Error handling routine. * @@ -241,6 +246,14 @@ static void notify5(GenericQueue *qp) { } #endif +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +static void notify6(GenericQueue *qp) { + + (void)qp; + USART6->CR1 |= USART_CR1_TXEIE; +} +#endif + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -325,6 +338,22 @@ CH_IRQ_HANDLER(UART5_IRQHandler) { } #endif +#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +/** + * @brief USART1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART6_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD6); + + CH_IRQ_EPILOGUE(); +} +#endif + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -360,6 +389,11 @@ void sd_lld_init(void) { sdObjectInit(&SD5, NULL, notify5); SD5.usart = UART5; #endif + +#if STM32_SERIAL_USE_USART6 + sdObjectInit(&SD6, NULL, notify6); + SD6.usart = USART6; +#endif } /** @@ -412,6 +446,13 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { NVICEnableVector(UART5_IRQn, CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); } +#endif +#if STM32_SERIAL_USE_USART6 + if (&SD6 == sdp) { + rccEnableUSART6(FALSE); + NVICEnableVector(USART6_IRQn, + CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY)); + } #endif } usart_init(sdp, config); @@ -464,6 +505,13 @@ void sd_lld_stop(SerialDriver *sdp) { NVICDisableVector(UART5_IRQn); return; } +#endif +#if STM32_SERIAL_USE_USART6 + if (&SD6 == sdp) { + rccDisableUSART6(FALSE); + NVICDisableVector(USART6_IRQn); + return; + } #endif } } diff --git a/os/hal/platforms/STM32/serial_lld.h b/os/hal/platforms/STM32/serial_lld.h index ceeccff67..fdd168201 100644 --- a/os/hal/platforms/STM32/serial_lld.h +++ b/os/hal/platforms/STM32/serial_lld.h @@ -42,7 +42,7 @@ /** * @brief USART1 driver enable switch. * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. + * @note The default is @p TRUE. */ #if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__) #define STM32_SERIAL_USE_USART1 TRUE @@ -60,7 +60,7 @@ /** * @brief USART3 driver enable switch. * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. + * @note The default is @p TRUE. */ #if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__) #define STM32_SERIAL_USE_USART3 TRUE @@ -69,7 +69,7 @@ /** * @brief UART4 driver enable switch. * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p FALSE. + * @note The default is @p TRUE. */ #if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__) #define STM32_SERIAL_USE_UART4 TRUE @@ -78,12 +78,21 @@ /** * @brief UART5 driver enable switch. * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p FALSE. + * @note The default is @p TRUE. */ #if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__) #define STM32_SERIAL_USE_UART5 TRUE #endif +/** + * @brief USART6 driver enable switch. + * @details If set to @p TRUE the support for USART6 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__) +#define STM32_SERIAL_USE_USART6 TRUE +#endif + /** * @brief USART1 interrupt priority level setting. */ @@ -119,6 +128,13 @@ #define STM32_SERIAL_UART5_PRIORITY 12 #endif +/** + * @brief USART6 interrupt priority level setting. + */ +#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SERIAL_USART6_PRIORITY 12 +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -143,9 +159,13 @@ #error "UART5 not present in the selected device" #endif +#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6 +#error "USART6 not present in the selected device" +#endif + #if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \ !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \ - !STM32_SERIAL_USE_UART5 + !STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 #error "SERIAL driver activated but no USART/UART peripheral assigned" #endif @@ -230,6 +250,9 @@ extern SerialDriver SD4; #if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__) extern SerialDriver SD5; #endif +#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__) +extern SerialDriver SD6; +#endif #ifdef __cplusplus extern "C" { diff --git a/readme.txt b/readme.txt index ffce54fea..d2180bc8a 100644 --- a/readme.txt +++ b/readme.txt @@ -74,11 +74,15 @@ ***************************************************************************** *** 2.3.4 *** +- FIX: Fixed broken support for UART5 in STM32 serial driver (bug 3434094) + (backported to 2.2.8). - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). - NEW: Reorganized the STM32F1xx hal_lld_xxx.h files in order to distribute the capability macros into the appropriate file (previously those were all in the common hal_lld.h). +- NEW: Added HAL support for the STM32F4xx sub-family. +- NEW: Added handling of USART6 to the STM32 serial driver. - NEW: Added USE_COPT setting to all makefiles, contributed by Mabl. - NEW: Added EXT driver implementation for AT91SAM7x, contributed by Florian. (TODO: Test application missing). @@ -111,7 +115,7 @@ - FIX: Fixed uninitialized variable in STM32 PWM and ICU drivers (bug 3413558). - FIX: Fixed wrong parameter passed to the DMA error hook in STM32 ADC driver, the DMA error hook has been removed entirely in the new ADC driver model - (bug 3413214)(to be fixed in 2.2.8). + (bug 3413214). - FIX: The function chThdExit() triggers an error on shell return when the system state checker is enabled (bug 3411207)(backported to 2.2.8). - FIX: Some ARMCMx makefiles refer the file rules.mk in the ARM7 port (bug -- cgit v1.2.3 From d3adba6d993ef0c15e5b8d33297d3cd108e2f8b6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 6 Nov 2011 15:27:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3478 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/stm32_dma.c | 66 ++++++++++++++------------------ os/hal/platforms/STM32F4xx/stm32_dma.h | 69 +++++++++++++++++++++++++++++++--- 2 files changed, 92 insertions(+), 43 deletions(-) diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.c b/os/hal/platforms/STM32F4xx/stm32_dma.c index e35d93543..dd5a92afb 100644 --- a/os/hal/platforms/STM32F4xx/stm32_dma.c +++ b/os/hal/platforms/STM32F4xx/stm32_dma.c @@ -22,7 +22,7 @@ * @file STM32F4xx/stm32_dma.c * @brief Enhanced DMA helper driver code. * - * @addtogroup STM32_DMA + * @addtogroup STM32F4xx_DMA * @details DMA sharing helper driver. In the STM32 the DMA streams are a * shared resource, this driver allows to allocate and free DMA * streams at runtime in order to allow all the other device @@ -76,22 +76,22 @@ * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc. */ const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { - {0, DMA1, DMA1_Stream0, &DMA1->LIFCR, 0}, - {1, DMA1, DMA1_Stream1, &DMA1->LIFCR, 6}, - {2, DMA1, DMA1_Stream2, &DMA1->LIFCR, 16}, - {3, DMA1, DMA1_Stream3, &DMA1->LIFCR, 22}, - {4, DMA1, DMA1_Stream4, &DMA1->HIFCR, 0}, - {5, DMA1, DMA1_Stream5, &DMA1->HIFCR, 6}, - {6, DMA1, DMA1_Stream6, &DMA1->HIFCR, 16}, - {7, DMA1, DMA1_Stream7, &DMA1->HIFCR, 22}, - {8, DMA2, DMA2_Stream0, &DMA2->LIFCR, 0}, - {9, DMA2, DMA2_Stream1, &DMA2->LIFCR, 6}, - {10, DMA2, DMA2_Stream2, &DMA2->LIFCR, 16}, - {11, DMA2, DMA2_Stream3, &DMA2->LIFCR, 22}, - {12, DMA2, DMA2_Stream4, &DMA2->HIFCR, 0}, - {13, DMA2, DMA2_Stream5, &DMA2->HIFCR, 6}, - {14, DMA2, DMA2_Stream6, &DMA2->HIFCR, 16}, - {15, DMA2, DMA2_Stream7, &DMA2->HIFCR, 22}, + {DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn}, + {DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn}, + {DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn}, + {DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn}, + {DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn}, + {DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn}, + {DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn}, + {DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn}, + {DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn}, + {DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn}, + {DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn}, + {DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn}, + {DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn}, + {DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn}, + {DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn}, + {DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn}, }; /*===========================================================================*/ @@ -102,8 +102,8 @@ const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { * @brief DMA ISR redirector type. */ typedef struct { - stm32_dmaisr_t dma_func; - void *dma_param; + stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */ + void *dma_param; /**< @brief DMA callback parameter. */ } dma_isr_redir_t; /** @@ -467,7 +467,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, chDbgCheck(dmastp != NULL, "dmaAllocate"); /* Checks if the stream is already taken.*/ - if ((dma_streams_mask & dmastp->mask) != 0) + if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) return TRUE; /* Marks the stream as allocated.*/ @@ -476,14 +476,10 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, dma_streams_mask |= (1 << dmastp->selfindex); /* Enabling DMA clocks required by the current streams set.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) { - RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; - RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA1LPEN; - } - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) { - RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; - RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA2LPEN; - } + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) + rccEnableDMA1(FALSE); + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) + rccEnableDMA2(FALSE); /* Putting the stream in a safe state.*/ dmaStreamDisable(dmastp); @@ -516,7 +512,7 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { chDbgCheck(dmastp != NULL, "dmaRelease"); /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & dmastp->mask) != 0, + chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, "dmaRelease(), #1", "not allocated"); /* Disables the associated IRQ vector.*/ @@ -526,14 +522,10 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { dma_streams_mask &= ~(1 << dmastp->selfindex); /* Shutting down clocks that are no more required, if any.*/ - if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) { - RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA1EN; - RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA1LPEN; - } - if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) { - RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2EN; - RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA2LPEN; - } + if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) + rccDisableDMA1(FALSE); + if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) + rccDisableDMA2(FALSE); } #endif /* STM32_DMA_REQUIRED */ diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h index 327b1bc55..9aaadb681 100644 --- a/os/hal/platforms/STM32F4xx/stm32_dma.h +++ b/os/hal/platforms/STM32F4xx/stm32_dma.h @@ -21,8 +21,8 @@ /** * @file STM32F4xx/stm32_dma.h * @brief Enhanced-DMA helper driver header. - * @note This file requires definitions from the ST STM32F2xx header file - * stm32f2xx.h. + * @note This file requires definitions from the ST STM32F4xx header file + * stm32f4xx.h. * * @addtogroup STM32_DMA * @{ @@ -95,7 +95,7 @@ /** @} */ /** - * @name CR register constants only found in STM32F2xx + * @name CR register constants only found in STM32F2xx/STM32F4xx */ #define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE #define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL @@ -155,7 +155,7 @@ * @brief STM32 DMA stream descriptor structure. */ typedef struct { - DMA_Stream_TypeDef *stream; /**< @brief Associated DMA channel. */ + DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */ volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */ uint8_t ishift; /**< @brief Bits offset in xIFCR register. */ @@ -179,6 +179,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Associates a peripheral data register to a DMA stream. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @param[in] addr value to be written in the PAR register @@ -192,6 +194,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Associates a memory destination to a DMA stream. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @param[in] addr value to be written in the M0AR register @@ -218,6 +222,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Sets the number of transfers to be performed. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @param[in] size value to be written in the CNDTR register @@ -231,6 +237,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Returns the number of transfers to be performed. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @return The number of transfers to be performed. @@ -242,6 +250,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Programs the stream mode settings. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @param[in] mode value to be written in the CR register @@ -255,6 +265,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief Programs the stream FIFO settings. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @param[in] mode value to be written in the FCR register @@ -268,18 +280,22 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief DMA stream enable. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * - * @param[in] dmachp pointer to a stm32_dma_stream_t structure + * @param[in] dmastp pointer to a stm32_dma_stream_t structure * * @special */ -#define dmaStreamEnable(dmachp) { \ +#define dmaStreamEnable(dmastp) { \ (dmastp)->stream->CR |= STM32_DMA_CR_EN; \ } /** * @brief DMA stream disable. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @@ -292,6 +308,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /** * @brief DMA stream interrupt sources clear. * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a stm32_dma_stream_t structure * @@ -301,6 +319,45 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \ } +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamGetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) \ + while (((dmastp)->stream->CNDTR > 0) && \ + ((dmastp)->stream->CCR & STM32_DMA_CR_EN)) + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ -- cgit v1.2.3 From debee3a5c68cc02e8c3d6424077b8461df9d329c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 6 Nov 2011 18:22:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3479 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F407-DISCOVERY/readme.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt b/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt index 61e619628..ab3c5199a 100644 --- a/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt +++ b/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt @@ -13,7 +13,7 @@ APIs. The ADC samples two channels (temperature sensor and PC0) and modulates the PWM using the sampled values. The sample data is also transmitted using the SPI port 1. By pressing the button located on the board the test procedure is activated -with output on the serial port COM1 (USART1). +with output on the serial port SD2 (USART2). ** Build Procedure ** -- cgit v1.2.3 From b81fe69f7174006176e505ac66aff44eb8e246f2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 6 Nov 2011 20:48:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3480 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F407-DISCOVERY/Makefile | 209 --- demos/ARMCM3-STM32F407-DISCOVERY/chconf.h | 535 ------- demos/ARMCM3-STM32F407-DISCOVERY/halconf.h | 335 ---- demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp | 2256 --------------------------- demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww | 10 - demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf | 39 - demos/ARMCM3-STM32F407-DISCOVERY/main.c | 268 ---- demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h | 191 --- demos/ARMCM3-STM32F407-DISCOVERY/readme.txt | 31 - demos/ARMCM4-STM32F407-DISCOVERY/Makefile | 209 +++ demos/ARMCM4-STM32F407-DISCOVERY/chconf.h | 535 +++++++ demos/ARMCM4-STM32F407-DISCOVERY/halconf.h | 335 ++++ demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp | 2256 +++++++++++++++++++++++++++ demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.eww | 10 + demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.icf | 39 + demos/ARMCM4-STM32F407-DISCOVERY/main.c | 268 ++++ demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h | 191 +++ demos/ARMCM4-STM32F407-DISCOVERY/readme.txt | 31 + 18 files changed, 3874 insertions(+), 3874 deletions(-) delete mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/Makefile delete mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/chconf.h delete mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/halconf.h delete mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp delete mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww delete mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf delete mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/main.c delete mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h delete mode 100644 demos/ARMCM3-STM32F407-DISCOVERY/readme.txt create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/Makefile create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/chconf.h create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/halconf.h create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.eww create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.icf create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/main.c create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/readme.txt diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/Makefile b/demos/ARMCM3-STM32F407-DISCOVERY/Makefile deleted file mode 100644 index 28a823c16..000000000 --- a/demos/ARMCM3-STM32F407-DISCOVERY/Makefile +++ /dev/null @@ -1,209 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -endif - -# C specific options here (added to USE_OPT). -ifeq ($(USE_COPT),) - USE_COPT = -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable this if you want to see the full log while compiling. -ifeq ($(USE_VERBOSE_COMPILE),) - USE_VERBOSE_COMPILE = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Enable this if you really want to use the STM FWLib. -ifeq ($(USE_FWLIB),) - USE_FWLIB = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Imported source files and paths -CHIBIOS = ../.. -include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk -include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# Define linker script file here -LDSCRIPT= $(PORTLD)/STM32F407xG.ld - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m3 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -ifeq ($(USE_FWLIB),yes) - include $(CHIBIOS)/ext/stm32lib/stm32lib.mk - CSRC += $(STM32SRC) - INCDIR += $(STM32INC) - USE_OPT += -DUSE_STDPERIPH_DRIVER -endif - -include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/chconf.h b/demos/ARMCM3-STM32F407-DISCOVERY/chconf.h deleted file mode 100644 index 9dd831c96..000000000 --- a/demos/ARMCM3-STM32F407-DISCOVERY/chconf.h +++ /dev/null @@ -1,535 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_MEMCORE. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread automatically. The application has - * then the responsibility to do one of the following: - * - Spawn a custom idle thread at priority @p IDLEPRIO. - * - Change the main() thread priority to @p IDLEPRIO then enter - * an endless loop. In this scenario the @p main() thread acts as - * the idle thread. - * . - * @note Unless an idle thread is spawned the @p main() thread must not - * enter a sleep state. - */ -#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) -#define CH_NO_IDLE_THREAD FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE -#endif - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ - /* Add threads custom fields here.*/ -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) -#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* System halt code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_TICK_EVENT_HOOK() { \ - /* System tick event code here.*/ \ -} -#endif - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_HALT_HOOK() { \ - /* System halt code here.*/ \ -} -#endif - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/halconf.h b/demos/ARMCM3-STM32F407-DISCOVERY/halconf.h deleted file mode 100644 index b4fb49092..000000000 --- a/demos/ARMCM3-STM32F407-DISCOVERY/halconf.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT FALSE -#endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -#define HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the RTC subsystem. - */ -#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -#define HAL_USE_RTC FALSE -#endif - -/** - * @brief Enables the SDC subsystem. - */ -#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -#define HAL_USE_SDC FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the UART subsystem. - */ -#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -#define HAL_USE_UART FALSE -#endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Block size for MMC transfers. - */ -#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) -#define MMC_SECTOR_SIZE 512 -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/** - * @brief Number of positive insertion queries before generating the - * insertion event. - */ -#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) -#define MMC_POLLING_INTERVAL 10 -#endif - -/** - * @brief Interval, in milliseconds, between insertion queries. - */ -#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) -#define MMC_POLLING_DELAY 10 -#endif - -/** - * @brief Uses the SPI polled API for small data transfers. - * @details Polled transfers usually improve performance because it - * saves two context switches and interrupt servicing. Note - * that this option has no effect on large transfers which - * are always performed using DMAs/IRQs. - */ -#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) -#define MMC_USE_SPI_POLLING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intevals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 38400 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 64 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp b/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp deleted file mode 100644 index cf9763bbe..000000000 --- a/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.ewp +++ /dev/null @@ -1,2256 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 21 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 21 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 13 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - board - - $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.c - - - $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.h - - - - os - - hal - - include - - $PROJ_DIR$\..\..\..\os\hal\include\adc.h - - - $PROJ_DIR$\..\..\..\os\hal\include\can.h - - - $PROJ_DIR$\..\..\..\os\hal\include\ext.h - - - $PROJ_DIR$\..\..\..\os\hal\include\gpt.h - - - $PROJ_DIR$\..\..\..\os\hal\include\hal.h - - - $PROJ_DIR$\..\..\..\os\hal\include\i2c.h - - - $PROJ_DIR$\..\..\..\os\hal\include\icu.h - - - $PROJ_DIR$\..\..\..\os\hal\include\mac.h - - - $PROJ_DIR$\..\..\..\os\hal\include\mii.h - - - $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h - - - $PROJ_DIR$\..\..\..\os\hal\include\pal.h - - - $PROJ_DIR$\..\..\..\os\hal\include\pwm.h - - - $PROJ_DIR$\..\..\..\os\hal\include\rtc.h - - - $PROJ_DIR$\..\..\..\os\hal\include\sdc.h - - - $PROJ_DIR$\..\..\..\os\hal\include\serial.h - - - $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h - - - $PROJ_DIR$\..\..\..\os\hal\include\spi.h - - - $PROJ_DIR$\..\..\..\os\hal\include\uart.h - - - $PROJ_DIR$\..\..\..\os\hal\include\usb.h - - - $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h - - - - src - - $PROJ_DIR$\..\..\..\os\hal\src\adc.c - - - $PROJ_DIR$\..\..\..\os\hal\src\can.c - - - $PROJ_DIR$\..\..\..\os\hal\src\ext.c - - - $PROJ_DIR$\..\..\..\os\hal\src\gpt.c - - - $PROJ_DIR$\..\..\..\os\hal\src\hal.c - - - $PROJ_DIR$\..\..\..\os\hal\src\i2c.c - - - $PROJ_DIR$\..\..\..\os\hal\src\icu.c - - - $PROJ_DIR$\..\..\..\os\hal\src\mac.c - - - $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c - - - $PROJ_DIR$\..\..\..\os\hal\src\pal.c - - - $PROJ_DIR$\..\..\..\os\hal\src\pwm.c - - - $PROJ_DIR$\..\..\..\os\hal\src\rtc.c - - - $PROJ_DIR$\..\..\..\os\hal\src\sdc.c - - - $PROJ_DIR$\..\..\..\os\hal\src\serial.c - - - $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c - - - $PROJ_DIR$\..\..\..\os\hal\src\spi.c - - - $PROJ_DIR$\..\..\..\os\hal\src\uart.c - - - $PROJ_DIR$\..\..\..\os\hal\src\usb.c - - - - - kernel - - include - - $PROJ_DIR$\..\..\..\os\kernel\include\ch.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h - - - $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h - - - - src - - $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c - - - $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c - - - - - platform - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h - - - $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32f4xx.h - - - - port - - STM32F4xx - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\cmparams.h - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\vectors.s - - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\nvic.c - - - $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\nvic.h - - - - - test - - $PROJ_DIR$\..\..\..\test\test.c - - - $PROJ_DIR$\..\..\..\test\test.h - - - $PROJ_DIR$\..\..\..\test\testbmk.c - - - $PROJ_DIR$\..\..\..\test\testbmk.h - - - $PROJ_DIR$\..\..\..\test\testdyn.c - - - $PROJ_DIR$\..\..\..\test\testdyn.h - - - $PROJ_DIR$\..\..\..\test\testevt.c - - - $PROJ_DIR$\..\..\..\test\testevt.h - - - $PROJ_DIR$\..\..\..\test\testheap.c - - - $PROJ_DIR$\..\..\..\test\testheap.h - - - $PROJ_DIR$\..\..\..\test\testmbox.c - - - $PROJ_DIR$\..\..\..\test\testmbox.h - - - $PROJ_DIR$\..\..\..\test\testmsg.c - - - $PROJ_DIR$\..\..\..\test\testmsg.h - - - $PROJ_DIR$\..\..\..\test\testmtx.c - - - $PROJ_DIR$\..\..\..\test\testmtx.h - - - $PROJ_DIR$\..\..\..\test\testpools.c - - - $PROJ_DIR$\..\..\..\test\testpools.h - - - $PROJ_DIR$\..\..\..\test\testqueues.c - - - $PROJ_DIR$\..\..\..\test\testqueues.h - - - $PROJ_DIR$\..\..\..\test\testsem.c - - - $PROJ_DIR$\..\..\..\test\testsem.h - - - $PROJ_DIR$\..\..\..\test\testthd.c - - - $PROJ_DIR$\..\..\..\test\testthd.h - - - - $PROJ_DIR$\..\chconf.h - - - $PROJ_DIR$\..\halconf.h - - - $PROJ_DIR$\..\main.c - - - $PROJ_DIR$\..\mcuconf.h - - - - diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww b/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww deleted file mode 100644 index f9b3b2000..000000000 --- a/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\ch.ewp - - - - - diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf b/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf deleted file mode 100644 index c0a51f44c..000000000 --- a/demos/ARMCM3-STM32F407-DISCOVERY/iar/ch.icf +++ /dev/null @@ -1,39 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x400; -/**** End of ICF editor section. ###ICF###*/ - -/* Size of the IRQ Stack (Main Stack).*/ -define symbol __ICFEDIT_size_irqstack__ = 0x400; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; -define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; -define block SYSHEAP with alignment = 8 {section SYSHEAP}; -define block DATABSS with alignment = 8 {readwrite, zeroinit}; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section .intvec }; - -place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; -place in ROM_region {readonly}; -place at start of RAM_region {block IRQSTACK}; -place in RAM_region {block DATABSS, block HEAP}; -place in RAM_region {block SYSHEAP}; -place at end of RAM_region {block CSTACK}; diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/main.c b/demos/ARMCM3-STM32F407-DISCOVERY/main.c deleted file mode 100644 index cc12871d4..000000000 --- a/demos/ARMCM3-STM32F407-DISCOVERY/main.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -#if 0 -static void pwmpcb(PWMDriver *pwmp); -static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); -static void spicb(SPIDriver *spip); - -/* Total number of channels to be sampled by a single ADC operation.*/ -#define ADC_GRP1_NUM_CHANNELS 2 - -/* Depth of the conversion buffer, channels are sampled four times each.*/ -#define ADC_GRP1_BUF_DEPTH 4 - -/* - * ADC samples buffer. - */ -static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; - -/* - * ADC conversion group. - * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. - * Channels: IN10 (48 cycles sample time) - * Sensor (192 cycles sample time) - */ -static const ADCConversionGroup adcgrpcfg = { - FALSE, - ADC_GRP1_NUM_CHANNELS, - adccb, - NULL, - /* HW dependent part.*/ - 0, - 0, - 0, - ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192), - 0, - ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), - 0, - 0, - 0, - ADC_SQR5_SQ2_N(ADC_CHANNEL_IN10) | ADC_SQR5_SQ1_N(ADC_CHANNEL_SENSOR) -}; - -/* - * PWM configuration structure. - * Cyclic callback enabled, channels 3 and 4 enabled without callbacks, - * the active state is a logic one. - */ -static PWMConfig pwmcfg = { - 10000, /* 10KHz PWM clock frequency. */ - 10000, /* PWM period 1S (in ticks). */ - pwmpcb, - { - {PWM_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL} - }, - /* HW dependent part.*/ - 0 -}; - -/* - * SPI configuration structure. - * Maximum speed (12MHz), CPHA=0, CPOL=0, 16bits frames, MSb transmitted first. - * The slave select line is the pin GPIOA_SPI1NSS on the port GPIOA. - */ -static const SPIConfig spicfg = { - spicb, - /* HW dependent part.*/ - GPIOB, - 12, - SPI_CR1_DFF -}; - -/* - * PWM cyclic callback. - * A new ADC conversion is started. - */ -static void pwmpcb(PWMDriver *pwmp) { - - (void)pwmp; - - /* Starts an asynchronous ADC conversion operation, the conversion - will be executed in parallel to the current PWM cycle and will - terminate before the next PWM cycle.*/ - chSysLockFromIsr(); - adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); - chSysUnlockFromIsr(); -} - -/* - * ADC end conversion callback. - * The PWM channels are reprogrammed using the latest ADC samples. - * The latest samples are transmitted into a single SPI transaction. - */ -void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { - - (void) buffer; (void) n; - /* Note, only in the ADC_COMPLETE state because the ADC driver fires an - intermediate callback when the buffer is half full.*/ - if (adcp->state == ADC_COMPLETE) { - adcsample_t avg_ch1, avg_ch2; - - /* Calculates the average values from the ADC samples.*/ - avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; - avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; - - chSysLockFromIsr(); - - /* Changes the channels pulse width, the change will be effective - starting from the next cycle.*/ - pwmEnableChannelI(&PWMD4, 0, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch1)); - pwmEnableChannelI(&PWMD4, 1, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); - - /* SPI slave selection and transmission start.*/ - spiSelectI(&SPID2); - spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); - - chSysUnlockFromIsr(); - } -} - -/* - * SPI end transfer callback. - */ -static void spicb(SPIDriver *spip) { - - /* On transfer end just releases the slave select line.*/ - chSysLockFromIsr(); - spiUnselectI(spip); - chSysUnlockFromIsr(); -} -#endif - -/* - * This is a periodic thread that does absolutely nothing except increasing - * a seconds counter. - */ -static WORKING_AREA(waThread1, 128); -#if 0 -static msg_t Thread1(void *arg) { - static uint32_t seconds_counter; - - (void)arg; - chRegSetThreadName("counter"); - while (TRUE) { - chThdSleepMilliseconds(1000); - seconds_counter++; - } -} -#else -static msg_t Thread1(void *arg) { - - (void)arg; - chRegSetThreadName("blinker"); - while (TRUE) { - palSetPad(GPIOD, GPIOD_LED5); - chThdSleepMilliseconds(500); - palClearPad(GPIOD, GPIOD_LED5); - chThdSleepMilliseconds(500); - } -} -#endif - -/* - * Application entry point. - */ -int main(void) { - - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - - /* - * Activates the serial driver 1 using the driver default configuration. - * PA2(TX) and PA3(RX) are routed to USART1. - */ - sdStart(&SD2, NULL); - palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); - palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); - - /* - * If the user button is pressed after the reset then the test suite is - * executed immediately before activating the various device drivers in - * order to not alter the benchmark scores. - */ - if (palReadPad(GPIOA, GPIOA_BUTTON)) - TestThread(&SD2); - - /* - * Initializes the SPI driver 2. The SPI2 signals are routed as follow: - * PB12 - NSS. - * PB13 - SCK. - * PB14 - MISO. - * PB15 - MOSI. - */ -#if 0 - spiStart(&SPID2, &spicfg); - palSetPad(GPIOB, 12); - palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | - PAL_STM32_OSPEED_HIGHEST); /* NSS. */ - palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | - PAL_STM32_OSPEED_HIGHEST); /* SCK. */ - palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ - palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | - PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ - - /* - * Initializes the ADC driver 1 and enable the thermal sensor. - * The pin PC0 on the port GPIOC is programmed as analog input. - */ - adcStart(&ADCD1, NULL); - adcSTM32EnableTSVREFE(); - palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); - - /* - * Initializes the PWM driver 4, routes the TIM4 outputs to the board LEDs. - */ - pwmStart(&PWMD4, &pwmcfg); - palSetPadMode(GPIOB, GPIOB_LED4, PAL_MODE_ALTERNATE(2)); - palSetPadMode(GPIOB, GPIOB_LED3, PAL_MODE_ALTERNATE(2)); -#endif - - /* - * Creates the example thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state, when the button is - * pressed the test procedure is launched with output on the serial - * driver 1. - */ - while (TRUE) { - if (palReadPad(GPIOA, GPIOA_BUTTON)) - TestThread(&SD2); - chThdSleepMilliseconds(500); - } -} diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h deleted file mode 100644 index 058cc7a76..000000000 --- a/demos/ARMCM3-STM32F407-DISCOVERY/mcuconf.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * STM32L1xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_VOS STM32_VOS_HIGH -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 8 -#define STM32_PLLN_VALUE 336 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 -#define STM32_I2SSRC STM32_I2CSRC_CKIN -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SR_VALUE 5 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 TRUE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 - -/* - * EXT driver system settings. - */ -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 TRUE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 TRUE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 TRUE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 TRUE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt b/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt deleted file mode 100644 index ab3c5199a..000000000 --- a/demos/ARMCM3-STM32F407-DISCOVERY/readme.txt +++ /dev/null @@ -1,31 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM-Cortex-M3 STM32F100xB. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an ST STM32F4-Discovery board. - -** The Demo ** - -The demo shows how to use the ADC, PWM and SPI drivers using asynchronous -APIs. The ADC samples two channels (temperature sensor and PC0) and modulates -the PWM using the sampled values. The sample data is also transmitted using -the SPI port 1. -By pressing the button located on the board the test procedure is activated -with output on the serial port SD2 (USART2). - -** Build Procedure ** - -The demo has been tested by using the free Codesourcery GCC-based toolchain -and YAGARTO. just modify the TRGT line in the makefile in order to use -different GCC toolchains. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are copyright of -ST Microelectronics and are licensed under a different license. -Also note that not all the files present in the ST library are distribited -with ChibiOS/RT, you can find the whole library on the ST web site: - - http://www.st.com diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/Makefile b/demos/ARMCM4-STM32F407-DISCOVERY/Makefile new file mode 100644 index 000000000..28a823c16 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h new file mode 100644 index 000000000..9dd831c96 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h new file mode 100644 index 000000000..b4fb49092 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h @@ -0,0 +1,335 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp new file mode 100644 index 000000000..cf9763bbe --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp @@ -0,0 +1,2256 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 13 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + board + + $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.c + + + $PROJ_DIR$\..\..\..\boards\ST_STM32F4_DISCOVERY\board.h + + + + os + + hal + + include + + $PROJ_DIR$\..\..\..\os\hal\include\adc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\can.h + + + $PROJ_DIR$\..\..\..\os\hal\include\ext.h + + + $PROJ_DIR$\..\..\..\os\hal\include\gpt.h + + + $PROJ_DIR$\..\..\..\os\hal\include\hal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\i2c.h + + + $PROJ_DIR$\..\..\..\os\hal\include\icu.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mac.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mii.h + + + $PROJ_DIR$\..\..\..\os\hal\include\mmc_spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pal.h + + + $PROJ_DIR$\..\..\..\os\hal\include\pwm.h + + + $PROJ_DIR$\..\..\..\os\hal\include\rtc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\sdc.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial.h + + + $PROJ_DIR$\..\..\..\os\hal\include\serial_usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\spi.h + + + $PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb.h + + + $PROJ_DIR$\..\..\..\os\hal\include\usb_cdc.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\ext.c + + + $PROJ_DIR$\..\..\..\os\hal\src\gpt.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\icu.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\rtc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\sdc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial_usb.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + $PROJ_DIR$\..\..\..\os\hal\src\usb.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\serial_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\spi_lld.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\stm32f4xx.h + + + + port + + STM32F4xx + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32F4xx\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.eww b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.icf b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.icf new file mode 100644 index 000000000..c0a51f44c --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.icf @@ -0,0 +1,39 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the IRQ Stack (Main Stack).*/ +define symbol __ICFEDIT_size_irqstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK}; +define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {}; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {}; +define block SYSHEAP with alignment = 8 {section SYSHEAP}; +define block DATABSS with alignment = 8 {readwrite, zeroinit}; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec}; +place in ROM_region {readonly}; +place at start of RAM_region {block IRQSTACK}; +place in RAM_region {block DATABSS, block HEAP}; +place in RAM_region {block SYSHEAP}; +place at end of RAM_region {block CSTACK}; diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/main.c b/demos/ARMCM4-STM32F407-DISCOVERY/main.c new file mode 100644 index 000000000..cc12871d4 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/main.c @@ -0,0 +1,268 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#if 0 +static void pwmpcb(PWMDriver *pwmp); +static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); +static void spicb(SPIDriver *spip); + +/* Total number of channels to be sampled by a single ADC operation.*/ +#define ADC_GRP1_NUM_CHANNELS 2 + +/* Depth of the conversion buffer, channels are sampled four times each.*/ +#define ADC_GRP1_BUF_DEPTH 4 + +/* + * ADC samples buffer. + */ +static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; + +/* + * ADC conversion group. + * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. + * Channels: IN10 (48 cycles sample time) + * Sensor (192 cycles sample time) + */ +static const ADCConversionGroup adcgrpcfg = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + adccb, + NULL, + /* HW dependent part.*/ + 0, + 0, + 0, + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192), + 0, + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, + 0, + 0, + ADC_SQR5_SQ2_N(ADC_CHANNEL_IN10) | ADC_SQR5_SQ1_N(ADC_CHANNEL_SENSOR) +}; + +/* + * PWM configuration structure. + * Cyclic callback enabled, channels 3 and 4 enabled without callbacks, + * the active state is a logic one. + */ +static PWMConfig pwmcfg = { + 10000, /* 10KHz PWM clock frequency. */ + 10000, /* PWM period 1S (in ticks). */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + /* HW dependent part.*/ + 0 +}; + +/* + * SPI configuration structure. + * Maximum speed (12MHz), CPHA=0, CPOL=0, 16bits frames, MSb transmitted first. + * The slave select line is the pin GPIOA_SPI1NSS on the port GPIOA. + */ +static const SPIConfig spicfg = { + spicb, + /* HW dependent part.*/ + GPIOB, + 12, + SPI_CR1_DFF +}; + +/* + * PWM cyclic callback. + * A new ADC conversion is started. + */ +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + + /* Starts an asynchronous ADC conversion operation, the conversion + will be executed in parallel to the current PWM cycle and will + terminate before the next PWM cycle.*/ + chSysLockFromIsr(); + adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + chSysUnlockFromIsr(); +} + +/* + * ADC end conversion callback. + * The PWM channels are reprogrammed using the latest ADC samples. + * The latest samples are transmitted into a single SPI transaction. + */ +void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void) buffer; (void) n; + /* Note, only in the ADC_COMPLETE state because the ADC driver fires an + intermediate callback when the buffer is half full.*/ + if (adcp->state == ADC_COMPLETE) { + adcsample_t avg_ch1, avg_ch2; + + /* Calculates the average values from the ADC samples.*/ + avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; + avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; + + chSysLockFromIsr(); + + /* Changes the channels pulse width, the change will be effective + starting from the next cycle.*/ + pwmEnableChannelI(&PWMD4, 0, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch1)); + pwmEnableChannelI(&PWMD4, 1, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); + + /* SPI slave selection and transmission start.*/ + spiSelectI(&SPID2); + spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); + + chSysUnlockFromIsr(); + } +} + +/* + * SPI end transfer callback. + */ +static void spicb(SPIDriver *spip) { + + /* On transfer end just releases the slave select line.*/ + chSysLockFromIsr(); + spiUnselectI(spip); + chSysUnlockFromIsr(); +} +#endif + +/* + * This is a periodic thread that does absolutely nothing except increasing + * a seconds counter. + */ +static WORKING_AREA(waThread1, 128); +#if 0 +static msg_t Thread1(void *arg) { + static uint32_t seconds_counter; + + (void)arg; + chRegSetThreadName("counter"); + while (TRUE) { + chThdSleepMilliseconds(1000); + seconds_counter++; + } +} +#else +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOD, GPIOD_LED5); + chThdSleepMilliseconds(500); + palClearPad(GPIOD, GPIOD_LED5); + chThdSleepMilliseconds(500); + } +} +#endif + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + * PA2(TX) and PA3(RX) are routed to USART1. + */ + sdStart(&SD2, NULL); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + + /* + * If the user button is pressed after the reset then the test suite is + * executed immediately before activating the various device drivers in + * order to not alter the benchmark scores. + */ + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD2); + + /* + * Initializes the SPI driver 2. The SPI2 signals are routed as follow: + * PB12 - NSS. + * PB13 - SCK. + * PB14 - MISO. + * PB15 - MOSI. + */ +#if 0 + spiStart(&SPID2, &spicfg); + palSetPad(GPIOB, 12); + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); /* NSS. */ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5)); /* MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ + + /* + * Initializes the ADC driver 1 and enable the thermal sensor. + * The pin PC0 on the port GPIOC is programmed as analog input. + */ + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); + + /* + * Initializes the PWM driver 4, routes the TIM4 outputs to the board LEDs. + */ + pwmStart(&PWMD4, &pwmcfg); + palSetPadMode(GPIOB, GPIOB_LED4, PAL_MODE_ALTERNATE(2)); + palSetPadMode(GPIOB, GPIOB_LED3, PAL_MODE_ALTERNATE(2)); +#endif + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state, when the button is + * pressed the test procedure is launched with output on the serial + * driver 1. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..058cc7a76 --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h @@ -0,0 +1,191 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_HIGH +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2CSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt b/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt new file mode 100644 index 000000000..ab3c5199a --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F100xB. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F4-Discovery board. + +** The Demo ** + +The demo shows how to use the ADC, PWM and SPI drivers using asynchronous +APIs. The ADC samples two channels (temperature sensor and PC0) and modulates +the PWM using the sampled values. The sample data is also transmitted using +the SPI port 1. +By pressing the button located on the board the test procedure is activated +with output on the serial port SD2 (USART2). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From ed26815f85668f5eedc6c28581e8900f037cbba1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Nov 2011 17:54:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3481 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/ext.h | 5 + os/hal/platforms/STM32/can_lld.h | 5 + os/hal/platforms/STM32/ext_lld.h | 5 + os/hal/platforms/STM32/gpt_lld.h | 5 + os/hal/platforms/STM32/i2c_lld.h | 6 + os/hal/platforms/STM32/icu_lld.h | 5 + os/hal/platforms/STM32/mac_lld.h | 5 + os/hal/platforms/STM32/pwm_lld.h | 5 + os/hal/platforms/STM32/sdc_lld.h | 5 + os/hal/platforms/STM32/serial_lld.h | 5 + os/hal/platforms/STM32/spi_lld.c | 183 ++++++++++++++----------- os/hal/platforms/STM32/spi_lld.h | 136 ++++++++++++++++-- os/hal/platforms/STM32/uart_lld.h | 5 + os/hal/platforms/STM32F1xx/adc_lld.h | 5 + os/hal/platforms/STM32F1xx/hal_lld_f100.h | 5 + os/hal/platforms/STM32F1xx/hal_lld_f103.h | 6 + os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 5 + os/hal/platforms/STM32F1xx/stm32_dma.h | 61 +++++++-- os/hal/platforms/STM32F4xx/hal_lld.h | 74 +++++++--- os/hal/platforms/STM32F4xx/platform.mk | 4 +- os/hal/platforms/STM32F4xx/stm32_dma.c | 4 +- os/hal/platforms/STM32F4xx/stm32_dma.h | 92 ++++++++++--- os/hal/platforms/STM32F4xx/stm32_rcc.h | 13 +- os/hal/platforms/STM32L1xx/adc_lld.h | 5 + os/hal/platforms/STM32L1xx/hal_lld.h | 5 + os/hal/platforms/STM32L1xx/stm32_dma.h | 51 ++++++- os/hal/platforms/STM32L1xx/stm32l1xx.h | 1 - readme.txt | 8 +- 28 files changed, 553 insertions(+), 161 deletions(-) diff --git a/os/hal/include/ext.h b/os/hal/include/ext.h index 5d904cf4e..852c3d07f 100644 --- a/os/hal/include/ext.h +++ b/os/hal/include/ext.h @@ -81,6 +81,10 @@ typedef struct EXTDriver EXTDriver; /* Driver macros. */ /*===========================================================================*/ +/** + * @name Macro Functions + * @{ + */ /** * @brief Enables an EXT channel. * @@ -100,6 +104,7 @@ typedef struct EXTDriver EXTDriver; * @iclass */ #define extChannelDisableI(extp, channel) ext_lld_channel_disable(extp, channel) +/** @} */ /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h index a9a086e5b..d99897935 100644 --- a/os/hal/platforms/STM32/can_lld.h +++ b/os/hal/platforms/STM32/can_lld.h @@ -74,6 +74,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief CAN1 driver enable switch. * @details If set to @p TRUE the support for ADC1 is included. @@ -89,6 +93,7 @@ #if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_CAN_CAN1_IRQ_PRIORITY 11 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32/ext_lld.h b/os/hal/platforms/STM32/ext_lld.h index 753b12608..1a6102057 100644 --- a/os/hal/platforms/STM32/ext_lld.h +++ b/os/hal/platforms/STM32/ext_lld.h @@ -77,6 +77,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief EXTI0 interrupt priority level setting. */ @@ -174,6 +178,7 @@ #if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_EXT_EXTI22_IRQ_PRIORITY 6 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32/gpt_lld.h b/os/hal/platforms/STM32/gpt_lld.h index ef00c23a9..f61c5d030 100644 --- a/os/hal/platforms/STM32/gpt_lld.h +++ b/os/hal/platforms/STM32/gpt_lld.h @@ -39,6 +39,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief GPTD1 driver enable switch. * @details If set to @p TRUE the support for GPTD1 is included. @@ -134,6 +138,7 @@ #if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_GPT_TIM8_IRQ_PRIORITY 7 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index b66ba5d6a..81a9f62dc 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -37,6 +37,11 @@ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ /** * @brief Switch between callback based and synchronouse driver. * @note The default is synchronouse. @@ -98,6 +103,7 @@ #if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_I2C_I2C2_IRQ_PRIORITY 0xA0 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h index 4c440b868..3156023eb 100644 --- a/os/hal/platforms/STM32/icu_lld.h +++ b/os/hal/platforms/STM32/icu_lld.h @@ -39,6 +39,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief ICUD1 driver enable switch. * @details If set to @p TRUE the support for ICUD1 is included. @@ -134,6 +138,7 @@ #if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_ICU_TIM8_IRQ_PRIORITY 7 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h index 3e00639cc..d6eb4bfc4 100644 --- a/os/hal/platforms/STM32/mac_lld.h +++ b/os/hal/platforms/STM32/mac_lld.h @@ -114,6 +114,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief Number of available transmit buffers. */ @@ -134,6 +138,7 @@ #if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) #define MAC_BUFFERS_SIZE 1518 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index d084b3dc7..78e411592 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -74,6 +74,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief If advanced timer features switch. * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are @@ -179,6 +183,7 @@ #if !defined(STM32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_PWM_TIM8_IRQ_PRIORITY 7 #endif +/** @} */ /*===========================================================================*/ /* Configuration checks. */ diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h index eea76dadd..f670e6bbe 100644 --- a/os/hal/platforms/STM32/sdc_lld.h +++ b/os/hal/platforms/STM32/sdc_lld.h @@ -40,6 +40,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief SDIO data timeout in SDIO clock cycles. */ @@ -67,6 +71,7 @@ #if !defined(STM32_SDC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) #define STM32_SDC_UNALIGNED_SUPPORT TRUE #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32/serial_lld.h b/os/hal/platforms/STM32/serial_lld.h index fdd168201..ccafe736a 100644 --- a/os/hal/platforms/STM32/serial_lld.h +++ b/os/hal/platforms/STM32/serial_lld.h @@ -39,6 +39,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief USART1 driver enable switch. * @details If set to @p TRUE the support for USART1 is included. @@ -134,6 +138,7 @@ #if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__) #define STM32_SERIAL_USART6_PRIORITY 12 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index f8ec8546c..1511547d5 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -31,6 +31,34 @@ #if HAL_USE_SPI || defined(__DOXYGEN__) +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define SPI1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \ + STM32_SPI1_RX_DMA_CHN) + +#define SPI1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \ + STM32_SPI1_TX_DMA_CHN) + +#define SPI2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \ + STM32_SPI2_RX_DMA_CHN) + +#define SPI2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \ + STM32_SPI2_TX_DMA_CHN) + +#define SPI3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \ + STM32_SPI3_RX_DMA_CHN) + +#define SPI3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \ + STM32_SPI3_TX_DMA_CHN) + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -61,26 +89,6 @@ static uint16_t dummyrx; /* Driver local functions. */ /*===========================================================================*/ -/** - * @brief Stops the SPI DMA channels. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -#define dma_stop(spip) { \ - dmaStreamDisable(spip->dmatx); \ - dmaStreamDisable(spip->dmarx); \ -} - -/** - * @brief Starts the SPI DMA channels. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -#define dma_start(spip) { \ - dmaChannelEnable((spip)->dmarx); \ - dmaChannelEnable((spip)->dmatx); \ -} - /** * @brief Shared end-of-rx service routine. * @@ -99,7 +107,8 @@ static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { #endif /* Stop everything.*/ - dma_stop(spip); + dmaStreamDisable(spip->dmatx); + dmaStreamDisable(spip->dmarx); /* Portable SPI ISR code defined in the high level driver, note, it is a macro.*/ @@ -145,26 +154,50 @@ void spi_lld_init(void) { #if STM32_SPI_USE_SPI1 spiObjectInit(&SPID1); - SPID1.thread = NULL; - SPID1.spi = SPI1; - SPID1.dmarx = STM32_DMA1_STREAM2; - SPID1.dmatx = STM32_DMA1_STREAM3; + SPID1.spi = SPI1; + SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM); + SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM); + SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE; + SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_TEIE; #endif #if STM32_SPI_USE_SPI2 spiObjectInit(&SPID2); - SPID2.thread = NULL; - SPID2.spi = SPI2; - SPID2.dmarx = STM32_DMA1_STREAM4; - SPID2.dmatx = STM32_DMA1_STREAM5; + SPID2.spi = SPI2; + SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); + SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); + SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE; + SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_TEIE; #endif #if STM32_SPI_USE_SPI3 spiObjectInit(&SPID3); - SPID3.thread = NULL; - SPID3.spi = SPI3; - SPID3.dmarx = STM32_DMA2_STREAM1; - SPID3.dmatx = STM32_DMA2_STREAM2; + SPID3.spi = SPI3; + SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM); + SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM); + SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE; + SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_TEIE; #endif } @@ -182,12 +215,12 @@ void spi_lld_start(SPIDriver *spip) { #if STM32_SPI_USE_SPI1 if (&SPID1 == spip) { bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM2, + b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI1_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM3, + b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI1_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); @@ -198,12 +231,12 @@ void spi_lld_start(SPIDriver *spip) { #if STM32_SPI_USE_SPI2 if (&SPID2 == spip) { bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM4, + b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI2_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM5, + b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI2_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); @@ -214,12 +247,12 @@ void spi_lld_start(SPIDriver *spip) { #if STM32_SPI_USE_SPI3 if (&SPID3 == spip) { bool_t b; - b = dmaStreamAllocate(STM32_DMA2_STREAM1, + b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA2_STREAM2, + b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); @@ -233,18 +266,19 @@ void spi_lld_start(SPIDriver *spip) { dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); } - /* More DMA setup.*/ - if ((spip->config->cr1 & SPI_CR1_DFF) == 0) - spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_PSIZE_BYTE | - STM32_DMA_CR_MSIZE_BYTE; /* 8 bits transfers. */ - else - spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MSIZE_HWORD; /* 16 bits transfers. */ - + /* Configuration-specific DMA setup.*/ + if ((spip->config->cr1 & SPI_CR1_DFF) == 0) { /* 8 bits transfers. */ + spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + } + else { /* 16 bits transfers. */ + spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + } /* SPI setup and enable.*/ spip->spi->CR1 = 0; spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | @@ -267,27 +301,20 @@ void spi_lld_stop(SPIDriver *spip) { /* SPI disable.*/ spip->spi->CR1 = 0; + dmaStreamRelease(spip->dmarx); + dmaStreamRelease(spip->dmatx); #if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) { - dmaStreamRelease(STM32_DMA1_STREAM2); - dmaStreamRelease(STM32_DMA1_STREAM3); + if (&SPID1 == spip) rccDisableSPI1(FALSE); - } #endif #if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - dmaStreamRelease(STM32_DMA1_STREAM4); - dmaStreamRelease(STM32_DMA1_STREAM5); + if (&SPID2 == spip) rccDisableSPI2(FALSE); - } #endif #if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - dmaStreamRelease(STM32_DMA2_STREAM1); - dmaStreamRelease(STM32_DMA2_STREAM2); + if (&SPID3 == spip) rccDisableSPI3(FALSE); - } #endif } } @@ -332,12 +359,10 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) { dmaStreamSetMemory0(spip->dmarx, &dummyrx); dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | STM32_DMA_CR_EN); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN); dmaStreamSetMemory0(spip->dmatx, &dummytx); dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_EN); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN); } /** @@ -360,13 +385,12 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, dmaStreamSetMemory0(spip->dmarx, rxbuf); dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | - STM32_DMA_CR_EN); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC | + STM32_DMA_CR_EN); dmaStreamSetMemory0(spip->dmatx, txbuf); dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_EN); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC | + STM32_DMA_CR_EN); } /** @@ -386,12 +410,11 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { dmaStreamSetMemory0(spip->dmarx, &dummyrx); dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | STM32_DMA_CR_EN); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN); dmaStreamSetMemory0(spip->dmatx, txbuf); dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_EN); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC | + STM32_DMA_CR_EN); } /** @@ -411,13 +434,11 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { dmaStreamSetMemory0(spip->dmarx, rxbuf); dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC | - STM32_DMA_CR_EN); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC | + STM32_DMA_CR_EN); dmaStreamSetMemory0(spip->dmatx, &dummytx); dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_EN); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN); } /** diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h index c8c1e0661..5f4fd9224 100644 --- a/os/hal/platforms/STM32/spi_lld.h +++ b/os/hal/platforms/STM32/spi_lld.h @@ -39,6 +39,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief SPI1 driver enable switch. * @details If set to @p TRUE the support for SPI1 is included. @@ -68,9 +72,9 @@ /** * @brief SPI1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. */ #if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) #define STM32_SPI_SPI1_DMA_PRIORITY 1 @@ -78,9 +82,9 @@ /** * @brief SPI2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. */ #if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) #define STM32_SPI_SPI2_DMA_PRIORITY 1 @@ -88,9 +92,9 @@ /** * @brief SPI3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. */ #if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) #define STM32_SPI_SPI3_DMA_PRIORITY 1 @@ -119,13 +123,64 @@ /** * @brief SPI DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. */ #if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) #define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() #endif +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for SPI1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#endif + +/** + * @brief DMA stream used for SPI1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#endif + +/** + * @brief DMA stream used for SPI2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#endif + +/** + * @brief DMA stream used for SPI2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif + +/** + * @brief DMA stream used for SPI3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#endif + +/** + * @brief DMA stream used for SPI3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#endif + +#endif /* STM32_ADVANCED_DMA*/ +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -146,6 +201,53 @@ #error "SPI driver activated but no SPI peripheral assigned" #endif +#if STM32_ADVANCED_DMA + +/* Checks to be performed only on platforms using the advanced DMA + peripheral.*/ +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 RX" +#endif + +#if STM32_SPI_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 TX" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI2 RX" +#endif + +#if STM32_SPI_USE_SPI2 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI2 TX" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI3 RX" +#endif + +#if STM32_SPI_USE_SPI3 && \ + !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI3 TX" +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) + +#endif /* !STM32_ADVANCED_DMA */ + #if !defined(STM32_DMA_REQUIRED) #define STM32_DMA_REQUIRED #endif @@ -227,17 +329,21 @@ struct SPIDriver{ */ SPI_TypeDef *spi; /** - * @brief Receive DMA channel. + * @brief Receive DMA stream. */ const stm32_dma_stream_t *dmarx; /** - * @brief Transmit DMA channel. + * @brief Transmit DMA stream. */ const stm32_dma_stream_t *dmatx; /** - * @brief DMA mode bit mask. + * @brief RX DMA mode bit mask. + */ + uint32_t rxdmamode; + /** + * @brief TX DMA mode bit mask. */ - uint32_t dmamode; + uint32_t txdmamode; }; /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/uart_lld.h b/os/hal/platforms/STM32/uart_lld.h index aff7f52ba..d97bea91b 100644 --- a/os/hal/platforms/STM32/uart_lld.h +++ b/os/hal/platforms/STM32/uart_lld.h @@ -39,6 +39,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief UART driver on USART1 enable switch. * @details If set to @p TRUE the support for USART1 is included. @@ -124,6 +128,7 @@ #if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32F1xx/adc_lld.h b/os/hal/platforms/STM32F1xx/adc_lld.h index e3a327afa..bd4ec3dee 100644 --- a/os/hal/platforms/STM32F1xx/adc_lld.h +++ b/os/hal/platforms/STM32F1xx/adc_lld.h @@ -85,6 +85,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief ADC1 driver enable switch. * @details If set to @p TRUE the support for ADC1 is included. @@ -107,6 +111,7 @@ #if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index cdad07bc5..230b415ef 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -337,6 +337,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief Main clock source selection. * @note If the selected clock source is not the PLL then the PLL is not @@ -423,6 +427,7 @@ #if !defined(STM32_RTC) || defined(__DOXYGEN__) #define STM32_RTC STM32_RTC_LSI #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 92144b5dc..ee265fe7f 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -508,6 +508,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief Main clock source selection. * @note If the selected clock source is not the PLL then the PLL is not @@ -601,6 +605,8 @@ #if !defined(STM32_RTC) || defined(__DOXYGEN__) #define STM32_RTC STM32_RTC_LSI #endif +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 52de807d2..cc9b2f796 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -278,6 +278,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief PLL1 main switch. * @note If this constant is set to @p TRUE then the PLL1 is initialized @@ -430,6 +434,7 @@ #if !defined(STM32_RTC) || defined(__DOXYGEN__) #define STM32_RTC STM32_RTC_LSI #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h index bacd0a809..a33577af8 100644 --- a/os/hal/platforms/STM32F1xx/stm32_dma.h +++ b/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -51,26 +51,56 @@ */ #define STM32_DMA_ISR_MASK 0x0F +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + /** * @name DMA streams identifiers * @{ */ -#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0]) -#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1]) -#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2]) -#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3]) -#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4]) -#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5]) -#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6]) -#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[7]) -#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[8]) -#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[9]) -#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[10]) -#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[11]) +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) + +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] n the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(n) (&_stm32_dma_streams[n]) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) /** @} */ /** * @name CR register constants common to all DMA types + * @{ */ #define STM32_DMA_CR_EN DMA_CCR1_EN #define STM32_DMA_CR_TEIE DMA_CCR1_TEIE @@ -97,6 +127,7 @@ /** * @name CR register constants only found in enhanced DMA + * @{ */ #define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ #define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ @@ -104,6 +135,7 @@ /** * @name Status flags passed to the ISR callbacks + * @{ */ #define STM32_DMA_ISR_FEIF 0 #define STM32_DMA_ISR_DMEIF 0 @@ -149,6 +181,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /* Driver macros. */ /*===========================================================================*/ +/** + * @name Macro Functions + * @{ + */ /** * @brief Associates a peripheral data register to a DMA stream. * @note This function can be invoked in both ISR or thread context. @@ -302,6 +338,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); #define dmaWaitCompletion(dmastp) \ while (((dmastp)->channel->CNDTR > 0) && \ ((dmastp)->channel->CCR & STM32_DMA_CR_EN)) +/** @} */ /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index ca46e5287..fc40b51a9 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -40,6 +40,10 @@ #include "stm32f4xx.h" +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -58,67 +62,67 @@ /** * @brief Maximum HSE clock frequency. */ -#define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_MAX 26000000 /** * @brief Minimum HSE clock frequency. */ -#define STM32_HSECLK_MIN 1000000 +#define STM32_HSECLK_MIN 1000000 /** * @brief Maximum LSE clock frequency. */ -#define STM32_LSECLK_MAX 1000000 +#define STM32_LSECLK_MAX 1000000 /** * @brief Minimum LSE clock frequency. */ -#define STM32_LSECLK_MIN 1000 +#define STM32_LSECLK_MIN 1000 /** * @brief Maximum PLLs input clock frequency. */ -#define STM32_PLLIN_MAX 2000000 +#define STM32_PLLIN_MAX 2000000 /** * @brief Maximum PLLs input clock frequency. */ -#define STM32_PLLIN_MIN 950000 +#define STM32_PLLIN_MIN 950000 /** * @brief Maximum PLLs VCO clock frequency. */ -#define STM32_PLLVCO_MAX 432000000 +#define STM32_PLLVCO_MAX 432000000 /** * @brief Maximum PLLs VCO clock frequency. */ -#define STM32_PLLVCO_MIN 192000000 +#define STM32_PLLVCO_MIN 192000000 /** * @brief Maximum PLL output clock frequency. */ -#define STM32_PLLOUT_MAX 168000000 +#define STM32_PLLOUT_MAX 168000000 /** * @brief Maximum PLL output clock frequency. */ -#define STM32_PLLOUT_MIN 24000000 +#define STM32_PLLOUT_MIN 24000000 /** * @brief Maximum APB1 clock frequency. */ -#define STM32_PCLK1_MAX 42000000 +#define STM32_PCLK1_MAX 42000000 /** * @brief Maximum APB2 clock frequency. */ -#define STM32_PCLK2_MAX 84000000 +#define STM32_PCLK2_MAX 84000000 /** * @brief Maximum SPI/I2S clock frequency. */ -#define STM32_SPII2S_MAX 37500000 +#define STM32_SPII2S_MAX 37500000 /** @} */ /** @@ -245,22 +249,30 @@ * @name STM32F4xx capabilities * @{ */ +/* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE #define STM32_HAS_ADC3 TRUE +/* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 TRUE +/* DAC attributes.*/ #define STM32_HAS_DAC TRUE +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE #define STM32_HAS_DMA1 TRUE #define STM32_HAS_DMA2 TRUE +/* ETH attributes.*/ #define STM32_HAS_ETH TRUE +/* EXTI attributes.*/ #define STM32_EXTI_NUM_CHANNELS 23 +/* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -271,18 +283,41 @@ #define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOI TRUE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE #define STM32_HAS_I2C3 TRUE +/* RTC attributes.*/ #define STM32_HAS_RTC TRUE +/* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE +/* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI1_TX_DMA_CHN 0x00303000 + #define STM32_HAS_SPI2 TRUE -#define STM32_HAS_SPI3 TRUE +#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) | \ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ #define STM32_HAS_TIM1 TRUE #define STM32_HAS_TIM2 TRUE #define STM32_HAS_TIM3 TRUE @@ -301,6 +336,7 @@ #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE +/* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE @@ -308,6 +344,7 @@ #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 TRUE +/* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 TRUE #define STM32_HAS_OTG2 TRUE @@ -415,6 +452,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief Disables the PWR/RCC initialization in the HAL. */ @@ -620,6 +661,7 @@ #if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) #define STM32_PLLI2SR_VALUE 5 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ @@ -1208,10 +1250,6 @@ /* External declarations. */ /*===========================================================================*/ -/* STM32 DMA and RCC helpers.*/ -#include "stm32_dma.h" -#include "stm32_rcc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk index 36d555536..6b7df146b 100644 --- a/os/hal/platforms/STM32F4xx/platform.mk +++ b/os/hal/platforms/STM32F4xx/platform.mk @@ -1,6 +1,8 @@ # List of all the STM32L1xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c # Required include directories diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.c b/os/hal/platforms/STM32F4xx/stm32_dma.c index dd5a92afb..d7005b77b 100644 --- a/os/hal/platforms/STM32F4xx/stm32_dma.c +++ b/os/hal/platforms/STM32F4xx/stm32_dma.c @@ -484,8 +484,8 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, /* Putting the stream in a safe state.*/ dmaStreamDisable(dmastp); dmaStreamClearInterrupt(dmastp); - dmastp->channel->CR = STM32_DMA_CR_RESET_VALUE; - dmastp->channel->FCR = STM32_DMA_FCR_RESET_VALUE; + dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE; + dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE; /* Enables the associated IRQ vector if a callback is defined.*/ if (func != NULL) diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h index 9aaadb681..d07a9dbe9 100644 --- a/os/hal/platforms/STM32F4xx/stm32_dma.h +++ b/os/hal/platforms/STM32F4xx/stm32_dma.h @@ -46,30 +46,81 @@ */ #define STM32_DMA_ISR_MASK 0x3D +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] id the unique numeric stream identifier + * @param[in] c a stream/channel association word, one channel per + * nibble + * @return Returns the channel associated to the stream. + */ +#define STM32_DMA_GETCHANNEL(id, c) ((c) >> (((id) & 7) * 4)) + +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream)) + +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + /** * @name DMA streams identifiers * @{ */ -#define STM32_DMA1_STREAM0 (&_stm32_dma_streams[0]) -#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[1]) -#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[2]) -#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[3]) -#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[4]) -#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[5]) -#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[6]) -#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[7]) -#define STM32_DMA2_STREAM0 (&_stm32_dma_streams[8]) -#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[9]) -#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[10]) -#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[11]) -#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[12]) -#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[13]) -#define STM32_DMA2_STREAM6 (&_stm32_dma_streams[14]) -#define STM32_DMA2_STREAM7 (&_stm32_dma_streams[15]) +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] id the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) + +#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13) +#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14) +#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15) /** @} */ /** * @name CR register constants common to all DMA types + * @{ */ #define STM32_DMA_CR_EN DMA_SxCR_EN #define STM32_DMA_CR_TEIE DMA_SxCR_TEIE @@ -90,12 +141,15 @@ #define STM32_DMA_CR_MSIZE_BYTE 0 #define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0 #define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_MSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) #define STM32_DMA_CR_PL_MASK DMA_SxCR_PL #define STM32_DMA_CR_PL(n) ((n) << 16) /** @} */ /** * @name CR register constants only found in STM32F2xx/STM32F4xx + * @{ */ #define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE #define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL @@ -118,6 +172,7 @@ /** * @name FCR register constants only found in STM32F2xx + * @{ */ #define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE #define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS @@ -176,6 +231,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /* Driver macros. */ /*===========================================================================*/ +/** + * @name Macro Functions + * @{ + */ /** * @brief Associates a peripheral data register to a DMA stream. * @note This function can be invoked in both ISR or thread context. @@ -357,6 +416,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); #define dmaWaitCompletion(dmastp) \ while (((dmastp)->stream->CNDTR > 0) && \ ((dmastp)->stream->CCR & STM32_DMA_CR_EN)) +/** @} */ /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h index 3a10e57b2..4971a71c5 100644 --- a/os/hal/platforms/STM32F4xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -27,7 +27,6 @@ * @addtogroup STM32F4xx_RCC * @{ */ - #ifndef _STM32_RCC_ #define _STM32_RCC_ @@ -347,7 +346,7 @@ * * @api */ -#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHB1ENR_DMA1EN, lp) +#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) /** * @brief Disables the DMA1 peripheral clock. @@ -356,14 +355,14 @@ * * @api */ -#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHB1ENR_DMA1EN, lp) +#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp) /** * @brief Resets the DMA1 peripheral. * * @api */ -#define rccResetDMA1() rccResetAHB(RCC_AHB1RSTR_DMA1RST) +#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) /** * @brief Enables the DMA2 peripheral clock. @@ -372,7 +371,7 @@ * * @api */ -#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHB1ENR_DMA2EN, lp) +#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) /** * @brief Disables the DMA2 peripheral clock. @@ -381,14 +380,14 @@ * * @api */ -#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHB1ENR_DMA2EN, lp) +#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp) /** * @brief Resets the DMA2 peripheral. * * @api */ -#define rccResetDMA2() rccResetAHB(RCC_AHB1RSTR_DMA2RST) +#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) /** @} */ /** diff --git a/os/hal/platforms/STM32L1xx/adc_lld.h b/os/hal/platforms/STM32L1xx/adc_lld.h index 0ca41c269..58fb7bda1 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.h +++ b/os/hal/platforms/STM32L1xx/adc_lld.h @@ -101,6 +101,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief ADC1 driver enable switch. * @details If set to @p TRUE the support for ADC1 is included. @@ -134,6 +138,7 @@ #if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 9ca34fb7c..f61550170 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -298,6 +298,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief Disables the PWR/RCC initialization in the HAL. */ @@ -456,6 +460,7 @@ #if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) #define STM32_RTCPRE STM32_RTCPRE_DIV2 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h index e23980f9f..43ffdb668 100644 --- a/os/hal/platforms/STM32L1xx/stm32_dma.h +++ b/os/hal/platforms/STM32L1xx/stm32_dma.h @@ -47,21 +47,51 @@ */ #define STM32_DMA_ISR_MASK 0x0F +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + /** * @name DMA streams identifiers * @{ */ -#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0]) -#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1]) -#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2]) -#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3]) -#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4]) -#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5]) -#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6]) +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1) + +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] n the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(n) (&_stm32_dma_streams[n)) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) /** @} */ /** * @name CR register constants common to all DMA types + * @{ */ #define STM32_DMA_CR_EN DMA_CCR1_EN #define STM32_DMA_CR_TEIE DMA_CCR1_TEIE @@ -88,6 +118,7 @@ /** * @name CR register constants only found in enhanced DMA + * @{ */ #define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ #define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ @@ -95,6 +126,7 @@ /** * @name Status flags passed to the ISR callbacks + * @{ */ #define STM32_DMA_ISR_FEIF 0 #define STM32_DMA_ISR_DMEIF 0 @@ -140,6 +172,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /* Driver macros. */ /*===========================================================================*/ +/** + * @name Macro Functions + * @{ + */ /** * @brief Associates a peripheral data register to a DMA stream. * @note This function can be invoked in both ISR or thread context. @@ -293,6 +329,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); #define dmaWaitCompletion(dmastp) \ while (((dmastp)->channel->CNDTR > 0) && \ ((dmastp)->channel->CCR & STM32_DMA_CR_EN)) +/** @} */ /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h index 9723158c8..32ddcb79d 100644 --- a/os/hal/platforms/STM32L1xx/stm32l1xx.h +++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h @@ -430,7 +430,6 @@ typedef struct __IO uint32_t AFR[2]; } GPIO_TypeDef; #endif -#endif /** * @brief SysTem Configuration diff --git a/readme.txt b/readme.txt index d2180bc8a..842946621 100644 --- a/readme.txt +++ b/readme.txt @@ -74,6 +74,12 @@ ***************************************************************************** *** 2.3.4 *** +- FIX: Fixed Extra initialization in STM32 SPI driver (bug 3436127) + (backported to 2.2.8). +- FIX: Fixed DMA priority setting error in STM32 UART driver (bug 3436125) + (backported to 2.2.8). +- FIX: Fixed DMA priority setting error in STM32 SPI driver (bug 3436124) + (backported to 2.2.8). - FIX: Fixed broken support for UART5 in STM32 serial driver (bug 3434094) (backported to 2.2.8). - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). @@ -81,7 +87,7 @@ - NEW: Reorganized the STM32F1xx hal_lld_xxx.h files in order to distribute the capability macros into the appropriate file (previously those were all in the common hal_lld.h). -- NEW: Added HAL support for the STM32F4xx sub-family. +- NEW: Added HAL, Serial, SPI support for the STM32F4xx sub-family. - NEW: Added handling of USART6 to the STM32 serial driver. - NEW: Added USE_COPT setting to all makefiles, contributed by Mabl. - NEW: Added EXT driver implementation for AT91SAM7x, contributed by Florian. -- cgit v1.2.3 From fc2265ab23c0e086694dc0208f790f3f55329b07 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Nov 2011 17:59:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3482 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F4xx/SPI/Makefile | 209 +++++++++++++++ testhal/STM32F4xx/SPI/chconf.h | 535 +++++++++++++++++++++++++++++++++++++++ testhal/STM32F4xx/SPI/halconf.h | 335 ++++++++++++++++++++++++ testhal/STM32F4xx/SPI/main.c | 142 +++++++++++ testhal/STM32F4xx/SPI/mcuconf.h | 195 ++++++++++++++ testhal/STM32F4xx/SPI/readme.txt | 26 ++ 6 files changed, 1442 insertions(+) create mode 100644 testhal/STM32F4xx/SPI/Makefile create mode 100644 testhal/STM32F4xx/SPI/chconf.h create mode 100644 testhal/STM32F4xx/SPI/halconf.h create mode 100644 testhal/STM32F4xx/SPI/main.c create mode 100644 testhal/STM32F4xx/SPI/mcuconf.h create mode 100644 testhal/STM32F4xx/SPI/readme.txt diff --git a/testhal/STM32F4xx/SPI/Makefile b/testhal/STM32F4xx/SPI/Makefile new file mode 100644 index 000000000..43ed3c6f2 --- /dev/null +++ b/testhal/STM32F4xx/SPI/Makefile @@ -0,0 +1,209 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/SPI/chconf.h b/testhal/STM32F4xx/SPI/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F4xx/SPI/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/SPI/halconf.h b/testhal/STM32F4xx/SPI/halconf.h new file mode 100644 index 000000000..b3bbd85fd --- /dev/null +++ b/testhal/STM32F4xx/SPI/halconf.h @@ -0,0 +1,335 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/SPI/main.c b/testhal/STM32F4xx/SPI/main.c new file mode 100644 index 000000000..d12da4215 --- /dev/null +++ b/testhal/STM32F4xx/SPI/main.c @@ -0,0 +1,142 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, + GPIOB, + 12, + 0 +}; + +/* + * Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, + GPIOB, + 12, + SPI_CR1_BR_2 | SPI_CR1_BR_1 +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palSetPad(GPIOD, GPIOD_LED5); /* LED ON. */ + spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palClearPad(GPIOD, GPIOD_LED5); /* LED OFF. */ + spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * SPI1 I/O pins setup. + */ + palSetPadMode(GPIOA, 5, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SCK. */ + palSetPadMode(GPIOA, 6, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MISO.*/ + palSetPadMode(GPIOA, 7, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* MOSI.*/ + palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | + PAL_STM32_OSPEED_HIGHEST); + palSetPad(GPIOB, 12); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F4xx/SPI/mcuconf.h b/testhal/STM32F4xx/SPI/mcuconf.h new file mode 100644 index 000000000..2afbf074f --- /dev/null +++ b/testhal/STM32F4xx/SPI/mcuconf.h @@ -0,0 +1,195 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_HIGH +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2CSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 TRUE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F4xx/SPI/readme.txt b/testhal/STM32F4xx/SPI/readme.txt new file mode 100644 index 000000000..c1914bc43 --- /dev/null +++ b/testhal/STM32F4xx/SPI/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32 SPI driver. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From c505341e78165415765743d423eedf9f62df0d1e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Nov 2011 20:15:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3483 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/stm32_dma.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h index 43ffdb668..7cfcf7536 100644 --- a/os/hal/platforms/STM32L1xx/stm32_dma.h +++ b/os/hal/platforms/STM32L1xx/stm32_dma.h @@ -74,11 +74,11 @@ /** * @brief Returns a pointer to a stm32_dma_stream_t structure. * - * @param[in] n the stream numeric identifier + * @param[in] id the stream numeric identifier * @return A pointer to the stm32_dma_stream_t constant structure * associated to the DMA stream. */ -#define STM32_DMA_STREAM(n) (&_stm32_dma_streams[n)) +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) #define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) #define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) @@ -112,6 +112,8 @@ #define STM32_DMA_CR_MSIZE_BYTE 0 #define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 #define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_MSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) #define STM32_DMA_CR_PL_MASK DMA_CCR1_PL #define STM32_DMA_CR_PL(n) ((n) << 12) /** @} */ -- cgit v1.2.3 From 97d1a377042e1847cb45adeafac98fedf97ccefe Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Nov 2011 20:27:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3484 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h | 2 ++ demos/ARMCM3-STM32F103-FATFS/mcuconf.h | 2 ++ demos/ARMCM3-STM32F103-G++/mcuconf.h | 2 ++ demos/ARMCM3-STM32F103/mcuconf.h | 2 ++ demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h | 2 ++ demos/ARMCM3-STM32F107/mcuconf.h | 2 ++ demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h | 2 ++ demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h | 1 + testhal/STM32F1xx/ADC/mcuconf.h | 2 ++ testhal/STM32F1xx/CAN/mcuconf.h | 2 ++ testhal/STM32F1xx/EXT/mcuconf.h | 2 ++ testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h | 2 ++ testhal/STM32F1xx/GPT/mcuconf.h | 2 ++ testhal/STM32F1xx/I2C/mcuconf.h | 2 ++ testhal/STM32F1xx/IRQ_STORM/mcuconf.h | 2 ++ testhal/STM32F1xx/MAC/mcuconf.h | 2 ++ testhal/STM32F1xx/PWM-ICU/mcuconf.h | 2 ++ testhal/STM32F1xx/RTC/mcuconf.h | 12 +++++++----- testhal/STM32F1xx/SDC/mcuconf.h | 2 ++ testhal/STM32F1xx/SPI/mcuconf.h | 2 ++ testhal/STM32F1xx/UART/mcuconf.h | 2 ++ testhal/STM32F1xx/USB_CDC/mcuconf.h | 2 ++ testhal/STM32F1xx/USB_MSC/mcuconf.h | 2 ++ testhal/STM32F4xx/SPI/mcuconf.h | 2 ++ testhal/STM32L1xx/ADC/mcuconf.h | 2 ++ testhal/STM32L1xx/EXT/mcuconf.h | 2 ++ testhal/STM32L1xx/GPT/mcuconf.h | 2 ++ testhal/STM32L1xx/IRQ_STORM/mcuconf.h | 2 ++ testhal/STM32L1xx/PWM-ICU/mcuconf.h | 2 ++ testhal/STM32L1xx/SPI/mcuconf.h | 2 ++ testhal/STM32L1xx/UART/mcuconf.h | 2 ++ 31 files changed, 66 insertions(+), 5 deletions(-) diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h index e0b78e3ed..7a7c6c25a 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY/mcuconf.h @@ -130,11 +130,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/demos/ARMCM3-STM32F103-FATFS/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS/mcuconf.h index a563b0e49..bce5518d6 100644 --- a/demos/ARMCM3-STM32F103-FATFS/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/demos/ARMCM3-STM32F103-G++/mcuconf.h b/demos/ARMCM3-STM32F103-G++/mcuconf.h index a563b0e49..bce5518d6 100644 --- a/demos/ARMCM3-STM32F103-G++/mcuconf.h +++ b/demos/ARMCM3-STM32F103-G++/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/demos/ARMCM3-STM32F103/mcuconf.h b/demos/ARMCM3-STM32F103/mcuconf.h index 8fbf4710c..c6dc0ce8a 100644 --- a/demos/ARMCM3-STM32F103/mcuconf.h +++ b/demos/ARMCM3-STM32F103/mcuconf.h @@ -128,11 +128,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h index bb01745f7..b0dedacac 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h +++ b/demos/ARMCM3-STM32F103ZG-FATFS/mcuconf.h @@ -138,11 +138,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/demos/ARMCM3-STM32F107/mcuconf.h b/demos/ARMCM3-STM32F107/mcuconf.h index 360788253..b8d72d861 100644 --- a/demos/ARMCM3-STM32F107/mcuconf.h +++ b/demos/ARMCM3-STM32F107/mcuconf.h @@ -138,11 +138,13 @@ #define STM32_SERIAL_USE_USART3 TRUE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h index 3aa958d8f..b29e6a6fa 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h @@ -141,11 +141,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h index 058cc7a76..4aa3d6cc2 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h +++ b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h @@ -147,6 +147,7 @@ #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE #define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 diff --git a/testhal/STM32F1xx/ADC/mcuconf.h b/testhal/STM32F1xx/ADC/mcuconf.h index a563b0e49..bce5518d6 100644 --- a/testhal/STM32F1xx/ADC/mcuconf.h +++ b/testhal/STM32F1xx/ADC/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/CAN/mcuconf.h b/testhal/STM32F1xx/CAN/mcuconf.h index a563b0e49..bce5518d6 100644 --- a/testhal/STM32F1xx/CAN/mcuconf.h +++ b/testhal/STM32F1xx/CAN/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/EXT/mcuconf.h b/testhal/STM32F1xx/EXT/mcuconf.h index 8fbf4710c..c6dc0ce8a 100644 --- a/testhal/STM32F1xx/EXT/mcuconf.h +++ b/testhal/STM32F1xx/EXT/mcuconf.h @@ -128,11 +128,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h index 95b5ebd73..bf077cbae 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/mcuconf.h @@ -128,11 +128,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/GPT/mcuconf.h b/testhal/STM32F1xx/GPT/mcuconf.h index 37eddd3d3..011b609ae 100644 --- a/testhal/STM32F1xx/GPT/mcuconf.h +++ b/testhal/STM32F1xx/GPT/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/I2C/mcuconf.h b/testhal/STM32F1xx/I2C/mcuconf.h index 446af067e..6afc97f28 100644 --- a/testhal/STM32F1xx/I2C/mcuconf.h +++ b/testhal/STM32F1xx/I2C/mcuconf.h @@ -127,11 +127,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/IRQ_STORM/mcuconf.h b/testhal/STM32F1xx/IRQ_STORM/mcuconf.h index 4398818f7..f37ecca3c 100644 --- a/testhal/STM32F1xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32F1xx/IRQ_STORM/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/MAC/mcuconf.h b/testhal/STM32F1xx/MAC/mcuconf.h index 360788253..b8d72d861 100644 --- a/testhal/STM32F1xx/MAC/mcuconf.h +++ b/testhal/STM32F1xx/MAC/mcuconf.h @@ -138,11 +138,13 @@ #define STM32_SERIAL_USE_USART3 TRUE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/PWM-ICU/mcuconf.h b/testhal/STM32F1xx/PWM-ICU/mcuconf.h index a563b0e49..bce5518d6 100644 --- a/testhal/STM32F1xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32F1xx/PWM-ICU/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/RTC/mcuconf.h b/testhal/STM32F1xx/RTC/mcuconf.h index 2c5d4d8be..8413e2421 100644 --- a/testhal/STM32F1xx/RTC/mcuconf.h +++ b/testhal/STM32F1xx/RTC/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USART1_PRIORITY 9 -#define STM32_SERIAL_USART2_PRIORITY 10 -#define STM32_SERIAL_USART3_PRIORITY 2 -#define STM32_SERIAL_UART4_PRIORITY 2 -#define STM32_SERIAL_UART5_PRIORITY 2 +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/SDC/mcuconf.h b/testhal/STM32F1xx/SDC/mcuconf.h index 49ae48fff..d70b08473 100644 --- a/testhal/STM32F1xx/SDC/mcuconf.h +++ b/testhal/STM32F1xx/SDC/mcuconf.h @@ -138,11 +138,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/SPI/mcuconf.h b/testhal/STM32F1xx/SPI/mcuconf.h index a563b0e49..bce5518d6 100644 --- a/testhal/STM32F1xx/SPI/mcuconf.h +++ b/testhal/STM32F1xx/SPI/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/UART/mcuconf.h b/testhal/STM32F1xx/UART/mcuconf.h index 4c46b0213..4b23c2e7d 100644 --- a/testhal/STM32F1xx/UART/mcuconf.h +++ b/testhal/STM32F1xx/UART/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/USB_CDC/mcuconf.h b/testhal/STM32F1xx/USB_CDC/mcuconf.h index a563b0e49..bce5518d6 100644 --- a/testhal/STM32F1xx/USB_CDC/mcuconf.h +++ b/testhal/STM32F1xx/USB_CDC/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F1xx/USB_MSC/mcuconf.h b/testhal/STM32F1xx/USB_MSC/mcuconf.h index a563b0e49..bce5518d6 100644 --- a/testhal/STM32F1xx/USB_MSC/mcuconf.h +++ b/testhal/STM32F1xx/USB_MSC/mcuconf.h @@ -131,11 +131,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32F4xx/SPI/mcuconf.h b/testhal/STM32F4xx/SPI/mcuconf.h index 2afbf074f..9f13048a6 100644 --- a/testhal/STM32F4xx/SPI/mcuconf.h +++ b/testhal/STM32F4xx/SPI/mcuconf.h @@ -146,11 +146,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32L1xx/ADC/mcuconf.h b/testhal/STM32L1xx/ADC/mcuconf.h index 3702fa62f..b2ad1faca 100644 --- a/testhal/STM32L1xx/ADC/mcuconf.h +++ b/testhal/STM32L1xx/ADC/mcuconf.h @@ -141,11 +141,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32L1xx/EXT/mcuconf.h b/testhal/STM32L1xx/EXT/mcuconf.h index 3702fa62f..b2ad1faca 100644 --- a/testhal/STM32L1xx/EXT/mcuconf.h +++ b/testhal/STM32L1xx/EXT/mcuconf.h @@ -141,11 +141,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32L1xx/GPT/mcuconf.h b/testhal/STM32L1xx/GPT/mcuconf.h index 3702fa62f..b2ad1faca 100644 --- a/testhal/STM32L1xx/GPT/mcuconf.h +++ b/testhal/STM32L1xx/GPT/mcuconf.h @@ -141,11 +141,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h index 2562d6b67..4458168c1 100644 --- a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h @@ -141,11 +141,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32L1xx/PWM-ICU/mcuconf.h b/testhal/STM32L1xx/PWM-ICU/mcuconf.h index 4f9182094..433013b38 100644 --- a/testhal/STM32L1xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32L1xx/PWM-ICU/mcuconf.h @@ -141,11 +141,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32L1xx/SPI/mcuconf.h b/testhal/STM32L1xx/SPI/mcuconf.h index 4071c4507..116f26170 100644 --- a/testhal/STM32L1xx/SPI/mcuconf.h +++ b/testhal/STM32L1xx/SPI/mcuconf.h @@ -141,11 +141,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. diff --git a/testhal/STM32L1xx/UART/mcuconf.h b/testhal/STM32L1xx/UART/mcuconf.h index 33119bd78..d1b9069be 100644 --- a/testhal/STM32L1xx/UART/mcuconf.h +++ b/testhal/STM32L1xx/UART/mcuconf.h @@ -141,11 +141,13 @@ #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. -- cgit v1.2.3 From 1ae84c9323e76f02ec4bc4d71aff4301ba5d00e7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Nov 2011 20:33:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3485 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/stm32_dma.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h index a33577af8..e01708d64 100644 --- a/os/hal/platforms/STM32F1xx/stm32_dma.h +++ b/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -78,11 +78,11 @@ /** * @brief Returns a pointer to a stm32_dma_stream_t structure. * - * @param[in] n the stream numeric identifier + * @param[in] id the stream numeric identifier * @return A pointer to the stm32_dma_stream_t constant structure * associated to the DMA stream. */ -#define STM32_DMA_STREAM(n) (&_stm32_dma_streams[n]) +#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id]) #define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) #define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) @@ -121,6 +121,8 @@ #define STM32_DMA_CR_MSIZE_BYTE 0 #define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0 #define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_MSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) #define STM32_DMA_CR_PL_MASK DMA_CCR1_PL #define STM32_DMA_CR_PL(n) ((n) << 12) /** @} */ -- cgit v1.2.3 From 3d09e9e86c134035e02ecf92255f72d8d08fdcf5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 11 Nov 2011 14:11:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3486 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/spi_lld.h | 30 ++++++++++++------------------ os/hal/platforms/STM32L1xx/hal_lld.h | 29 +++++++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/stm32_dma.h | 22 ++++++++++++++++++++++ 3 files changed, 63 insertions(+), 18 deletions(-) diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h index 5f4fd9224..ccffe5f8b 100644 --- a/os/hal/platforms/STM32/spi_lld.h +++ b/os/hal/platforms/STM32/spi_lld.h @@ -178,7 +178,18 @@ #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #endif -#endif /* STM32_ADVANCED_DMA*/ +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) + +#endif /* !STM32_ADVANCED_DMA*/ /** @} */ /*===========================================================================*/ @@ -201,10 +212,6 @@ #error "SPI driver activated but no SPI peripheral assigned" #endif -#if STM32_ADVANCED_DMA - -/* Checks to be performed only on platforms using the advanced DMA - peripheral.*/ #if STM32_SPI_USE_SPI1 && \ !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) #error "invalid DMA stream associated to SPI1 RX" @@ -235,19 +242,6 @@ #error "invalid DMA stream associated to SPI3 TX" #endif -#else /* !STM32_ADVANCED_DMA */ - -/* Fixed streams for platforms using the old DMA peripheral, the values are - valid for both STM32F1xx and STM32L1xx.*/ -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) - -#endif /* !STM32_ADVANCED_DMA */ - #if !defined(STM32_DMA_REQUIRED) #define STM32_DMA_REQUIRED #endif diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index f61550170..08990ee13 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -168,22 +168,30 @@ * @name STM32L1xx capabilities * @{ */ +/* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE +/* CAN attributes.*/ #define STM32_HAS_CAN1 FALSE #define STM32_HAS_CAN2 FALSE +/* DAC attributes.*/ #define STM32_HAS_DAC TRUE +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE #define STM32_HAS_DMA1 TRUE #define STM32_HAS_DMA2 FALSE +/* ETH attributes.*/ #define STM32_HAS_ETH FALSE +/* EXTI attributes.*/ #define STM32_EXTI_NUM_CHANNELS 23 +/* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -194,18 +202,37 @@ #define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOI FALSE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE #define STM32_HAS_I2C3 FALSE +/* RTC attributes.*/ #define STM32_HAS_RTC TRUE +/* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE +/* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 +/* TIM attributes.*/ #define STM32_HAS_TIM1 FALSE #define STM32_HAS_TIM2 TRUE #define STM32_HAS_TIM3 TRUE @@ -224,6 +251,7 @@ #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE +/* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE @@ -231,6 +259,7 @@ #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE +/* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h index 7cfcf7536..e22d99f2b 100644 --- a/os/hal/platforms/STM32L1xx/stm32_dma.h +++ b/os/hal/platforms/STM32L1xx/stm32_dma.h @@ -71,6 +71,28 @@ */ #define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1) +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + /** * @brief Returns a pointer to a stm32_dma_stream_t structure. * -- cgit v1.2.3 From 6eae3c1de5a1936247676750132758d17d9bdaf1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 11 Nov 2011 14:40:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3487 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/hal_lld_f100.h | 57 ++++++++++++ os/hal/platforms/STM32F1xx/hal_lld_f103.h | 116 +++++++++++++++++++++++++ os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 29 +++++++ os/hal/platforms/STM32F1xx/stm32_dma.h | 22 +++++ os/hal/platforms/STM32L1xx/hal_lld.h | 4 +- 5 files changed, 226 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 230b415ef..91be2eadb 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -128,22 +128,30 @@ * @name STM32F100 LD capabilities * @{ */ +/* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE +/* CAN attributes.*/ #define STM32_HAS_CAN1 FALSE #define STM32_HAS_CAN2 FALSE +/* DAC attributes.*/ #define STM32_HAS_DAC TRUE +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE #define STM32_HAS_DMA1 TRUE #define STM32_HAS_DMA2 FALSE +/* ETH attributes.*/ #define STM32_HAS_ETH FALSE +/* EXTI attributes.*/ #define STM32_EXTI_NUM_CHANNELS 19 +/* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -154,18 +162,36 @@ #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C3 FALSE #define STM32_HAS_RTC TRUE +/* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE +/* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI2 FALSE +#define STM32_SPI2_RX_DMA_MSK 0 +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK 0 +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 +/* TIM attributes.*/ #define STM32_HAS_TIM1 TRUE #define STM32_HAS_TIM2 TRUE #define STM32_HAS_TIM3 TRUE @@ -184,6 +210,7 @@ #define STM32_HAS_TIM16 TRUE #define STM32_HAS_TIM17 TRUE +/* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 FALSE @@ -191,6 +218,7 @@ #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE +/* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -202,22 +230,30 @@ * @name STM32F100 MD capabilities * @{ */ +/* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE +/* CAN attributes.*/ #define STM32_HAS_CAN1 FALSE #define STM32_HAS_CAN2 FALSE +/* DAC attributes.*/ #define STM32_HAS_DAC TRUE +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE #define STM32_HAS_DMA1 TRUE #define STM32_HAS_DMA2 FALSE +/* ETH attributes.*/ #define STM32_HAS_ETH FALSE +/* EXTI attributes.*/ #define STM32_EXTI_NUM_CHANNELS 19 +/* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -228,18 +264,37 @@ #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE #define STM32_HAS_I2C3 FALSE +/* RTC attributes.*/ #define STM32_HAS_RTC TRUE +/* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE +/* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 +/* TIM attributes.*/ #define STM32_HAS_TIM1 TRUE #define STM32_HAS_TIM2 TRUE #define STM32_HAS_TIM3 TRUE @@ -258,6 +313,7 @@ #define STM32_HAS_TIM16 TRUE #define STM32_HAS_TIM17 TRUE +/* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE @@ -265,6 +321,7 @@ #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE +/* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index ee265fe7f..1375bf7cf 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -138,22 +138,30 @@ * @name STM32F103 LD capabilities * @{ */ +/* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE #define STM32_HAS_ADC3 FALSE +/* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE +/* DAC attributes.*/ #define STM32_HAS_DAC FALSE +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE #define STM32_HAS_DMA1 TRUE #define STM32_HAS_DMA2 FALSE +/* ETH attributes.*/ #define STM32_HAS_ETH FALSE +/* EXTI attributes.*/ #define STM32_EXTI_NUM_CHANNELS 19 +/* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -164,18 +172,37 @@ #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C3 FALSE +/* RTC attributes.*/ #define STM32_HAS_RTC TRUE +/* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE +/* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI2 FALSE +#define STM32_SPI2_RX_DMA_MSK 0 +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK 0 +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 +/* TIM attributes.*/ #define STM32_HAS_TIM1 TRUE #define STM32_HAS_TIM2 TRUE #define STM32_HAS_TIM3 TRUE @@ -194,6 +221,7 @@ #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE +/* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 FALSE @@ -201,6 +229,7 @@ #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE +/* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -212,22 +241,30 @@ * @name STM32F103 MD capabilities * @{ */ +/* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE #define STM32_HAS_ADC3 FALSE +/* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE +/* DAC attributes.*/ #define STM32_HAS_DAC FALSE +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE #define STM32_HAS_DMA1 TRUE #define STM32_HAS_DMA2 FALSE +/* ETH attributes.*/ #define STM32_HAS_ETH FALSE +/* EXTI attributes.*/ #define STM32_EXTI_NUM_CHANNELS 19 +/* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -238,18 +275,37 @@ #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE #define STM32_HAS_I2C3 FALSE +/* RTC attributes.*/ #define STM32_HAS_RTC TRUE +/* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE +/* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 +/* TIM attributes.*/ #define STM32_HAS_TIM1 TRUE #define STM32_HAS_TIM2 TRUE #define STM32_HAS_TIM3 TRUE @@ -268,6 +324,7 @@ #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE +/* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE @@ -275,6 +332,7 @@ #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE +/* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -286,22 +344,30 @@ * @name STM32F103 HD capabilities * @{ */ +/* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE #define STM32_HAS_ADC3 TRUE +/* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE +/* DAC attributes.*/ #define STM32_HAS_DAC TRUE +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE #define STM32_HAS_DMA1 TRUE #define STM32_HAS_DMA2 TRUE +/* ETH attributes.*/ #define STM32_HAS_ETH FALSE +/* EXTI attributes.*/ #define STM32_EXTI_NUM_CHANNELS 19 +/* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -312,18 +378,37 @@ #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE #define STM32_HAS_I2C3 FALSE +/* RTC attributes.*/ #define STM32_HAS_RTC TRUE +/* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE +/* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 +/* TIM attributes.*/ #define STM32_HAS_TIM1 TRUE #define STM32_HAS_TIM2 TRUE #define STM32_HAS_TIM3 TRUE @@ -342,6 +427,7 @@ #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE +/* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE @@ -349,6 +435,7 @@ #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 FALSE +/* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -360,22 +447,30 @@ * @name STM32F103 XL capabilities * @{ */ +/* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE #define STM32_HAS_ADC3 TRUE +/* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE +/* DAC attributes.*/ #define STM32_HAS_DAC TRUE +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE #define STM32_HAS_DMA1 TRUE #define STM32_HAS_DMA2 TRUE +/* ETH attributes.*/ #define STM32_HAS_ETH FALSE +/* EXTI attributes.*/ #define STM32_EXTI_NUM_CHANNELS 19 +/* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -386,18 +481,37 @@ #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE #define STM32_HAS_I2C3 FALSE +/* RTC attributes.*/ #define STM32_HAS_RTC TRUE +/* SDIO attributes.*/ #define STM32_HAS_SDIO TRUE +/* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 +/* TIM attributes.*/ #define STM32_HAS_TIM1 TRUE #define STM32_HAS_TIM2 TRUE #define STM32_HAS_TIM3 TRUE @@ -416,6 +530,7 @@ #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE +/* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE @@ -423,6 +538,7 @@ #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 FALSE +/* USB attributes.*/ #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index cc9b2f796..b8eb11c3b 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -130,22 +130,30 @@ * @name STM32F105/F107 CL capabilities * @{ */ +/* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE #define STM32_HAS_ADC3 FALSE +/* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 TRUE +/* DAC attributes.*/ #define STM32_HAS_DAC TRUE +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE #define STM32_HAS_DMA1 TRUE #define STM32_HAS_DMA2 TRUE +/* ETH attributes.*/ #define STM32_HAS_ETH TRUE +/* EXTI attributes.*/ #define STM32_EXTI_NUM_CHANNELS 20 +/* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE @@ -156,18 +164,37 @@ #define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOI FALSE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE #define STM32_HAS_I2C3 FALSE +/* RTC attributes.*/ #define STM32_HAS_RTC TRUE +/* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE +/* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 +/* TIM attributes.*/ #define STM32_HAS_TIM1 TRUE #define STM32_HAS_TIM2 TRUE #define STM32_HAS_TIM3 TRUE @@ -186,6 +213,7 @@ #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE +/* USART attributes.*/ #define STM32_HAS_USART1 TRUE #define STM32_HAS_USART2 TRUE #define STM32_HAS_USART3 TRUE @@ -193,6 +221,7 @@ #define STM32_HAS_UART5 TRUE #define STM32_HAS_USART6 FALSE +/* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 TRUE #define STM32_HAS_OTG2 FALSE diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h index e01708d64..4469bef67 100644 --- a/os/hal/platforms/STM32F1xx/stm32_dma.h +++ b/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -62,6 +62,28 @@ */ #define STM32_DMA_GETCHANNEL(n, c) 0 +/** + * @brief Returns a DMA stream identifier mask. + * + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return A DMA stream identifier mask. + */ +#define STM32_DMA_STREAM_ID_MSK(dma, stream) \ + (1 << STM32_DMA_STREAM_ID(dma, stream)) + +/** + * @brief Checks if a DMA stream unique identifier belongs to a mask. + * @param[in] id the stream numeric identifier + * @param[in] mask the stream numeric identifiers mask + * + * @retval The check result. + * @retval FALSE id does not belong to the mask. + * @retval TRUE id belongs to the mask. + */ +#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask))) + /** * @name DMA streams identifiers * @{ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 08990ee13..8d8f1b23b 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -227,9 +227,9 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI3_RX_DMA_MSK 0 #define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI3_TX_DMA_MSK 0 #define STM32_SPI3_TX_DMA_CHN 0x00000000 /* TIM attributes.*/ -- cgit v1.2.3 From 30e29ea2155b522e962cd2778cb001089feb58c5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 12 Nov 2011 10:10:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3488 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32F4_DISCOVERY/board.h | 42 +++++++++++++++++-------------------- testhal/STM32F4xx/SPI/main.c | 40 +++++++++++++++++------------------ testhal/STM32F4xx/SPI/readme.txt | 6 +++++- 3 files changed, 44 insertions(+), 44 deletions(-) diff --git a/boards/ST_STM32F4_DISCOVERY/board.h b/boards/ST_STM32F4_DISCOVERY/board.h index 227f96ce9..d93e4a125 100644 --- a/boards/ST_STM32F4_DISCOVERY/board.h +++ b/boards/ST_STM32F4_DISCOVERY/board.h @@ -159,15 +159,15 @@ PIN_PUDR_PULLDOWN(GPIOA_SWCLK) | \ PIN_PUDR_PULLUP(15)) #define VAL_GPIOA_ODR 0xFFFFFFFF -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(4, 6) | \ - PIN_AFIO_AF(5, 5) | \ - PIN_AFIO_AF(6, 5) | \ - PIN_AFIO_AF(7, 5)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(10, 10) | \ - PIN_AFIO_AF(11, 10) | \ - PIN_AFIO_AF(12, 10) | \ - PIN_AFIO_AF(13, 0) | \ - PIN_AFIO_AF(14, 0)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_LRCK, 6) | \ + PIN_AFIO_AF(GPIOA_SPC, 5) | \ + PIN_AFIO_AF(GPIOA_SDO, 5) | \ + PIN_AFIO_AF(GPIOA_SDI, 5)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0)) /* * Port B setup. @@ -175,7 +175,6 @@ * PB3 - GPIOB_SWO (alternate 0). * PB6 - GPIOB_SCL (alternate 4). * PB9 - GPIOB_SDA (alternate 4). - * PB10 - GPIOB_SCK (alternate 5). */ #define VAL_GPIOB_MODER (PIN_MODE_INPUT(0) | \ PIN_MODE_INPUT(1) | \ @@ -187,7 +186,7 @@ PIN_MODE_INPUT(7) | \ PIN_MODE_INPUT(8) | \ PIN_MODE_ALTERNATE(GPIOB_SDA) | \ - PIN_MODE_ALTERNATE(GPIOB_SCK) | \ + PIN_MODE_INPUT(10) | \ PIN_MODE_INPUT(11) | \ PIN_MODE_INPUT(12) | \ PIN_MODE_INPUT(13) | \ @@ -206,23 +205,21 @@ PIN_PUDR_PULLUP(7) | \ PIN_PUDR_PULLUP(8) | \ PIN_PUDR_FLOATING(GPIOB_SDA) | \ - PIN_PUDR_FLOATING(GPIOB_SCK) | \ + PIN_PUDR_PULLUP(10) | \ PIN_PUDR_PULLUP(11) | \ PIN_PUDR_PULLUP(12) | \ PIN_PUDR_PULLUP(13) | \ PIN_PUDR_PULLUP(14) | \ PIN_PUDR_PULLUP(15)) #define VAL_GPIOB_ODR 0xFFFFFFFF -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(3, 0) | \ - PIN_AFIO_AF(6, 4)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(9, 4) | \ - PIN_AFIO_AF(10, 5)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_SWO, 0) | \ + PIN_AFIO_AF(GPIOB_SCL, 4)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_SDA, 4)) /* * Port C setup. * All input with pull-up except: * PC0 - GPIOC_OTG_FS_POWER_ON (output push-pull). - * PC3 - GPIOC_DOUT (alternate 5). * PC7 - GPIOC_MCLK (alternate 6). * PC10 - GPIOC_SCLK (alternate 6). * PC12 - GPIOC_SDIN (alternate 6). @@ -230,7 +227,7 @@ #define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ PIN_MODE_INPUT(1) | \ PIN_MODE_INPUT(2) | \ - PIN_MODE_ALTERNATE(GPIOC_DOUT) | \ + PIN_MODE_INPUT(3) | \ PIN_MODE_INPUT(4) | \ PIN_MODE_INPUT(5) | \ PIN_MODE_INPUT(6) | \ @@ -248,7 +245,7 @@ #define VAL_GPIOC_PUPDR (PIN_PUDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ PIN_PUDR_PULLUP(1) | \ PIN_PUDR_PULLUP(2) | \ - PIN_PUDR_FLOATING(GPIOC_DOUT) | \ + PIN_PUDR_PULLUP(3) | \ PIN_PUDR_PULLUP(4) | \ PIN_PUDR_PULLUP(5) | \ PIN_PUDR_PULLUP(6) | \ @@ -262,10 +259,9 @@ PIN_PUDR_PULLUP(14) | \ PIN_PUDR_PULLUP(15)) #define VAL_GPIOC_ODR 0xFFFFFFFF -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(3, 5) | \ - PIN_AFIO_AF(7, 6)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(10, 6) | \ - PIN_AFIO_AF(12, 6)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_MCLK, 6)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SCLK, 6) | \ + PIN_AFIO_AF(GPIOC_SDIN, 6)) /* * Port D setup. diff --git a/testhal/STM32F4xx/SPI/main.c b/testhal/STM32F4xx/SPI/main.c index d12da4215..2414cc559 100644 --- a/testhal/STM32F4xx/SPI/main.c +++ b/testhal/STM32F4xx/SPI/main.c @@ -56,14 +56,14 @@ static msg_t spi_thread_1(void *p) { (void)p; chRegSetThreadName("SPI thread 1"); while (TRUE) { - spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ palSetPad(GPIOD, GPIOD_LED5); /* LED ON. */ - spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ - spiSelect(&SPID1); /* Slave Select assertion. */ - spiExchange(&SPID1, 512, + spiStart(&SPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, txbuf, rxbuf); /* Atomic transfer operations. */ - spiUnselect(&SPID1); /* Slave Select de-assertion. */ - spiReleaseBus(&SPID1); /* Ownership release. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ } return 0; } @@ -77,14 +77,14 @@ static msg_t spi_thread_2(void *p) { (void)p; chRegSetThreadName("SPI thread 2"); while (TRUE) { - spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + spiAcquireBus(&SPID2); /* Acquire ownership of the bus. */ palClearPad(GPIOD, GPIOD_LED5); /* LED OFF. */ - spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ - spiSelect(&SPID1); /* Slave Select assertion. */ - spiExchange(&SPID1, 512, + spiStart(&SPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID2); /* Slave Select assertion. */ + spiExchange(&SPID2, 512, txbuf, rxbuf); /* Atomic transfer operations. */ - spiUnselect(&SPID1); /* Slave Select de-assertion. */ - spiReleaseBus(&SPID1); /* Ownership release. */ + spiUnselect(&SPID2); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID2); /* Ownership release. */ } return 0; } @@ -106,16 +106,16 @@ int main(void) { chSysInit(); /* - * SPI1 I/O pins setup. + * SPI2 I/O pins setup. */ - palSetPadMode(GPIOA, 5, PAL_MODE_ALTERNATE(5) | - PAL_STM32_OSPEED_HIGHEST); /* SCK. */ - palSetPadMode(GPIOA, 6, PAL_MODE_ALTERNATE(5) | - PAL_STM32_OSPEED_HIGHEST); /* MISO.*/ - palSetPadMode(GPIOA, 7, PAL_MODE_ALTERNATE(5) | - PAL_STM32_OSPEED_HIGHEST); /* MOSI.*/ + palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New SCK. */ + palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MISO. */ + palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* New MOSI. */ palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | - PAL_STM32_OSPEED_HIGHEST); + PAL_STM32_OSPEED_HIGHEST); /* New CS. */ palSetPad(GPIOB, 12); /* diff --git a/testhal/STM32F4xx/SPI/readme.txt b/testhal/STM32F4xx/SPI/readme.txt index c1914bc43..2a7751877 100644 --- a/testhal/STM32F4xx/SPI/readme.txt +++ b/testhal/STM32F4xx/SPI/readme.txt @@ -8,7 +8,11 @@ The demo runs on an ST STM32F4-Discovery board. ** The Demo ** -The application demonstrates the use of the STM32 SPI driver. +The application demonstrates the use of the STM32F4xx SPI driver. + +** Board Setup ** + +- Connect PB14 and PB15 together for SPI loop-back. ** Build Procedure ** -- cgit v1.2.3 From 1e80eff6a8167b3f0d8a960fec96d922107a8be7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 12 Nov 2011 10:16:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3489 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F4xx/SPI/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testhal/STM32F4xx/SPI/main.c b/testhal/STM32F4xx/SPI/main.c index 2414cc559..4a2b1ad3f 100644 --- a/testhal/STM32F4xx/SPI/main.c +++ b/testhal/STM32F4xx/SPI/main.c @@ -22,7 +22,7 @@ #include "hal.h" /* - * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). + * Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first). */ static const SPIConfig hs_spicfg = { NULL, @@ -32,7 +32,7 @@ static const SPIConfig hs_spicfg = { }; /* - * Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first). + * Low speed SPI configuration (328.125KHz, CPHA=0, CPOL=0, MSb first). */ static const SPIConfig ls_spicfg = { NULL, -- cgit v1.2.3 From ec1bf1b741390d7b6128382971b504a3ee9b7111 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 13 Nov 2011 10:55:33 +0000 Subject: STM32F4xx SPI driver working. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3490 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/spi_lld.c | 12 +++++++++++- os/hal/platforms/STM32F1xx/stm32_dma.h | 1 + os/hal/platforms/STM32F4xx/stm32_dma.h | 2 +- os/hal/platforms/STM32L1xx/stm32_dma.h | 1 + 4 files changed, 14 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index 1511547d5..2610031b6 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -106,9 +106,11 @@ static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { (void)flags; #endif - /* Stop everything.*/ + /* Stop everything. The status of the TX DMA is cleared here because its + handler is only invoked in case of error.*/ dmaStreamDisable(spip->dmatx); dmaStreamDisable(spip->dmarx); + dmaStreamClearInterrupt(spip->dmatx); /* Portable SPI ISR code defined in the high level driver, note, it is a macro.*/ @@ -161,10 +163,12 @@ void spi_lld_init(void) { STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif @@ -177,10 +181,12 @@ void spi_lld_init(void) { STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif @@ -193,10 +199,12 @@ void spi_lld_init(void) { STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) | STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; #endif } @@ -360,6 +368,7 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) { dmaStreamSetMemory0(spip->dmarx, &dummyrx); dmaStreamSetTransactionSize(spip->dmarx, n); dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN); + dmaStreamSetMemory0(spip->dmatx, &dummytx); dmaStreamSetTransactionSize(spip->dmatx, n); dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN); @@ -411,6 +420,7 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { dmaStreamSetMemory0(spip->dmarx, &dummyrx); dmaStreamSetTransactionSize(spip->dmarx, n); dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN); + dmaStreamSetMemory0(spip->dmatx, txbuf); dmaStreamSetTransactionSize(spip->dmatx, n); dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC | diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h index 4469bef67..fdfd0bc7b 100644 --- a/os/hal/platforms/STM32F1xx/stm32_dma.h +++ b/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -153,6 +153,7 @@ * @name CR register constants only found in enhanced DMA * @{ */ +#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ #define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ #define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ /** @} */ diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h index d07a9dbe9..4b3302f39 100644 --- a/os/hal/platforms/STM32F4xx/stm32_dma.h +++ b/os/hal/platforms/STM32F4xx/stm32_dma.h @@ -171,7 +171,7 @@ /** @} */ /** - * @name FCR register constants only found in STM32F2xx + * @name FCR register constants only found in STM32F2xx/STM32F4xx * @{ */ #define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h index e22d99f2b..0d80a39e7 100644 --- a/os/hal/platforms/STM32L1xx/stm32_dma.h +++ b/os/hal/platforms/STM32L1xx/stm32_dma.h @@ -144,6 +144,7 @@ * @name CR register constants only found in enhanced DMA * @{ */ +#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */ #define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ #define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ /** @} */ -- cgit v1.2.3 From e1f35463ed863f65de82314d0ac06118d095fa7e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 13 Nov 2011 11:14:10 +0000 Subject: Cortex-M4 officially supported. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3491 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/reports/STM32F407-168-GCC.txt | 6 +++--- os/ports/GCC/ARMCMx/LPC11xx/cmparams.h | 5 +++++ os/ports/GCC/ARMCMx/LPC13xx/cmparams.h | 5 +++++ os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h | 5 +++++ os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h | 7 ++++++- os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h | 5 +++++ os/ports/GCC/ARMCMx/chcore.h | 5 +++-- os/ports/IAR/ARMCMx/LPC11xx/cmparams.h | 5 +++++ os/ports/IAR/ARMCMx/LPC13xx/cmparams.h | 5 +++++ os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h | 5 +++++ os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h | 5 +++++ os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h | 5 +++++ os/ports/IAR/ARMCMx/chcore.h | 7 ++++--- os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h | 5 +++++ os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h | 5 +++++ os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h | 5 +++++ os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h | 5 +++++ os/ports/RVCT/ARMCMx/chcore.h | 5 +++-- readme.txt | 2 ++ 19 files changed, 86 insertions(+), 11 deletions(-) diff --git a/docs/reports/STM32F407-168-GCC.txt b/docs/reports/STM32F407-168-GCC.txt index 9b2702146..7069e8d0e 100644 --- a/docs/reports/STM32F407-168-GCC.txt +++ b/docs/reports/STM32F407-168-GCC.txt @@ -6,10 +6,10 @@ Settings: SYSCLK=168, ACR=0x705 (5 wait states) *** ChibiOS/RT test suite *** *** Kernel: 2.3.4unstable -*** Compiled: Nov 6 2011 - 12:43:29 +*** Compiled: Nov 13 2011 - 12:07:02 *** Compiler: GCC 4.6.0 -*** Architecture: ARMv7-M -*** Core Variant: Cortex-M3 +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4 *** Port Info: Advanced kernel mode *** Platform: STM32F4 High Performance & DSP *** Test Board: ST STM32F4-Discovery diff --git a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h index 4016e6aa1..89520b96d 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU FALSE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h index ee49e5de9..2da699460 100644 --- a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU FALSE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h index 02d07e73d..a61698008 100644 --- a/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/STM32F1xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU FALSE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h index 96ea09ff8..338fd5363 100644 --- a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h @@ -35,7 +35,7 @@ /** * @brief Cortex core model. */ -#define CORTEX_MODEL CORTEX_M3 +#define CORTEX_MODEL CORTEX_M4 /** * @brief Systick unit presence. @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU TRUE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h index e21f9cdd2..c545b07fa 100644 --- a/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/STM32L1xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU TRUE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h index 944094925..9db7c816a 100644 --- a/os/ports/GCC/ARMCMx/chcore.h +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -50,8 +50,9 @@ #include "cmparams.h" /* Cortex model check, only M0 and M3 supported right now.*/ -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) -#elif (CORTEX_MODEL == CORTEX_M1) || (CORTEX_MODEL == CORTEX_M4) +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ + (CORTEX_MODEL == CORTEX_M4) +#elif (CORTEX_MODEL == CORTEX_M1) #warning "untested Cortex-M model" #else #error "unknown or unsupported Cortex-M model" diff --git a/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h b/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h index 2b66fbf4a..284d6cecf 100644 --- a/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h +++ b/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU FALSE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h b/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h index 1e970e72a..439768f84 100644 --- a/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h +++ b/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU FALSE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h index 8f9795822..74a7fe232 100644 --- a/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h +++ b/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU FALSE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h index 733c952d5..de175091d 100644 --- a/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h +++ b/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU TRUE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h index e4012ef82..491417957 100644 --- a/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h +++ b/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU TRUE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/IAR/ARMCMx/chcore.h b/os/ports/IAR/ARMCMx/chcore.h index c3e91cc02..9572a48c8 100644 --- a/os/ports/IAR/ARMCMx/chcore.h +++ b/os/ports/IAR/ARMCMx/chcore.h @@ -50,9 +50,10 @@ #include "cmparams.h" /* Cortex model check, only M0 and M3 supported right now.*/ -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) -#elif (CORTEX_MODEL == CORTEX_M1) || (CORTEX_MODEL == CORTEX_M4) -#error "untested Cortex-M model, manually remove this check in chcore.h" +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ + (CORTEX_MODEL == CORTEX_M4) +#elif (CORTEX_MODEL == CORTEX_M1) +#error "untested Cortex-M model" #else #error "unknown or unsupported Cortex-M model" #endif diff --git a/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h b/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h index 7289af9e7..63f22c0a0 100644 --- a/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h +++ b/os/ports/RVCT/ARMCMx/LPC11xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU FALSE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h b/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h index e484d7aad..46af8fc4e 100644 --- a/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h +++ b/os/ports/RVCT/ARMCMx/LPC13xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU FALSE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h b/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h index 2bd7715a4..67f0fb969 100644 --- a/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h +++ b/os/ports/RVCT/ARMCMx/STM32F1xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU FALSE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h b/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h index b43bbd92a..a6617e33d 100644 --- a/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h +++ b/os/ports/RVCT/ARMCMx/STM32L1xx/cmparams.h @@ -47,6 +47,11 @@ */ #define CORTEX_HAS_MPU TRUE +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + /** * @brief Number of bits in priority masks. */ diff --git a/os/ports/RVCT/ARMCMx/chcore.h b/os/ports/RVCT/ARMCMx/chcore.h index 7c4e82613..08b3a2ccb 100644 --- a/os/ports/RVCT/ARMCMx/chcore.h +++ b/os/ports/RVCT/ARMCMx/chcore.h @@ -50,8 +50,9 @@ #include "cmparams.h" /* Cortex model check, only M0 and M3 supported right now.*/ -#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) -#elif (CORTEX_MODEL == CORTEX_M1) || (CORTEX_MODEL == CORTEX_M4) +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \ + (CORTEX_MODEL == CORTEX_M4) +#elif (CORTEX_MODEL == CORTEX_M1) #warning "untested Cortex-M model" #else #error "unknown or unsupported Cortex-M model" diff --git a/readme.txt b/readme.txt index 842946621..3adb886b9 100644 --- a/readme.txt +++ b/readme.txt @@ -84,6 +84,8 @@ (backported to 2.2.8). - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). +- NEW: Removed the warning about the "untested M4 platform", now it is + tested and officially supported. - NEW: Reorganized the STM32F1xx hal_lld_xxx.h files in order to distribute the capability macros into the appropriate file (previously those were all in the common hal_lld.h). -- cgit v1.2.3 From 375244fdc49a7dfbe592914bc28fb24312386771 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 14 Nov 2011 17:59:02 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3492 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/ports/GCC/ARMCMx/chcore_v7m.h | 8 ++++++++ os/ports/IAR/ARMCMx/chcore_v7m.h | 8 ++++++++ os/ports/RVCT/ARMCMx/chcore_v7m.h | 8 ++++++++ readme.txt | 3 +++ 4 files changed, 27 insertions(+) diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index a2427c27e..96149cae9 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -66,6 +66,13 @@ #endif #endif +/** + * @brief NVIC VTOR initialization expression. + */ +#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) +#define CORTEX_VTOR_INIT 0x00000000 +#endif + /*===========================================================================*/ /* Port derived parameters. */ /*===========================================================================*/ @@ -192,6 +199,7 @@ struct intctx { * @brief Port-related initialization code. */ #define port_init() { \ + SCB_VTOR = CORTEX_VTOR_INIT; \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.h b/os/ports/IAR/ARMCMx/chcore_v7m.h index ee077749c..8ebd45bda 100644 --- a/os/ports/IAR/ARMCMx/chcore_v7m.h +++ b/os/ports/IAR/ARMCMx/chcore_v7m.h @@ -66,6 +66,13 @@ #endif #endif +/** + * @brief NVIC VTOR initialization expression. + */ +#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) +#define CORTEX_VTOR_INIT 0x00000000 +#endif + /*===========================================================================*/ /* Port derived parameters. */ /*===========================================================================*/ @@ -192,6 +199,7 @@ struct intctx { * @brief Port-related initialization code. */ #define port_init() { \ + SCB_VTOR = CORTEX_VTOR_INIT; \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h index ef04fa15e..b4181d517 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v7m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -66,6 +66,13 @@ #endif #endif +/** + * @brief NVIC VTOR initialization expression. + */ +#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__) +#define CORTEX_VTOR_INIT 0x00000000 +#endif + /*===========================================================================*/ /* Port derived parameters. */ /*===========================================================================*/ @@ -192,6 +199,7 @@ struct intctx { * @brief Port-related initialization code. */ #define port_init() { \ + SCB_VTOR = CORTEX_VTOR_INIT; \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ diff --git a/readme.txt b/readme.txt index 3adb886b9..1c1bc7808 100644 --- a/readme.txt +++ b/readme.txt @@ -84,6 +84,9 @@ (backported to 2.2.8). - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). +- NEW: Added initialization of the NVIC VTOR register to all Cortex-Mx (v7M) + ports. Also added a port option CORTEX_VTOR_INIT to enforce a different + default value into the register. - NEW: Removed the warning about the "untested M4 platform", now it is tested and officially supported. - NEW: Reorganized the STM32F1xx hal_lld_xxx.h files in order to distribute -- cgit v1.2.3 From dfab65f9f80d9a20e8e3b6bc9014ad21cf5b1bdc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 14 Nov 2011 19:13:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3493 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM4-STM32F407-DISCOVERY/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/main.c b/demos/ARMCM4-STM32F407-DISCOVERY/main.c index cc12871d4..ab126427b 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/main.c +++ b/demos/ARMCM4-STM32F407-DISCOVERY/main.c @@ -201,7 +201,7 @@ int main(void) { /* * Activates the serial driver 1 using the driver default configuration. - * PA2(TX) and PA3(RX) are routed to USART1. + * PA2(TX) and PA3(RX) are routed to USART2. */ sdStart(&SD2, NULL); palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); -- cgit v1.2.3 From d4187a3454cbfb1735d286d4acf23b062b1febdf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 15 Nov 2011 19:06:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3494 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/hal_lld.h | 9 + os/hal/platforms/STM32F4xx/platform.mk | 1 + testhal/STM32F1xx/IRQ_STORM/main.c | 12 +- testhal/STM32F1xx/IRQ_STORM/readme.txt | 8 +- testhal/STM32F4xx/GPT/Makefile | 207 +++++++++++++ testhal/STM32F4xx/GPT/chconf.h | 535 +++++++++++++++++++++++++++++++++ testhal/STM32F4xx/GPT/halconf.h | 335 +++++++++++++++++++++ testhal/STM32F4xx/GPT/main.c | 98 ++++++ testhal/STM32F4xx/GPT/mcuconf.h | 197 ++++++++++++ testhal/STM32F4xx/GPT/readme.txt | 30 ++ testhal/STM32F4xx/IRQ_STORM/Makefile | 207 +++++++++++++ testhal/STM32F4xx/IRQ_STORM/chconf.h | 535 +++++++++++++++++++++++++++++++++ testhal/STM32F4xx/IRQ_STORM/halconf.h | 335 +++++++++++++++++++++ testhal/STM32F4xx/IRQ_STORM/main.c | 332 ++++++++++++++++++++ testhal/STM32F4xx/IRQ_STORM/mcuconf.h | 197 ++++++++++++ testhal/STM32F4xx/IRQ_STORM/readme.txt | 31 ++ testhal/STM32L1xx/GPT/main.c | 2 +- testhal/STM32L1xx/IRQ_STORM/main.c | 12 +- testhal/STM32L1xx/IRQ_STORM/mcuconf.h | 2 +- testhal/STM32L1xx/IRQ_STORM/readme.txt | 6 +- 20 files changed, 3078 insertions(+), 13 deletions(-) create mode 100644 testhal/STM32F4xx/GPT/Makefile create mode 100644 testhal/STM32F4xx/GPT/chconf.h create mode 100644 testhal/STM32F4xx/GPT/halconf.h create mode 100644 testhal/STM32F4xx/GPT/main.c create mode 100644 testhal/STM32F4xx/GPT/mcuconf.h create mode 100644 testhal/STM32F4xx/GPT/readme.txt create mode 100644 testhal/STM32F4xx/IRQ_STORM/Makefile create mode 100644 testhal/STM32F4xx/IRQ_STORM/chconf.h create mode 100644 testhal/STM32F4xx/IRQ_STORM/halconf.h create mode 100644 testhal/STM32F4xx/IRQ_STORM/main.c create mode 100644 testhal/STM32F4xx/IRQ_STORM/mcuconf.h create mode 100644 testhal/STM32F4xx/IRQ_STORM/readme.txt diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index fc40b51a9..8bcde1083 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -1238,6 +1238,15 @@ #define STM32_FLASHBITS 0x00000007 #endif +/* There are differences in vector names in the various sub-families, + normalizing.*/ +#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn +#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn +#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn +#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn +#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk index 6b7df146b..ca66471d5 100644 --- a/os/hal/platforms/STM32F4xx/platform.mk +++ b/os/hal/platforms/STM32F4xx/platform.mk @@ -1,6 +1,7 @@ # List of all the STM32L1xx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c diff --git a/testhal/STM32F1xx/IRQ_STORM/main.c b/testhal/STM32F1xx/IRQ_STORM/main.c index 7dcc62d61..fd963553c 100644 --- a/testhal/STM32F1xx/IRQ_STORM/main.c +++ b/testhal/STM32F1xx/IRQ_STORM/main.c @@ -237,9 +237,11 @@ int main(void) { println("***"); print("*** Kernel: "); println(CH_KERNEL_VERSION); -#ifdef __GNUC__ - print("*** GCC Version: "); - println(__VERSION__); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); #endif print("*** Architecture: "); println(CH_ARCHITECTURE_NAME); @@ -247,6 +249,10 @@ int main(void) { print("*** Core Variant: "); println(CH_CORE_VARIANT_NAME); #endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif #ifdef PLATFORM_NAME print("*** Platform: "); println(PLATFORM_NAME); diff --git a/testhal/STM32F1xx/IRQ_STORM/readme.txt b/testhal/STM32F1xx/IRQ_STORM/readme.txt index d06bff965..94dfa4cd6 100644 --- a/testhal/STM32F1xx/IRQ_STORM/readme.txt +++ b/testhal/STM32F1xx/IRQ_STORM/readme.txt @@ -8,8 +8,12 @@ The demo runs on an Olimex STM32-P103 board. ** The Demo ** -The application demonstrates the use of the STM32 GPT, PAL and Serial drivers -in order to implement a system stress demo. +The application demonstrates the use of the STM32F1xx GPT, PAL and Serial +drivers in order to implement a system stress demo. + +** Board Setup ** + +None. ** Build Procedure ** diff --git a/testhal/STM32F4xx/GPT/Makefile b/testhal/STM32F4xx/GPT/Makefile new file mode 100644 index 000000000..9456d0488 --- /dev/null +++ b/testhal/STM32F4xx/GPT/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/GPT/chconf.h b/testhal/STM32F4xx/GPT/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F4xx/GPT/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/GPT/halconf.h b/testhal/STM32F4xx/GPT/halconf.h new file mode 100644 index 000000000..3be209376 --- /dev/null +++ b/testhal/STM32F4xx/GPT/halconf.h @@ -0,0 +1,335 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/GPT/main.c b/testhal/STM32F4xx/GPT/main.c new file mode 100644 index 000000000..be73f2a99 --- /dev/null +++ b/testhal/STM32F4xx/GPT/main.c @@ -0,0 +1,98 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + + (void)gptp; + palSetPad(GPIOD, GPIOD_LED5); + chSysLockFromIsr(); + gptStartOneShotI(&GPTD3, 1000); /* 0.1 second pulse.*/ + chSysUnlockFromIsr(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + + (void)gptp; + palClearPad(GPIOD, GPIOD_LED5); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 10000, /* 10KHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 10000, /* 10KHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the GPT drivers 2 and 3. + */ + gptStart(&GPTD2, &gpt2cfg); + gptPolledDelay(&GPTD2, 10); /* Small delay.*/ + gptStart(&GPTD3, &gpt3cfg); + gptPolledDelay(&GPTD3, 10); /* Small delay.*/ + + /* + * Normal main() thread activity, it changes the GPT1 period every + * five seconds. + */ + while (TRUE) { + palSetPad(GPIOD, GPIOD_LED4); + gptStartContinuous(&GPTD2, 5000); + chThdSleepMilliseconds(5000); + gptStopTimer(&GPTD2); + palClearPad(GPIOD, GPIOD_LED4); + gptStartContinuous(&GPTD2, 2500); + chThdSleepMilliseconds(5000); + gptStopTimer(&GPTD2); + } +} diff --git a/testhal/STM32F4xx/GPT/mcuconf.h b/testhal/STM32F4xx/GPT/mcuconf.h new file mode 100644 index 000000000..dec461caf --- /dev/null +++ b/testhal/STM32F4xx/GPT/mcuconf.h @@ -0,0 +1,197 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_HIGH +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2CSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 TRUE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 TRUE +#define STM32_GPT_USE_TIM8 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F4xx/GPT/readme.txt b/testhal/STM32F4xx/GPT/readme.txt new file mode 100644 index 000000000..347c8bf01 --- /dev/null +++ b/testhal/STM32F4xx/GPT/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - GPT driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx GPT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32F4xx/IRQ_STORM/Makefile b/testhal/STM32F4xx/IRQ_STORM/Makefile new file mode 100644 index 000000000..9456d0488 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/IRQ_STORM/chconf.h b/testhal/STM32F4xx/IRQ_STORM/chconf.h new file mode 100644 index 000000000..9dd831c96 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/IRQ_STORM/halconf.h b/testhal/STM32F4xx/IRQ_STORM/halconf.h new file mode 100644 index 000000000..f9a1b78f6 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/halconf.h @@ -0,0 +1,335 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/IRQ_STORM/main.c b/testhal/STM32F4xx/IRQ_STORM/main.c new file mode 100644 index 000000000..ef4ca4307 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/main.c @@ -0,0 +1,332 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Configurable settings. */ +/*===========================================================================*/ + +#ifndef RANDOMIZE +#define RANDOMIZE FALSE +#endif + +#ifndef ITERATIONS +#define ITERATIONS 100 +#endif + +#ifndef NUM_THREADS +#define NUM_THREADS 4 +#endif + +#ifndef MAILBOX_SIZE +#define MAILBOX_SIZE 4 +#endif + +/*===========================================================================*/ +/* Test related code. */ +/*===========================================================================*/ + +#define MSG_SEND_LEFT 0 +#define MSG_SEND_RIGHT 1 + +static bool_t saturated; + +/* + * Mailboxes and buffers. + */ +static Mailbox mb[NUM_THREADS]; +static msg_t b[NUM_THREADS][MAILBOX_SIZE]; + +/* + * Test worker threads. + */ +static WORKING_AREA(waWorkerThread[NUM_THREADS], 128); +static msg_t WorkerThread(void *arg) { + static volatile unsigned x = 0; + static unsigned cnt = 0; + unsigned me = (unsigned)arg; + unsigned target; + unsigned r; + msg_t msg; + + chRegSetThreadName("worker"); + + /* Work loop.*/ + while (TRUE) { + /* Waiting for a message.*/ + chMBFetch(&mb[me], &msg, TIME_INFINITE); + +#if RANDOMIZE + /* Pseudo-random delay.*/ + { + chSysLock(); + r = rand() & 15; + chSysUnlock(); + while (r--) + x++; + } +#else + /* Fixed delay.*/ + { + r = me >> 4; + while (r--) + x++; + } +#endif + + /* Deciding in which direction to re-send the message.*/ + if (msg == MSG_SEND_LEFT) + target = me - 1; + else + target = me + 1; + + if (target < NUM_THREADS) { + /* If this thread is not at the end of a chain re-sending the message, + note this check works because the variable target is unsigned.*/ + msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE); + if (msg != RDY_OK) + saturated = TRUE; + } + else { + /* Provides a visual feedback about the system.*/ + if (++cnt >= 500) { + cnt = 0; + palTogglePad(GPIOD, GPIOD_LED5); + } + } + } +} + +/* + * GPT2 callback. + */ +static void gpt2cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[0], MSG_SEND_RIGHT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT3 callback. + */ +static void gpt3cb(GPTDriver *gptp) { + msg_t msg; + + (void)gptp; + chSysLockFromIsr(); + msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT); + if (msg != RDY_OK) + saturated = TRUE; + chSysUnlockFromIsr(); +} + +/* + * GPT2 configuration. + */ +static const GPTConfig gpt2cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt2cb /* Timer callback.*/ +}; + +/* + * GPT3 configuration. + */ +static const GPTConfig gpt3cfg = { + 1000000, /* 1MHz timer clock.*/ + gpt3cb /* Timer callback.*/ +}; + + +/*===========================================================================*/ +/* Generic demo code. */ +/*===========================================================================*/ + +static void print(char *p) { + + while (*p) { + chIOPut(&SD2, *p++); + } +} + +static void println(char *p) { + + while (*p) { + chIOPut(&SD2, *p++); + } + chIOWriteTimeout(&SD2, (uint8_t *)"\r\n", 2, TIME_INFINITE); +} + +static void printn(uint32_t n) { + char buf[16], *p; + + if (!n) + chIOPut(&SD2, '0'); + else { + p = buf; + while (n) + *p++ = (n % 10) + '0', n /= 10; + while (p > buf) + chIOPut(&SD2, *--p); + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + gptcnt_t interval, threshold, worst; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepares the Serial driver 2 and GPT drivers 2 and 3. + */ + sdStart(&SD2, NULL); /* Default is 38400-8-N-1.*/ + palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); + gptStart(&GPTD2, &gpt2cfg); + gptStart(&GPTD3, &gpt3cfg); + + /* + * Initializes the mailboxes and creates the worker threads. + */ + for (i = 0; i < NUM_THREADS; i++) { + chMBInit(&mb[i], b[i], MAILBOX_SIZE); + chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i], + NORMALPRIO - 20, WorkerThread, (void *)i); + } + + /* + * Test procedure. + */ + println(""); + println("*** ChibiOS/RT IRQ-STORM long duration test"); + println("***"); + print("*** Kernel: "); + println(CH_KERNEL_VERSION); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); +#endif + print("*** Architecture: "); + println(CH_ARCHITECTURE_NAME); +#ifdef CH_CORE_VARIANT_NAME + print("*** Core Variant: "); + println(CH_CORE_VARIANT_NAME); +#endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif +#ifdef PLATFORM_NAME + print("*** Platform: "); + println(PLATFORM_NAME); +#endif +#ifdef BOARD_NAME + print("*** Test Board: "); + println(BOARD_NAME); +#endif + println("***"); + print("*** System Clock: "); + printn(STM32_SYSCLK); + println(""); + print("*** Iterations: "); + printn(ITERATIONS); + println(""); + print("*** Randomize: "); + printn(RANDOMIZE); + println(""); + print("*** Threads: "); + printn(NUM_THREADS); + println(""); + print("*** Mailbox size: "); + printn(MAILBOX_SIZE); + println(""); + + println(""); + worst = 0; + for (i = 1; i <= ITERATIONS; i++){ + print("Iteration "); + printn(i); + println(""); + saturated = FALSE; + threshold = 0; + for (interval = 2000; interval >= 20; interval -= interval / 10) { + gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/ + gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ + chThdSleepMilliseconds(1000); + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + if (!saturated) + print("."); + else { + print("#"); + if (threshold == 0) + threshold = interval; + } + } + /* Gives the worker threads a chance to empty the mailboxes before next + cycle.*/ + chThdSleepMilliseconds(20); + println(""); + print("Saturated at "); + printn(threshold); + println(" uS"); + println(""); + if (threshold > worst) + worst = threshold; + } + gptStopTimer(&GPTD2); + gptStopTimer(&GPTD3); + + print("Worst case at "); + printn(worst); + println(" uS"); + println(""); + println("Test Complete"); + + /* + * Normal main() thread activity, nothing in this test. + */ + while (TRUE) { + chThdSleepMilliseconds(5000); + } + return 0; +} diff --git a/testhal/STM32F4xx/IRQ_STORM/mcuconf.h b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h new file mode 100644 index 000000000..469fdfbc0 --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h @@ -0,0 +1,197 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_HIGH +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2CSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 6 +#define STM32_GPT_TIM3_IRQ_PRIORITY 10 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F4xx/IRQ_STORM/readme.txt b/testhal/STM32F4xx/IRQ_STORM/readme.txt new file mode 100644 index 000000000..836300e5c --- /dev/null +++ b/testhal/STM32F4xx/IRQ_STORM/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx GPT, PAL and Serial +drivers in order to implement a system stress demo. + +** Board Setup ** + +None. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/GPT/main.c b/testhal/STM32L1xx/GPT/main.c index 380d9650c..d63743628 100644 --- a/testhal/STM32L1xx/GPT/main.c +++ b/testhal/STM32L1xx/GPT/main.c @@ -29,7 +29,7 @@ static void gpt2cb(GPTDriver *gptp) { (void)gptp; palSetPad(GPIOB, GPIOB_LED4); chSysLockFromIsr(); - gptStartOneShotI(&GPTD3, 1000); /* 0.02 second pulse.*/ + gptStartOneShotI(&GPTD3, 1000); /* 0.1 second pulse.*/ chSysUnlockFromIsr(); } diff --git a/testhal/STM32L1xx/IRQ_STORM/main.c b/testhal/STM32L1xx/IRQ_STORM/main.c index d3c7a6521..f8e7b7bc5 100644 --- a/testhal/STM32L1xx/IRQ_STORM/main.c +++ b/testhal/STM32L1xx/IRQ_STORM/main.c @@ -239,9 +239,11 @@ int main(void) { println("***"); print("*** Kernel: "); println(CH_KERNEL_VERSION); -#ifdef __GNUC__ - print("*** GCC Version: "); - println(__VERSION__); + print("*** Compiled: "); + println(__DATE__ " - " __TIME__); +#ifdef CH_COMPILER_NAME + print("*** Compiler: "); + println(CH_COMPILER_NAME); #endif print("*** Architecture: "); println(CH_ARCHITECTURE_NAME); @@ -249,6 +251,10 @@ int main(void) { print("*** Core Variant: "); println(CH_CORE_VARIANT_NAME); #endif +#ifdef CH_PORT_INFO + print("*** Port Info: "); + println(CH_PORT_INFO); +#endif #ifdef PLATFORM_NAME print("*** Platform: "); println(PLATFORM_NAME); diff --git a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h index 4458168c1..b4e3ea258 100644 --- a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h @@ -90,7 +90,7 @@ #define STM32_GPT_USE_TIM1 FALSE #define STM32_GPT_USE_TIM2 TRUE #define STM32_GPT_USE_TIM3 TRUE -#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE #define STM32_GPT_USE_TIM8 FALSE #define STM32_GPT_TIM1_IRQ_PRIORITY 7 diff --git a/testhal/STM32L1xx/IRQ_STORM/readme.txt b/testhal/STM32L1xx/IRQ_STORM/readme.txt index f55cf8471..19af96363 100644 --- a/testhal/STM32L1xx/IRQ_STORM/readme.txt +++ b/testhal/STM32L1xx/IRQ_STORM/readme.txt @@ -8,12 +8,12 @@ The demo will on an STMicroelectronics STM32L-Discovery board. ** The Demo ** -The application demonstrates the use of the STM32L1xx PWM-ICU drivers. +The application demonstrates the use of the STM32L1xx GPT, PAL and Serial +drivers in order to implement a system stress demo. ** Board Setup ** -- Remove the LCD module. -- Connect PA15 and PC6 together. +None. ** Build Procedure ** -- cgit v1.2.3 From 57bf9c83de1453dad3e76d91054c12066c04fa18 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 15 Nov 2011 19:22:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3495 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F4xx/IRQ_STORM/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testhal/STM32F4xx/IRQ_STORM/main.c b/testhal/STM32F4xx/IRQ_STORM/main.c index ef4ca4307..338f102e0 100644 --- a/testhal/STM32F4xx/IRQ_STORM/main.c +++ b/testhal/STM32F4xx/IRQ_STORM/main.c @@ -217,8 +217,8 @@ int main(void) { * Prepares the Serial driver 2 and GPT drivers 2 and 3. */ sdStart(&SD2, NULL); /* Default is 38400-8-N-1.*/ - palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); - palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); gptStart(&GPTD2, &gpt2cfg); gptStart(&GPTD3, &gpt3cfg); -- cgit v1.2.3 From c99f165389491aa369e88d116985e03afe3fd587 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 15 Nov 2011 19:47:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3496 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F4xx/IRQ_STORM/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testhal/STM32F4xx/IRQ_STORM/main.c b/testhal/STM32F4xx/IRQ_STORM/main.c index 338f102e0..20dda712f 100644 --- a/testhal/STM32F4xx/IRQ_STORM/main.c +++ b/testhal/STM32F4xx/IRQ_STORM/main.c @@ -288,7 +288,7 @@ int main(void) { println(""); saturated = FALSE; threshold = 0; - for (interval = 2000; interval >= 20; interval -= interval / 10) { + for (interval = 2000; interval >= 10; interval -= interval / 10) { gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/ gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/ chThdSleepMilliseconds(1000); -- cgit v1.2.3 From 5bb68f6827e03e5b343c66f1236d84f73bc07df9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 16 Nov 2011 17:42:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3497 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/hal_lld.h | 11 + os/hal/platforms/STM32F4xx/platform.mk | 5 + testhal/STM32F4xx/ADC/Makefile | 207 +++++++++++++ testhal/STM32F4xx/ADC/chconf.h | 535 +++++++++++++++++++++++++++++++++ testhal/STM32F4xx/ADC/halconf.h | 335 +++++++++++++++++++++ testhal/STM32F4xx/ADC/main.c | 165 ++++++++++ testhal/STM32F4xx/ADC/mcuconf.h | 208 +++++++++++++ testhal/STM32F4xx/ADC/readme.txt | 30 ++ 8 files changed, 1496 insertions(+) create mode 100644 testhal/STM32F4xx/ADC/Makefile create mode 100644 testhal/STM32F4xx/ADC/chconf.h create mode 100644 testhal/STM32F4xx/ADC/halconf.h create mode 100644 testhal/STM32F4xx/ADC/main.c create mode 100644 testhal/STM32F4xx/ADC/mcuconf.h create mode 100644 testhal/STM32F4xx/ADC/readme.txt diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 8bcde1083..11bdfedd6 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -251,8 +251,19 @@ */ /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + #define STM32_HAS_ADC2 TRUE +#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC2_DMA_CHN 0x00001100 + #define STM32_HAS_ADC3 TRUE +#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ + STM32_DMA_STREAM_ID_MSK(2, 1)) +#define STM32_ADC3_DMA_CHN 0x00000022 /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk index ca66471d5..1b9ca04dc 100644 --- a/os/hal/platforms/STM32F4xx/platform.mk +++ b/os/hal/platforms/STM32F4xx/platform.mk @@ -1,9 +1,14 @@ # List of all the STM32L1xx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c # Required include directories diff --git a/testhal/STM32F4xx/ADC/Makefile b/testhal/STM32F4xx/ADC/Makefile new file mode 100644 index 000000000..9456d0488 --- /dev/null +++ b/testhal/STM32F4xx/ADC/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/ADC/chconf.h b/testhal/STM32F4xx/ADC/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F4xx/ADC/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/ADC/halconf.h b/testhal/STM32F4xx/ADC/halconf.h new file mode 100644 index 000000000..b1de4bf39 --- /dev/null +++ b/testhal/STM32F4xx/ADC/halconf.h @@ -0,0 +1,335 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/ADC/main.c b/testhal/STM32F4xx/ADC/main.c new file mode 100644 index 000000000..b9890100e --- /dev/null +++ b/testhal/STM32F4xx/ADC/main.c @@ -0,0 +1,165 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +#define ADC_GRP1_NUM_CHANNELS 1 +#define ADC_GRP1_BUF_DEPTH 8 + +#define ADC_GRP2_NUM_CHANNELS 8 +#define ADC_GRP2_BUF_DEPTH 16 + +static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; +static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH]; + +/* + * ADC streaming callback. + */ +size_t nx = 0, ny = 0; +static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; + if (samples2 == buffer) { + nx += n; + } + else { + ny += n; + } +} + +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { + + (void)adcp; + (void)err; +} + +/* + * ADC conversion group. + * Mode: Linear buffer, 16 samples of 8 channels, SW triggered. + * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg1 = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + NULL, + adcerrorcallback, + 0, 0, /* CR1, CR2 */ + 0, /* SMPR1 */ + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_4), + 0, /* SMPR3 */ + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, 0, 0, /* SQR2, SQR3, SQR4 */ + ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) +}; + +/* + * ADC conversion group. + * Mode: Continuous, 16 samples of 8 channels, SW triggered. + * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + */ +static const ADCConversionGroup adcgrpcfg2 = { + TRUE, + ADC_GRP2_NUM_CHANNELS, + adccallback, + adcerrorcallback, + 0, 0, /* CR1, CR2 */ + 0, /* SMPR1 */ + ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192) | + ADC_SMPR2_SMP_VREF(ADC_SAMPLE_192), + 0, /* SMPR3 */ + ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), + 0, 0, /* SQR2, SQR3 */ + ADC_SQR4_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR4_SQ7_N(ADC_CHANNEL_VREFINT), + ADC_SQR5_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ5_N(ADC_CHANNEL_IN10) | + ADC_SQR5_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ3_N(ADC_CHANNEL_IN10) | + ADC_SQR5_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) +}; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (TRUE) { + palSetPad(GPIOB, GPIOB_LED4); + chThdSleepMilliseconds(500); + palClearPad(GPIOB, GPIOB_LED4); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Setting up analog inputs used by the demo. + */ + palSetGroupMode(GPIOC, PAL_PORT_BIT(0) | PAL_PORT_BIT(1), + PAL_MODE_INPUT_ANALOG); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Activates the ADC1 driver and the thermal sensor. + */ + adcStart(&ADCD1, NULL); + adcSTM32EnableTSVREFE(); + + /* + * Linear conversion. + */ + adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH); + chThdSleepMilliseconds(1000); + + /* + * Starts an ADC continuous conversion. + */ + adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + if (palReadPad(GPIOA, GPIOA_BUTTON)) { + adcStopConversion(&ADCD1); + adcSTM32DisableTSVREFE(); + } + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F4xx/ADC/mcuconf.h b/testhal/STM32F4xx/ADC/mcuconf.h new file mode 100644 index 000000000..acb1183ed --- /dev/null +++ b/testhal/STM32F4xx/ADC/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_HIGH +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2CSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 TRUE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 TRUE +#define STM32_GPT_USE_TIM8 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F4xx/ADC/readme.txt b/testhal/STM32F4xx/ADC/readme.txt new file mode 100644 index 000000000..24ff92f25 --- /dev/null +++ b/testhal/STM32F4xx/ADC/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - ADC driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx ADC driver. + +** Board Setup ** + +- Connect PC0 to 3.3V and PC1 to GND for analog measurements. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From 5ed2f28ec0e5031ab79b50f6c61964273023567e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 16 Nov 2011 17:45:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3498 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/adc_lld.c | 378 +++++++++++++++++++++++ os/hal/platforms/STM32F4xx/adc_lld.h | 567 +++++++++++++++++++++++++++++++++++ 2 files changed, 945 insertions(+) create mode 100644 os/hal/platforms/STM32F4xx/adc_lld.c create mode 100644 os/hal/platforms/STM32F4xx/adc_lld.h diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c new file mode 100644 index 000000000..f78c7ac0f --- /dev/null +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -0,0 +1,378 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F4xx/adc_lld.c + * @brief STM32F4xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define ADC1_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN) + +#define ADC2_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN) + +#define ADC3_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/** @brief ADC2 driver identifier.*/ +#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__) +ADCDriver ADCD2; +#endif + +/** @brief ADC3 driver identifier.*/ +#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__) +ADCDriver ADCD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & STM32_DMA_ISR_TEIF) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \ + defined(__DOXYGEN__) +/** + * @brief ADC interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { + uint32_t sr; + + CH_IRQ_PROLOGUE(); + +#if STM32_ADC_USE_ADC1 + sr = ADC1->SR; + ADC1->SR = 0; + if (sr & ADC_SR_OVR) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC2 + sr = ADC2->SR; + ADC2->SR = 0; + if (sr & ADC_SR_OVR) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC2 */ + +#if STM32_ADC_USE_ADC3 + sr = ADC3->SR; + ADC3->SR = 0; + if (sr & ADC_SR_OVR) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ +#endif /* STM32_ADC_USE_ADC3 */ + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + + ADC->CCR = STM32_ADC_ADCPRE; + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); + ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; +#endif + +#if STM32_ADC_USE_ADC2 + /* Driver initialization.*/ + adcObjectInit(&ADCD2); + ADCD1.adc = ADC2; + ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); + ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; +#endif + +#if STM32_ADC_USE_ADC3 + /* Driver initialization.*/ + adcObjectInit(&ADCD3); + ADCD1.adc = ADC3; + ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); + ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; +#endif + + /* The shared vector is initialized on driver initialization and never + disabled.*/ + NVICEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_ADC2 + if (&ADCD2 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC2_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR); + rccEnableADC2(FALSE); + } +#endif /* STM32_ADC_USE_ADC2 */ + +#if STM32_ADC_USE_ADC3 + if (&ADCD3 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC3_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR); + rccEnableADC3(FALSE); + } +#endif /* STM32_ADC_USE_ADC3 */ + + /* ADC initial setup, just resetting control registers in this case.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) + rccDisableADC1(FALSE); +#endif + +#if STM32_ADC_USE_ADC2 + if (&ADCD2 == adcp) + rccDisableADC2(FALSE); +#endif + +#if STM32_ADC_USE_ADC3 + if (&ADCD3 == adcp) + rccDisableADC3(FALSE); +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + } + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; + adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS | + ADC_CR2_ADON; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + /* Must wait the ADC to be ready for conversion, see 9.3.6 "Timing diagram" + in the Reference Manual.*/ + while ((adcp->adc->SR & ADC_SR_ADONS) == 0) + ; + /* ADC start by raising ADC_CR2_SWSTART.*/ + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_CONT | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; +} + +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableTSVREFE(void) { + + ADC->CCR |= ADC_CCR_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableTSVREFE(void) { + + ADC->CCR &= ~ADC_CCR_TSVREFE; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h new file mode 100644 index 000000000..0e846f50a --- /dev/null +++ b/os/hal/platforms/STM32F4xx/adc_lld.h @@ -0,0 +1,567 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F4xx/adc_lld.h + * @brief STM32F4xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_ADCCLK_MIN 600000 + +/** + * @brief Maximum HSE clock frequency. + * @note This value is arbitrary defined, the current datasheet does not + * define a maximum value (it is TBD). A value of 36MHz is mentioned + * but without relationship to VDD ranges. + */ +#define STM32_ADCCLK_MAX 42000000 +/** @} */ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV2 0 +#define ADC_CCR_ADCPRE_DIV4 1 +#define ADC_CCR_ADCPRE_DIV6 2 +#define ADC_CCR_ADCPRE_DIV8 3 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor. + @note Available onADC1 only. */ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. + @note Available onADC1 only. */ +#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. + @note Available onADC1 only. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_3 0 /**< @brief 3 cycles sampling time. */ +#define ADC_SAMPLE_15 1 /**< @brief 15 cycles sampling time. */ +#define ADC_SAMPLE_28 2 /**< @brief 28 cycles sampling time. */ +#define ADC_SAMPLE_56 3 /**< @brief 56 cycles sampling time. */ +#define ADC_SAMPLE_84 4 /**< @brief 84 cycles sampling time. */ +#define ADC_SAMPLE_112 5 /**< @brief 112 cycles sampling time. */ +#define ADC_SAMPLE_144 6 /**< @brief 144 cycles sampling time. */ +#define ADC_SAMPLE_480 7 /**< @brief 480 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC common clock divider. + * @note This setting is influenced by the VDDA voltage and other + * external conditions, please refer to the STM32L15x datasheet + * for more info.
+ * See section 6.3.15 "12-bit ADC characteristics". + */ +#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 +#endif + +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 TRUE +#endif + +/** + * @brief ADC2 driver enable switch. + * @details If set to @p TRUE the support for ADC2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC2 TRUE +#endif + +/** + * @brief ADC3 driver enable switch. + * @details If set to @p TRUE the support for ADC3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC3 TRUE +#endif + +/** + * @brief DMA stream used for ADC1 operations. + */ +#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#endif + +/** + * @brief DMA stream used for ADC2 operations. + */ +#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#endif + +/** + * @brief DMA stream used for ADC3 operations. + */ +#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC2 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC3 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + * @note This setting is shared among ADC1, ADC2 and ADC3 because + * all ADCs share the same vector. + */ +#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC2 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC3 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2 +#error "ADC2 not present in the selected device" +#endif + +#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3 +#error "ADC3 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK) +#error "invalid DMA stream associated to ADC1" +#endif + +#if STM32_ADC_USE_ADC2 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK) +#error "invalid DMA stream associated to ADC2" +#endif + +#if STM32_ADC_USE_ADC3 && \ + !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK) +#error "invalid DMA stream associated to ADC3" +#endif + +/* ADC clock related settings and checks.*/ +#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2 +#define STM32_ADCCLK (STM32_PCLK2 / 2) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_PCLK2 / 4) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6 +#define STM32_ADCCLK (STM32_PCLK2 / 6) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8 +#define STM32_ADCCLK (STM32_PCLK2 / 8) +#else +#error "invalid STM32_ADC_ADCPRE value specified" +#endif + +#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX) +#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...18. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr2; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 13...16 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr3; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated SMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__) +extern ADCDriver ADCD2; +#endif + +#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__) +extern ADCDriver ADCD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ -- cgit v1.2.3 From 0435bb5b4e1435924490f4a268dba5f75e998951 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 16 Nov 2011 18:03:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3499 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/adc_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c index bc04df615..308fd90d0 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.c +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -219,7 +219,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adc->SQR3 = grpp->sqr3; adcp->adc->SQR4 = grpp->sqr4; adcp->adc->SQR5 = grpp->sqr5; - /* Must wait the ADC to be ready for conversion, see 9.3.6 "Timing diagram" + /* Must wait the ADC to be ready for conversion, see 10.3.6 "Timing diagram" in the Reference Manual.*/ while ((adcp->adc->SR & ADC_SR_ADONS) == 0) ; -- cgit v1.2.3 From cef04f5f4b8ea66ad3ab5a628a4aad8da509039e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 16 Nov 2011 18:55:34 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3500 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/adc_lld.c | 31 +++++++++++++++++++++++++------ os/hal/platforms/STM32F4xx/adc_lld.h | 2 ++ testhal/STM32F4xx/ADC/main.c | 33 +++++++++++++++------------------ 3 files changed, 42 insertions(+), 24 deletions(-) diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index f78c7ac0f..f34c4fd61 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -321,17 +321,16 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC setup.*/ adcp->adc->SR = 0; adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; - adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ - adcp->adc->SMPR2 = grpp->smpr2; adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; adcp->adc->SQR1 = grpp->sqr1; adcp->adc->SQR2 = grpp->sqr2; adcp->adc->SQR3 = grpp->sqr3; - /* Must wait the ADC to be ready for conversion, see 9.3.6 "Timing diagram" - in the Reference Manual.*/ - while ((adcp->adc->SR & ADC_SR_ADONS) == 0) - ; + /* TODO: According to section 10.3.6 of the reference manual there should + be a 2uS delay between the ADC activation and conversion start.*/ + /* ADC start by raising ADC_CR2_SWSTART.*/ adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON; @@ -373,6 +372,26 @@ void adcSTM32DisableTSVREFE(void) { ADC->CCR &= ~ADC_CCR_TSVREFE; } +/** + * @brief Enables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableVBATE(void) { + + ADC->CCR |= ADC_CCR_VBATE; +} + +/** + * @brief Disables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableVBATE(void) { + + ADC->CCR &= ~ADC_CCR_VBATE; +} + #endif /* HAL_USE_ADC */ /** @} */ diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h index 0e846f50a..6260773a2 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.h +++ b/os/hal/platforms/STM32F4xx/adc_lld.h @@ -556,6 +556,8 @@ extern "C" { void adc_lld_stop_conversion(ADCDriver *adcp); void adcSTM32EnableTSVREFE(void); void adcSTM32DisableTSVREFE(void); + void adcSTM32EnableVBATE(void); + void adcSTM32DisableVBATE(void); #ifdef __cplusplus } #endif diff --git a/testhal/STM32F4xx/ADC/main.c b/testhal/STM32F4xx/ADC/main.c index b9890100e..80dab61b2 100644 --- a/testhal/STM32F4xx/ADC/main.c +++ b/testhal/STM32F4xx/ADC/main.c @@ -53,8 +53,8 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { /* * ADC conversion group. - * Mode: Linear buffer, 16 samples of 8 channels, SW triggered. - * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + * Mode: Linear buffer, 16 samples of 1 channel, SW triggered. + * Channels: IN10. */ static const ADCConversionGroup adcgrpcfg1 = { FALSE, @@ -62,12 +62,11 @@ static const ADCConversionGroup adcgrpcfg1 = { NULL, adcerrorcallback, 0, 0, /* CR1, CR2 */ - 0, /* SMPR1 */ - ADC_SMPR2_SMP_AN10(ADC_SAMPLE_4), - 0, /* SMPR3 */ + ADC_SMPR1_SMP_AN10(ADC_SAMPLE_3), + 0, /* SMPR2 */ ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), - 0, 0, 0, /* SQR2, SQR3, SQR4 */ - ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) + 0, /* SQR2 */ + ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) }; /* @@ -81,16 +80,14 @@ static const ADCConversionGroup adcgrpcfg2 = { adccallback, adcerrorcallback, 0, 0, /* CR1, CR2 */ - 0, /* SMPR1 */ - ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192) | - ADC_SMPR2_SMP_VREF(ADC_SAMPLE_192), - 0, /* SMPR3 */ + ADC_SMPR1_SMP_AN11(ADC_SAMPLE_56) | ADC_SMPR1_SMP_AN10(ADC_SAMPLE_56) | + ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_144), + 0, /* SMPR2 */ ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), - 0, 0, /* SQR2, SQR3 */ - ADC_SQR4_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR4_SQ7_N(ADC_CHANNEL_VREFINT), - ADC_SQR5_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ5_N(ADC_CHANNEL_IN10) | - ADC_SQR5_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ3_N(ADC_CHANNEL_IN10) | - ADC_SQR5_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) + ADC_SQR2_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ7_N(ADC_CHANNEL_VREFINT), + ADC_SQR3_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ5_N(ADC_CHANNEL_IN10) | + ADC_SQR3_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ3_N(ADC_CHANNEL_IN10) | + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) }; /* @@ -102,9 +99,9 @@ static msg_t Thread1(void *arg) { (void)arg; chRegSetThreadName("blinker"); while (TRUE) { - palSetPad(GPIOB, GPIOB_LED4); + palSetPad(GPIOD, GPIOD_LED5); chThdSleepMilliseconds(500); - palClearPad(GPIOB, GPIOB_LED4); + palClearPad(GPIOD, GPIOD_LED5); chThdSleepMilliseconds(500); } } -- cgit v1.2.3 From 759a95a23a2e41651f46d25dfdface09525760d1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 16 Nov 2011 18:58:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3501 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F1xx/ADC/main.c | 9 ++++----- testhal/STM32F4xx/ADC/main.c | 2 +- testhal/STM32L1xx/ADC/main.c | 8 ++++---- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/testhal/STM32F1xx/ADC/main.c b/testhal/STM32F1xx/ADC/main.c index 9cc316fa8..bfe8997f9 100644 --- a/testhal/STM32F1xx/ADC/main.c +++ b/testhal/STM32F1xx/ADC/main.c @@ -53,8 +53,8 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { /* * ADC conversion group. - * Mode: Linear buffer, 16 samples of 8 channels, SW triggered. - * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + * Mode: Linear buffer, 8 samples of 1 channel, SW triggered. + * Channels: IN10. */ static const ADCConversionGroup adcgrpcfg1 = { FALSE, @@ -80,9 +80,8 @@ static const ADCConversionGroup adcgrpcfg2 = { adccallback, adcerrorcallback, 0, ADC_CR2_TSVREFE, /* CR1, CR2 */ - ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | - ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5) | - ADC_SMPR1_SMP_VREF(ADC_SAMPLE_239P5), + ADC_SMPR1_SMP_AN11(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | + ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_239P5), 0, /* SMPR2 */ ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), ADC_SQR2_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ7_N(ADC_CHANNEL_VREFINT), diff --git a/testhal/STM32F4xx/ADC/main.c b/testhal/STM32F4xx/ADC/main.c index 80dab61b2..103c05b89 100644 --- a/testhal/STM32F4xx/ADC/main.c +++ b/testhal/STM32F4xx/ADC/main.c @@ -53,7 +53,7 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { /* * ADC conversion group. - * Mode: Linear buffer, 16 samples of 1 channel, SW triggered. + * Mode: Linear buffer, 8 samples of 1 channel, SW triggered. * Channels: IN10. */ static const ADCConversionGroup adcgrpcfg1 = { diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c index b9890100e..c13ebfe2a 100644 --- a/testhal/STM32L1xx/ADC/main.c +++ b/testhal/STM32L1xx/ADC/main.c @@ -53,8 +53,8 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { /* * ADC conversion group. - * Mode: Linear buffer, 16 samples of 8 channels, SW triggered. - * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + * Mode: Linear buffer, 8 samples of 1 channel, SW triggered. + * Channels: IN10. */ static const ADCConversionGroup adcgrpcfg1 = { FALSE, @@ -82,8 +82,8 @@ static const ADCConversionGroup adcgrpcfg2 = { adcerrorcallback, 0, 0, /* CR1, CR2 */ 0, /* SMPR1 */ - ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192) | - ADC_SMPR2_SMP_VREF(ADC_SAMPLE_192), + ADC_SMPR2_SMP_AN11(ADC_SAMPLE_48) | ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | + ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192) | ADC_SMPR2_SMP_VREF(ADC_SAMPLE_192), 0, /* SMPR3 */ ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), 0, 0, /* SQR2, SQR3 */ -- cgit v1.2.3 From eb37378b3e424589a37e525bb4080cc667bbe0fc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 16 Nov 2011 19:00:42 +0000 Subject: STM32F4 ADC driver, not tested yet. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3502 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/readme.txt b/readme.txt index 1c1bc7808..ff4cea1f9 100644 --- a/readme.txt +++ b/readme.txt @@ -84,6 +84,7 @@ (backported to 2.2.8). - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). +- NEW: STM32F4 ADC driver implementation. - NEW: Added initialization of the NVIC VTOR register to all Cortex-Mx (v7M) ports. Also added a port option CORTEX_VTOR_INIT to enforce a different default value into the register. -- cgit v1.2.3 From d70b7e599250fae96dbdc9cbfab11bb9c6d5a649 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 16 Nov 2011 19:52:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3503 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/adc_lld.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index f34c4fd61..97d1623d8 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -178,9 +178,9 @@ void adc_lld_init(void) { #if STM32_ADC_USE_ADC2 /* Driver initialization.*/ adcObjectInit(&ADCD2); - ADCD1.adc = ADC2; - ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); - ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | + ADCD2.adc = ADC2; + ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); + ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | @@ -190,9 +190,9 @@ void adc_lld_init(void) { #if STM32_ADC_USE_ADC3 /* Driver initialization.*/ adcObjectInit(&ADCD3); - ADCD1.adc = ADC3; - ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); - ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | + ADCD3.adc = ADC3; + ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); + ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | -- cgit v1.2.3 From 83d562f6b2842c4ec03ff08662ddc629ccc4e424 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 16 Nov 2011 21:21:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3504 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/adc.h | 8 ++++---- os/hal/platforms/STM32F4xx/adc_lld.c | 12 +++++++++--- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/os/hal/include/adc.h b/os/hal/include/adc.h index ff9e6b18f..9ebe3754c 100644 --- a/os/hal/include/adc.h +++ b/os/hal/include/adc.h @@ -134,15 +134,15 @@ typedef enum { * @notapi */ #define _adc_wakeup_isr(adcp) { \ + chSysLockFromIsr(); \ if ((adcp)->thread != NULL) { \ Thread *tp; \ - chSysLockFromIsr(); \ tp = (adcp)->thread; \ (adcp)->thread = NULL; \ tp->p_u.rdymsg = RDY_OK; \ chSchReadyI(tp); \ - chSysUnlockFromIsr(); \ } \ + chSysUnlockFromIsr(); \ } /** @@ -153,15 +153,15 @@ typedef enum { * @notapi */ #define _adc_timeout_isr(adcp) { \ + chSysLockFromIsr(); \ if ((adcp)->thread != NULL) { \ Thread *tp; \ - chSysLockFromIsr(); \ tp = (adcp)->thread; \ (adcp)->thread = NULL; \ tp->p_u.rdymsg = RDY_TIMEOUT; \ chSchReadyI(tp); \ - chSysUnlockFromIsr(); \ } \ + chSysUnlockFromIsr(); \ } #else /* !ADC_USE_WAIT */ diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index 97d1623d8..69cef5d57 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -170,9 +170,11 @@ void adc_lld_init(void) { ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | + STM32_DMA_CR_EN; #endif #if STM32_ADC_USE_ADC2 @@ -182,9 +184,11 @@ void adc_lld_init(void) { ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | + STM32_DMA_CR_EN; #endif #if STM32_ADC_USE_ADC3 @@ -194,9 +198,11 @@ void adc_lld_init(void) { ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | + STM32_DMA_CR_EN; #endif /* The shared vector is initialized on driver initialization and never -- cgit v1.2.3 From f670263432c8d0496d71739dff806ddf70216961 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Nov 2011 20:28:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3505 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/platform.mk | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk index 1b9ca04dc..7acce0172 100644 --- a/os/hal/platforms/STM32F4xx/platform.mk +++ b/os/hal/platforms/STM32F4xx/platform.mk @@ -1,7 +1,7 @@ -# List of all the STM32L1xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \ +# List of all the STM32F4xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/adc_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32F4xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ -- cgit v1.2.3 From 02d23695cdf37650bb6fe9672f01fc029516a86d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Nov 2011 20:30:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3506 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h | 1 - 1 file changed, 1 deletion(-) diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h index 4aa3d6cc2..058cc7a76 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h +++ b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h @@ -147,7 +147,6 @@ #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE #define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 -- cgit v1.2.3 From 33d9231ad21123694aa3932d88fa4c87dc829b98 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Nov 2011 20:31:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3507 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/readme.txt b/readme.txt index ff4cea1f9..7cc5ac572 100644 --- a/readme.txt +++ b/readme.txt @@ -156,7 +156,7 @@ - NEW: STM32L1xx sub-family support, all STM32 drivers adapted and re-tested on the new platform except ADC that will need a specific implementation. - NEW: Added new API chThdExitS() in order to allow atomic operations on - thead exit (backported to 2.2.8). + thread exit (backported to 2.2.8). - NEW: New EXT driver model and STM32 implementation. - NEW: New I2C driver model and STM32 implementation. (evaluate the option to change the API to a synchronous model) -- cgit v1.2.3 From bcdb92f134f82921cbfe12774cc83e83ddee8eef Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Nov 2011 08:48:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3508 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/stm32_dma.h | 2 +- os/hal/platforms/STM32F4xx/adc_lld.c | 12 +++++++++--- os/hal/platforms/STM32F4xx/stm32_dma.h | 2 +- os/hal/platforms/STM32L1xx/stm32_dma.h | 2 +- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h index fdfd0bc7b..7e230d851 100644 --- a/os/hal/platforms/STM32F1xx/stm32_dma.h +++ b/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -347,7 +347,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); #define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ dmaStreamSetPeripheral(dmastp, src); \ dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamGetTransactionSize(dmastp, n); \ + dmaStreamSetTransactionSize(dmastp, n); \ dmaStreamSetMode(dmastp, (mode) | \ STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index 69cef5d57..603b32135 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -116,7 +116,9 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { #if STM32_ADC_USE_ADC1 sr = ADC1->SR; ADC1->SR = 0; - if (sr & ADC_SR_OVR) { + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/ _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); @@ -127,7 +129,9 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { #if STM32_ADC_USE_ADC2 sr = ADC2->SR; ADC2->SR = 0; - if (sr & ADC_SR_OVR) { + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) { /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/ _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW); @@ -138,7 +142,9 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { #if STM32_ADC_USE_ADC3 sr = ADC3->SR; ADC3->SR = 0; - if (sr & ADC_SR_OVR) { + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) { /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/ _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW); diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h index 4b3302f39..fe15dbd22 100644 --- a/os/hal/platforms/STM32F4xx/stm32_dma.h +++ b/os/hal/platforms/STM32F4xx/stm32_dma.h @@ -400,7 +400,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); #define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ dmaStreamSetPeripheral(dmastp, src); \ dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamGetTransactionSize(dmastp, n); \ + dmaStreamSetTransactionSize(dmastp, n); \ dmaStreamSetMode(dmastp, (mode) | \ STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.h b/os/hal/platforms/STM32L1xx/stm32_dma.h index 0d80a39e7..6afadfcc1 100644 --- a/os/hal/platforms/STM32L1xx/stm32_dma.h +++ b/os/hal/platforms/STM32L1xx/stm32_dma.h @@ -338,7 +338,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); #define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ dmaStreamSetPeripheral(dmastp, src); \ dmaStreamSetMemory0(dmastp, dst); \ - dmaStreamGetTransactionSize(dmastp, n); \ + dmaStreamSetTransactionSize(dmastp, n); \ dmaStreamSetMode(dmastp, (mode) | \ STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ -- cgit v1.2.3 From b1762e9295dfe92f8d682aba3954adde498ff129 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Nov 2011 09:32:59 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3509 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/adc_lld.c | 16 +++++++--------- testhal/STM32F4xx/ADC/main.c | 30 ++++++++++++++++-------------- testhal/STM32F4xx/ADC/readme.txt | 2 +- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index 603b32135..b31ca178c 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -266,9 +266,9 @@ void adc_lld_start(ADCDriver *adcp) { } #endif /* STM32_ADC_USE_ADC3 */ - /* ADC initial setup, just resetting control registers in this case.*/ + /* ADC initial setup, starting the analog part.*/ adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; } } @@ -332,19 +332,16 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC setup.*/ adcp->adc->SR = 0; - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS | - ADC_CR2_ADON; adcp->adc->SMPR1 = grpp->smpr1; adcp->adc->SMPR2 = grpp->smpr2; adcp->adc->SQR1 = grpp->sqr1; adcp->adc->SQR2 = grpp->sqr2; adcp->adc->SQR3 = grpp->sqr3; - /* TODO: According to section 10.3.6 of the reference manual there should - be a 2uS delay between the ADC activation and conversion start.*/ - /* ADC start by raising ADC_CR2_SWSTART.*/ - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_CONT | ADC_CR2_DMA | + /* ADC configuration and start, the start is performed using the method + specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON; } @@ -360,6 +357,7 @@ void adc_lld_stop_conversion(ADCDriver *adcp) { dmaStreamDisable(adcp->dmastp); adcp->adc->CR1 = 0; adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; } /** diff --git a/testhal/STM32F4xx/ADC/main.c b/testhal/STM32F4xx/ADC/main.c index 103c05b89..221792a57 100644 --- a/testhal/STM32F4xx/ADC/main.c +++ b/testhal/STM32F4xx/ADC/main.c @@ -54,40 +54,42 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) { /* * ADC conversion group. * Mode: Linear buffer, 8 samples of 1 channel, SW triggered. - * Channels: IN10. + * Channels: IN11. */ static const ADCConversionGroup adcgrpcfg1 = { FALSE, ADC_GRP1_NUM_CHANNELS, NULL, adcerrorcallback, - 0, 0, /* CR1, CR2 */ - ADC_SMPR1_SMP_AN10(ADC_SAMPLE_3), - 0, /* SMPR2 */ + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + ADC_SMPR1_SMP_AN11(ADC_SAMPLE_3), + 0, /* SMPR2 */ ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), - 0, /* SQR2 */ - ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) + 0, /* SQR2 */ + ADC_SQR3_SQ1_N(ADC_CHANNEL_IN11) }; /* * ADC conversion group. * Mode: Continuous, 16 samples of 8 channels, SW triggered. - * Channels: IN10, IN11, IN10, IN11, IN10, IN11, Sensor, VRef. + * Channels: IN11, IN12, IN11, IN12, IN11, IN12, Sensor, VRef. */ static const ADCConversionGroup adcgrpcfg2 = { TRUE, ADC_GRP2_NUM_CHANNELS, adccallback, adcerrorcallback, - 0, 0, /* CR1, CR2 */ - ADC_SMPR1_SMP_AN11(ADC_SAMPLE_56) | ADC_SMPR1_SMP_AN10(ADC_SAMPLE_56) | + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + ADC_SMPR1_SMP_AN12(ADC_SAMPLE_56) | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_56) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_144), - 0, /* SMPR2 */ + 0, /* SMPR2 */ ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), ADC_SQR2_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ7_N(ADC_CHANNEL_VREFINT), - ADC_SQR3_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ5_N(ADC_CHANNEL_IN10) | - ADC_SQR3_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ3_N(ADC_CHANNEL_IN10) | - ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) + ADC_SQR3_SQ6_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ5_N(ADC_CHANNEL_IN11) | + ADC_SQR3_SQ4_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ3_N(ADC_CHANNEL_IN11) | + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN11) }; /* @@ -124,7 +126,7 @@ int main(void) { /* * Setting up analog inputs used by the demo. */ - palSetGroupMode(GPIOC, PAL_PORT_BIT(0) | PAL_PORT_BIT(1), + palSetGroupMode(GPIOC, PAL_PORT_BIT(1) | PAL_PORT_BIT(2), PAL_MODE_INPUT_ANALOG); /* diff --git a/testhal/STM32F4xx/ADC/readme.txt b/testhal/STM32F4xx/ADC/readme.txt index 24ff92f25..7fd60b1c6 100644 --- a/testhal/STM32F4xx/ADC/readme.txt +++ b/testhal/STM32F4xx/ADC/readme.txt @@ -12,7 +12,7 @@ The application demonstrates the use of the STM32L1xx ADC driver. ** Board Setup ** -- Connect PC0 to 3.3V and PC1 to GND for analog measurements. +- Connect PC1 to 3.3V and PC2 to GND for analog measurements. ** Build Procedure ** -- cgit v1.2.3 From ba01ba301e003f5022c5d406e785de4bc65d70fc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Nov 2011 09:37:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3510 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/adc_lld.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index b31ca178c..29ed6fcc2 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -266,7 +266,8 @@ void adc_lld_start(ADCDriver *adcp) { } #endif /* STM32_ADC_USE_ADC3 */ - /* ADC initial setup, starting the analog part.*/ + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ adcp->adc->CR1 = 0; adcp->adc->CR2 = ADC_CR2_ADON; } -- cgit v1.2.3 From fd9b356d6c3e0c691f51cae7834d72c1c67da100 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Nov 2011 09:53:22 +0000 Subject: STM32F4 ADC driver tested. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3511 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/adc_lld.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index 29ed6fcc2..5edac0163 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -86,13 +86,17 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); } else { - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } } } } @@ -121,7 +125,8 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/ - _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + if (ADCD1.grpp != NULL) + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); } /* TODO: Add here analog watchdog handling.*/ #endif /* STM32_ADC_USE_ADC1 */ @@ -134,7 +139,8 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) { /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/ - _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW); + if (ADCD2.grpp != NULL) + _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW); } /* TODO: Add here analog watchdog handling.*/ #endif /* STM32_ADC_USE_ADC2 */ @@ -147,7 +153,8 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) { if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) { /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/ - _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW); + if (ADCD3.grpp != NULL) + _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW); } /* TODO: Add here analog watchdog handling.*/ #endif /* STM32_ADC_USE_ADC3 */ @@ -342,8 +349,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC configuration and start, the start is performed using the method specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | - ADC_CR2_DDS | ADC_CR2_ADON; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; } /** -- cgit v1.2.3 From cba1d7b4a73109eccedc5dc705ae20000ee8d17e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Nov 2011 09:54:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3512 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/readme.txt b/readme.txt index 7cc5ac572..1693c5f44 100644 --- a/readme.txt +++ b/readme.txt @@ -84,7 +84,9 @@ (backported to 2.2.8). - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). -- NEW: STM32F4 ADC driver implementation. +- NEW: STM32F4xx ADC driver implementation. + TODO: Backport the new solutions implemented in this ADC driver to the + STM32L1xx ADC driver. - NEW: Added initialization of the NVIC VTOR register to all Cortex-Mx (v7M) ports. Also added a port option CORTEX_VTOR_INIT to enforce a different default value into the register. -- cgit v1.2.3 From 23c901559fcc310ca964f7db1a7f182e01c8ccd4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Nov 2011 15:42:58 +0000 Subject: PWM and ICU drivers tested on STM32F4xx. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3513 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32F4xx/PWM-ICU/Makefile | 207 ++++++++++++++ testhal/STM32F4xx/PWM-ICU/chconf.h | 535 +++++++++++++++++++++++++++++++++++ testhal/STM32F4xx/PWM-ICU/halconf.h | 335 ++++++++++++++++++++++ testhal/STM32F4xx/PWM-ICU/main.c | 140 +++++++++ testhal/STM32F4xx/PWM-ICU/mcuconf.h | 208 ++++++++++++++ testhal/STM32F4xx/PWM-ICU/readme.txt | 30 ++ 6 files changed, 1455 insertions(+) create mode 100644 testhal/STM32F4xx/PWM-ICU/Makefile create mode 100644 testhal/STM32F4xx/PWM-ICU/chconf.h create mode 100644 testhal/STM32F4xx/PWM-ICU/halconf.h create mode 100644 testhal/STM32F4xx/PWM-ICU/main.c create mode 100644 testhal/STM32F4xx/PWM-ICU/mcuconf.h create mode 100644 testhal/STM32F4xx/PWM-ICU/readme.txt diff --git a/testhal/STM32F4xx/PWM-ICU/Makefile b/testhal/STM32F4xx/PWM-ICU/Makefile new file mode 100644 index 000000000..9456d0488 --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/PWM-ICU/chconf.h b/testhal/STM32F4xx/PWM-ICU/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/PWM-ICU/halconf.h b/testhal/STM32F4xx/PWM-ICU/halconf.h new file mode 100644 index 000000000..5d3985cdd --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/halconf.h @@ -0,0 +1,335 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/PWM-ICU/main.c b/testhal/STM32F4xx/PWM-ICU/main.c new file mode 100644 index 000000000..0979fc70d --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/main.c @@ -0,0 +1,140 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(GPIOD, GPIOD_LED5); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(GPIOD, GPIOD_LED5); +} + +static PWMConfig pwmcfg = { + 10000, /* 10KHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + palSetPad(GPIOD, GPIOD_LED4); + last_width = icuGetWidthI(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + palClearPad(GPIOD, GPIOD_LED4); + last_period = icuGetPeriodI(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10KHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes the PWM driver 2 and ICU driver 3. + * GPIOA15 is the PWM output. + * GPIOC6 is the ICU input. + * The two pins have to be externally connected together. + */ + pwmStart(&PWMD2, &pwmcfg); + palSetPadMode(GPIOA, 15, PAL_MODE_ALTERNATE(1)); + icuStart(&ICUD3, &icucfg); + palSetPadMode(GPIOC, 6, PAL_MODE_ALTERNATE(2)); + icuEnable(&ICUD3); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 7500)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD2, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD2, 0); + pwmStop(&PWMD2); + icuDisable(&ICUD3); + icuStop(&ICUD3); + palClearPad(GPIOD, GPIOD_LED4); + palClearPad(GPIOD, GPIOD_LED5); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/STM32F4xx/PWM-ICU/mcuconf.h b/testhal/STM32F4xx/PWM-ICU/mcuconf.h new file mode 100644 index 000000000..280778593 --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/mcuconf.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32L1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_HIGH +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2CSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 TRUE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 TRUE +#define STM32_GPT_USE_TIM8 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F4xx/PWM-ICU/readme.txt b/testhal/STM32F4xx/PWM-ICU/readme.txt new file mode 100644 index 000000000..05e7cb95f --- /dev/null +++ b/testhal/STM32F4xx/PWM-ICU/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - PWM-ICU drivers demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32L-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32L1xx PWM-ICU drivers. + +** Board Setup ** + +- Connect PA15 and PC6 together. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From 1e04df415dcb1a44c21edbc53149c7ba6e2ea3e1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Nov 2011 11:09:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3514 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/reports/STM32F407-168-GCC.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/reports/STM32F407-168-GCC.txt b/docs/reports/STM32F407-168-GCC.txt index 7069e8d0e..dd98686bf 100644 --- a/docs/reports/STM32F407-168-GCC.txt +++ b/docs/reports/STM32F407-168-GCC.txt @@ -6,8 +6,8 @@ Settings: SYSCLK=168, ACR=0x705 (5 wait states) *** ChibiOS/RT test suite *** *** Kernel: 2.3.4unstable -*** Compiled: Nov 13 2011 - 12:07:02 -*** Compiler: GCC 4.6.0 +*** Compiled: Nov 20 2011 - 12:03:44 +*** Compiler: GCC 4.6.2 *** Architecture: ARMv7-ME *** Core Variant: Cortex-M4 *** Port Info: Advanced kernel mode -- cgit v1.2.3 From d4901e2acc5d3924ca766ed35949c0b90823d1fa Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Nov 2011 15:31:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3515 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32L152-DISCOVERY/main.c | 2 +- demos/ARMCM4-STM32F407-DISCOVERY/halconf.h | 6 ++-- demos/ARMCM4-STM32F407-DISCOVERY/main.c | 54 ++++++++++-------------------- demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h | 19 ++++++++++- 4 files changed, 39 insertions(+), 42 deletions(-) diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/main.c b/demos/ARMCM3-STM32L152-DISCOVERY/main.c index 61532bcbd..3b538854f 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32L152-DISCOVERY/main.c @@ -63,7 +63,7 @@ static const ADCConversionGroup adcgrpcfg = { /* * PWM configuration structure. - * Cyclic callback enabled, channels 3 and 4 enabled without callbacks, + * Cyclic callback enabled, channels 1 and 2 enabled without callbacks, * the active state is a logic one. */ static PWMConfig pwmcfg = { diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h index b4fb49092..2c109a7ef 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h +++ b/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h @@ -45,7 +45,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE +#define HAL_USE_ADC TRUE #endif /** @@ -101,7 +101,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE +#define HAL_USE_PWM TRUE #endif /** @@ -136,7 +136,7 @@ * @brief Enables the SPI subsystem. */ #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE +#define HAL_USE_SPI TRUE #endif /** diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/main.c b/demos/ARMCM4-STM32F407-DISCOVERY/main.c index ab126427b..34893edda 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/main.c +++ b/demos/ARMCM4-STM32F407-DISCOVERY/main.c @@ -22,7 +22,6 @@ #include "hal.h" #include "test.h" -#if 0 static void pwmpcb(PWMDriver *pwmp); static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); static void spicb(SPIDriver *spip); @@ -41,7 +40,7 @@ static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; /* * ADC conversion group. * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. - * Channels: IN10 (48 cycles sample time) + * Channels: IN11 (48 cycles sample time) * Sensor (192 cycles sample time) */ static const ADCConversionGroup adcgrpcfg = { @@ -51,20 +50,17 @@ static const ADCConversionGroup adcgrpcfg = { NULL, /* HW dependent part.*/ 0, - 0, - 0, - ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192), + ADC_CR2_SWSTART, + ADC_SMPR1_SMP_AN11(ADC_SAMPLE_56) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144), 0, ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), 0, - 0, - 0, - ADC_SQR5_SQ2_N(ADC_CHANNEL_IN10) | ADC_SQR5_SQ1_N(ADC_CHANNEL_SENSOR) + ADC_SQR3_SQ2_N(ADC_CHANNEL_IN11) | ADC_SQR3_SQ1_N(ADC_CHANNEL_SENSOR) }; /* * PWM configuration structure. - * Cyclic callback enabled, channels 3 and 4 enabled without callbacks, + * Cyclic callback enabled, channels 1 and 4 enabled without callbacks, * the active state is a logic one. */ static PWMConfig pwmcfg = { @@ -73,9 +69,9 @@ static PWMConfig pwmcfg = { pwmpcb, { {PWM_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_ACTIVE_HIGH, NULL}, {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL} + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL} }, /* HW dependent part.*/ 0 @@ -132,11 +128,11 @@ void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { /* Changes the channels pulse width, the change will be effective starting from the next cycle.*/ pwmEnableChannelI(&PWMD4, 0, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch1)); - pwmEnableChannelI(&PWMD4, 1, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); +// pwmEnableChannelI(&PWMD4, 3, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); /* SPI slave selection and transmission start.*/ - spiSelectI(&SPID2); - spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); +// spiSelectI(&SPID2); +// spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); chSysUnlockFromIsr(); } @@ -152,37 +148,23 @@ static void spicb(SPIDriver *spip) { spiUnselectI(spip); chSysUnlockFromIsr(); } -#endif /* - * This is a periodic thread that does absolutely nothing except increasing - * a seconds counter. + * This is a periodic thread that does absolutely nothing except flashing + * a LED. */ static WORKING_AREA(waThread1, 128); -#if 0 -static msg_t Thread1(void *arg) { - static uint32_t seconds_counter; - - (void)arg; - chRegSetThreadName("counter"); - while (TRUE) { - chThdSleepMilliseconds(1000); - seconds_counter++; - } -} -#else static msg_t Thread1(void *arg) { (void)arg; chRegSetThreadName("blinker"); while (TRUE) { - palSetPad(GPIOD, GPIOD_LED5); + palSetPad(GPIOD, GPIOD_LED3); /* Orange. */ chThdSleepMilliseconds(500); - palClearPad(GPIOD, GPIOD_LED5); + palClearPad(GPIOD, GPIOD_LED3); /* Orange. */ chThdSleepMilliseconds(500); } } -#endif /* * Application entry point. @@ -222,7 +204,6 @@ int main(void) { * PB14 - MISO. * PB15 - MOSI. */ -#if 0 spiStart(&SPID2, &spicfg); palSetPad(GPIOB, 12); palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL | @@ -239,15 +220,14 @@ int main(void) { */ adcStart(&ADCD1, NULL); adcSTM32EnableTSVREFE(); - palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); + palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG); /* * Initializes the PWM driver 4, routes the TIM4 outputs to the board LEDs. */ pwmStart(&PWMD4, &pwmcfg); - palSetPadMode(GPIOB, GPIOB_LED4, PAL_MODE_ALTERNATE(2)); - palSetPadMode(GPIOB, GPIOB_LED3, PAL_MODE_ALTERNATE(2)); -#endif + palSetPadMode(GPIOD, GPIOD_LED4, PAL_MODE_ALTERNATE(2)); /* Green. */ + palSetPadMode(GPIOD, GPIOD_LED6, PAL_MODE_ALTERNATE(2)); /* Blue. */ /* * Creates the example thread. diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h index 058cc7a76..d3485d257 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h +++ b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h @@ -64,9 +64,20 @@ /* * ADC driver system settings. */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 #define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. @@ -160,6 +171,12 @@ #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 TRUE #define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 -- cgit v1.2.3 From 9369d75516d5edb0e892f5ce1a5d7781917a64a5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Nov 2011 18:04:07 +0000 Subject: STM32F4-Discovery demo working. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3516 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32L152-DISCOVERY/readme.txt | 2 +- demos/ARMCM4-STM32F407-DISCOVERY/main.c | 6 +-- demos/ARMCM4-STM32F407-DISCOVERY/readme.txt | 4 +- os/hal/platforms/STM32/icu_lld.c | 12 +++--- os/hal/platforms/STM32/icu_lld.h | 4 +- os/hal/platforms/STM32/pwm_lld.c | 18 ++++----- os/hal/platforms/STM32F1xx/hal_lld.h | 59 +++++++++++++++++++++++------ os/hal/platforms/STM32F1xx/stm32f10x.h | 3 ++ os/hal/platforms/STM32F4xx/hal_lld.h | 41 ++++++++++++++++++++ os/hal/platforms/STM32F4xx/stm32f4xx.h | 3 ++ os/hal/platforms/STM32L1xx/hal_lld.h | 55 ++++++++++++++++++++++----- os/hal/platforms/STM32L1xx/stm32l1xx.h | 3 ++ readme.txt | 1 + 13 files changed, 166 insertions(+), 45 deletions(-) diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt b/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt index a79e306a4..ce8ade8fc 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt +++ b/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt @@ -11,7 +11,7 @@ The demo runs on an ST STM32L-Discovery board. The demo shows how to use the ADC, PWM and SPI drivers using asynchronous APIs. The ADC samples two channels (temperature sensor and PC0) and modulates the PWM using the sampled values. The sample data is also transmitted using -the SPI port 1. +the SPI port 2 (NSS=PB12, SCK=PB13, MISO=PB14, MOSI=PB15). By pressing the button located on the board the test procedure is activated with output on the serial port COM1 (USART1). diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/main.c b/demos/ARMCM4-STM32F407-DISCOVERY/main.c index 34893edda..e7e05d0bb 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/main.c +++ b/demos/ARMCM4-STM32F407-DISCOVERY/main.c @@ -128,11 +128,11 @@ void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { /* Changes the channels pulse width, the change will be effective starting from the next cycle.*/ pwmEnableChannelI(&PWMD4, 0, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch1)); -// pwmEnableChannelI(&PWMD4, 3, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); + pwmEnableChannelI(&PWMD4, 3, PWM_FRACTION_TO_WIDTH(&PWMD4, 4096, avg_ch2)); /* SPI slave selection and transmission start.*/ -// spiSelectI(&SPID2); -// spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); + spiSelectI(&SPID2); + spiStartSendI(&SPID2, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); chSysUnlockFromIsr(); } diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt b/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt index ab3c5199a..b82983548 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt +++ b/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt @@ -9,9 +9,9 @@ The demo runs on an ST STM32F4-Discovery board. ** The Demo ** The demo shows how to use the ADC, PWM and SPI drivers using asynchronous -APIs. The ADC samples two channels (temperature sensor and PC0) and modulates +APIs. The ADC samples two channels (temperature sensor and PC1) and modulates the PWM using the sampled values. The sample data is also transmitted using -the SPI port 1. +the SPI port 2 (NSS=PB12, SCK=PB13, MISO=PB14, MOSI=PB15). By pressing the button located on the board the test procedure is activated with output on the serial port SD2 (USART2). diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c index 33eff67d5..ab3e12f26 100644 --- a/os/hal/platforms/STM32/icu_lld.c +++ b/os/hal/platforms/STM32/icu_lld.c @@ -343,12 +343,12 @@ void icu_lld_start(ICUDriver *icup) { } else { /* Driver re-configuration scenario, it must be stopped first.*/ - icup->tim->CR1 = 0; /* Timer disabled. */ - icup->tim->DIER = 0; /* All IRQs disabled. */ - icup->tim->SR = 0; /* Clear eventual pending IRQs. */ - icup->tim->CCR1 = 0; /* Comparator 1 disabled. */ - icup->tim->CCR2 = 0; /* Comparator 2 disabled. */ - icup->tim->CNT = 0; /* Counter reset to zero. */ + icup->tim->CR1 = 0; /* Timer disabled. */ + icup->tim->DIER = 0; /* All IRQs disabled. */ + icup->tim->SR = 0; /* Clear eventual pending IRQs. */ + icup->tim->CCR[0] = 0; /* Comparator 1 disabled. */ + icup->tim->CCR[1] = 0; /* Comparator 2 disabled. */ + icup->tim->CNT = 0; /* Counter reset to zero. */ } /* Timer configuration.*/ diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h index 3156023eb..b97930609 100644 --- a/os/hal/platforms/STM32/icu_lld.h +++ b/os/hal/platforms/STM32/icu_lld.h @@ -262,7 +262,7 @@ struct ICUDriver { * * @notapi */ -#define icu_lld_get_width(icup) ((icup)->tim->CCR2 + 1) +#define icu_lld_get_width(icup) ((icup)->tim->CCR[1] + 1) /** * @brief Returns the width of the latest cycle. @@ -274,7 +274,7 @@ struct ICUDriver { * * @notapi */ -#define icu_lld_get_period(icup) ((icup)->tim->CCR1 + 1) +#define icu_lld_get_period(icup) ((icup)->tim->CCR[0] + 1) /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index ab3c1c2bb..fb5d12adf 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -419,13 +419,13 @@ void pwm_lld_start(PWMDriver *pwmp) { } else { /* Driver re-configuration scenario, it must be stopped first.*/ - pwmp->tim->CR1 = 0; /* Timer disabled. */ - pwmp->tim->DIER = 0; /* All IRQs disabled. */ - pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */ - pwmp->tim->CCR1 = 0; /* Comparator 1 disabled. */ - pwmp->tim->CCR2 = 0; /* Comparator 2 disabled. */ - pwmp->tim->CCR3 = 0; /* Comparator 3 disabled. */ - pwmp->tim->CCR4 = 0; /* Comparator 4 disabled. */ + pwmp->tim->CR1 = 0; /* Timer disabled. */ + pwmp->tim->DIER = 0; /* All IRQs disabled. */ + pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */ + pwmp->tim->CCR[0] = 0; /* Comparator 1 disabled. */ + pwmp->tim->CCR[1] = 0; /* Comparator 2 disabled. */ + pwmp->tim->CCR[2] = 0; /* Comparator 3 disabled. */ + pwmp->tim->CCR[3] = 0; /* Comparator 4 disabled. */ pwmp->tim->CNT = 0; /* Counter reset to zero. */ } @@ -599,7 +599,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width) { - *(&pwmp->tim->CCR1 + (channel * 2)) = width; /* New duty cycle. */ + pwmp->tim->CCR[channel] = width; /* New duty cycle. */ /* If there is a callback defined for the channel then the associated interrupt must be enabled.*/ if (pwmp->config->channels[channel].callback != NULL) { @@ -627,7 +627,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, */ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - *(&pwmp->tim->CCR1 + (channel * 2)) = 0; + pwmp->tim->CCR[channel] = 0; pwmp->tim->DIER &= ~(2 << channel); } diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index 9b87b0a85..a4ccd3118 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -43,6 +43,12 @@ #ifndef _HAL_LLD_H_ #define _HAL_LLD_H_ +#include "stm32f10x.h" + +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -100,6 +106,47 @@ /* Driver data structures and types. */ /*===========================================================================*/ +/** + * @brief STM32 TIM registers block. + * @note Removed from the ST headers and redefined because the non uniform + * declaration of the CCR registers among the various sub-families. + */ +typedef struct { + volatile uint16_t CR1; + uint16_t _resvd0; + volatile uint16_t CR2; + uint16_t _resvd1; + volatile uint16_t SMCR; + uint16_t _resvd2; + volatile uint16_t DIER; + uint16_t _resvd3; + volatile uint16_t SR; + uint16_t _resvd4; + volatile uint16_t EGR; + uint16_t _resvd5; + volatile uint16_t CCMR1; + uint16_t _resvd6; + volatile uint16_t CCMR2; + uint16_t _resvd7; + volatile uint16_t CCER; + uint16_t _resvd8; + volatile uint32_t CNT; + volatile uint16_t PSC; + uint16_t _resvd9; + volatile uint32_t ARR; + volatile uint16_t RCR; + uint16_t _resvd10; + volatile uint32_t CCR[4]; + volatile uint16_t BDTR; + uint16_t _resvd11; + volatile uint16_t DCR; + uint16_t _resvd12; + volatile uint16_t DMAR; + uint16_t _resvd13; + volatile uint16_t OR; + uint16_t _resvd14; +} TIM_TypeDef; + /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ @@ -108,18 +155,6 @@ /* External declarations. */ /*===========================================================================*/ -/* Tricks required to make the TRUE/FALSE declaration inside the library - compatible.*/ -#undef FALSE -#undef TRUE -#include "stm32f10x.h" -#define FALSE 0 -#define TRUE (!FALSE) - -/* STM32 DMA and RCC helpers.*/ -#include "stm32_dma.h" -#include "stm32_rcc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/platforms/STM32F1xx/stm32f10x.h b/os/hal/platforms/STM32F1xx/stm32f10x.h index 6697b9648..e8f413763 100644 --- a/os/hal/platforms/STM32F1xx/stm32f10x.h +++ b/os/hal/platforms/STM32F1xx/stm32f10x.h @@ -1198,6 +1198,8 @@ typedef struct * @brief TIM */ +/* CHIBIOS FIX */ +#if 0 typedef struct { __IO uint16_t CR1; @@ -1241,6 +1243,7 @@ typedef struct __IO uint16_t DMAR; uint16_t RESERVED19; } TIM_TypeDef; +#endif /** * @brief Universal Synchronous Asynchronous Receiver Transmitter diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 11bdfedd6..71207efd5 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -1262,6 +1262,47 @@ /* Driver data structures and types. */ /*===========================================================================*/ +/** + * @brief STM32 TIM registers block. + * @note Removed from the ST headers and redefined because the non uniform + * declaration of the CCR registers among the various sub-families. + */ +typedef struct { + volatile uint16_t CR1; + uint16_t _resvd0; + volatile uint16_t CR2; + uint16_t _resvd1; + volatile uint16_t SMCR; + uint16_t _resvd2; + volatile uint16_t DIER; + uint16_t _resvd3; + volatile uint16_t SR; + uint16_t _resvd4; + volatile uint16_t EGR; + uint16_t _resvd5; + volatile uint16_t CCMR1; + uint16_t _resvd6; + volatile uint16_t CCMR2; + uint16_t _resvd7; + volatile uint16_t CCER; + uint16_t _resvd8; + volatile uint32_t CNT; + volatile uint16_t PSC; + uint16_t _resvd9; + volatile uint32_t ARR; + volatile uint16_t RCR; + uint16_t _resvd10; + volatile uint32_t CCR[4]; + volatile uint16_t BDTR; + uint16_t _resvd11; + volatile uint16_t DCR; + uint16_t _resvd12; + volatile uint16_t DMAR; + uint16_t _resvd13; + volatile uint16_t OR; + uint16_t _resvd14; +} TIM_TypeDef; + /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F4xx/stm32f4xx.h b/os/hal/platforms/STM32F4xx/stm32f4xx.h index ccc1a3565..cd8ed7887 100644 --- a/os/hal/platforms/STM32F4xx/stm32f4xx.h +++ b/os/hal/platforms/STM32F4xx/stm32f4xx.h @@ -868,6 +868,8 @@ typedef struct * @brief TIM */ +/* CHIBIOS FIX */ +#if 0 typedef struct { __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ @@ -907,6 +909,7 @@ typedef struct __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ uint16_t RESERVED14; /*!< Reserved, 0x52 */ } TIM_TypeDef; +#endif /** * @brief Universal Synchronous Asynchronous Receiver Transmitter diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 8d8f1b23b..d62176a16 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -37,13 +37,11 @@ #ifndef _HAL_LLD_H_ #define _HAL_LLD_H_ -/* Tricks required to make the TRUE/FALSE declaration inside the library - compatible.*/ -#undef FALSE -#undef TRUE #include "stm32l1xx.h" -#define FALSE 0 -#define TRUE (!FALSE) + +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" /*===========================================================================*/ /* Driver constants. */ @@ -933,6 +931,47 @@ /* Driver data structures and types. */ /*===========================================================================*/ +/** + * @brief STM32 TIM registers block. + * @note Removed from the ST headers and redefined because the non uniform + * declaration of the CCR registers among the various sub-families. + */ +typedef struct { + volatile uint16_t CR1; + uint16_t _resvd0; + volatile uint16_t CR2; + uint16_t _resvd1; + volatile uint16_t SMCR; + uint16_t _resvd2; + volatile uint16_t DIER; + uint16_t _resvd3; + volatile uint16_t SR; + uint16_t _resvd4; + volatile uint16_t EGR; + uint16_t _resvd5; + volatile uint16_t CCMR1; + uint16_t _resvd6; + volatile uint16_t CCMR2; + uint16_t _resvd7; + volatile uint16_t CCER; + uint16_t _resvd8; + volatile uint32_t CNT; + volatile uint16_t PSC; + uint16_t _resvd9; + volatile uint32_t ARR; + volatile uint16_t RCR; + uint16_t _resvd10; + volatile uint32_t CCR[4]; + volatile uint16_t BDTR; + uint16_t _resvd11; + volatile uint16_t DCR; + uint16_t _resvd12; + volatile uint16_t DMAR; + uint16_t _resvd13; + volatile uint16_t OR; + uint16_t _resvd14; +} TIM_TypeDef; + /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ @@ -941,10 +980,6 @@ /* External declarations. */ /*===========================================================================*/ -/* STM32 DMA and RCC helpers.*/ -#include "stm32_dma.h" -#include "stm32_rcc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h index 32ddcb79d..5fadee5db 100644 --- a/os/hal/platforms/STM32L1xx/stm32l1xx.h +++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h @@ -615,6 +615,8 @@ typedef struct * @brief TIM */ +/* CHIBIOS FIX */ +#if 0 typedef struct { __IO uint16_t CR1; @@ -658,6 +660,7 @@ typedef struct __IO uint16_t OR; uint16_t RESERVED20; } TIM_TypeDef; +#endif /** * @brief Universal Synchronous Asynchronous Receiver Transmitter diff --git a/readme.txt b/readme.txt index 1693c5f44..787f549ef 100644 --- a/readme.txt +++ b/readme.txt @@ -84,6 +84,7 @@ (backported to 2.2.8). - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). +- NEW: Added demo for the ST STM32F4-Discovery kit. - NEW: STM32F4xx ADC driver implementation. TODO: Backport the new solutions implemented in this ADC driver to the STM32L1xx ADC driver. -- cgit v1.2.3 From a30f84ac78043e7535c338b680b93b43e0b8332e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 21 Nov 2011 18:47:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3517 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM4-STM32F407-DISCOVERY/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/main.c b/demos/ARMCM4-STM32F407-DISCOVERY/main.c index e7e05d0bb..e923de4aa 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/main.c +++ b/demos/ARMCM4-STM32F407-DISCOVERY/main.c @@ -238,7 +238,7 @@ int main(void) { * Normal main() thread activity, in this demo it does nothing except * sleeping in a loop and check the button state, when the button is * pressed the test procedure is launched with output on the serial - * driver 1. + * driver 2. */ while (TRUE) { if (palReadPad(GPIOA, GPIOA_BUTTON)) -- cgit v1.2.3 From c399cbbddf5e5f0ed2209aadc8eec0f188d11340 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 22 Nov 2011 08:00:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3518 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h | 10 +--------- os/hal/platforms/STM32/GPIOv2/pal_lld.c | 2 +- os/hal/platforms/STM32/GPIOv2/pal_lld.h | 2 +- testhal/STM32F4xx/ADC/mcuconf.h | 10 +--------- testhal/STM32F4xx/GPT/mcuconf.h | 10 +--------- testhal/STM32F4xx/IRQ_STORM/mcuconf.h | 10 +--------- testhal/STM32F4xx/PWM-ICU/mcuconf.h | 10 +--------- testhal/STM32F4xx/SPI/mcuconf.h | 23 +++++++++++++---------- 8 files changed, 20 insertions(+), 57 deletions(-) diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h index d3485d257..c91fae0cd 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h +++ b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h @@ -19,7 +19,7 @@ */ /* - * STM32L1xx drivers configuration. + * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -198,11 +198,3 @@ #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/os/hal/platforms/STM32/GPIOv2/pal_lld.c index 728523719..cb9c102df 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.c +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.c @@ -20,7 +20,7 @@ /** * @file STM32/GPIOv2/pal_lld.c - * @brief STM32L1xx/STM32F2xx GPIO low level driver code. + * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver code. * * @addtogroup PAL * @{ diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h index 7f8c2e17a..60dd84307 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -20,7 +20,7 @@ /** * @file STM32/GPIOv2/pal_lld.h - * @brief STM32L1xx/STM32F2xx GPIO low level driver header. + * @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver header. * * @addtogroup PAL * @{ diff --git a/testhal/STM32F4xx/ADC/mcuconf.h b/testhal/STM32F4xx/ADC/mcuconf.h index acb1183ed..e3f9b95db 100644 --- a/testhal/STM32F4xx/ADC/mcuconf.h +++ b/testhal/STM32F4xx/ADC/mcuconf.h @@ -19,7 +19,7 @@ */ /* - * STM32L1xx drivers configuration. + * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -198,11 +198,3 @@ #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F4xx/GPT/mcuconf.h b/testhal/STM32F4xx/GPT/mcuconf.h index dec461caf..4f0647db3 100644 --- a/testhal/STM32F4xx/GPT/mcuconf.h +++ b/testhal/STM32F4xx/GPT/mcuconf.h @@ -19,7 +19,7 @@ */ /* - * STM32L1xx drivers configuration. + * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -187,11 +187,3 @@ #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F4xx/IRQ_STORM/mcuconf.h b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h index 469fdfbc0..59b5989bf 100644 --- a/testhal/STM32F4xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h @@ -19,7 +19,7 @@ */ /* - * STM32L1xx drivers configuration. + * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -187,11 +187,3 @@ #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F4xx/PWM-ICU/mcuconf.h b/testhal/STM32F4xx/PWM-ICU/mcuconf.h index 280778593..06d7a8705 100644 --- a/testhal/STM32F4xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32F4xx/PWM-ICU/mcuconf.h @@ -19,7 +19,7 @@ */ /* - * STM32L1xx drivers configuration. + * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -198,11 +198,3 @@ #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 diff --git a/testhal/STM32F4xx/SPI/mcuconf.h b/testhal/STM32F4xx/SPI/mcuconf.h index 9f13048a6..02b8304b0 100644 --- a/testhal/STM32F4xx/SPI/mcuconf.h +++ b/testhal/STM32F4xx/SPI/mcuconf.h @@ -19,7 +19,7 @@ */ /* - * STM32 drivers configuration. + * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole @@ -64,9 +64,20 @@ /* * ADC driver system settings. */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 #define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. @@ -187,11 +198,3 @@ #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_HP_IRQ_PRIORITY 6 -#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 -- cgit v1.2.3 From e241378765ef67e3c804753a54a30e1e6b4431e3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Nov 2011 19:25:55 +0000 Subject: Fixed DMA assignment for SPI3 on STM32F1xx devices. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3519 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/spi_lld.h | 4 ++-- os/hal/platforms/STM32F1xx/hal_lld_f103.h | 8 ++++---- os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h index ccffe5f8b..e10a5edce 100644 --- a/os/hal/platforms/STM32/spi_lld.h +++ b/os/hal/platforms/STM32/spi_lld.h @@ -186,8 +186,8 @@ #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #endif /* !STM32_ADVANCED_DMA*/ /** @} */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 1375bf7cf..4090502a1 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -403,9 +403,9 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) #define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) #define STM32_SPI3_TX_DMA_CHN 0x00000000 /* TIM attributes.*/ @@ -506,9 +506,9 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) #define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) #define STM32_SPI3_TX_DMA_CHN 0x00000000 /* TIM attributes.*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index b8eb11c3b..dff2f7b2e 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -189,9 +189,9 @@ #define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) #define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) #define STM32_SPI3_TX_DMA_CHN 0x00000000 /* TIM attributes.*/ -- cgit v1.2.3 From 4286b14a9e6d82823c8e5c759495575b1b7fa5ef Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Nov 2011 19:58:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3520 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM4-STM32F407-DISCOVERY/main.c | 2 +- demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h | 8 +- os/hal/platforms/STM32/spi_lld.c | 2 +- os/hal/platforms/STM32/spi_lld.h | 44 +- os/hal/platforms/STM32/uart_lld.c | 96 +++-- os/hal/platforms/STM32/uart_lld.h | 100 +++++ os/hal/platforms/STM32F1xx/hal_lld_f100.h | 29 ++ os/hal/platforms/STM32F1xx/hal_lld_f103.h | 116 ++++++ os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 29 ++ os/hal/platforms/STM32F4xx/adc_lld.c | 2 +- os/hal/platforms/STM32F4xx/hal_lld.h | 33 ++ os/hal/platforms/STM32L1xx/hal_lld.h | 29 ++ testhal/STM32F4xx/ADC/mcuconf.h | 8 +- testhal/STM32F4xx/GPT/mcuconf.h | 21 +- testhal/STM32F4xx/IRQ_STORM/mcuconf.h | 23 +- testhal/STM32F4xx/PWM-ICU/mcuconf.h | 8 +- testhal/STM32F4xx/SPI/mcuconf.h | 8 +- testhal/STM32F4xx/UART/Makefile | 207 ++++++++++ testhal/STM32F4xx/UART/chconf.h | 535 +++++++++++++++++++++++++ testhal/STM32F4xx/UART/halconf.h | 328 +++++++++++++++ testhal/STM32F4xx/UART/main.c | 145 +++++++ testhal/STM32F4xx/UART/mcuconf.h | 206 ++++++++++ testhal/STM32F4xx/UART/readme.txt | 31 ++ testhal/STM32L1xx/UART/main.c | 3 +- testhal/STM32L1xx/UART/readme.txt | 2 +- 25 files changed, 1946 insertions(+), 69 deletions(-) create mode 100644 testhal/STM32F4xx/UART/Makefile create mode 100644 testhal/STM32F4xx/UART/chconf.h create mode 100644 testhal/STM32F4xx/UART/halconf.h create mode 100644 testhal/STM32F4xx/UART/main.c create mode 100644 testhal/STM32F4xx/UART/mcuconf.h create mode 100644 testhal/STM32F4xx/UART/readme.txt diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/main.c b/demos/ARMCM4-STM32F407-DISCOVERY/main.c index e923de4aa..161bc63b5 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/main.c +++ b/demos/ARMCM4-STM32F407-DISCOVERY/main.c @@ -182,7 +182,7 @@ int main(void) { chSysInit(); /* - * Activates the serial driver 1 using the driver default configuration. + * Activates the serial driver 2 using the driver default configuration. * PA2(TX) and PA3(RX) are routed to USART2. */ sdStart(&SD2, NULL); diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h index c91fae0cd..ae08b035d 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h +++ b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h @@ -176,7 +176,7 @@ #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 @@ -191,6 +191,12 @@ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index 2610031b6..34a892d48 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -99,7 +99,7 @@ static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { /* DMA errors handling.*/ #if defined(STM32_SPI_DMA_ERROR_HOOK) - if ((flags & STM32_DMA_ISR_TEIF) != 0) { + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { STM32_SPI_DMA_ERROR_HOOK(spip); } #else diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h index e10a5edce..ee2586ea1 100644 --- a/os/hal/platforms/STM32/spi_lld.h +++ b/os/hal/platforms/STM32/spi_lld.h @@ -70,6 +70,27 @@ #define STM32_SPI_USE_SPI3 FALSE #endif +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI2 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI3 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#endif + /** * @brief SPI1 DMA priority (0..3|lowest..highest). * @note The priority level is used for both the TX and RX DMA streams but @@ -100,27 +121,6 @@ #define STM32_SPI_SPI3_DMA_PRIORITY 1 #endif -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI2 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI3 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#endif - /** * @brief SPI DMA error hook. */ @@ -175,7 +175,7 @@ * @note This option is only available on platforms with enhanced DMA. */ #if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #endif #else /* !STM32_ADVANCED_DMA */ diff --git a/os/hal/platforms/STM32/uart_lld.c b/os/hal/platforms/STM32/uart_lld.c index 3841be8fa..be63fc695 100644 --- a/os/hal/platforms/STM32/uart_lld.c +++ b/os/hal/platforms/STM32/uart_lld.c @@ -31,6 +31,34 @@ #if HAL_USE_UART || defined(__DOXYGEN__) +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define USART1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \ + STM32_USART1_RX_DMA_CHN) + +#define USART1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \ + STM32_USART1_TX_DMA_CHN) + +#define USART2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \ + STM32_USART2_RX_DMA_CHN) + +#define USART2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \ + STM32_USART2_TX_DMA_CHN) + +#define USART3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \ + STM32_USART3_RX_DMA_CHN) + +#define USART3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \ + STM32_USART3_TX_DMA_CHN) + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -92,10 +120,9 @@ static void set_rx_idle_loop(UARTDriver *uartp) { /* RX DMA channel preparation, if the char callback is defined then the TCIE interrupt is enabled too.*/ if (uartp->config->rxchar_cb == NULL) - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TEIE; + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC; else - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE; + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); dmaStreamSetTransactionSize(uartp->dmarx, 1); dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); @@ -172,7 +199,7 @@ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { /* DMA errors handling.*/ #if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & STM32_DMA_ISR_TEIF) != 0) { + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { STM32_UART_DMA_ERROR_HOOK(uartp); } #else @@ -192,6 +219,7 @@ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { uartp->rxstate = UART_RX_COMPLETE; if (uartp->config->rxend_cb != NULL) uartp->config->rxend_cb(uartp); + /* If the callback didn't explicitly change state then the receiver automatically returns to the idle state.*/ if (uartp->rxstate == UART_RX_COMPLETE) { @@ -211,7 +239,7 @@ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { /* DMA errors handling.*/ #if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & STM32_DMA_ISR_TEIF) != 0) { + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { STM32_UART_DMA_ERROR_HOOK(uartp); } #else @@ -219,10 +247,12 @@ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { #endif dmaStreamDisable(uartp->dmatx); + /* A callback is generated, if enabled, after a completed transfer.*/ uartp->txstate = UART_TX_COMPLETE; if (uartp->config->txend1_cb != NULL) uartp->config->txend1_cb(uartp); + /* If the callback didn't explicitly change state then the transmitter automatically returns to the idle state.*/ if (uartp->txstate == UART_TX_COMPLETE) @@ -248,6 +278,7 @@ static void serve_usart_irq(UARTDriver *uartp) { } if (sr & USART_SR_TC) { u->SR = ~USART_SR_TC; + /* End of transmission, a callback is generated.*/ if (uartp->config->txend2_cb != NULL) uartp->config->txend2_cb(uartp); @@ -320,22 +351,22 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART1 uartObjectInit(&UARTD1); UARTD1.usart = USART1; - UARTD1.dmarx = STM32_DMA1_STREAM5; - UARTD1.dmatx = STM32_DMA1_STREAM4; + UARTD1.dmarx = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM); + UARTD1.dmatx = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM); #endif #if STM32_UART_USE_USART2 uartObjectInit(&UARTD2); UARTD2.usart = USART2; - UARTD2.dmarx = STM32_DMA1_STREAM6; - UARTD2.dmatx = STM32_DMA1_STREAM7; + UARTD2.dmarx = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM); + UARTD2.dmatx = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM); #endif #if STM32_UART_USE_USART3 uartObjectInit(&UARTD3); UARTD3.usart = USART3; - UARTD3.dmarx = STM32_DMA1_STREAM3; - UARTD3.dmatx = STM32_DMA1_STREAM2; + UARTD3.dmarx = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM); + UARTD3.dmatx = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM); #endif } @@ -348,35 +379,39 @@ void uart_lld_init(void) { */ void uart_lld_start(UARTDriver *uartp) { + uartp->dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + if (uartp->state == UART_STOP) { #if STM32_UART_USE_USART1 if (&UARTD1 == uartp) { bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM4, + b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM5, + b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART1_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); rccEnableUSART1(FALSE); NVICEnableVector(USART1_IRQn, CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART2 if (&UARTD2 == uartp) { bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM6, + b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM7, + b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); @@ -384,31 +419,34 @@ void uart_lld_start(UARTDriver *uartp) { rccEnableUSART2(FALSE); NVICEnableVector(USART2_IRQn, CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART3 if (&UARTD3 == uartp) { bool_t b; - b = dmaStreamAllocate(STM32_DMA1_STREAM2, + b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); - b = dmaStreamAllocate(STM32_DMA1_STREAM3, + b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART3_IRQ_PRIORITY, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); rccEnableUSART3(FALSE); NVICEnableVector(USART3_IRQn, CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); + uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); } #endif /* Static DMA setup, the transfer size depends on the USART settings, it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ - uartp->dmamode = STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); @@ -432,11 +470,11 @@ void uart_lld_stop(UARTDriver *uartp) { if (uartp->state == UART_READY) { usart_stop(uartp); + dmaStreamRelease(uartp->dmarx); + dmaStreamRelease(uartp->dmatx); #if STM32_UART_USE_USART1 if (&UARTD1 == uartp) { - dmaStreamRelease(STM32_DMA1_STREAM4); - dmaStreamRelease(STM32_DMA1_STREAM5); NVICDisableVector(USART1_IRQn); rccDisableUSART1(FALSE); return; @@ -445,8 +483,6 @@ void uart_lld_stop(UARTDriver *uartp) { #if STM32_UART_USE_USART2 if (&UARTD2 == uartp) { - dmaStreamRelease(STM32_DMA1_STREAM6); - dmaStreamRelease(STM32_DMA1_STREAM7); NVICDisableVector(USART2_IRQn); rccDisableUSART2(FALSE); return; @@ -455,8 +491,6 @@ void uart_lld_stop(UARTDriver *uartp) { #if STM32_UART_USE_USART3 if (&UARTD3 == uartp) { - dmaStreamRelease(STM32_DMA1_STREAM2); - dmaStreamRelease(STM32_DMA1_STREAM3); NVICDisableVector(USART3_IRQn); rccDisableUSART3(FALSE); return; @@ -482,8 +516,7 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { dmaStreamSetMemory0(uartp->dmatx, txbuf); dmaStreamSetTransactionSize(uartp->dmatx, n); dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | - STM32_DMA_CR_MINC | STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE); + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); dmaStreamEnable(uartp->dmatx); } @@ -526,8 +559,7 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { dmaStreamSetMemory0(uartp->dmarx, rxbuf); dmaStreamSetTransactionSize(uartp->dmarx, n); dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MINC | STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE); + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); dmaStreamEnable(uartp->dmarx); } diff --git a/os/hal/platforms/STM32/uart_lld.h b/os/hal/platforms/STM32/uart_lld.h index d97bea91b..742a8a37d 100644 --- a/os/hal/platforms/STM32/uart_lld.h +++ b/os/hal/platforms/STM32/uart_lld.h @@ -110,6 +110,7 @@ #if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) #define STM32_UART_USART2_DMA_PRIORITY 0 #endif + /** * @brief USART3 DMA priority (0..3|lowest..highest). * @note The priority level is used for both the TX and RX DMA channels but @@ -128,6 +129,69 @@ #if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() #endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for USART1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#endif + +/** + * @brief DMA stream used for USART1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#endif + +/** + * @brief DMA stream used for USART2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#endif + +/** + * @brief DMA stream used for USART2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#endif + +/** + * @brief DMA stream used for USART3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#endif + +/** + * @brief DMA stream used for USART3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#endif /* !STM32_ADVANCED_DMA*/ /** @} */ /*===========================================================================*/ @@ -151,6 +215,42 @@ #error "UART driver activated but no USART/UART peripheral assigned" #endif +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \ + STM32_USART1_RX_DMA_MSK) +#error "invalid DMA stream associated to USART1 RX" +#endif + +#if STM32_UART_USE_USART1 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \ + STM32_USART1_TX_DMA_MSK) +#error "invalid DMA stream associated to USART1 TX" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \ + STM32_USART2_RX_DMA_MSK) +#error "invalid DMA stream associated to USART2 RX" +#endif + +#if STM32_UART_USE_USART2 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \ + STM32_USART2_TX_DMA_MSK) +#error "invalid DMA stream associated to USART2 TX" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \ + STM32_USART3_RX_DMA_MSK) +#error "invalid DMA stream associated to USART3 RX" +#endif + +#if STM32_UART_USE_USART3 && \ + !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \ + STM32_USART3_TX_DMA_MSK) +#error "invalid DMA stream associated to USART3 TX" +#endif + #if !defined(STM32_DMA_REQUIRED) #define STM32_DMA_REQUIRED #endif diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 91be2eadb..3f5d9502b 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -212,11 +212,40 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART3 FALSE +#define STM32_USART3_RX_DMA_MSK 0 +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK 0 +#define STM32_USART3_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 /* USB attributes.*/ #define STM32_HAS_USB FALSE diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 4090502a1..22d955c65 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -223,11 +223,40 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART3 FALSE +#define STM32_USART3_RX_DMA_MSK 0 +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK 0 +#define STM32_USART3_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 /* USB attributes.*/ #define STM32_HAS_USB FALSE @@ -326,11 +355,40 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 /* USB attributes.*/ #define STM32_HAS_USB TRUE @@ -429,11 +487,40 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 /* USB attributes.*/ #define STM32_HAS_USB TRUE @@ -532,11 +619,40 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 /* USB attributes.*/ #define STM32_HAS_USB TRUE diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index dff2f7b2e..882ec6094 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -215,11 +215,40 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_UART4_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 /* USB attributes.*/ #define STM32_HAS_USB FALSE diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index 5edac0163..a4bfac99f 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -80,7 +80,7 @@ ADCDriver ADCD3; static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { /* DMA errors handling.*/ - if ((flags & STM32_DMA_ISR_TEIF) != 0) { + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { /* DMA, this could help only if the DMA tries to access an unmapped address space or violates alignment rules.*/ _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 71207efd5..bdb8cb86b 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -349,11 +349,44 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + #define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART2_RX_DMA_CHN 0x00400000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + #define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) +#define STM32_USART3_RX_DMA_CHN 0x00400400 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART3_TX_DMA_CHN 0x00074040 + #define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_UART4_RX_DMA_CHN 0x00000400 +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_UART4_TX_DMA_CHN 0x00040000 + #define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) +#define STM32_UART5_RX_DMA_CHN 0x00000004 +#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_UART5_TX_DMA_CHN 0x40000000 + #define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) | \ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 /* USB attributes.*/ #define STM32_HAS_USB FALSE diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index d62176a16..b6b0060d6 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -251,11 +251,40 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + #define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 /* USB attributes.*/ #define STM32_HAS_USB TRUE diff --git a/testhal/STM32F4xx/ADC/mcuconf.h b/testhal/STM32F4xx/ADC/mcuconf.h index e3f9b95db..b0611f1e6 100644 --- a/testhal/STM32F4xx/ADC/mcuconf.h +++ b/testhal/STM32F4xx/ADC/mcuconf.h @@ -176,7 +176,7 @@ #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 @@ -191,6 +191,12 @@ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 diff --git a/testhal/STM32F4xx/GPT/mcuconf.h b/testhal/STM32F4xx/GPT/mcuconf.h index 4f0647db3..b0611f1e6 100644 --- a/testhal/STM32F4xx/GPT/mcuconf.h +++ b/testhal/STM32F4xx/GPT/mcuconf.h @@ -64,9 +64,20 @@ /* * ADC driver system settings. */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 #define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. @@ -165,7 +176,7 @@ #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 @@ -180,6 +191,12 @@ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 diff --git a/testhal/STM32F4xx/IRQ_STORM/mcuconf.h b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h index 59b5989bf..eeeffb742 100644 --- a/testhal/STM32F4xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h @@ -64,9 +64,20 @@ /* * ADC driver system settings. */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 #define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. @@ -126,7 +137,7 @@ */ #define STM32_PWM_USE_ADVANCED FALSE #define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 TRUE +#define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE @@ -165,7 +176,7 @@ #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 @@ -180,6 +191,12 @@ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 diff --git a/testhal/STM32F4xx/PWM-ICU/mcuconf.h b/testhal/STM32F4xx/PWM-ICU/mcuconf.h index 06d7a8705..df92209ae 100644 --- a/testhal/STM32F4xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32F4xx/PWM-ICU/mcuconf.h @@ -176,7 +176,7 @@ #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 @@ -191,6 +191,12 @@ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 diff --git a/testhal/STM32F4xx/SPI/mcuconf.h b/testhal/STM32F4xx/SPI/mcuconf.h index 02b8304b0..5f7e3f024 100644 --- a/testhal/STM32F4xx/SPI/mcuconf.h +++ b/testhal/STM32F4xx/SPI/mcuconf.h @@ -176,7 +176,7 @@ #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 @@ -191,6 +191,12 @@ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 diff --git a/testhal/STM32F4xx/UART/Makefile b/testhal/STM32F4xx/UART/Makefile new file mode 100644 index 000000000..9456d0488 --- /dev/null +++ b/testhal/STM32F4xx/UART/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/UART/chconf.h b/testhal/STM32F4xx/UART/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F4xx/UART/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/UART/halconf.h b/testhal/STM32F4xx/UART/halconf.h new file mode 100644 index 000000000..8a458d702 --- /dev/null +++ b/testhal/STM32F4xx/UART/halconf.h @@ -0,0 +1,328 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/UART/main.c b/testhal/STM32F4xx/UART/main.c new file mode 100644 index 000000000..f82c43be0 --- /dev/null +++ b/testhal/STM32F4xx/UART/main.c @@ -0,0 +1,145 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +static VirtualTimer vt1, vt2; + +static void restart(void *p) { + + (void)p; + uartStartSendI(&UARTD2, 14, "Hello World!\r\n"); +} + +static void ledoff(void *p) { + + (void)p; + palClearPad(GPIOD, GPIOD_LED4); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; + palSetPad(GPIOD, GPIOD_LED4); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + palClearPad(GPIOD, GPIOD_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt1)) + chVTResetI(&vt1); + chVTSetI(&vt1, MS2ST(5000), restart, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + /* Flashing the LED each time a character is received.*/ + palSetPad(GPIOD, GPIOD_LED4); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt2)) + chVTResetI(&vt2); + chVTSetI(&vt2, MS2ST(200), ledoff, NULL); + chSysUnlockFromIsr(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + 0, + USART_CR2_LINEN, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the UART driver 2, PA2 and PA3 are routed to USART2. + */ + uartStart(&UARTD2, &uart_cfg_1); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&UARTD2, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/STM32F4xx/UART/mcuconf.h b/testhal/STM32F4xx/UART/mcuconf.h new file mode 100644 index 000000000..b0611f1e6 --- /dev/null +++ b/testhal/STM32F4xx/UART/mcuconf.h @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_HIGH +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2CSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 TRUE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 TRUE +#define STM32_GPT_USE_TIM8 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/testhal/STM32F4xx/UART/readme.txt b/testhal/STM32F4xx/UART/readme.txt new file mode 100644 index 000000000..b649f1398 --- /dev/null +++ b/testhal/STM32F4xx/UART/readme.txt @@ -0,0 +1,31 @@ +***************************************************************************** +** ChibiOS/RT HAL - UART driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx UART driver. + +** Board Setup ** + +- Connect an RS232 transceiver to pins PA2(TX) and PA10(9). +- Connect a terminal emulator to the transceiver (38400-N-8-1). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/UART/main.c b/testhal/STM32L1xx/UART/main.c index 30f4c3326..ce1804f2e 100644 --- a/testhal/STM32L1xx/UART/main.c +++ b/testhal/STM32L1xx/UART/main.c @@ -125,8 +125,7 @@ int main(void) { chSysInit(); /* - * Activates the serial driver 2 using the driver default configuration. - * PA9 and PA10 are routed to USART1. + * Activates the serial driver 1, PA9 and PA10 are routed to USART1. */ uartStart(&UARTD1, &uart_cfg_1); palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); diff --git a/testhal/STM32L1xx/UART/readme.txt b/testhal/STM32L1xx/UART/readme.txt index ac65242ac..2968b2288 100644 --- a/testhal/STM32L1xx/UART/readme.txt +++ b/testhal/STM32L1xx/UART/readme.txt @@ -1,5 +1,5 @@ ***************************************************************************** -** ChibiOS/RT HAL - UART driver demo for STM32F1xx. ** +** ChibiOS/RT HAL - UART driver demo for STM32L1xx. ** ***************************************************************************** ** TARGET ** -- cgit v1.2.3 From 63ae69408a2839eaa595117c126be11b58996416 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Nov 2011 21:46:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3521 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/reports/STM32F107-72-GCC.txt | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/docs/reports/STM32F107-72-GCC.txt b/docs/reports/STM32F107-72-GCC.txt index 3240b2663..0a1ec3e0e 100644 --- a/docs/reports/STM32F107-72-GCC.txt +++ b/docs/reports/STM32F107-72-GCC.txt @@ -5,11 +5,13 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) *** ChibiOS/RT test suite *** -*** Kernel: 2.3.1unstable -*** GCC Version: 4.5.2 +*** Kernel: 2.3.4unstable +*** Compiled: Nov 23 2011 - 22:42:22 +*** Compiler: GCC 4.6.2 *** Architecture: ARMv7-M *** Core Variant: Cortex-M3 -*** Platform: STM32 Connectivity Line +*** Port Info: Advanced kernel mode +*** Platform: STM32F1 Connectivity Line *** Test Board: Olimex STM32-P107 ---------------------------------------------------------------------------- @@ -98,56 +100,56 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.1 (Benchmark, messages #1) ---- Score : 249426 msgs/S, 498852 ctxswc/S +--- Score : 266998 msgs/S, 533996 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.2 (Benchmark, messages #2) ---- Score : 198438 msgs/S, 396876 ctxswc/S +--- Score : 213739 msgs/S, 427478 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.3 (Benchmark, messages #3) ---- Score : 198438 msgs/S, 396876 ctxswc/S +--- Score : 213739 msgs/S, 427478 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.4 (Benchmark, context switch) ---- Score : 848888 ctxswc/S +--- Score : 962400 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.5 (Benchmark, threads, full cycle) ---- Score : 156166 threads/S +--- Score : 159245 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.6 (Benchmark, threads, create only) ---- Score : 235534 threads/S +--- Score : 236248 threads/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) ---- Score : 61032 reschedules/S, 366192 ctxswc/S +--- Score : 64816 reschedules/S, 388896 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.8 (Benchmark, round robin context switching) ---- Score : 472600 ctxswc/S +--- Score : 474824 ctxswc/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 478964 bytes/S +--- Score : 607996 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.10 (Benchmark, virtual timers set/reset) ---- Score : 644340 timers/S +--- Score : 644128 timers/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.11 (Benchmark, semaphores wait/signal) ---- Score : 787320 wait+signal/S +--- Score : 787068 wait+signal/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.12 (Benchmark, mutexes lock/unlock) ---- Score : 586488 lock+unlock/S +--- Score : 595996 lock+unlock/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.13 (Benchmark, RAM footprint) ---- System: 360 bytes ---- Thread: 68 bytes +--- System: 376 bytes +--- Thread: 72 bytes --- Timer : 20 bytes --- Semaph: 12 bytes --- EventS: 4 bytes -- cgit v1.2.3 From 5a74dd3c2e3aa7c2a72f1bfe69a39b047710c429 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Nov 2011 22:01:13 +0000 Subject: Fixed a problem of inclusion order that caused DMA2 problems in STM32 HAls. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3522 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/hal_lld.h | 8 ++++---- os/hal/platforms/STM32F4xx/hal_lld.h | 8 ++++---- os/hal/platforms/STM32L1xx/hal_lld.h | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index a4ccd3118..b1ba1a5ed 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -45,10 +45,6 @@ #include "stm32f10x.h" -/* STM32 DMA and RCC helpers.*/ -#include "stm32_dma.h" -#include "stm32_rcc.h" - /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -155,6 +151,10 @@ typedef struct { /* External declarations. */ /*===========================================================================*/ +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index bdb8cb86b..29018e86f 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -40,10 +40,6 @@ #include "stm32f4xx.h" -/* STM32 DMA and RCC helpers.*/ -#include "stm32_dma.h" -#include "stm32_rcc.h" - /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -1344,6 +1340,10 @@ typedef struct { /* External declarations. */ /*===========================================================================*/ +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index b6b0060d6..fe2909536 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -39,10 +39,6 @@ #include "stm32l1xx.h" -/* STM32 DMA and RCC helpers.*/ -#include "stm32_dma.h" -#include "stm32_rcc.h" - /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -1009,6 +1005,10 @@ typedef struct { /* External declarations. */ /*===========================================================================*/ +/* STM32 DMA and RCC helpers.*/ +#include "stm32_dma.h" +#include "stm32_rcc.h" + #ifdef __cplusplus extern "C" { #endif -- cgit v1.2.3 From 46870077b874696c09704da37dc4c33c8eb21402 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 24 Nov 2011 17:58:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3523 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32L152-DISCOVERY/main.c | 4 +- demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h | 3 +- os/hal/platforms/STM32/ext_lld.c | 16 +- os/hal/platforms/STM32L1xx/adc_lld.c | 81 +++-- os/hal/platforms/STM32L1xx/adc_lld.h | 14 +- readme.txt | 2 - testhal/STM32F4xx/EXT/Makefile | 207 +++++++++++ testhal/STM32F4xx/EXT/chconf.h | 535 +++++++++++++++++++++++++++++ testhal/STM32F4xx/EXT/halconf.h | 335 ++++++++++++++++++ testhal/STM32F4xx/EXT/main.c | 110 ++++++ testhal/STM32F4xx/EXT/mcuconf.h | 206 +++++++++++ testhal/STM32F4xx/EXT/readme.txt | 30 ++ testhal/STM32L1xx/ADC/main.c | 18 +- testhal/STM32L1xx/ADC/mcuconf.h | 3 +- testhal/STM32L1xx/EXT/mcuconf.h | 3 +- testhal/STM32L1xx/GPT/mcuconf.h | 3 +- testhal/STM32L1xx/IRQ_STORM/mcuconf.h | 3 +- testhal/STM32L1xx/PWM-ICU/mcuconf.h | 3 +- testhal/STM32L1xx/SPI/mcuconf.h | 3 +- testhal/STM32L1xx/UART/mcuconf.h | 3 +- 20 files changed, 1515 insertions(+), 67 deletions(-) create mode 100644 testhal/STM32F4xx/EXT/Makefile create mode 100644 testhal/STM32F4xx/EXT/chconf.h create mode 100644 testhal/STM32F4xx/EXT/halconf.h create mode 100644 testhal/STM32F4xx/EXT/main.c create mode 100644 testhal/STM32F4xx/EXT/mcuconf.h create mode 100644 testhal/STM32F4xx/EXT/readme.txt diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/main.c b/demos/ARMCM3-STM32L152-DISCOVERY/main.c index 3b538854f..7eb3815fc 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32L152-DISCOVERY/main.c @@ -49,8 +49,8 @@ static const ADCConversionGroup adcgrpcfg = { adccb, NULL, /* HW dependent part.*/ - 0, - 0, + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ 0, ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192), 0, diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h index b29e6a6fa..ab26b77a3 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/mcuconf.h @@ -61,7 +61,8 @@ */ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. diff --git a/os/hal/platforms/STM32/ext_lld.c b/os/hal/platforms/STM32/ext_lld.c index 13eca6f3b..c9b4b75c2 100644 --- a/os/hal/platforms/STM32/ext_lld.c +++ b/os/hal/platforms/STM32/ext_lld.c @@ -282,7 +282,7 @@ CH_IRQ_HANDLER(COMP_IRQHandler) { CH_IRQ_EPILOGUE(); } -#elif defined(STM32F2XX) +#elif defined(STM32F2XX) || defined(STM32F4XX) /** * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). * @@ -462,15 +462,15 @@ void ext_lld_start(EXTDriver *extp) { CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); NVICEnableVector(COMP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); -#elif defined(STM32F2XX) - /* EXTI vectors specific to STM32F2xx.*/ +#elif defined(STM32F2XX) || defined(STM32F4XX) + /* EXTI vectors specific to STM32F2xx/STM32F4xx.*/ NVICEnableVector(OTG_FS_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); NVICEnableVector(ETH_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); NVICEnableVector(OTG_HS_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); - NVICEnableVector(TAMPER_STAMP_IRQn, + NVICEnableVector(TAMP_STAMP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); NVICEnableVector(RTC_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY)); @@ -500,7 +500,7 @@ void ext_lld_start(EXTDriver *extp) { ftsr |= (1 << i); } } -#if defined(STM32L1XX_MD) || defined(STM32F2XX) +#if defined(STM32L1XX_MD) || defined(STM32F2XX) || defined(STM32F4XX) SYSCFG->EXTICR[0] = extp->config->exti[0]; SYSCFG->EXTICR[1] = extp->config->exti[1]; SYSCFG->EXTICR[2] = extp->config->exti[2]; @@ -544,12 +544,12 @@ void ext_lld_stop(EXTDriver *extp) { NVICDisableVector(TAMPER_STAMP_IRQn); NVICDisableVector(RTC_WKUP_IRQn); NVICDisableVector(COMP_IRQn); -#elif defined(STM32F2XX) - /* EXTI vectors specific to STM32F2xx.*/ +#elif defined(STM32F2XX) || defined(STM32F4XX) + /* EXTI vectors specific to STM32F2xx/STM32F4xx.*/ NVICDisableVector(OTG_FS_WKUP_IRQn); NVICDisableVector(ETH_WKUP_IRQn); NVICDisableVector(OTG_HS_WKUP_IRQn); - NVICDisableVector(TAMPER_STAMP_IRQn); + NVICDisableVector(TAMP_STAMP_IRQn); NVICDisableVector(RTC_WKUP_IRQn); #elif defined(STM32F10X_CL) /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c index 308fd90d0..428d8e452 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.c +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -57,19 +57,23 @@ ADCDriver ADCD1; static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { /* DMA errors handling.*/ - if ((flags & STM32_DMA_ISR_TEIF) != 0) { + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { /* DMA, this could help only if the DMA tries to access an unmapped address space or violates alignment rules.*/ _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); } else { - if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } } } } @@ -80,7 +84,7 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { #if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) /** - * @brief ADC1 interrupt handler. + * @brief ADC interrupt handler. * * @isr */ @@ -91,10 +95,13 @@ CH_IRQ_HANDLER(ADC1_IRQHandler) { sr = ADC1->SR; ADC1->SR = 0; - if (sr & ADC_SR_OVR) { + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/ - _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + if (ADCD1.grpp != NULL) + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); } /* TODO: Add here analog watchdog handling.*/ @@ -119,11 +126,16 @@ void adc_lld_init(void) { ADCD1.adc = ADC1; ADCD1.dmastp = STM32_DMA1_STREAM1; ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; - ADC->CCR = STM32_ADC_ADCPRE; + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | + STM32_DMA_CR_EN; #endif + + /* The shared vector is initialized on driver initialization and never + disabled.*/ + NVICEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY)); } /** @@ -141,20 +153,20 @@ void adc_lld_start(ADCDriver *adcp) { if (&ADCD1 == adcp) { bool_t b; b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_IRQ_PRIORITY, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, (void *)adcp); chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); rccEnableADC1(FALSE); - NVICEnableVector(ADC1_IRQn, - CORTEX_PRIORITY_MASK(STM32_ADC_ADC1_IRQ_PRIORITY)); } -#endif +#endif /* STM32_ADC_USE_ADC1 */ + - /* ADC initial setup, just resetting control registers in this case.*/ + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; } } @@ -167,15 +179,15 @@ void adc_lld_start(ADCDriver *adcp) { */ void adc_lld_stop(ADCDriver *adcp) { - /* If in ready state then disables the ADC clock.*/ + /* If in ready state then disables the ADC clock and analog part.*/ if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + #if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - ADC1->CR1 = 0; - ADC1->CR2 = 0; - dmaStreamRelease(adcp->dmastp); + if (&ADCD1 == adcp) rccDisableADC1(FALSE); - } #endif } } @@ -208,24 +220,20 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC setup.*/ adcp->adc->SR = 0; - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; - adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ + adcp->adc->SMPR1 = grpp->smpr1; adcp->adc->SMPR2 = grpp->smpr2; adcp->adc->SMPR3 = grpp->smpr3; - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS | - ADC_CR2_ADON; adcp->adc->SQR1 = grpp->sqr1; adcp->adc->SQR2 = grpp->sqr2; adcp->adc->SQR3 = grpp->sqr3; adcp->adc->SQR4 = grpp->sqr4; adcp->adc->SQR5 = grpp->sqr5; - /* Must wait the ADC to be ready for conversion, see 10.3.6 "Timing diagram" - in the Reference Manual.*/ - while ((adcp->adc->SR & ADC_SR_ADONS) == 0) - ; - /* ADC start by raising ADC_CR2_SWSTART.*/ - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_CONT | ADC_CR2_DMA | - ADC_CR2_DDS | ADC_CR2_ADON; + + /* ADC configuration and start, the start is performed using the method + specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | + ADC_CR2_DDS | ADC_CR2_ADON; } /** @@ -240,6 +248,7 @@ void adc_lld_stop_conversion(ADCDriver *adcp) { dmaStreamDisable(adcp->dmastp); adcp->adc->CR1 = 0; adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; } /** diff --git a/os/hal/platforms/STM32L1xx/adc_lld.h b/os/hal/platforms/STM32L1xx/adc_lld.h index 58fb7bda1..29b5ff8c5 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.h +++ b/os/hal/platforms/STM32L1xx/adc_lld.h @@ -133,11 +133,19 @@ #endif /** - * @brief ADC1 interrupt priority level setting. + * @brief ADC interrupt priority level setting. */ -#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_IRQ_PRIORITY 5 #endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + /** @} */ /*===========================================================================*/ diff --git a/readme.txt b/readme.txt index 787f549ef..c3762963f 100644 --- a/readme.txt +++ b/readme.txt @@ -86,8 +86,6 @@ - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). - NEW: Added demo for the ST STM32F4-Discovery kit. - NEW: STM32F4xx ADC driver implementation. - TODO: Backport the new solutions implemented in this ADC driver to the - STM32L1xx ADC driver. - NEW: Added initialization of the NVIC VTOR register to all Cortex-Mx (v7M) ports. Also added a port option CORTEX_VTOR_INIT to enforce a different default value into the register. diff --git a/testhal/STM32F4xx/EXT/Makefile b/testhal/STM32F4xx/EXT/Makefile new file mode 100644 index 000000000..9456d0488 --- /dev/null +++ b/testhal/STM32F4xx/EXT/Makefile @@ -0,0 +1,207 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/testhal/STM32F4xx/EXT/chconf.h b/testhal/STM32F4xx/EXT/chconf.h new file mode 100644 index 000000000..a5d129956 --- /dev/null +++ b/testhal/STM32F4xx/EXT/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/EXT/halconf.h b/testhal/STM32F4xx/EXT/halconf.h new file mode 100644 index 000000000..775428e22 --- /dev/null +++ b/testhal/STM32F4xx/EXT/halconf.h @@ -0,0 +1,335 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intevals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32F4xx/EXT/main.c b/testhal/STM32F4xx/EXT/main.c new file mode 100644 index 000000000..495428478 --- /dev/null +++ b/testhal/STM32F4xx/EXT/main.c @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +static void led5off(void *arg) { + + (void)arg; + palClearPad(GPIOD, GPIOD_LED5); +} + +/* Triggered when the button is pressed or released. The LED5 is set to ON.*/ +static void extcb1(EXTDriver *extp, expchannel_t channel) { + static VirtualTimer vt4; + + (void)extp; + (void)channel; + + palSetPad(GPIOD, GPIOD_LED5); + chSysLockFromIsr(); + if (chVTIsArmedI(&vt4)) + chVTResetI(&vt4); + + /* LED4 set to OFF after 200mS.*/ + chVTSetI(&vt4, MS2ST(200), led5off, NULL); + chSysUnlockFromIsr(); +} + +static const EXTConfig extcfg = { + { + {EXT_CH_MODE_BOTH_EDGES | EXT_CH_MODE_AUTOSTART, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + }, + EXT_MODE_EXTI(EXT_MODE_GPIOA, /* Button.*/ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0) +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the EXT driver 1. + */ + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity, in this demo it enables and disables the + * button EXT channel using 5 seconds intervals. + */ + while (TRUE) { + EXTI->SWIER = 64; + chThdSleepMilliseconds(5000); + extChannelDisable(&EXTD1, 0); + EXTI->SWIER = 64; + chThdSleepMilliseconds(5000); + extChannelEnable(&EXTD1, 0); + } +} diff --git a/testhal/STM32F4xx/EXT/mcuconf.h b/testhal/STM32F4xx/EXT/mcuconf.h new file mode 100644 index 000000000..b0611f1e6 --- /dev/null +++ b/testhal/STM32F4xx/EXT/mcuconf.h @@ -0,0 +1,206 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_HIGH +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2CSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 TRUE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_USE_TIM5 TRUE +#define STM32_GPT_USE_TIM8 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() diff --git a/testhal/STM32F4xx/EXT/readme.txt b/testhal/STM32F4xx/EXT/readme.txt new file mode 100644 index 000000000..6180a7a81 --- /dev/null +++ b/testhal/STM32F4xx/EXT/readme.txt @@ -0,0 +1,30 @@ +***************************************************************************** +** ChibiOS/RT HAL - EXT driver demo for STM32F4xx. ** +***************************************************************************** + +** TARGET ** + +The demo will on an STMicroelectronics STM32F4-Discovery board. + +** The Demo ** + +The application demonstrates the use of the STM32F4xx EXT driver. + +** Board Setup ** + +None required. + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32L1xx/ADC/main.c b/testhal/STM32L1xx/ADC/main.c index c13ebfe2a..2af3703e8 100644 --- a/testhal/STM32L1xx/ADC/main.c +++ b/testhal/STM32L1xx/ADC/main.c @@ -61,12 +61,13 @@ static const ADCConversionGroup adcgrpcfg1 = { ADC_GRP1_NUM_CHANNELS, NULL, adcerrorcallback, - 0, 0, /* CR1, CR2 */ - 0, /* SMPR1 */ + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + 0, /* SMPR1 */ ADC_SMPR2_SMP_AN10(ADC_SAMPLE_4), - 0, /* SMPR3 */ + 0, /* SMPR3 */ ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), - 0, 0, 0, /* SQR2, SQR3, SQR4 */ + 0, 0, 0, /* SQR2, SQR3, SQR4 */ ADC_SQR5_SQ1_N(ADC_CHANNEL_IN10) }; @@ -80,13 +81,14 @@ static const ADCConversionGroup adcgrpcfg2 = { ADC_GRP2_NUM_CHANNELS, adccallback, adcerrorcallback, - 0, 0, /* CR1, CR2 */ - 0, /* SMPR1 */ + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + 0, /* SMPR1 */ ADC_SMPR2_SMP_AN11(ADC_SAMPLE_48) | ADC_SMPR2_SMP_AN10(ADC_SAMPLE_48) | ADC_SMPR2_SMP_SENSOR(ADC_SAMPLE_192) | ADC_SMPR2_SMP_VREF(ADC_SAMPLE_192), - 0, /* SMPR3 */ + 0, /* SMPR3 */ ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS), - 0, 0, /* SQR2, SQR3 */ + 0, 0, /* SQR2, SQR3 */ ADC_SQR4_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR4_SQ7_N(ADC_CHANNEL_VREFINT), ADC_SQR5_SQ6_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ5_N(ADC_CHANNEL_IN10) | ADC_SQR5_SQ4_N(ADC_CHANNEL_IN11) | ADC_SQR5_SQ3_N(ADC_CHANNEL_IN10) | diff --git a/testhal/STM32L1xx/ADC/mcuconf.h b/testhal/STM32L1xx/ADC/mcuconf.h index b2ad1faca..a75fb49cf 100644 --- a/testhal/STM32L1xx/ADC/mcuconf.h +++ b/testhal/STM32L1xx/ADC/mcuconf.h @@ -61,7 +61,8 @@ */ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/EXT/mcuconf.h b/testhal/STM32L1xx/EXT/mcuconf.h index b2ad1faca..a75fb49cf 100644 --- a/testhal/STM32L1xx/EXT/mcuconf.h +++ b/testhal/STM32L1xx/EXT/mcuconf.h @@ -61,7 +61,8 @@ */ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/GPT/mcuconf.h b/testhal/STM32L1xx/GPT/mcuconf.h index b2ad1faca..a75fb49cf 100644 --- a/testhal/STM32L1xx/GPT/mcuconf.h +++ b/testhal/STM32L1xx/GPT/mcuconf.h @@ -61,7 +61,8 @@ */ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h index b4e3ea258..b17805089 100644 --- a/testhal/STM32L1xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32L1xx/IRQ_STORM/mcuconf.h @@ -61,7 +61,8 @@ */ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/PWM-ICU/mcuconf.h b/testhal/STM32L1xx/PWM-ICU/mcuconf.h index 433013b38..b1e760697 100644 --- a/testhal/STM32L1xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32L1xx/PWM-ICU/mcuconf.h @@ -61,7 +61,8 @@ */ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/SPI/mcuconf.h b/testhal/STM32L1xx/SPI/mcuconf.h index 116f26170..0e6333b7a 100644 --- a/testhal/STM32L1xx/SPI/mcuconf.h +++ b/testhal/STM32L1xx/SPI/mcuconf.h @@ -61,7 +61,8 @@ */ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. diff --git a/testhal/STM32L1xx/UART/mcuconf.h b/testhal/STM32L1xx/UART/mcuconf.h index d1b9069be..8a232fe4d 100644 --- a/testhal/STM32L1xx/UART/mcuconf.h +++ b/testhal/STM32L1xx/UART/mcuconf.h @@ -61,7 +61,8 @@ */ #define STM32_ADC_USE_ADC1 TRUE #define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 /* * CAN driver system settings. -- cgit v1.2.3 From e6b38cdd3741b822c3be51aba268f90fc1771032 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 24 Nov 2011 21:00:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3524 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/adc_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c index 428d8e452..3d91a9991 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.c +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -162,10 +162,10 @@ void adc_lld_start(ADCDriver *adcp) { } #endif /* STM32_ADC_USE_ADC1 */ - /* ADC initial setup, starting the analog part here in order to reduce the latency when starting a conversion.*/ adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; adcp->adc->CR2 = ADC_CR2_ADON; } } -- cgit v1.2.3 From f3bbf4800acff7c34a24306c534b7414fd481b6a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 24 Nov 2011 21:25:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3525 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/adc_lld.c | 1 + 1 file changed, 1 insertion(+) diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index a4bfac99f..777804b5a 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -276,6 +276,7 @@ void adc_lld_start(ADCDriver *adcp) { /* ADC initial setup, starting the analog part here in order to reduce the latency when starting a conversion.*/ adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; adcp->adc->CR2 = ADC_CR2_ADON; } } -- cgit v1.2.3 From c1a535d343d6ea6e84f99b9b0b760d9a582ad969 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Nov 2011 10:30:56 +0000 Subject: Unified STM32 registers header file stm32.h. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3526 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/gpt_lld.c | 14 +-- os/hal/platforms/STM32/gpt_lld.h | 2 +- os/hal/platforms/STM32/icu_lld.c | 12 +-- os/hal/platforms/STM32/icu_lld.h | 2 +- os/hal/platforms/STM32/pwm_lld.c | 12 +-- os/hal/platforms/STM32/pwm_lld.h | 2 +- os/hal/platforms/STM32/stm32.h | 169 +++++++++++++++++++++++++++++++++ os/hal/platforms/STM32F1xx/hal_lld.h | 43 +-------- os/hal/platforms/STM32F1xx/stm32f10x.h | 3 - os/hal/platforms/STM32F2xx/stm32f2xx.h | 3 + os/hal/platforms/STM32F4xx/hal_lld.h | 43 +-------- os/hal/platforms/STM32F4xx/stm32f4xx.h | 5 +- os/hal/platforms/STM32L1xx/hal_lld.h | 43 +-------- os/hal/platforms/STM32L1xx/stm32l1xx.h | 4 +- readme.txt | 6 +- 15 files changed, 204 insertions(+), 159 deletions(-) create mode 100644 os/hal/platforms/STM32/stm32.h diff --git a/os/hal/platforms/STM32/gpt_lld.c b/os/hal/platforms/STM32/gpt_lld.c index af8737f04..e40843ccb 100644 --- a/os/hal/platforms/STM32/gpt_lld.c +++ b/os/hal/platforms/STM32/gpt_lld.c @@ -192,7 +192,7 @@ CH_IRQ_HANDLER(TIM5_IRQHandler) { #if STM32_GPT_USE_TIM8 /** - * @brief TIM5 interrupt handler. + * @brief TIM8 interrupt handler. * * @isr */ @@ -219,37 +219,37 @@ void gpt_lld_init(void) { #if STM32_GPT_USE_TIM1 /* Driver initialization.*/ - GPTD1.tim = TIM1; + GPTD1.tim = STM32_TIM1; gptObjectInit(&GPTD1); #endif #if STM32_GPT_USE_TIM2 /* Driver initialization.*/ - GPTD2.tim = TIM2; + GPTD2.tim = STM32_TIM2; gptObjectInit(&GPTD2); #endif #if STM32_GPT_USE_TIM3 /* Driver initialization.*/ - GPTD3.tim = TIM3; + GPTD3.tim = STM32_TIM3; gptObjectInit(&GPTD3); #endif #if STM32_GPT_USE_TIM4 /* Driver initialization.*/ - GPTD4.tim = TIM4; + GPTD4.tim = STM32_TIM4; gptObjectInit(&GPTD4); #endif #if STM32_GPT_USE_TIM5 /* Driver initialization.*/ - GPTD5.tim = TIM5; + GPTD5.tim = STM32_TIM5; gptObjectInit(&GPTD5); #endif #if STM32_GPT_USE_TIM8 /* Driver initialization.*/ - GPTD5.tim = TIM8; + GPTD5.tim = STM32_TIM8; gptObjectInit(&GPTD8); #endif } diff --git a/os/hal/platforms/STM32/gpt_lld.h b/os/hal/platforms/STM32/gpt_lld.h index f61c5d030..13c5e1f4b 100644 --- a/os/hal/platforms/STM32/gpt_lld.h +++ b/os/hal/platforms/STM32/gpt_lld.h @@ -230,7 +230,7 @@ struct GPTDriver { /** * @brief Pointer to the TIMx registers block. */ - TIM_TypeDef *tim; + stm32_tim_t *tim; }; /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c index ab3e12f26..e76f8a109 100644 --- a/os/hal/platforms/STM32/icu_lld.c +++ b/os/hal/platforms/STM32/icu_lld.c @@ -239,37 +239,37 @@ void icu_lld_init(void) { #if STM32_ICU_USE_TIM1 /* Driver initialization.*/ icuObjectInit(&ICUD1); - ICUD1.tim = TIM1; + ICUD1.tim = STM32_TIM1; #endif #if STM32_ICU_USE_TIM2 /* Driver initialization.*/ icuObjectInit(&ICUD2); - ICUD2.tim = TIM2; + ICUD2.tim = STM32_TIM2; #endif #if STM32_ICU_USE_TIM3 /* Driver initialization.*/ icuObjectInit(&ICUD3); - ICUD3.tim = TIM3; + ICUD3.tim = STM32_TIM3; #endif #if STM32_ICU_USE_TIM4 /* Driver initialization.*/ icuObjectInit(&ICUD4); - ICUD4.tim = TIM4; + ICUD4.tim = STM32_TIM4; #endif #if STM32_ICU_USE_TIM5 /* Driver initialization.*/ icuObjectInit(&ICUD5); - ICUD5.tim = TIM5; + ICUD5.tim = STM32_TIM5; #endif #if STM32_ICU_USE_TIM8 /* Driver initialization.*/ icuObjectInit(&ICUD8); - ICUD5.tim = TIM8; + ICUD5.tim = STM32_TIM8; #endif } diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h index b97930609..f5b6bf695 100644 --- a/os/hal/platforms/STM32/icu_lld.h +++ b/os/hal/platforms/STM32/icu_lld.h @@ -245,7 +245,7 @@ struct ICUDriver { /** * @brief Pointer to the TIMx registers block. */ - TIM_TypeDef *tim; + stm32_tim_t *tim; }; /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index fb5d12adf..4392d5db9 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -297,37 +297,37 @@ void pwm_lld_init(void) { #if STM32_PWM_USE_TIM1 /* Driver initialization.*/ pwmObjectInit(&PWMD1); - PWMD1.tim = TIM1; + PWMD1.tim = STM32_TIM1; #endif #if STM32_PWM_USE_TIM2 /* Driver initialization.*/ pwmObjectInit(&PWMD2); - PWMD2.tim = TIM2; + PWMD2.tim = STM32_TIM2; #endif #if STM32_PWM_USE_TIM3 /* Driver initialization.*/ pwmObjectInit(&PWMD3); - PWMD3.tim = TIM3; + PWMD3.tim = STM32_TIM3; #endif #if STM32_PWM_USE_TIM4 /* Driver initialization.*/ pwmObjectInit(&PWMD4); - PWMD4.tim = TIM4; + PWMD4.tim = STM32_TIM4; #endif #if STM32_PWM_USE_TIM5 /* Driver initialization.*/ pwmObjectInit(&PWMD5); - PWMD5.tim = TIM5; + PWMD5.tim = STM32_TIM5; #endif #if STM32_PWM_USE_TIM8 /* Driver initialization.*/ pwmObjectInit(&PWMD8); - PWMD8.tim = TIM8; + PWMD8.tim = STM32_TIM8; #endif } diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index 78e411592..ca890e8f0 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -327,7 +327,7 @@ struct PWMDriver { /** * @brief Pointer to the TIMx registers block. */ - TIM_TypeDef *tim; + stm32_tim_t *tim; }; /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/stm32.h b/os/hal/platforms/STM32/stm32.h new file mode 100644 index 000000000..0ee083dcc --- /dev/null +++ b/os/hal/platforms/STM32/stm32.h @@ -0,0 +1,169 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/stm32.h + * @brief STM32 common header. + * @pre One of the following macros must be defined before including + * this header, the macro selects the inclusion of the appropriate + * vendor header: + * - STM32F10X_LD_VL for Value Line Low Density devices. + * - STM32F10X_MD_VL for Value Line Medium Density devices. + * - STM32F10X_LD for Performance Low Density devices. + * - STM32F10X_MD for Performance Medium Density devices. + * - STM32F10X_HD for Performance High Density devices. + * - STM32F10X_XL for Performance eXtra Density devices. + * - STM32F10X_CL for Connectivity Line devices. + * - STM32F2XX for High-performance STM32 F-2 devices. + * - STM32F4XX for High-performance STM32 F-4 devices. + * - STM32L1XX_MD for Ultra Low Power Medium-density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _STM32_H_ +#define _STM32_H_ + +#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \ + defined(STM32F10X_MD) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) || \ + defined(__DOXYGEN__) +#include "stm32f10x.h" +#endif + +#if defined(STM32F2XX) || defined(__DOXYGEN__) +#include "stm32f2xx.h" +#endif + +#if defined(STM32F4XX) || defined(__DOXYGEN__) +#include "stm32f4xx.h" +#endif + +#if defined(STM32L1XX_MD) || defined(__DOXYGEN__) +#include "stm32l1xx.h" +#endif + +#undef TIM1 +#undef TIM2 +#undef TIM3 +#undef TIM4 +#undef TIM5 +#undef TIM6 +#undef TIM7 +#undef TIM8 +#undef TIM9 +#undef TIM10 +#undef TIM11 +#undef TIM12 +#undef TIM13 +#undef TIM14 + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 TIM registers block. + * @note Redefined from the ST headers because the non uniform + * declaration of the CCR registers among the various + * sub-families. + */ +typedef struct { + volatile uint16_t CR1; + uint16_t _resvd0; + volatile uint16_t CR2; + uint16_t _resvd1; + volatile uint16_t SMCR; + uint16_t _resvd2; + volatile uint16_t DIER; + uint16_t _resvd3; + volatile uint16_t SR; + uint16_t _resvd4; + volatile uint16_t EGR; + uint16_t _resvd5; + volatile uint16_t CCMR1; + uint16_t _resvd6; + volatile uint16_t CCMR2; + uint16_t _resvd7; + volatile uint16_t CCER; + uint16_t _resvd8; + volatile uint32_t CNT; + volatile uint16_t PSC; + uint16_t _resvd9; + volatile uint32_t ARR; + volatile uint16_t RCR; + uint16_t _resvd10; + volatile uint32_t CCR[4]; + volatile uint16_t BDTR; + uint16_t _resvd11; + volatile uint16_t DCR; + uint16_t _resvd12; + volatile uint16_t DMAR; + uint16_t _resvd13; + volatile uint16_t OR; + uint16_t _resvd14; +} stm32_tim_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name TIM units references + * @{ + */ +#define STM32_TIM1 ((stm32_tim_t *)TIM1_BASE) +#define STM32_TIM2 ((stm32_tim_t *)TIM2_BASE) +#define STM32_TIM3 ((stm32_tim_t *)TIM3_BASE) +#define STM32_TIM4 ((stm32_tim_t *)TIM4_BASE) +#define STM32_TIM5 ((stm32_tim_t *)TIM5_BASE) +#define STM32_TIM6 ((stm32_tim_t *)TIM6_BASE) +#define STM32_TIM7 ((stm32_tim_t *)TIM7_BASE) +#define STM32_TIM8 ((stm32_tim_t *)TIM8_BASE) +#define STM32_TIM9 ((stm32_tim_t *)TIM9_BASE) +#define STM32_TIM10 ((stm32_tim_t *)TIM10_BASE) +#define STM32_TIM11 ((stm32_tim_t *)TIM11_BASE) +#define STM32_TIM12 ((stm32_tim_t *)TIM12_BASE) +#define STM32_TIM13 ((stm32_tim_t *)TIM13_BASE) +#define STM32_TIM14 ((stm32_tim_t *)TIM14_BASE) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* _STM32_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index b1ba1a5ed..64cf0165c 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -43,7 +43,7 @@ #ifndef _HAL_LLD_H_ #define _HAL_LLD_H_ -#include "stm32f10x.h" +#include "stm32.h" /*===========================================================================*/ /* Driver constants. */ @@ -102,47 +102,6 @@ /* Driver data structures and types. */ /*===========================================================================*/ -/** - * @brief STM32 TIM registers block. - * @note Removed from the ST headers and redefined because the non uniform - * declaration of the CCR registers among the various sub-families. - */ -typedef struct { - volatile uint16_t CR1; - uint16_t _resvd0; - volatile uint16_t CR2; - uint16_t _resvd1; - volatile uint16_t SMCR; - uint16_t _resvd2; - volatile uint16_t DIER; - uint16_t _resvd3; - volatile uint16_t SR; - uint16_t _resvd4; - volatile uint16_t EGR; - uint16_t _resvd5; - volatile uint16_t CCMR1; - uint16_t _resvd6; - volatile uint16_t CCMR2; - uint16_t _resvd7; - volatile uint16_t CCER; - uint16_t _resvd8; - volatile uint32_t CNT; - volatile uint16_t PSC; - uint16_t _resvd9; - volatile uint32_t ARR; - volatile uint16_t RCR; - uint16_t _resvd10; - volatile uint32_t CCR[4]; - volatile uint16_t BDTR; - uint16_t _resvd11; - volatile uint16_t DCR; - uint16_t _resvd12; - volatile uint16_t DMAR; - uint16_t _resvd13; - volatile uint16_t OR; - uint16_t _resvd14; -} TIM_TypeDef; - /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/stm32f10x.h b/os/hal/platforms/STM32F1xx/stm32f10x.h index e8f413763..6697b9648 100644 --- a/os/hal/platforms/STM32F1xx/stm32f10x.h +++ b/os/hal/platforms/STM32F1xx/stm32f10x.h @@ -1198,8 +1198,6 @@ typedef struct * @brief TIM */ -/* CHIBIOS FIX */ -#if 0 typedef struct { __IO uint16_t CR1; @@ -1243,7 +1241,6 @@ typedef struct __IO uint16_t DMAR; uint16_t RESERVED19; } TIM_TypeDef; -#endif /** * @brief Universal Synchronous Asynchronous Receiver Transmitter diff --git a/os/hal/platforms/STM32F2xx/stm32f2xx.h b/os/hal/platforms/STM32F2xx/stm32f2xx.h index 51bcaf363..5c6e27d76 100644 --- a/os/hal/platforms/STM32F2xx/stm32f2xx.h +++ b/os/hal/platforms/STM32F2xx/stm32f2xx.h @@ -227,6 +227,7 @@ typedef enum IRQn */ #include "core_cm3.h" +/* CHIBIOS FIX */ /* #include "system_stm32f2xx.h" */ #include @@ -634,6 +635,7 @@ typedef struct /** * @brief General Purpose I/O */ +/* CHIBIOS FIX */ #if 0 typedef struct { @@ -649,6 +651,7 @@ typedef struct __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */ } GPIO_TypeDef; #endif + /** * @brief System configuration controller */ diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 29018e86f..a4dd1b775 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -38,7 +38,7 @@ #ifndef _HAL_LLD_H_ #define _HAL_LLD_H_ -#include "stm32f4xx.h" +#include "stm32.h" /*===========================================================================*/ /* Driver constants. */ @@ -1291,47 +1291,6 @@ /* Driver data structures and types. */ /*===========================================================================*/ -/** - * @brief STM32 TIM registers block. - * @note Removed from the ST headers and redefined because the non uniform - * declaration of the CCR registers among the various sub-families. - */ -typedef struct { - volatile uint16_t CR1; - uint16_t _resvd0; - volatile uint16_t CR2; - uint16_t _resvd1; - volatile uint16_t SMCR; - uint16_t _resvd2; - volatile uint16_t DIER; - uint16_t _resvd3; - volatile uint16_t SR; - uint16_t _resvd4; - volatile uint16_t EGR; - uint16_t _resvd5; - volatile uint16_t CCMR1; - uint16_t _resvd6; - volatile uint16_t CCMR2; - uint16_t _resvd7; - volatile uint16_t CCER; - uint16_t _resvd8; - volatile uint32_t CNT; - volatile uint16_t PSC; - uint16_t _resvd9; - volatile uint32_t ARR; - volatile uint16_t RCR; - uint16_t _resvd10; - volatile uint32_t CCR[4]; - volatile uint16_t BDTR; - uint16_t _resvd11; - volatile uint16_t DCR; - uint16_t _resvd12; - volatile uint16_t DMAR; - uint16_t _resvd13; - volatile uint16_t OR; - uint16_t _resvd14; -} TIM_TypeDef; - /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F4xx/stm32f4xx.h b/os/hal/platforms/STM32F4xx/stm32f4xx.h index cd8ed7887..f4e88fc17 100644 --- a/os/hal/platforms/STM32F4xx/stm32f4xx.h +++ b/os/hal/platforms/STM32F4xx/stm32f4xx.h @@ -237,8 +237,8 @@ typedef enum IRQn * @} */ - /* CHIBIOS FIX */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +/* CHIBIOS FIX */ /*#include "system_stm32f4xx.h"*/ #include @@ -868,8 +868,6 @@ typedef struct * @brief TIM */ -/* CHIBIOS FIX */ -#if 0 typedef struct { __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ @@ -909,7 +907,6 @@ typedef struct __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ uint16_t RESERVED14; /*!< Reserved, 0x52 */ } TIM_TypeDef; -#endif /** * @brief Universal Synchronous Asynchronous Receiver Transmitter diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index fe2909536..b25bad51d 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -37,7 +37,7 @@ #ifndef _HAL_LLD_H_ #define _HAL_LLD_H_ -#include "stm32l1xx.h" +#include "stm32.h" /*===========================================================================*/ /* Driver constants. */ @@ -956,47 +956,6 @@ /* Driver data structures and types. */ /*===========================================================================*/ -/** - * @brief STM32 TIM registers block. - * @note Removed from the ST headers and redefined because the non uniform - * declaration of the CCR registers among the various sub-families. - */ -typedef struct { - volatile uint16_t CR1; - uint16_t _resvd0; - volatile uint16_t CR2; - uint16_t _resvd1; - volatile uint16_t SMCR; - uint16_t _resvd2; - volatile uint16_t DIER; - uint16_t _resvd3; - volatile uint16_t SR; - uint16_t _resvd4; - volatile uint16_t EGR; - uint16_t _resvd5; - volatile uint16_t CCMR1; - uint16_t _resvd6; - volatile uint16_t CCMR2; - uint16_t _resvd7; - volatile uint16_t CCER; - uint16_t _resvd8; - volatile uint32_t CNT; - volatile uint16_t PSC; - uint16_t _resvd9; - volatile uint32_t ARR; - volatile uint16_t RCR; - uint16_t _resvd10; - volatile uint32_t CCR[4]; - volatile uint16_t BDTR; - uint16_t _resvd11; - volatile uint16_t DCR; - uint16_t _resvd12; - volatile uint16_t DMAR; - uint16_t _resvd13; - volatile uint16_t OR; - uint16_t _resvd14; -} TIM_TypeDef; - /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h index 5fadee5db..9c665d29b 100644 --- a/os/hal/platforms/STM32L1xx/stm32l1xx.h +++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h @@ -191,6 +191,7 @@ typedef enum IRQn */ #include "core_cm3.h" +/* CHIBIOS FIX */ /*#include "system_stm32l1xx.h"*/ #include @@ -615,8 +616,6 @@ typedef struct * @brief TIM */ -/* CHIBIOS FIX */ -#if 0 typedef struct { __IO uint16_t CR1; @@ -660,7 +659,6 @@ typedef struct __IO uint16_t OR; uint16_t RESERVED20; } TIM_TypeDef; -#endif /** * @brief Universal Synchronous Asynchronous Receiver Transmitter diff --git a/readme.txt b/readme.txt index c3762963f..fb4e4add2 100644 --- a/readme.txt +++ b/readme.txt @@ -84,6 +84,8 @@ (backported to 2.2.8). - FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620). - FIX: Fixed halconf.h file corrupted in some STM32 demos (bug 3418626). +- NEW: Added an unified registers file for STM32: stm32.h. This file includes + the appropriate vendor file then adds its own additional definitions. - NEW: Added demo for the ST STM32F4-Discovery kit. - NEW: STM32F4xx ADC driver implementation. - NEW: Added initialization of the NVIC VTOR register to all Cortex-Mx (v7M) @@ -94,7 +96,9 @@ - NEW: Reorganized the STM32F1xx hal_lld_xxx.h files in order to distribute the capability macros into the appropriate file (previously those were all in the common hal_lld.h). -- NEW: Added HAL, Serial, SPI support for the STM32F4xx sub-family. +- NEW: Added HAL, Serial, ADC, EXT, GPT, ICU, PWM, SPI and UART support for + the STM32F4xx sub-family. + TODO: Add CAN and SDC, the drivers need to be ported and tested. - NEW: Added handling of USART6 to the STM32 serial driver. - NEW: Added USE_COPT setting to all makefiles, contributed by Mabl. - NEW: Added EXT driver implementation for AT91SAM7x, contributed by Florian. -- cgit v1.2.3 From 163edb0187652af76781cf88a9929b6bd782fe16 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Nov 2011 13:34:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3527 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/GPIOv1/pal_lld.h | 5 + os/hal/platforms/STM32/GPIOv2/pal_lld.h | 26 ++- os/hal/platforms/STM32F4xx/platform.dox | 312 ++++++++++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/platform.dox | 3 - 4 files changed, 335 insertions(+), 11 deletions(-) create mode 100644 os/hal/platforms/STM32F4xx/platform.dox diff --git a/os/hal/platforms/STM32/GPIOv1/pal_lld.h b/os/hal/platforms/STM32/GPIOv1/pal_lld.h index c9bb99de7..ab1c273bc 100644 --- a/os/hal/platforms/STM32/GPIOv1/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv1/pal_lld.h @@ -35,6 +35,10 @@ /* Unsupported modes and specific modes */ /*===========================================================================*/ +/** + * @name STM32-specific I/O mode flags + * @{ + */ /** * @brief STM32 specific alternate push-pull output mode. */ @@ -44,6 +48,7 @@ * @brief STM32 specific alternate open-drain output mode. */ #define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17 +/** @} */ /*===========================================================================*/ /* I/O Ports Types and constants. */ diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h index 60dd84307..ac564e8e3 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -44,6 +44,10 @@ #undef PAL_MODE_OUTPUT_PUSHPULL #undef PAL_MODE_OUTPUT_OPENDRAIN +/** + * @name STM32-specific I/O mode flags + * @{ + */ #define PAL_STM32_MODE_MASK (3 << 0) #define PAL_STM32_MODE_INPUT (0 << 0) #define PAL_STM32_MODE_OUTPUT (1 << 0) @@ -68,6 +72,19 @@ #define PAL_STM32_ALTERNATE_MASK (15 << 7) #define PAL_STM32_ALTERNATE(n) ((n) << 7) +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \ + PAL_STM32_ALTERNATE(n)) +/** @} */ + +/** + * @name Standard I/O mode flags + * @{ + */ /** * @brief This mode is implemented as input. */ @@ -111,14 +128,7 @@ */ #define PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | \ PAL_STM32_OTYPE_OPENDRAIN) - -/** - * @brief Alternate function. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \ - PAL_STM32_ALTERNATE(n)) +/** @} */ /*===========================================================================*/ /* I/O Ports Types and constants. */ diff --git a/os/hal/platforms/STM32F4xx/platform.dox b/os/hal/platforms/STM32F4xx/platform.dox new file mode 100644 index 000000000..ce59d3d99 --- /dev/null +++ b/os/hal/platforms/STM32F4xx/platform.dox @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup STM32F4xx_DRIVERS STM32F4xx Drivers + * @details This section describes all the supported drivers on the STM32F4xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM32F4xx_HAL STM32F4xx Initialization Support + * @details The STM32F4xx HAL support is responsible for system initialization. + * + * @section stm32f4xx_hal_1 Supported HW resources + * - PLL1. + * - PLL2. + * - RCC. + * - Flash. + * . + * @section stm32f4xx_hal_2 STM32F4xx HAL driver implementation features + * - PLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_ADC STM32F4xx ADC Support + * @details The STM32F4xx ADC driver supports the ADC peripherals using DMA + * channels for maximum performance. + * + * @section stm32f4xx_adc_1 Supported HW resources + * - ADC1. + * - ADC2. + * - ADC3. + * - DMA2. + * . + * @section stm32f4xx_adc_2 STM32F4xx ADC driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Streaming conversion using DMA for maximum performance. + * - Programmable ADC interrupt priority level. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - DMA and ADC errors detection. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_EXT STM32F4xx EXT Support + * @details The STM32F4xx EXT driver uses the EXTI peripheral. + * + * @section stm32f4xx_ext_1 Supported HW resources + * - EXTI. + * . + * @section stm32f4xx_ext_2 STM32F4xx EXT driver implementation features + * - Each EXTI channel can be independently enabled and programmed. + * - Programmable EXTI interrupts priority level. + * - Capability to work as event sources (WFE) rather than interrupt sources. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_GPT STM32F4xx GPT Support + * @details The STM32F4xx GPT driver uses the TIMx peripherals. + * + * @section stm32f4xx_gpt_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f4xx_gpt_2 STM32F4xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_ICU STM32F4xx ICU Support + * @details The STM32F4xx ICU driver uses the TIMx peripherals. + * + * @section stm32f4xx_icu_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f4xx_icu_2 STM32F4xx ICU driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_PAL STM32F4xx PAL Support + * @details The STM32F4xx PAL driver uses the GPIO peripherals. + * + * @section stm32f4xx_pal_1 Supported HW resources + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOF. + * - GPIOG. + * - GPIOH. + * - GPIOI. + * . + * @section stm32f4xx_pal_2 STM32F4xx PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 16 bits wide ports. + * - Atomic set/reset functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm32f4xx_pal_3 Supported PAL setup modes + * The STM32F4xx PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_INPUT_PULLDOWN. + * - @p PAL_MODE_INPUT_ANALOG. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * - @p PAL_MODE_ALTERNATE (non standard). + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm32f4xx_pal_4 Suboptimal behavior + * The STM32F4xx GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Pad/port toggling operations are not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_PWM STM32F4xx PWM Support + * @details The STM32F4xx PWM driver uses the TIMx peripherals. + * + * @section stm32f4xx_pwm_1 Supported HW resources + * - TIM1. + * - TIM2. + * - TIM3. + * - TIM4. + * - TIM5. + * - TIM8. + * . + * @section stm32f4xx_pwm_2 STM32F4xx PWM driver implementation features + * - Each timer can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Four independent PWM channels per timer. + * - Programmable TIMx interrupts priority level. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_SERIAL STM32F4xx Serial Support + * @details The STM32F4xx Serial driver uses the USART/UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm32f4xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3. + * - UART4. + * - UART5. + * - USART6. + * . + * @section stm32f4xx_serial_2 STM32F4xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each UART/USART. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_SPI STM32F4xx SPI Support + * @details The SPI driver supports the STM32F4xx SPI peripherals using DMA + * channels for maximum performance. + * + * @section stm32f4xx_spi_1 Supported HW resources + * - SPI1. + * - SPI2. + * - SPI3. + * - DMA1. + * - DMA2. + * . + * @section stm32f4xx_spi_2 STM32F4xx SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each SPI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each SPI. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_UART STM32F4xx UART Support + * @details The UART driver supports the STM32F4xx USART peripherals using DMA + * channels for maximum performance. + * + * @section stm32f4xx_uart_1 Supported HW resources + * The UART driver can support any of the following hardware resources: + * - USART1. + * - USART2. + * - USART3. + * - DMA1. + * - DMA2. + * . + * @section stm32f4xx_uart_2 STM32F4xx UART driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART/USART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Programmable interrupt priority levels for each UART/USART. + * - DMA is used for receiving and transmitting. + * - Programmable DMA bus priority for each DMA channel. + * - Programmable DMA interrupt priority for each DMA channel. + * - Programmable DMA error hook. + * . + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_PLATFORM_DRIVERS STM32F4xx Platform Drivers + * @details Platform support drivers. Platform drivers do not implement HAL + * standard driver templates, their role is to support platform + * specific functionalities. + * + * @ingroup STM32F4xx_DRIVERS + */ + +/** + * @defgroup STM32F4xx_DMA STM32F4xx DMA Support + * @details This DMA helper driver is used by the other drivers in order to + * access the shared DMA resources in a consistent way. + * + * @section stm32f4xx_dma_1 Supported HW resources + * The DMA driver can support any of the following hardware resources: + * - DMA1. + * - DMA2. + * . + * @section stm32f4xx_dma_2 STM32F4xx DMA driver implementation features + * - Exports helper functions/macros to the other drivers that share the + * DMA resource. + * - Automatic DMA clock stop when not in use by any driver. + * - DMA streams and interrupt vectors sharing among multiple drivers. + * . + * @ingroup STM32F4xx_PLATFORM_DRIVERS + */ + +/** + * @defgroup STM32F4xx_RCC STM32F4xx RCC Support + * @details This RCC helper driver is used by the other drivers in order to + * access the shared RCC resources in a consistent way. + * + * @section stm32f1xx_rcc_1 Supported HW resources + * - RCC. + * . + * @section stm32f4xx_rcc_2 STM32F4xx RCC driver implementation features + * - Peripherals reset. + * - Peripherals clock enable. + * - Periplerals clock disable. + * . + * @ingroup STM32F4xx_PLATFORM_DRIVERS + */ diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox index 33bf706ab..cd244a2c9 100644 --- a/os/hal/platforms/STM32L1xx/platform.dox +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -168,7 +168,6 @@ * - TIM2. * - TIM3. * - TIM4. - * - TIM5. * . * @section stm32l1xx_pwm_2 STM32L1xx PWM driver implementation features * - Each timer can be independently enabled and programmed. Unused @@ -237,9 +236,7 @@ * - USART1. * - USART2. * - USART3 (where present). - * - UART4 (where present). * - DMA1. - * - DMA2 (where present). * . * @section stm32l1xx_uart_2 STM32L1xx UART driver implementation features * - Clock stop for reduced power usage when the driver is in stop state. -- cgit v1.2.3 From 0132b4812df3bc3b8c2df9dbea6b75c372ed3453 Mon Sep 17 00:00:00 2001 From: barthess Date: Sat, 26 Nov 2011 15:47:19 +0000 Subject: Fixed mistype in comment. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3528 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/OLIMEX_STM32_103STK/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/OLIMEX_STM32_103STK/board.h b/boards/OLIMEX_STM32_103STK/board.h index a53695906..e8fd9e7dc 100644 --- a/boards/OLIMEX_STM32_103STK/board.h +++ b/boards/OLIMEX_STM32_103STK/board.h @@ -22,7 +22,7 @@ #define _BOARD_H_ /* - * Setup for the Olimex STM33-P103 proto board. + * Setup for the Olimex STM32-103STK proto board. */ /* -- cgit v1.2.3 From f00651ed156298a6030bdba8840726344b9e621c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Nov 2011 16:43:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3529 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/stm32_dma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h index fe15dbd22..bcadf153c 100644 --- a/os/hal/platforms/STM32F4xx/stm32_dma.h +++ b/os/hal/platforms/STM32F4xx/stm32_dma.h @@ -24,7 +24,7 @@ * @note This file requires definitions from the ST STM32F4xx header file * stm32f4xx.h. * - * @addtogroup STM32_DMA + * @addtogroup STM32F4xx_DMA * @{ */ -- cgit v1.2.3 From b7ad6679241b45526b752259488f908828788bea Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Nov 2011 16:48:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3530 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/AT91SAM7/ext_lld.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/os/hal/platforms/AT91SAM7/ext_lld.c b/os/hal/platforms/AT91SAM7/ext_lld.c index 2dbfc1562..bee226ca2 100644 --- a/os/hal/platforms/AT91SAM7/ext_lld.c +++ b/os/hal/platforms/AT91SAM7/ext_lld.c @@ -21,8 +21,8 @@ */ /** - * @file STM32/ext_lld.c - * @brief STM32 EXT subsystem low level driver source. + * @file AT91SAM7/ext_lld.c + * @brief AT91SAM7 EXT subsystem low level driver source. * * @addtogroup EXT * @{ -- cgit v1.2.3 From 64df619cf4d100c7c725873c9e58ce0c4b828209 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Nov 2011 16:54:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3531 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/USBv1/usb_lld.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/os/hal/platforms/STM32/USBv1/usb_lld.c b/os/hal/platforms/STM32/USBv1/usb_lld.c index 3ecf738da..e61fcadae 100644 --- a/os/hal/platforms/STM32/USBv1/usb_lld.c +++ b/os/hal/platforms/STM32/USBv1/usb_lld.c @@ -658,8 +658,6 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { * * @param[in] usbp pointer to the @p USBDriver object * @param[in] ep endpoint number - * @param[in] buf buffer where to fetch the endpoint data - * @param[in] n maximum number of bytes to copy * * @notapi */ -- cgit v1.2.3 From 98807ccef14218336bc10b1d17f3d4404949250d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Nov 2011 20:50:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3532 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp | 6 + docs/reports/STM32F407-168-IAR.txt | 165 ++++++++++++++++++++++++++++ docs/reports/STM32L152-32-GCC.txt | 13 +-- docs/reports/STM32L152-32-IAR.txt | 2 +- docs/reports/STM32L152-32-RVCT.txt | 2 +- 5 files changed, 178 insertions(+), 10 deletions(-) create mode 100644 docs/reports/STM32F407-168-IAR.txt diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp index cf9763bbe..52af4efb6 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp +++ b/demos/ARMCM4-STM32F407-DISCOVERY/iar/ch.ewp @@ -2081,6 +2081,12 @@ platform + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\adc_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\adc_lld.h + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c diff --git a/docs/reports/STM32F407-168-IAR.txt b/docs/reports/STM32F407-168-IAR.txt new file mode 100644 index 000000000..0011dc230 --- /dev/null +++ b/docs/reports/STM32F407-168-IAR.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -Ohs +Settings: SYSCLK=168, ACR=0x705 (5 wait states) +Compiler: IAR C/C++ Compiler for ARM 6.21.4.2946 +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.3.4unstable +*** Compiled: Nov 26 2011 - 21:41:02 +*** Compiler: IAR +*** Architecture: ARMv7-M +*** Core Variant: Cortex-M3 +*** Port Info: Advanced kernel mode +*** Platform: STM32F4 High Performance & DSP +*** Test Board: ST STM32F4-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 676791 msgs/S, 1353582 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 590999 msgs/S, 1181998 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 590999 msgs/S, 1181998 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 2268136 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 408379 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 597316 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 198164 reschedules/S, 1188984 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 1286160 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1669044 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 2124568 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 3010616 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1799916 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/docs/reports/STM32L152-32-GCC.txt b/docs/reports/STM32L152-32-GCC.txt index 8c9b5e380..6f91d94db 100644 --- a/docs/reports/STM32L152-32-GCC.txt +++ b/docs/reports/STM32L152-32-GCC.txt @@ -1,20 +1,17 @@ *************************************************************************** Options: -O2 -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 -Settings: SYSCLK=48, ACR=0x11 (1 wait state) +Settings: SYSCLK=32, ACR=0x11 (1 wait state) *************************************************************************** -*** ChibiOS/RT test suite -*** -*** Kern *** ChibiOS/RT test suite *** *** Kernel: 2.3.4unstable -*** Compiled: Oct 8 2011 - 16:20:37 -*** Compiler: GCC 4.6.0 +*** Compiled: Nov 26 2011 - 21:27:50 +*** Compiler: GCC 4.6.2 *** Architecture: ARMv7-M *** Core Variant: Cortex-M3 *** Port Info: Advanced kernel mode -*** Platform: STM32L Ultra Low Power Medium Density +*** Platform: STM32L1 Ultra Low Power Medium Density *** Test Board: ST STM32L-Discovery ---------------------------------------------------------------------------- @@ -135,7 +132,7 @@ Settings: SYSCLK=48, ACR=0x11 (1 wait state) --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.9 (Benchmark, I/O Queues throughput) ---- Score : 350684 bytes/S +--- Score : 328952 bytes/S --- Result: SUCCESS ---------------------------------------------------------------------------- --- Test Case 11.10 (Benchmark, virtual timers set/reset) diff --git a/docs/reports/STM32L152-32-IAR.txt b/docs/reports/STM32L152-32-IAR.txt index 17ba349f8..8c04ac510 100644 --- a/docs/reports/STM32L152-32-IAR.txt +++ b/docs/reports/STM32L152-32-IAR.txt @@ -1,6 +1,6 @@ *************************************************************************** Options: -Ohs -Settings: SYSCLK=24, ACR=0x10 (no wait states) +Settings: SYSCLK=32, ACR=0x11 (1 wait state) Compiler: IAR C/C++ Compiler for ARM 6.21.4.2946 *************************************************************************** diff --git a/docs/reports/STM32L152-32-RVCT.txt b/docs/reports/STM32L152-32-RVCT.txt index aadaddb7b..be53579aa 100644 --- a/docs/reports/STM32L152-32-RVCT.txt +++ b/docs/reports/STM32L152-32-RVCT.txt @@ -1,6 +1,6 @@ *************************************************************************** Options: -O3 -Otime --apcs=interwork -Settings: SYSCLK=24, ACR=0x10 (no wait states) +Settings: SYSCLK=32, ACR=0x11 (1 wait state) Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. *************************************************************************** -- cgit v1.2.3 From 6d11e44877536fd464bf6afd18b35bb17187f480 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Nov 2011 21:26:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3533 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM4-STM32F407-DISCOVERY/keil/ch.uvproj | 980 ++++++++++++++++++++++++ docs/reports/STM32F407-168-IAR.txt | 6 +- docs/reports/STM32F407-168-RVCT.txt | 165 ++++ os/hal/platforms/STM32F4xx/hal_lld.h | 10 +- os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h | 2 +- os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h | 4 +- os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h | 62 ++ os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s | 338 ++++++++ 8 files changed, 1556 insertions(+), 11 deletions(-) create mode 100644 demos/ARMCM4-STM32F407-DISCOVERY/keil/ch.uvproj create mode 100644 docs/reports/STM32F407-168-RVCT.txt create mode 100644 os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h create mode 100644 os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/keil/ch.uvproj b/demos/ARMCM4-STM32F407-DISCOVERY/keil/ch.uvproj new file mode 100644 index 000000000..24588192f --- /dev/null +++ b/demos/ARMCM4-STM32F407-DISCOVERY/keil/ch.uvproj @@ -0,0 +1,980 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32F407VG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6103 + stm32f4xx.h + + + + + + + + + + SFD\ST\STM32F4xx\STM32F4xx.sfr + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20020000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\os\hal\platforms\STM32\GPIOv2;..\..\..\os\hal\platforms\STM32F4xx;..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\;..\..\..\boards\ST_STM32F4_DISCOVERY;..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\ST_STM32L_DISCOVERY\board.c + + + board.h + 5 + ..\..\..\boards\ST_STM32L_DISCOVERY\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + nvic.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + nvic.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.h + + + cmparams.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\cmparams.h + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\STM32F4xx\vectors.s + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + + + platform + + + adc_lld.c + 1 + ..\..\..\os\hal\platforms\STM32F4xx\adc_lld.c + + + adc_lld.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\adc_lld.h + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32F4xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\hal_lld.h + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.c + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\GPIOv2\pal_lld.h + + + pwm_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + pwm_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\serial_lld.c + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\spi_lld.h + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\spi_lld.c + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\serial_lld.h + + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.c + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\stm32_dma.h + + + stm32_rcc.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\stm32_rcc.h + + + stm32l1xx.h + 5 + ..\..\..\os\hal\platforms\STM32F4xx\stm32l1xx.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + mcuconf.h + 5 + ..\mcuconf.h + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + + + + + + diff --git a/docs/reports/STM32F407-168-IAR.txt b/docs/reports/STM32F407-168-IAR.txt index 0011dc230..566c74038 100644 --- a/docs/reports/STM32F407-168-IAR.txt +++ b/docs/reports/STM32F407-168-IAR.txt @@ -7,10 +7,10 @@ Compiler: IAR C/C++ Compiler for ARM 6.21.4.2946 *** ChibiOS/RT test suite *** *** Kernel: 2.3.4unstable -*** Compiled: Nov 26 2011 - 21:41:02 +*** Compiled: Nov 26 2011 - 22:23:17 *** Compiler: IAR -*** Architecture: ARMv7-M -*** Core Variant: Cortex-M3 +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4 *** Port Info: Advanced kernel mode *** Platform: STM32F4 High Performance & DSP *** Test Board: ST STM32F4-Discovery diff --git a/docs/reports/STM32F407-168-RVCT.txt b/docs/reports/STM32F407-168-RVCT.txt new file mode 100644 index 000000000..40a194098 --- /dev/null +++ b/docs/reports/STM32F407-168-RVCT.txt @@ -0,0 +1,165 @@ +*************************************************************************** +Options: -O3 -Otime --apcs=interwork +Settings: SYSCLK=32, ACR=0x11 (1 wait state) +Compiler: RealView C/C++ Compiler V4.1.0.791 [Evaluation]. +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.3.4unstable +*** Compiled: Nov 26 2011 - 22:18:53 +*** Compiler: RVCT +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4 +*** Port Info: Advanced kernel mode +*** Platform: STM32F4 High Performance & DSP +*** Test Board: ST STM32F4-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 711240 msgs/S, 1422480 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 610371 msgs/S, 1220742 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 610371 msgs/S, 1220742 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 2376704 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 448805 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 640666 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 205448 reschedules/S, 1232688 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 1434640 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1724868 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 2223216 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 3197168 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1929332 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 376 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index a4dd1b775..0650c84f8 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -212,11 +212,11 @@ #define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ #define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ -#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */ -#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */ -#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */ -#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */ -#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */ +#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */ +#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */ +#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */ /** * @name RCC_PLLI2SCFGR register bits definitions diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h index 338fd5363..a5c043e4a 100644 --- a/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/STM32F4xx/cmparams.h @@ -24,7 +24,7 @@ * * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M3 specific parameters for the + * @details This file contains the Cortex-M4 specific parameters for the * STM32F4xx platform. * @{ */ diff --git a/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h b/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h index de175091d..046711d7a 100644 --- a/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h +++ b/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h @@ -24,7 +24,7 @@ * * @defgroup IAR_ARMCMx_STM32F4xx STM32F4xx Specific Parameters * @ingroup IAR_ARMCMx_SPECIFIC - * @details This file contains the Cortex-M3 specific parameters for the + * @details This file contains the Cortex-M4 specific parameters for the * STM32F4xx platform. * @{ */ @@ -35,7 +35,7 @@ /** * @brief Cortex core model. */ -#define CORTEX_MODEL CORTEX_M3 +#define CORTEX_MODEL CORTEX_M4 /** * @brief Systick unit presence. diff --git a/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h b/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h new file mode 100644 index 000000000..0e6c8b7b9 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32F4xx/cmparams.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/STM32F4xx/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32F4xx. + * + * @defgroup RVCT_ARMCMx_STM32F4xx STM32F4xx Specific Parameters + * @ingroup RVCT_ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * STM32F4xx platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s b/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s new file mode 100644 index 000000000..1d208ad03 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s @@ -0,0 +1,338 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#if !defined(STM32F4XX) +#define _FROM_ASM_ +#include "board.h" +#endif + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 + DCD VectorEC + DCD VectorF0 + DCD VectorF4 + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C + DCD Vector150 + DCD Vector154 + DCD Vector158 + DCD Vector15C + DCD Vector160 + DCD Vector164 + DCD Vector168 + DCD Vector16C + DCD Vector170 + DCD Vector174 + DCD Vector178 + DCD Vector17C + DCD Vector180 + DCD Vector184 + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + EXPORT VectorF4 [WEAK] + EXPORT VectorF8 [WEAK] + EXPORT VectorFC [WEAK] + EXPORT Vector100 [WEAK] + EXPORT Vector104 [WEAK] + EXPORT Vector108 [WEAK] + EXPORT Vector10C [WEAK] + EXPORT Vector110 [WEAK] + EXPORT Vector114 [WEAK] + EXPORT Vector118 [WEAK] + EXPORT Vector11C [WEAK] + EXPORT Vector120 [WEAK] + EXPORT Vector124 [WEAK] + EXPORT Vector128 [WEAK] + EXPORT Vector12C [WEAK] + EXPORT Vector130 [WEAK] + EXPORT Vector134 [WEAK] + EXPORT Vector138 [WEAK] + EXPORT Vector13C [WEAK] + EXPORT Vector140 [WEAK] + EXPORT Vector144 [WEAK] + EXPORT Vector148 [WEAK] + EXPORT Vector14C [WEAK] + EXPORT Vector150 [WEAK] + EXPORT Vector154 [WEAK] + EXPORT Vector158 [WEAK] + EXPORT Vector15C [WEAK] + EXPORT Vector160 [WEAK] + EXPORT Vector164 [WEAK] + EXPORT Vector168 [WEAK] + EXPORT Vector16C [WEAK] + EXPORT Vector170 [WEAK] + EXPORT Vector174 [WEAK] + EXPORT Vector178 [WEAK] + EXPORT Vector17C [WEAK] + EXPORT Vector180 [WEAK] + EXPORT Vector184 [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C +Vector150 +Vector154 +Vector158 +Vector15C +Vector160 +Vector164 +Vector168 +Vector16C +Vector170 +Vector174 +Vector178 +Vector17C +Vector180 +Vector184 + b _unhandled_exception + ENDP + + END -- cgit v1.2.3 From 46523770bd015c564abe140a5018f08c5aba89a0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Nov 2011 21:29:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3534 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- readme.txt | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/readme.txt b/readme.txt index fb4e4add2..de06681e8 100644 --- a/readme.txt +++ b/readme.txt @@ -102,7 +102,7 @@ - NEW: Added handling of USART6 to the STM32 serial driver. - NEW: Added USE_COPT setting to all makefiles, contributed by Mabl. - NEW: Added EXT driver implementation for AT91SAM7x, contributed by Florian. - (TODO: Test application missing). + TODO: Test application missing. - NEW: Updated USB driver model and STM32 implementation and fixed several problems. - Changed the API to move buffer copy operations out of critical zones. @@ -154,7 +154,6 @@ - FIX: Fixed timeout problem in the lwIP interface layer (bug 3302420) (backported to 2.2.4). - NEW: Added AVR implementation of the PAL driver contributed by Leszek. - (TODO: Update demos to use it) - NEW: STM32L ADC driver implementation. - NEW: Improved ADC driver model, now it is possible to handle error conditions during the conversion process. @@ -169,8 +168,8 @@ (API and functionality review) - NEW: Improved MAC driver model, it now follows the same template of other drivers. - (TODO: uIP demo to be adapted) - (TODO: implement macStop() in AT91SAM7X implementation) + TODO: uIP demo to be adapted. + TODO: implement macStop() in AT91SAM7X implementation. - NEW: New RCC helper driver for STM32F1xx and STM32L1xx, it simplifies the use of the RCC resources and hides most differences found among the various STM32 sub-families. -- cgit v1.2.3 From 3dbd2ceb81071669089275f5edbc8fddfe8c95d4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 27 Nov 2011 08:44:01 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3535 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- todo.txt | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/todo.txt b/todo.txt index 25809a9a1..2c9f6673a 100644 --- a/todo.txt +++ b/todo.txt @@ -7,22 +7,27 @@ N = Decided against. Current Pipeline (2.3.x): * Improved Makefile system. -- USB driver enhancements. - - USB and USB_SERIAL APIs reclassification. - - Incorporate the USB bus attach/detach handling in usbStart()/usbStop(). - - Fix zero size packets handling in USB_SERIAL driver. - - USB double buffering support for STM32 implementation. - - Evaluate using DMA channels for buffer copy. +* USB driver enhancements. + * USB and USB_SERIAL APIs reclassification. + * Incorporate the USB bus attach/detach handling in usbStart()/usbStop(). + * Fix zero size packets handling in USB_SERIAL driver. + ? USB double buffering support for STM32 implementation. + X Evaluate using DMA channels for buffer copy. X I2C device driver class support and at least one implementation. X Evaluate a modified I2C API where the synchronous mode is default and the callback mode optional. - Software I2C implementation using a GPT instance for timings. -X STM32F2xx/STM32F4xx support (adapt and re-verify all drivers). +* STM32F2xx/STM32F4xx support (adapt and re-verify all drivers). * New STM32 DMA helper driver abstracting differences between STM32F2xx/STM32F4xx and other sub-families. - - Specific ADC driver for STM32F2xx/STM32F4xx. + * Specific ADC driver for STM32F2xx/STM32F4xx. - MMC_SPI driver revision and speedup. - FatFs 0.9x integration. +- FPU support in CM4 port. +- Nios II support. +- LPC17xx support. +- Static memory allocation hook macros in kernel code. +? Revision of scheduling strategy for threads at equal priority. Within 2.x.x X File System infrastructure. @@ -31,7 +36,6 @@ X Implement the "transmission end" serial driver event on those platforms - Add a CH_THREAD macro for threads declaration in order to hide compiler-specific optimizations for thread functions. All demos will have to be updated. -- LPC17xx support. - Test suite overhaul, the API should be more generic in order to be used with different subsystems and not just the kernel. - Reduce number of demos globally, add demos to a repository or on web site. -- cgit v1.2.3 From 73b61b850bb16876a5e92f050b8c4aba0b2a668c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 27 Nov 2011 08:51:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3536 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- docs/Doxyfile_chm | 1 + docs/Doxyfile_html | 1 + docs/rsc/header_chm.html | 2 +- docs/rsc/header_html.html | 2 +- 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/Doxyfile_chm b/docs/Doxyfile_chm index dd7717de8..bcda68230 100644 --- a/docs/Doxyfile_chm +++ b/docs/Doxyfile_chm @@ -683,6 +683,7 @@ INPUT = ../docs/src \ ../os/hal/platforms/MSP430/platform.dox \ ../os/hal/platforms/SPC56x/platform.dox \ ../os/hal/platforms/STM32F1xx/platform.dox \ + ../os/hal/platforms/STM32F4xx/platform.dox \ ../os/hal/platforms/STM32L1xx/platform.dox \ ../os/hal/platforms/STM8L/platform.dox \ ../os/hal/platforms/STM8S/platform.dox \ diff --git a/docs/Doxyfile_html b/docs/Doxyfile_html index f66d3afd2..5cba063d7 100644 --- a/docs/Doxyfile_html +++ b/docs/Doxyfile_html @@ -683,6 +683,7 @@ INPUT = ../docs/src \ ../os/hal/platforms/MSP430/platform.dox \ ../os/hal/platforms/SPC56x/platform.dox \ ../os/hal/platforms/STM32F1xx/platform.dox \ + ../os/hal/platforms/STM32F4xx/platform.dox \ ../os/hal/platforms/STM32L1xx/platform.dox \ ../os/hal/platforms/STM8L/platform.dox \ ../os/hal/platforms/STM8S/platform.dox \ diff --git a/docs/rsc/header_chm.html b/docs/rsc/header_chm.html index a27feac41..1365da6dd 100644 --- a/docs/rsc/header_chm.html +++ b/docs/rsc/header_chm.html @@ -13,7 +13,7 @@ -
ChibiOS/RT 2.3.3
+
ChibiOS/RT 2.3.4
diff --git a/docs/rsc/header_html.html b/docs/rsc/header_html.html index 46b76b597..202da80ca 100644 --- a/docs/rsc/header_html.html +++ b/docs/rsc/header_html.html @@ -20,7 +20,7 @@ $(document).ready(initResizable); -
ChibiOS/RT
2.3.3
+
ChibiOS/RT
2.3.4