From 2f99ed97a977f64fd7a11cb6cce569c879be4420 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Apr 2008 14:05:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@258 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/board.c | 35 ++++-- demos/ARMCM3-STM32F103-GCC/board.h | 65 ++++++++-- .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h | 4 +- ports/ARM7-LPC214x/vic.h | 4 +- ports/ARMCM3/chcore.c | 5 +- ports/ARMCM3/nvic.c | 24 ++++ ports/ARMCM3/nvic.h | 139 +++++++++++++++++++++ readme.txt | 1 + 9 files changed, 249 insertions(+), 30 deletions(-) create mode 100644 ports/ARMCM3/nvic.c create mode 100644 ports/ARMCM3/nvic.h diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 5b0e8f23e..7fc33886a 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -62,7 +62,7 @@ UDEFS = UADEFS = # List ARM-mode C source files here -SRC = ../../ports/ARMCM3/chcore.c \ +SRC = ../../ports/ARMCM3/chcore.c ../../ports/ARMCM3/nvic.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 09636cb9d..631a13e0c 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -18,6 +18,7 @@ */ #include +#include #include "board.h" @@ -45,27 +46,29 @@ void hwinit(void) { * Clocks and PLL initialization. */ // HSI setup. - RCC->CR = 0x00000083; // Enforces a known state (HSI ON). - while (!(RCC->CR & (1 << 1))) + RCC->CR = HSITRIM_RESET_BITS | CR_HSION_MASK; + while (!(RCC->CR & CR_HSIRDY_MASK)) ; // Waits until HSI stable, it should already be. // HSE setup. - RCC->CR |= (1 << 16); // HSE ON. - while (!(RCC->CR & (1 << 17))) + RCC->CR |= CR_HSEON_MASK; + while (!(RCC->CR & CR_HSERDY_MASK)) ; // Waits until HSE stable. // PLL setup. - RCC->CFGR |= PLLPREBITS | PLLMULBITS | PLLSRCBITS; - RCC->CR |= (1 << 24); // PLL ON. - while (!(RCC->CR & (1 << 25))) + RCC->CFGR = PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS; + RCC->CR |= CR_PLLON_MASK; + while (!(RCC->CR & CR_PLLRDY_MASK)) ; // Waits until PLL stable. // Clock sources. - RCC->CFGR |= AHBBITS | PPRE1BITS | PPRE2BITS | ADCPREBITS | - USBPREBITS | MCOSRCBITS; + RCC->CFGR |= HPRE_DIV1_BITS | PPRE1_DIV2_BITS | PPRE2_DIV2_BITS | + ADCPRE_DIV8_BITS | USBPREBITS | MCO_DISABLED_BITS; /* * Flash setup and final clock selection. */ FLASH->ACR = FLASHBITS; // Flash wait states depending on clock. - RCC->CFGR |= SYSSRCBITS; // Switches on the PLL clock. + RCC->CFGR |= SW_PLL_BITS; // Switches on the PLL clock. + while ((RCC->CFGR & CFGR_SWS_MASK) != SWS_PLL_BITS) + ; /* * I/O ports initialization as specified in board.h. @@ -88,7 +91,15 @@ void hwinit(void) { GPIOD->ODR = VAL_GPIODODR; /* - * NVIC/SCB setup. + * NVIC/SCB initialization. */ - SCB->AIRCR = (0x5FA << 16) | (0x5 << 8); // PRIGROUP = 5 (2:6). + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0x3); // PRIGROUP 4:0 (4:4). + + /* + * SysTick initialization. + */ + SCB_SHPR(2) = 0x10 << 24; // SysTick at priority 1:0 (highest - 1). + ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1; + ST_CVR = 0; + ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS; } diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index b06745010..fa47168ed 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -52,24 +52,69 @@ #define AHB1CLK (SYSCLK / 1) /* - * Various clock settings. + * Values derived from clock settings. */ -#define SYSSRCBITS (0x2 << 0) // PLLCLK is SYSCLK (do not change) -#define AHBBITS (0x0 << 4) // Divided by 1 -#define PPRE1BITS (0x4 << 8) // Divided by 2 (must be <= 36MHz) -#define PPRE2BITS (0x4 << 11) // Divided by 2 -#define ADCPREBITS (0x3 << 14) // Divided by 8 -#define PLLSRCBITS (0x1 << 16) // PLL source is HSE/1 #define PLLPREBITS ((PLLPRE - 1) << 17) #define PLLMULBITS ((PLLMUL - 2) << 18) #ifdef SYSCLK_48 -#define USBPREBITS (0x1 << 22) // Divided by 1 +#define USBPREBITS USBPRE_DIV1_BITS #else -#define USBPREBITS (0x0 << 22) // Divided by 1.5 +#define USBPREBITS USBPRE_DIV1P5_BITS #endif -#define MCOSRCBITS (0x0 << 24) // No MCO output. +/* + * Definitions for RCC_CR register. + */ +#define CR_HSION_MASK (0x1 << 0) +#define CR_HSIRDY_MASK (0x1 << 1) +#define CR_HSITRIM_MASK (0x1F << 3) +#define HSITRIM_RESET_BITS (1 << 3) +#define CR_HSICAL_MASK (0xFF << 8) +#define CR_HSEON_MASK (0x1 << 16) +#define CR_HSERDY_MASK (0x1 << 17) +#define CR_HSEBYP_MASK (0x1 << 18) +#define CR_CSSON_MASK (0x1 << 19) +#define CR_PLLON_MASK (0x1 << 24) +#define CR_PLLRDY_MASK (0x1 << 25) +/* + * Definitions for RCC_CFGR register. + */ +#define CFGR_SW_MASK (0x3 << 0) +#define SW_HSI_BITS (0 << 2) +#define SW_HSE_BITS (1 << 2) +#define SW_PLL_BITS (2 << 2) +#define CFGR_SWS_MASK (0x3 << 2) +#define SWS_HSI_BITS (0 << 2) +#define SWS_HSE_BITS (1 << 2) +#define SWS_PLL_BITS (2 << 2) +#define CFGR_HPRE_MASK (0xF << 4) +#define HPRE_DIV1_BITS (0 << 4) +#define CFGR_PPRE1_MASK (0x7 << 8) +#define PPRE1_DIV1_BITS (0 << 8) +#define PPRE1_DIV2_BITS (4 << 8) +#define CFGR_PPRE2_MASK (0x7 << 11) +#define PPRE2_DIV1_BITS (0 << 11) +#define PPRE2_DIV2_BITS (4 << 11) +#define CFGR_ADCPRE_MASK (0x3 << 14) +#define ADCPRE_DIV2_BITS (0 << 14) +#define ADCPRE_DIV4_BITS (1 << 14) +#define ADCPRE_DIV6_BITS (2 << 14) +#define ADCPRE_DIV8_BITS (3 << 14) +#define CFGR_PLLSRC_MASK (0x1 << 16) +#define PLLSRC_HSI_BITS (0 << 16) +#define PLLSRC_HSE_BITS (1 << 16) +#define CFGR_PLLXTPRE_MASK (0x1 << 17) +#define CFGR_PLLMUL_MASK (0xF << 18) +#define CFGR_USBPRE_MASK (0x1 << 22) +#define USBPRE_DIV1P5_BITS (0 << 22) +#define USBPRE_DIV1_BITS (1 << 22) +#define CFGR_MCO_MASK (0x7 << 24) +#define MCO_DISABLED_BITS (0 << 24) + +/* + * IO pins assignments. + */ #define GPIOA_BUTTON (1 << 0) #define GPIOC_MMCWP (1 << 6) diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h index 8e51a48fd..7df30d90d 100644 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h @@ -77,7 +77,7 @@ //#define _IWDG /************************************* NVIC ***********************************/ -#define _NVIC +//#define _NVIC /************************************* PWR ************************************/ //#define _PWR @@ -94,7 +94,7 @@ //#define _SPI2 /************************************* SysTick ********************************/ -#define _SysTick +//#define _SysTick /************************************* TIM1 ***********************************/ //#define _TIM1 diff --git a/ports/ARM7-LPC214x/vic.h b/ports/ARM7-LPC214x/vic.h index 9d8ba93ad..2c3fdd32d 100644 --- a/ports/ARM7-LPC214x/vic.h +++ b/ports/ARM7-LPC214x/vic.h @@ -21,7 +21,7 @@ #define _VIC_H_ #ifdef __cplusplus -} +extern "C" { #endif void InitVIC(void); void SetVICVector(void *handler, int vector, int source); @@ -29,4 +29,4 @@ } #endif -#endif /* _VIC_H_*/ +#endif /* _VIC_H_ */ diff --git a/ports/ARMCM3/chcore.c b/ports/ARMCM3/chcore.c index cb95916c3..ea33f62eb 100644 --- a/ports/ARMCM3/chcore.c +++ b/ports/ARMCM3/chcore.c @@ -17,9 +17,8 @@ along with this program. If not, see . */ -#include "stm32lib/stm32f10x_map.h" - #include +#include /* * System idle thread loop. @@ -91,7 +90,7 @@ void *retaddr; void chSysIRQExitI(void) { chSysLock(); - if (SCB->ICSR & (1 << 11)) { /* RETTOBASE */ + if (SCB_ICSR & ICSR_RETTOBASE_MASK) { if (chSchRescRequiredI()) { asm volatile ("mrs r0, PSP \n\t" \ diff --git a/ports/ARMCM3/nvic.c b/ports/ARMCM3/nvic.c new file mode 100644 index 000000000..5d62ba10b --- /dev/null +++ b/ports/ARMCM3/nvic.c @@ -0,0 +1,24 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +void SetNVICVector(void) { +} diff --git a/ports/ARMCM3/nvic.h b/ports/ARMCM3/nvic.h new file mode 100644 index 000000000..62ea7317d --- /dev/null +++ b/ports/ARMCM3/nvic.h @@ -0,0 +1,139 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _NVIC_H_ +#define _NVIC_H_ + +typedef volatile unsigned char IOREG8; +typedef volatile unsigned int IOREG32; + +#define NVIC_ITCR (*((IOREG32 *)0xE000E004)) +#define NVIC_STIR (*((IOREG32 *)0xE000EF00)) + +typedef struct { + IOREG32 CSR; + IOREG32 RVR; + IOREG32 CVR; + IOREG32 CBVR; +} ST; + +#define STBase ((ST *)0xE000E010) +#define ST_CSR (STBase->CSR) +#define ST_RVR (STBase->RVR) +#define ST_CVR (STBase->CVR) +#define ST_CBVR (STBase->CBVR) + +#define CSR_ENABLE_MASK (0x1 << 0) +#define ENABLE_OFF_BITS (0 << 0) +#define ENABLE_ON_BITS (1 << 0) +#define CSR_TICKINT_MASK (0x1 << 1) +#define TICKINT_DISABLED_BITS (0 << 0) +#define TICKINT_ENABLED_BITS (1 << 0) +#define CSR_CLKSOURCE_MASK (0x1 << 2) +#define CLKSOURCE_EXT_BITS (0 << 2) +#define CLKSOURCE_CORE_BITS (1 << 2) +#define CSR_COUNTFLAG_MASK (0x1 << 16) + +#define RVR_RELOAD_MASK (0xFFFFFF << 0) + +#define CVR_CURRENT_MASK (0xFFFFFF << 0) + +#define CBVR_TENMS_MASK (0xFFFFFF << 0) +#define CBVR_SKEW_MASK (0x1 << 30) +#define CBVR_NOREF_MASK (0x1 << 31) + +typedef struct { + IOREG32 ISER[8]; + IOREG32 unused1[24]; + IOREG32 ICER[8]; + IOREG32 unused2[24]; + IOREG32 ISPR[8]; + IOREG32 unused3[24]; + IOREG32 ICPR[8]; + IOREG32 unused4[24]; + IOREG32 IABR[8]; + IOREG32 unused5[54]; + IOREG32 IPR[60]; +} NVIC; + +#define NVICBase ((NVIC *)0xE000E100) +#define NVIC_ISER(n) (NVICBase->ISER[n]) +#define NVIC_ICER(n) (NVICBase->ICER[n]) +#define NVIC_ISPR(n) (NVICBase->ISPR[n]) +#define NVIC_ICPR(n) (NVICBase->ICPR[n]) +#define NVIC_IABR(n) (NVICBase->IABR[n]) +#define NVIC_IPR(n) (NVICBase->IPR[n]) + +typedef struct { + IOREG32 CPUID; + IOREG32 ICSR; + IOREG32 VTOR; + IOREG32 AIRCR; + IOREG32 SCR; + IOREG32 CCR; + IOREG32 SHPR[3]; + IOREG32 SHCSR; + IOREG32 CFSR; + IOREG32 HFSR; + IOREG32 DFSR; + IOREG32 MMFAR; + IOREG32 BFAR; + IOREG32 AFSR; +} SCB; + +#define SCBBase ((SCB *)0xE000ED00) +#define SCB_CPUID (SCBBase->CPUID) +#define SCB_ICSR (SCBBase->ICSR) +#define SCB_VTOR (SCBBase->VTOR) +#define SCB_AIRCR (SCBBase->AIRCR) +#define SCB_SCR (SCBBase->SCR) +#define SCB_CCR (SCBBase->CCR) +#define SCB_SHPR(n) (SCBBase->SHPR[n]) +#define SCB_SHCSR (SCBBase->SHCSR) +#define SCB_CFSR (SCBBase->CFSR) +#define SCB_HFSR (SCBBase->HFSR) +#define SCB_DFSR (SCBBase->DFSR) +#define SCB_MMFAR (SCBBase->MMFAR) +#define SCB_BFAR (SCBBase->BFAR) +#define SCB_AFSR (SCBBase->AFSR) + +#define ICSR_VECTACTIVE_MASK (0x1FF << 0) +#define ICSR_RETTOBASE_MASK (0x1 << 11) +#define ICSR_VECTPENDING_MASK (0x1FF << 12) +#define ICSR_ISRPENDING_MASK (0x1 << 22) +#define ICSR_ISRPREEMPT_MASK (0x1 << 23) +#define ICSR_PENDSTCLR_MASK (0x1 << 25) +#define ICSR_PENDSTSET_MASK (0x1 << 26) +#define ICSR_PENDSVCLR_MASK (0x1 << 27) +#define ICSR_PENDSVSET_MASK (0x1 << 28) +#define ICSR_NMIPENDSET_MASK (0x1 << 31) + +#define AIRCR_VECTKEY 0x05FA0000 +#define AIRCR_PRIGROUP_MASK (0x7 << 8) +#define AIRCR_PRIGROUP(n) ((n) << 8) + +#ifdef __cplusplus +extern "C" { +#endif + void SetNVICVector(void); +#ifdef __cplusplus +} +#endif + +#endif /* _NVIC_H_ */ diff --git a/readme.txt b/readme.txt index 6d6778172..edda472f9 100644 --- a/readme.txt +++ b/readme.txt @@ -64,6 +64,7 @@ Win32-MinGW - ChibiOS/RT simulator and demo into a WIN32 process, ***************************************************************************** *** 0.6.3 *** +- Fixed a minor error in ./ports/ARM7/vic.h, it should not affect anything. *** 0.6.2 *** - NEW: Added C++ wrapper around the ChibiOS/RT core APIs, now it is possible -- cgit v1.2.3