From 2c615ccc91027f0ed03124ef55171a1dffdb7ffa Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 5 Oct 2012 09:59:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4737 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/PPC-SPC560P-GCC/halconf.h | 2 +- demos/PPC-SPC560P-GCC/mcuconf.h | 159 ++++++++++++++++++++++ os/hal/platforms/SPC560Pxx/hal_lld.h | 246 ++++++++++++++++++----------------- 3 files changed, 284 insertions(+), 123 deletions(-) create mode 100644 demos/PPC-SPC560P-GCC/mcuconf.h diff --git a/demos/PPC-SPC560P-GCC/halconf.h b/demos/PPC-SPC560P-GCC/halconf.h index 202137119..c9b3ad25a 100644 --- a/demos/PPC-SPC560P-GCC/halconf.h +++ b/demos/PPC-SPC560P-GCC/halconf.h @@ -32,7 +32,7 @@ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /** * @brief Enables the TM subsystem. diff --git a/demos/PPC-SPC560P-GCC/mcuconf.h b/demos/PPC-SPC560P-GCC/mcuconf.h new file mode 100644 index 000000000..49369ce5d --- /dev/null +++ b/demos/PPC-SPC560P-GCC/mcuconf.h @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560Pxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + */ + +#define SPC560Pxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_FMPLL0_IDF_VALUE 5 +#define SPC5_FMPLL0_NDIV_VALUE 32 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_FMPLL1_IDF_VALUE 5 +#define SPC5_FMPLL1_NDIV_VALUE 60 +#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT3_IRQ_PRIORITY 4 + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h index fcd94fd9e..a4e439fe9 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.h +++ b/os/hal/platforms/SPC560Pxx/hal_lld.h @@ -153,11 +153,11 @@ */ #define SPC5_ME_MC_SYSCLK_MASK (15U << 0) #define SPC5_ME_MC_SYSCLK(n) ((n) << 0) -#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) -#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) -#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) -#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5) -#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) +#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) +#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) +#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) +#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5) +#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) #define SPC5_ME_MC_IRCON (1U << 4) #define SPC5_ME_MC_XOSC0ON (1U << 5) #define SPC5_ME_MC_PLL0ON (1U << 6) @@ -290,128 +290,130 @@ * is no need to specify them. */ #if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | SPC5_ME_ME_RUN2 | \ - SPC5_ME_ME_RUN3 | SPC5_ME_ME_HALT0 | \ - SPC5_ME_ME_STOP0) +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0) #endif /** * @brief TEST mode settings. */ #if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ - SPC5_ME_MC_IRCON | \ - SPC5_ME_MC_XOSC0ON | \ - SPC5_ME_MC_PLL0ON | \ - SPC5_ME_MC_PLL1ON | \ - SPC5_ME_MC_CFLAON_NORMAL | \ - SPC5_ME_MC_DFLAON_NORMAL | \ - SPC5_ME_MC_MVRON) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) #endif /** * @brief SAFE mode settings. */ #if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) #endif /** * @brief DRUN mode settings. */ #if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ - SPC5_ME_MC_IRCON | \ - SPC5_ME_MC_XOSC0ON | \ - SPC5_ME_MC_PLL0ON | \ - SPC5_ME_MC_PLL1ON | \ - SPC5_ME_MC_CFLAON_NORMAL | \ - SPC5_ME_MC_DFLAON_NORMAL | \ - SPC5_ME_MC_MVRON) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) #endif /** * @brief RUN0 mode settings. */ #if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ - SPC5_ME_MC_IRCON | \ - SPC5_ME_MC_XOSC0ON | \ - SPC5_ME_MC_PLL0ON | \ - SPC5_ME_MC_PLL1ON | \ - SPC5_ME_MC_CFLAON_NORMAL | \ - SPC5_ME_MC_DFLAON_NORMAL | \ - SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) #endif /** * @brief RUN1 mode settings. */ #if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ - SPC5_ME_MC_IRCON | \ - SPC5_ME_MC_XOSC0ON | \ - SPC5_ME_MC_PLL0ON | \ - SPC5_ME_MC_PLL1ON | \ - SPC5_ME_MC_CFLAON_NORMAL | \ - SPC5_ME_MC_DFLAON_NORMAL | \ - SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) #endif /** * @brief RUN2 mode settings. */ #if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ - SPC5_ME_MC_IRCON | \ - SPC5_ME_MC_XOSC0ON | \ - SPC5_ME_MC_PLL0ON | \ - SPC5_ME_MC_PLL1ON | \ - SPC5_ME_MC_CFLAON_NORMAL | \ - SPC5_ME_MC_DFLAON_NORMAL | \ - SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) #endif /** * @brief RUN3 mode settings. */ #if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ - SPC5_ME_MC_IRCON | \ - SPC5_ME_MC_XOSC0ON | \ - SPC5_ME_MC_PLL0ON | \ - SPC5_ME_MC_PLL1ON | \ - SPC5_ME_MC_CFLAON_NORMAL | \ - SPC5_ME_MC_DFLAON_NORMAL | \ - SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) #endif /** * @brief HALT0 mode settings. */ #if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ - SPC5_ME_MC_IRCON | \ - SPC5_ME_MC_XOSC0ON | \ - SPC5_ME_MC_PLL0ON | \ - SPC5_ME_MC_PLL1ON | \ - SPC5_ME_MC_CFLAON_NORMAL | \ - SPC5_ME_MC_DFLAON_NORMAL | \ - SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) #endif /** * @brief STOP0 mode settings. */ #if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ - SPC5_ME_MC_IRCON | \ - SPC5_ME_MC_XOSC0ON | \ - SPC5_ME_MC_PLL0ON | \ - SPC5_ME_MC_PLL1ON | \ - SPC5_ME_MC_CFLAON_NORMAL | \ - SPC5_ME_MC_DFLAON_NORMAL | \ - SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_PLL1ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) #endif /** @@ -420,7 +422,7 @@ * mode. */ #if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN_PC0_BITS 0 +#define SPC5_ME_RUN_PC0_BITS 0 #endif /** @@ -429,13 +431,13 @@ * mode. */ #if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ - SPC5_ME_RUN_PC_SAFE | \ - SPC5_ME_RUN_PC_DRUN | \ - SPC5_ME_RUN_PC_RUN0 | \ - SPC5_ME_RUN_PC_RUN1 | \ - SPC5_ME_RUN_PC_RUN2 | \ - SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) #endif /** @@ -444,11 +446,11 @@ * normal run" mode. */ #if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ - SPC5_ME_RUN_PC_RUN0 | \ - SPC5_ME_RUN_PC_RUN1 | \ - SPC5_ME_RUN_PC_RUN2 | \ - SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) #endif /** @@ -456,10 +458,10 @@ * @note Not defined, available to application-specific modes. */ #if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ - SPC5_ME_RUN_PC_RUN1 | \ - SPC5_ME_RUN_PC_RUN2 | \ - SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) #endif /** @@ -467,10 +469,10 @@ * @note Not defined, available to application-specific modes. */ #if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ - SPC5_ME_RUN_PC_RUN1 | \ - SPC5_ME_RUN_PC_RUN2 | \ - SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) #endif /** @@ -478,10 +480,10 @@ * @note Not defined, available to application-specific modes. */ #if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ - SPC5_ME_RUN_PC_RUN1 | \ - SPC5_ME_RUN_PC_RUN2 | \ - SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) #endif /** @@ -489,10 +491,10 @@ * @note Not defined, available to application-specific modes. */ #if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ - SPC5_ME_RUN_PC_RUN1 | \ - SPC5_ME_RUN_PC_RUN2 | \ - SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) #endif /** @@ -500,10 +502,10 @@ * @note Not defined, available to application-specific modes. */ #if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ - SPC5_ME_RUN_PC_RUN1 | \ - SPC5_ME_RUN_PC_RUN2 | \ - SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) #endif /** @@ -512,7 +514,7 @@ * mode. */ #if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_LP_PC0_BITS 0 +#define SPC5_ME_LP_PC0_BITS 0 #endif /** @@ -521,8 +523,8 @@ * mode. */ #if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ - SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) #endif /** @@ -531,7 +533,7 @@ * mode. */ #if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) #endif /** @@ -540,7 +542,7 @@ * mode. */ #if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) #endif /** @@ -548,8 +550,8 @@ * @note Not defined, available to application-specific modes. */ #if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ - SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) #endif /** @@ -557,8 +559,8 @@ * @note Not defined, available to application-specific modes. */ #if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ - SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) #endif /** @@ -566,8 +568,8 @@ * @note Not defined, available to application-specific modes. */ #if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ - SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) #endif /** @@ -575,8 +577,8 @@ * @note Not defined, available to application-specific modes. */ #if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__) -#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ - SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) #endif /** @@ -585,7 +587,7 @@ * generation. */ #if !defined(SPC5_PIT3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define SPC5_PIT3_IRQ_PRIORITY 4 +#define SPC5_PIT3_IRQ_PRIORITY 4 #endif /*===========================================================================*/ @@ -719,8 +721,8 @@ extern "C" { #endif void hal_lld_init(void); void spc560p_clock_init(void); - bool_t halSPC560PSetRunMode(spc560prunmode_t mode); - void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl); + bool_t halSPC560PSetRunMode(spc560prunmode_t mode); + void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl); #if !SPC5_NO_INIT uint32_t halSPC560PGetSystemClock(void); #endif -- cgit v1.2.3