From 1f674a970324d5730f6178b210fe9f796587f246 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 17 Dec 2012 13:15:12 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4941
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/SPC563Mxx/hal_lld.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.c b/os/hal/platforms/SPC563Mxx/hal_lld.c
index 921fc744f..3ffcfd0b1 100644
--- a/os/hal/platforms/SPC563Mxx/hal_lld.c
+++ b/os/hal/platforms/SPC563Mxx/hal_lld.c
@@ -114,6 +114,7 @@ void spc_clock_init(void) {
   /* PLL activation.*/
   FMPLL.ESYNCR1.B.EMODE     = 1;                    /* Enhanced mode on.    */
   FMPLL.ESYNCR1.B.CLKCFG   &= 1;                    /* Bypass mode, PLL off.*/
+#if !SPC5_CLK_BYPASS
   FMPLL.ESYNCR1.B.CLKCFG   |= 2;                    /* PLL on.              */
   FMPLL.ESYNCR1.B.EPREDIV   = SPC5_CLK_PREDIV;
   FMPLL.ESYNCR1.B.EMFD      = SPC5_CLK_MFD;
@@ -121,6 +122,7 @@ void spc_clock_init(void) {
   while (!FMPLL.SYNSR.B.LOCK)
     ;
   FMPLL.ESYNCR1.B.CLKCFG   |= 4;                    /* Clock from the PLL.  */
+#endif /* !SPC5_CLK_BYPASS */
 #endif /* !SPC5_NO_INIT */
 }
 
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