aboutsummaryrefslogtreecommitdiffstats
path: root/testhal
diff options
context:
space:
mode:
Diffstat (limited to 'testhal')
-rw-r--r--testhal/STM32/STM32F4xx/DMA_STORM/main.c4
-rw-r--r--testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h82
-rw-r--r--testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h54
-rw-r--r--testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h82
-rw-r--r--testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h54
-rw-r--r--testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h82
-rw-r--r--testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h54
-rw-r--r--testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h54
-rw-r--r--testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h54
9 files changed, 260 insertions, 260 deletions
diff --git a/testhal/STM32/STM32F4xx/DMA_STORM/main.c b/testhal/STM32/STM32F4xx/DMA_STORM/main.c
index fa5ac83ea..b02bb1b80 100644
--- a/testhal/STM32/STM32F4xx/DMA_STORM/main.c
+++ b/testhal/STM32/STM32F4xx/DMA_STORM/main.c
@@ -187,9 +187,9 @@ int main(void) {
chThdCreateStatic(waSPI3, sizeof(waSPI3), NORMALPRIO + 1, spi_thread, &SPID3);
/* Allocating two DMA2 streams for memory copy operations.*/
- if (dmaStreamAllocate(STM32_DMA2_STREAM6, 0, NULL, NULL))
+ if (dmaStreamAlloc(STM32_DMA_STREAM_ID(2, 6), 0, NULL, NULL) == NULL)
chSysHalt("DMA already in use");
- if (dmaStreamAllocate(STM32_DMA2_STREAM7, 0, NULL, NULL))
+ if (dmaStreamAlloc(STM32_DMA_STREAM_ID(2, 7), 0, NULL, NULL) == NULL)
chSysHalt("DMA already in use");
for (i = 0; i < sizeof (patterns1); i++)
patterns1[i] = (uint8_t)i;
diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h
index 5b6e99c00..bc4eed683 100644
--- a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h
@@ -185,8 +185,8 @@
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 TRUE
#define STM32_ADC_USE_ADC3 TRUE
-#define STM32_ADC_ADC12_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_ADC_ADC3_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
+#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
@@ -214,8 +214,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@@ -253,14 +253,14 @@
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
-#define STM32_I2C_I2C1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C4_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
-#define STM32_I2C_I2C4_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@@ -335,7 +335,7 @@
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
-#define STM32_SDC_SDMMC1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
+#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
@@ -368,18 +368,18 @@
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
-#define STM32_SPI_SPI6_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@@ -411,22 +411,22 @@
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
-#define STM32_UART_USART1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART6_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART6_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART7_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART7_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART8_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART8_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
diff --git a/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
index 9083b5847..651afda60 100644
--- a/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
@@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 TRUE
-#define STM32_ADC_ADC1_DMA_CHANNEL 10
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
-#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
-#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
-#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
-#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
-#define STM32_UART_USART1_RX_DMA_CHANNEL 13
-#define STM32_UART_USART1_TX_DMA_CHANNEL 0
-#define STM32_UART_USART2_RX_DMA_CHANNEL 1
-#define STM32_UART_USART2_TX_DMA_CHANNEL 2
-#define STM32_UART_USART3_RX_DMA_CHANNEL 3
-#define STM32_UART_USART3_TX_DMA_CHANNEL 4
-#define STM32_UART_UART4_RX_DMA_CHANNEL 5
-#define STM32_UART_UART4_TX_DMA_CHANNEL 6
-#define STM32_UART_UART5_RX_DMA_CHANNEL 7
-#define STM32_UART_UART5_TX_DMA_CHANNEL 8
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
-#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
-#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
+#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
diff --git a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
index 0037a4d90..b692bf59e 100644
--- a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
@@ -185,8 +185,8 @@
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 FALSE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_ADC_ADC3_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
+#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
@@ -214,8 +214,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@@ -253,14 +253,14 @@
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
-#define STM32_I2C_I2C1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C4_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
-#define STM32_I2C_I2C4_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@@ -335,7 +335,7 @@
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
-#define STM32_SDC_SDMMC1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
+#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
@@ -368,18 +368,18 @@
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
-#define STM32_SPI_SPI6_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@@ -411,22 +411,22 @@
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
-#define STM32_UART_USART1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART6_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART6_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART7_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART7_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART8_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART8_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
diff --git a/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
index a01ddd3f9..f8597eaae 100644
--- a/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
@@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
-#define STM32_ADC_ADC1_DMA_CHANNEL 10
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
-#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
-#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
-#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
-#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
-#define STM32_UART_USART1_RX_DMA_CHANNEL 13
-#define STM32_UART_USART1_TX_DMA_CHANNEL 0
-#define STM32_UART_USART2_RX_DMA_CHANNEL 1
-#define STM32_UART_USART2_TX_DMA_CHANNEL 2
-#define STM32_UART_USART3_RX_DMA_CHANNEL 3
-#define STM32_UART_USART3_TX_DMA_CHANNEL 4
-#define STM32_UART_UART4_RX_DMA_CHANNEL 5
-#define STM32_UART_UART4_TX_DMA_CHANNEL 6
-#define STM32_UART_UART5_RX_DMA_CHANNEL 7
-#define STM32_UART_UART5_TX_DMA_CHANNEL 8
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
-#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
-#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
+#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
diff --git a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
index 18662c782..79a0ac12e 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
@@ -185,8 +185,8 @@
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC12 TRUE
#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_ADC12_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_ADC_ADC3_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
+#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_ADC_ADC12_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
@@ -214,8 +214,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@@ -253,14 +253,14 @@
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
-#define STM32_I2C_I2C1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_I2C_I2C4_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
-#define STM32_I2C_I2C4_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@@ -335,7 +335,7 @@
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
-#define STM32_SDC_SDMMC1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
+#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
@@ -368,18 +368,18 @@
#define STM32_SPI_USE_SPI4 TRUE
#define STM32_SPI_USE_SPI5 TRUE
#define STM32_SPI_USE_SPI6 TRUE
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
-#define STM32_SPI_SPI6_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@@ -411,22 +411,22 @@
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
-#define STM32_UART_USART1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART6_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_USART6_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART7_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART7_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART8_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
-#define STM32_UART_UART8_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
diff --git a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
index 12adc5480..eb33fd916 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
@@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
-#define STM32_ADC_ADC1_DMA_CHANNEL 10
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
-#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
-#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
-#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
-#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
-#define STM32_UART_USART1_RX_DMA_CHANNEL 13
-#define STM32_UART_USART1_TX_DMA_CHANNEL 0
-#define STM32_UART_USART2_RX_DMA_CHANNEL 1
-#define STM32_UART_USART2_TX_DMA_CHANNEL 2
-#define STM32_UART_USART3_RX_DMA_CHANNEL 3
-#define STM32_UART_USART3_TX_DMA_CHANNEL 4
-#define STM32_UART_UART4_RX_DMA_CHANNEL 5
-#define STM32_UART_UART4_TX_DMA_CHANNEL 6
-#define STM32_UART_UART5_RX_DMA_CHANNEL 7
-#define STM32_UART_UART5_TX_DMA_CHANNEL 8
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
-#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
-#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
+#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
diff --git a/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
index 0d4e95ee3..2098ce2f4 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
@@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
-#define STM32_ADC_ADC1_DMA_CHANNEL 10
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
-#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
-#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
-#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
-#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
-#define STM32_UART_USART1_RX_DMA_CHANNEL 13
-#define STM32_UART_USART1_TX_DMA_CHANNEL 0
-#define STM32_UART_USART2_RX_DMA_CHANNEL 1
-#define STM32_UART_USART2_TX_DMA_CHANNEL 2
-#define STM32_UART_USART3_RX_DMA_CHANNEL 3
-#define STM32_UART_USART3_TX_DMA_CHANNEL 4
-#define STM32_UART_UART4_RX_DMA_CHANNEL 5
-#define STM32_UART_UART4_TX_DMA_CHANNEL 6
-#define STM32_UART_UART5_RX_DMA_CHANNEL 7
-#define STM32_UART_UART5_TX_DMA_CHANNEL 8
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
-#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
-#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
+#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
diff --git a/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h b/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
index 2b9b8043a..9addab213 100644
--- a/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
@@ -128,7 +128,7 @@
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
-#define STM32_ADC_ADC1_DMA_CHANNEL 10
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@@ -150,8 +150,8 @@
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
/*
* GPT driver system settings.
@@ -180,12 +180,12 @@
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
-#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6
-#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7
-#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9
-#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8
-#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
@@ -261,12 +261,12 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL 0
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL 1
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL 2
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL 3
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL 4
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL 5
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@@ -294,16 +294,16 @@
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
-#define STM32_UART_USART1_RX_DMA_CHANNEL 13
-#define STM32_UART_USART1_TX_DMA_CHANNEL 0
-#define STM32_UART_USART2_RX_DMA_CHANNEL 1
-#define STM32_UART_USART2_TX_DMA_CHANNEL 2
-#define STM32_UART_USART3_RX_DMA_CHANNEL 3
-#define STM32_UART_USART3_TX_DMA_CHANNEL 4
-#define STM32_UART_UART4_RX_DMA_CHANNEL 5
-#define STM32_UART_UART4_TX_DMA_CHANNEL 6
-#define STM32_UART_UART5_RX_DMA_CHANNEL 7
-#define STM32_UART_UART5_TX_DMA_CHANNEL 8
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
@@ -337,8 +337,8 @@
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
-#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
-#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
+#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-31 04:06:51 +0000