6 files changed, 76 insertions, 9 deletions
diff --git a/os/hal/platforms/STM32F2xx/adc_lld.h b/os/hal/platforms/STM32F2xx/adc_lld.h
index 737fa05c9..0ed939462 100644
--- a/os/hal/platforms/STM32F2xx/adc_lld.h
+++ b/os/hal/platforms/STM32F2xx/adc_lld.h
@@ -40,12 +40,12 @@
  * @{
  */
 /**
- * @brief   Maximum HSE  clock frequency.
+ * @brief   Minimum ADC clock frequency.
  */
 #define STM32_ADCCLK_MIN        600000
 
 /**
- * @brief   Maximum HSE  clock frequency.
+ * @brief   Maximum ADC clock frequency.
  */
 #define STM32_ADCCLK_MAX        30000000
 /** @} */
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h
index 165a10448..c93aa29a7 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.h
+++ b/os/hal/platforms/STM32F2xx/hal_lld.h
@@ -400,10 +400,10 @@
 
 #define STM32_HAS_USART3        TRUE
 #define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_USART3_RX_DMA_CHN 0x00400400
+#define STM32_USART3_RX_DMA_CHN 0x00000040
 #define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \
                                  STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074040
+#define STM32_USART3_TX_DMA_CHN 0x00074000
 
 #define STM32_HAS_UART4         TRUE
 #define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 2))
diff --git a/os/hal/platforms/STM32F2xx/platform.dox b/os/hal/platforms/STM32F2xx/platform.dox
index e247a1779..536a9780a 100644
--- a/os/hal/platforms/STM32F2xx/platform.dox
+++ b/os/hal/platforms/STM32F2xx/platform.dox
@@ -306,7 +306,7 @@
  * @section stm32f2xx_rcc_2 STM32F2xx RCC driver implementation features
  * - Peripherals reset.
  * - Peripherals clock enable.
- * - Periplerals clock disable.
+ * - Peripherals clock disable.
  * .
  * @ingroup STM32F2xx_PLATFORM_DRIVERS
  */
diff --git a/os/hal/platforms/STM32F2xx/platform.mk b/os/hal/platforms/STM32F2xx/platform.mk
index 37b37bc93..92dca2228 100644
--- a/os/hal/platforms/STM32F2xx/platform.mk
+++ b/os/hal/platforms/STM32F2xx/platform.mk
@@ -6,17 +6,18 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F2xx \
               ${CHIBIOS}/os/hal/platforms/STM32 \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
-
-
+              ${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \
+              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2
diff --git a/os/hal/platforms/STM32F2xx/stm32_dma.c b/os/hal/platforms/STM32F2xx/stm32_dma.c
index 3c1aac444..8e0226747 100644
--- a/os/hal/platforms/STM32F2xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F2xx/stm32_dma.c
@@ -29,7 +29,7 @@
  *          drivers to coordinate the access to the resource.
  * @note    The DMA ISR handlers are all declared into this module because
  *          sharing, the various device drivers can associate a callback to
- *          IRSs when allocating streams.
+ *          ISRs when allocating streams.
  * @{
  */
 
diff --git a/os/hal/platforms/STM32F2xx/stm32_rcc.h b/os/hal/platforms/STM32F2xx/stm32_rcc.h
index c624279ea..af070d814 100644
--- a/os/hal/platforms/STM32F2xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F2xx/stm32_rcc.h
@@ -423,6 +423,42 @@
 /** @} */
 
 /**
+ * @name    ETH peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the ETH peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN |               \
+                                       RCC_AHB1ENR_ETHMACTXEN |             \
+                                       RCC_AHB1ENR_ETHMACRXEN, lp)
+
+/**
+ * @brief   Disables the ETH peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN |             \
+                                         RCC_AHB1ENR_ETHMACTXEN |           \
+                                         RCC_AHB1ENR_ETHMACRXEN, lp)
+
+/**
+ * @brief   Resets the ETH peripheral.
+ *
+ * @api
+ */
+#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)
+/** @} */
+
+/**
  * @name    I2C peripherals specific RCC operations
  * @{
  */
@@ -503,6 +539,36 @@
 /** @} */
 
 /**
+ * @name    OTG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+
+/**
+ * @brief   Disables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+
+/**
+ * @brief   Resets the OTG_FS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
+/** @} */
+
+/**
  * @name    SPI peripherals specific RCC operations
  * @{
  */