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-rw-r--r--demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch2
-rw-r--r--demos/STM32/RT-STM32H743I-NUCLEO144/main.c10
-rw-r--r--demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h8
-rw-r--r--os/hal/boards/ST_NUCLEO144_H743ZI/board.c4
-rw-r--r--os/hal/ports/STM32/LLD/GPIOv2/stm32_gpio.h1
-rw-r--r--os/hal/ports/STM32/STM32H7xx/hal_lld.h6
6 files changed, 11 insertions, 20 deletions
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
index 798eef66e..fa9261ad2 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
@@ -33,7 +33,7 @@
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;CR3-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR2-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED10-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED9-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED8-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3AMR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED7-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;GCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED6-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BDCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED5-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CICR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIFR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIER-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED4-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP2R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP1R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED3-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCKSELR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED2-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED1-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED0-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CRRCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ICSCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r3-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r2-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;r3-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r2-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ICSCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CRRCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED0-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED1-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED2-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCKSELR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED3-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP1R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP2R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED4-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIER-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIFR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CICR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED5-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BDCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED6-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;GCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED7-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3AMR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED8-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED9-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED10-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR2-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR3-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRH-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRH-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0x0&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0x11087000&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/main.c b/demos/STM32/RT-STM32H743I-NUCLEO144/main.c
index c070cd9a9..13849bd2b 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/main.c
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/main.c
@@ -29,9 +29,9 @@ static THD_FUNCTION(Thread1, arg) {
(void)arg;
chRegSetThreadName("blinker");
while (true) {
- palSetLine(LINE_ARD_D13);
+ palSetLine(LINE_ZIO_D33);
chThdSleepMilliseconds(500);
- palClearLine(LINE_ARD_D13);
+ palClearLine(LINE_ZIO_D33);
chThdSleepMilliseconds(500);
}
}
@@ -52,12 +52,6 @@ int main(void) {
chSysInit();
/*
- * ARD_D13 is programmed as output (board LED).
- */
- palClearLine(LINE_ARD_D13);
- palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL);
-
- /*
* Activates the serial driver 1 using the driver default configuration.
*/
// sdStart(&SD1, NULL);
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
index 39359e7c6..d317d47f6 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
@@ -102,10 +102,6 @@
#define STM32_PLL3_DIVP_VALUE 2
#define STM32_PLL3_DIVQ_VALUE 8
#define STM32_PLL3_DIVR_VALUE 8
-#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
-#define STM32_MCO1PRE_VALUE 4
-#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
-#define STM32_MCO2PRE_VALUE 4
/*
* Core clocks dynamic settings (can be changed at runtime).
@@ -124,6 +120,10 @@
* Peripherals clocks static settings.
* Reading STM32 Reference Manual is required.
*/
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
+#define STM32_MCO1PRE_VALUE 4
+#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
+#define STM32_MCO2PRE_VALUE 4
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
#define STM32_QSPISEL STM32_QSPISEL_HCLK
diff --git a/os/hal/boards/ST_NUCLEO144_H743ZI/board.c b/os/hal/boards/ST_NUCLEO144_H743ZI/board.c
index 5ee0873d7..7173084e8 100644
--- a/os/hal/boards/ST_NUCLEO144_H743ZI/board.c
+++ b/os/hal/boards/ST_NUCLEO144_H743ZI/board.c
@@ -155,8 +155,8 @@ static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
- rccResetAHB1(STM32_GPIO_EN_MASK);
- rccEnableAHB1(STM32_GPIO_EN_MASK, true);
+ rccResetAHB4(STM32_GPIO_EN_MASK);
+ rccEnableAHB4(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA
diff --git a/os/hal/ports/STM32/LLD/GPIOv2/stm32_gpio.h b/os/hal/ports/STM32/LLD/GPIOv2/stm32_gpio.h
index acc5324e3..5dec0825d 100644
--- a/os/hal/ports/STM32/LLD/GPIOv2/stm32_gpio.h
+++ b/os/hal/ports/STM32/LLD/GPIOv2/stm32_gpio.h
@@ -96,7 +96,6 @@ typedef struct {
volatile uint32_t LOCKR;
volatile uint32_t AFRL;
volatile uint32_t AFRH;
- volatile uint32_t BRR;
} stm32_gpio_t;
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
index 9f9818f18..639269b05 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
@@ -1607,8 +1607,7 @@
/**
* @brief PLL2 DIVP field.
*/
-#if ((STM32_PLL2_DIVP_VALUE >= 2) && (STM32_PLL2_DIVP_VALUE <= 128) && \
- ((STM32_PLL2_DIVP_VALUE & 1U) == 0U)) || \
+#if ((STM32_PLL2_DIVP_VALUE >= 2) && (STM32_PLL2_DIVP_VALUE <= 128)) || \
defined(__DOXYGEN__)
#define STM32_PLL2_DIVP ((STM32_PLL2_DIVP_VALUE - 1U) << 9U)
#else
@@ -1618,8 +1617,7 @@
/**
* @brief PLL3 DIVP field.
*/
-#if ((STM32_PLL3_DIVP_VALUE >= 2) && (STM32_PLL3_DIVP_VALUE <= 128) && \
- ((STM32_PLL3_DIVP_VALUE & 1U) == 0U)) || \
+#if ((STM32_PLL3_DIVP_VALUE >= 2) && (STM32_PLL3_DIVP_VALUE <= 128)) || \
defined(__DOXYGEN__)
#define STM32_PLL3_DIVP ((STM32_PLL3_DIVP_VALUE - 1U) << 9U)
#else
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-11 05:55:01 +0000