From c845d1fd340f1ce33629dc76ce5134c5dcbf6eb5 Mon Sep 17 00:00:00 2001 From: Rocco Marco Date: Sun, 12 Apr 2015 17:39:52 +0200 Subject: Added email contact Fixed Bug on chDbgAssert() passing 2 arguments instead of 3 --- os/various/devices_lib/l3gd20.c | 10 ++++++---- os/various/devices_lib/l3gd20.h | 6 ++++-- os/various/devices_lib/lis3mdl.c | 8 +++++--- os/various/devices_lib/lis3mdl.h | 6 ++++-- os/various/devices_lib/lsm303dlhc.c | 10 ++++++---- os/various/devices_lib/lsm303dlhc.h | 6 ++++-- os/various/devices_lib/lsm6ds0.c | 8 +++++--- os/various/devices_lib/lsm6ds0.h | 6 ++++-- os/various/devices_lib/max7219.c | 8 +++++--- os/various/devices_lib/max7219.h | 6 ++++-- os/various/devices_lib/nrf24l01.c | 14 ++++++++------ os/various/devices_lib/nrf24l01.h | 6 ++++-- 12 files changed, 59 insertions(+), 35 deletions(-) diff --git a/os/various/devices_lib/l3gd20.c b/os/various/devices_lib/l3gd20.c index 2d93ee8..13238e5 100644 --- a/os/various/devices_lib/l3gd20.c +++ b/os/various/devices_lib/l3gd20.c @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -21,7 +21,9 @@ Special thanks to Giovanni Di Sirio for teachings, his moral support and friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use it. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** @@ -85,7 +87,7 @@ void l3gd20WriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) { /* Reserved register must not be written, according to the datasheet * this could permanently damage the device. */ - chDbgAssert(FALSE, "lg3d20WriteRegister(), #1", "reserved register"); + chDbgAssert(FALSE, "lg3d20WriteRegister(), reserved register"); case L3GD20_AD_WHO_AM_I: case L3GD20_AD_OUT_TEMP : case L3GD20_AD_STATUS_REG: diff --git a/os/various/devices_lib/l3gd20.h b/os/various/devices_lib/l3gd20.h index 3fc58cb..f36fee1 100644 --- a/os/various/devices_lib/l3gd20.h +++ b/os/various/devices_lib/l3gd20.h @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -22,6 +22,8 @@ friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** diff --git a/os/various/devices_lib/lis3mdl.c b/os/various/devices_lib/lis3mdl.c index dba95c3..12aba53 100644 --- a/os/various/devices_lib/lis3mdl.c +++ b/os/various/devices_lib/lis3mdl.c @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -22,6 +22,8 @@ friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** @@ -117,7 +119,7 @@ void lis3mdlWriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, /* Reserved register must not be written, according to the datasheet * this could permanently damage the device. */ - chDbgAssert(FALSE, "lis3mdlWriteRegister(), #1", "reserved register"); + chDbgAssert(FALSE, "lis3mdlWriteRegister(), reserved register"); case LIS3MDL_SUB_WHO_AM_I: case LIS3MDL_SUB_STATUS_REG: case LIS3MDL_SUB_OUT_X_L: diff --git a/os/various/devices_lib/lis3mdl.h b/os/various/devices_lib/lis3mdl.h index 8ef37ef..458e5b7 100644 --- a/os/various/devices_lib/lis3mdl.h +++ b/os/various/devices_lib/lis3mdl.h @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -22,6 +22,8 @@ friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** diff --git a/os/various/devices_lib/lsm303dlhc.c b/os/various/devices_lib/lsm303dlhc.c index 7861255..59faa16 100644 --- a/os/various/devices_lib/lsm303dlhc.c +++ b/os/various/devices_lib/lsm303dlhc.c @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -22,6 +22,8 @@ friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** @@ -121,7 +123,7 @@ void lsm303dlhcWriteRegister(I2CDriver *i2cp,uint8_t sad, uint8_t sub, /* Reserved register must not be written, according to the datasheet * this could permanently damage the device. */ - chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), #1", "reserved register"); + chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), reserved register"); case LSM303DLHC_SUB_ACC_STATUS_REG: case LSM303DLHC_SUB_ACC_OUT_X_L: case LSM303DLHC_SUB_ACC_OUT_X_H: @@ -172,7 +174,7 @@ void lsm303dlhcWriteRegister(I2CDriver *i2cp,uint8_t sad, uint8_t sub, /* Reserved register must not be written, according to the datasheet * this could permanently damage the device. */ - chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), #1", "reserved register"); + chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), reserved register"); case LSM303DLHC_SUB_COMP_OUT_X_H: case LSM303DLHC_SUB_COMP_OUT_X_L: case LSM303DLHC_SUB_COMP_OUT_Z_H: diff --git a/os/various/devices_lib/lsm303dlhc.h b/os/various/devices_lib/lsm303dlhc.h index 4ea788a..f96a890 100644 --- a/os/various/devices_lib/lsm303dlhc.h +++ b/os/various/devices_lib/lsm303dlhc.h @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -22,6 +22,8 @@ friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** diff --git a/os/various/devices_lib/lsm6ds0.c b/os/various/devices_lib/lsm6ds0.c index 304b340..6d0c3ae 100644 --- a/os/various/devices_lib/lsm6ds0.c +++ b/os/various/devices_lib/lsm6ds0.c @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -22,6 +22,8 @@ friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** @@ -117,7 +119,7 @@ void lsm6ds0WriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, /* Reserved register must not be written, according to the datasheet * this could permanently damage the device. */ - chDbgAssert(FALSE, "lsm6ds0WriteRegister(), #1", "reserved register"); + chDbgAssert(FALSE, "lsm6ds0WriteRegister(), reserved register"); case LSM6DS0_SUB_WHO_AM_I: case LSM6DS0_SUB_INT_GEN_SRC_G: case LSM6DS0_SUB_OUT_TEMP_L: diff --git a/os/various/devices_lib/lsm6ds0.h b/os/various/devices_lib/lsm6ds0.h index 9f27e1b..c32dfcb 100644 --- a/os/various/devices_lib/lsm6ds0.h +++ b/os/various/devices_lib/lsm6ds0.h @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -22,6 +22,8 @@ friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** diff --git a/os/various/devices_lib/max7219.c b/os/various/devices_lib/max7219.c index b15699e..527176e 100644 --- a/os/various/devices_lib/max7219.c +++ b/os/various/devices_lib/max7219.c @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -21,7 +21,9 @@ Special thanks to Giovanni Di Sirio for teachings, his moral support and friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use it. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** diff --git a/os/various/devices_lib/max7219.h b/os/various/devices_lib/max7219.h index 80524be..8b90260 100644 --- a/os/various/devices_lib/max7219.h +++ b/os/various/devices_lib/max7219.h @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -22,6 +22,8 @@ friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** diff --git a/os/various/devices_lib/nrf24l01.c b/os/various/devices_lib/nrf24l01.c index 34d8bff..31e4513 100644 --- a/os/various/devices_lib/nrf24l01.c +++ b/os/various/devices_lib/nrf24l01.c @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -21,7 +21,9 @@ Special thanks to Giovanni Di Sirio for teachings, his moral support and friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use it. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** @@ -123,7 +125,7 @@ NRF24L01_status_t nrf24l01WriteRegister(SPIDriver *spip, uint8_t reg, /* Reserved register must not be written, according to the datasheet * this could permanently damage the device. */ - chDbgAssert(FALSE, "lg3d20WriteRegister(), #1", "reserved register"); + chDbgAssert(FALSE, "lg3d20WriteRegister(), reserved register"); case NRF24L01_AD_OBSERVE_TX: case NRF24L01_AD_CD: case NRF24L01_AD_RX_ADDR_P0: @@ -182,7 +184,7 @@ NRF24L01_status_t nrf24l01WriteAddress(SPIDriver *spip, uint8_t reg, unsigned i; if(addlen > NRF24L01_MAX_ADD_LENGHT) { - chDbgAssert(FALSE, "nrf24l01WriteAddress(), #1", "wrong address length"); + chDbgAssert(FALSE, "nrf24l01WriteAddress(), wrong address length"); return 0; } txbuf[0] = (NRF24L01_CMD_WRITE | reg); @@ -197,7 +199,7 @@ NRF24L01_status_t nrf24l01WriteAddress(SPIDriver *spip, uint8_t reg, /* Reserved register must not be written, according to the datasheet * this could permanently damage the device. */ - chDbgAssert(FALSE, "nrf24l01WriteAddress(), #1", "reserved register"); + chDbgAssert(FALSE, "nrf24l01WriteAddress(), reserved register"); case NRF24L01_AD_OBSERVE_TX: case NRF24L01_AD_CD: case NRF24L01_AD_CONFIG: diff --git a/os/various/devices_lib/nrf24l01.h b/os/various/devices_lib/nrf24l01.h index 7112b9f..c56c66f 100644 --- a/os/various/devices_lib/nrf24l01.h +++ b/os/various/devices_lib/nrf24l01.h @@ -1,6 +1,6 @@ /* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2014 Rocco Marco Guglielmi - + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + This file is part of PLAY for ChibiOS/RT. PLAY is free software; you can redistribute it and/or modify @@ -22,6 +22,8 @@ friendship. Note that some or every piece of this file could be part of the ChibiOS project that is intellectual property of Giovanni Di Sirio. Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org */ /** -- cgit v1.2.3 From 8b32af98adc0f61cbc2ab715a628b84236eb009c Mon Sep 17 00:00:00 2001 From: Rocco Marco Date: Mon, 13 Apr 2015 21:24:47 +0200 Subject: Lib are now totally independent from PLAY --- os/various/devices_lib/l3gd20.c | 5 ----- os/various/devices_lib/l3gd20.h | 5 ----- os/various/devices_lib/lis3mdl.c | 5 ----- os/various/devices_lib/lis3mdl.h | 10 +++------- os/various/devices_lib/lsm303dlhc.c | 4 ---- os/various/devices_lib/lsm303dlhc.h | 5 ----- os/various/devices_lib/lsm6ds0.c | 4 ---- os/various/devices_lib/lsm6ds0.h | 2 -- os/various/devices_lib/max7219.c | 3 --- os/various/devices_lib/max7219.h | 2 -- os/various/devices_lib/nrf24l01.c | 3 --- os/various/devices_lib/nrf24l01.h | 4 ---- 12 files changed, 3 insertions(+), 49 deletions(-) diff --git a/os/various/devices_lib/l3gd20.c b/os/various/devices_lib/l3gd20.c index 13238e5..1cc52c9 100644 --- a/os/various/devices_lib/l3gd20.c +++ b/os/various/devices_lib/l3gd20.c @@ -37,10 +37,8 @@ #include "ch.h" #include "hal.h" -#include "play.h" #include "l3gd20.h" -#if (GYRO_USE_L3GD20) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ @@ -122,7 +120,4 @@ void l3gd20WriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) { spiUnselect(spip); } } - -#endif /* (GYRO_USE_L3GD20) */ - /** @} */ diff --git a/os/various/devices_lib/l3gd20.h b/os/various/devices_lib/l3gd20.h index f36fee1..ff67b21 100644 --- a/os/various/devices_lib/l3gd20.h +++ b/os/various/devices_lib/l3gd20.h @@ -36,7 +36,6 @@ #ifndef _L3GD20_H_ #define _L3GD20_H_ -#if (GYRO_USE_L3GD20) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -240,11 +239,7 @@ extern "C" { } #endif -#endif /* GYRO_USE_L3GD20 */ #endif /* _L3GD20_H_ */ /** @} */ -/* - * TODO PLAY--> add i2c support, and Multiple reg read. - */ diff --git a/os/various/devices_lib/lis3mdl.c b/os/various/devices_lib/lis3mdl.c index 12aba53..99b71e4 100644 --- a/os/various/devices_lib/lis3mdl.c +++ b/os/various/devices_lib/lis3mdl.c @@ -37,11 +37,8 @@ #include "ch.h" #include "hal.h" -#include "play.h" #include "lis3mdl.h" -#if (COMP_USE_LIS3MDL) || defined(__DOXYGEN__) - /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ @@ -151,6 +148,4 @@ void lis3mdlWriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, break; } } - -#endif /* COMP_USE_LIS3MDL */ /** @} */ diff --git a/os/various/devices_lib/lis3mdl.h b/os/various/devices_lib/lis3mdl.h index 458e5b7..e55978e 100644 --- a/os/various/devices_lib/lis3mdl.h +++ b/os/various/devices_lib/lis3mdl.h @@ -36,17 +36,14 @@ #ifndef _LIS3MDL_H_ #define _LIS3MDL_H_ -#if (COMP_USE_LIS3MDL) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ -#if (PLAY_USE_FLOAT) || defined(__DOXYGEN__) #define LIS3MDL_COMP_SENS_4GA ((float)6842.0f) /*!< compass sensitivity with 4 GA full scale [LSB / Ga] */ -#define LIS3MDL_COMP_SENS_8GA ((float)3421.0f) /*!< compass sensitivity with 8 GA full scale [LSB / Ga] */ -#define LIS3MDL_COMP_SENS_12GA ((float)2281.0f) /*!< compass sensitivity with 12 GA full scale [LSB / Ga] */ -#define LIS3MDL_COMP_SENS_16GA ((float)1711.0f) /*!< compass sensitivity with 16 GA full scale [LSB / Ga] */ -#endif /* PLAY_USE_FLOAT */ +#define LIS3MDL_COMP_SENS_8GA ((float)3421.0f) /*!< compass sensitivity with 8 GA full scale [LSB / Ga] */ +#define LIS3MDL_COMP_SENS_12GA ((float)2281.0f) /*!< compass sensitivity with 12 GA full scale [LSB / Ga] */ +#define LIS3MDL_COMP_SENS_16GA ((float)1711.0f) /*!< compass sensitivity with 16 GA full scale [LSB / Ga] */ /** * @name LIS3MDL register names * @{ @@ -256,7 +253,6 @@ extern "C" { } #endif -#endif /* COMP_USE_LIS3MDL */ #endif /* _LIS3MDL_H_ */ /** @} */ diff --git a/os/various/devices_lib/lsm303dlhc.c b/os/various/devices_lib/lsm303dlhc.c index 59faa16..070c49c 100644 --- a/os/various/devices_lib/lsm303dlhc.c +++ b/os/various/devices_lib/lsm303dlhc.c @@ -37,11 +37,8 @@ #include "ch.h" #include "hal.h" -#include "play.h" #include "lsm303dlhc.h" -#if (ACCEL_USE_LSM303DLHC) || (COMP_USE_LSM303DLHC) || defined(__DOXYGEN__) - /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ @@ -205,5 +202,4 @@ void lsm303dlhcWriteRegister(I2CDriver *i2cp,uint8_t sad, uint8_t sub, } } } -#endif /* (ACCEL_USE_LSM303DLHC) || (COMP_USE_LSM303DLHC) */ /** @} */ diff --git a/os/various/devices_lib/lsm303dlhc.h b/os/various/devices_lib/lsm303dlhc.h index f96a890..ed52e68 100644 --- a/os/various/devices_lib/lsm303dlhc.h +++ b/os/various/devices_lib/lsm303dlhc.h @@ -37,7 +37,6 @@ #ifndef _LSM303DLHC_H_ #define _LSM303DLHC_H_ -#if (ACCEL_USE_LSM303DLHC) || (COMP_USE_LSM303DLHC) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -350,10 +349,6 @@ extern "C" { #ifdef __cplusplus } #endif -#endif /* (ACCEL_USE_LSM303DLHC) || (COMP_USE_LSM303DLHC) */ #endif /* _LSM303DLHC_H_ */ /** @} */ -/* - * TODO PLAY--> add spi support, and Multiple reg read. - */ diff --git a/os/various/devices_lib/lsm6ds0.c b/os/various/devices_lib/lsm6ds0.c index 6d0c3ae..da67f12 100644 --- a/os/various/devices_lib/lsm6ds0.c +++ b/os/various/devices_lib/lsm6ds0.c @@ -37,11 +37,8 @@ #include "ch.h" #include "hal.h" -#include "play.h" #include "lsm6ds0.h" -#if (ACCEL_USE_LSM6DS0) || (GYRO_USE_LSM6DS0) || defined(__DOXYGEN__) - /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ @@ -184,5 +181,4 @@ void lsm6ds0WriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, } } -#endif /* (ACCEL_USE_LSM6DS0) || (GYRO_USE_LSM6DS0) */ /** @} */ diff --git a/os/various/devices_lib/lsm6ds0.h b/os/various/devices_lib/lsm6ds0.h index c32dfcb..3631493 100644 --- a/os/various/devices_lib/lsm6ds0.h +++ b/os/various/devices_lib/lsm6ds0.h @@ -36,7 +36,6 @@ #ifndef _LSM6DS0_H_ #define _LSM6DS0_H_ -#if (ACCEL_USE_LSM6DS0) || (GYRO_USE_LSM6DS0) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -481,7 +480,6 @@ extern "C" { } #endif -#endif /* (ACCEL_USE_LSM6DS0) || (GYRO_USE_LSM6DS0) */ #endif /* _LSM6DS0_H_ */ /** @} */ diff --git a/os/various/devices_lib/max7219.c b/os/various/devices_lib/max7219.c index 527176e..0e51167 100644 --- a/os/various/devices_lib/max7219.c +++ b/os/various/devices_lib/max7219.c @@ -37,10 +37,8 @@ #include "ch.h" #include "hal.h" -#include "play.h" #include "max7219.h" -#if (PLAY_USE_MAX7219) || defined (__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ @@ -93,5 +91,4 @@ void max7219WriteRegister(SPIDriver *spip, uint16_t adr, uint8_t data) { spiUnselect(spip); } } -#endif /* PLAY_USE_MAX7219 */ /** @} */ diff --git a/os/various/devices_lib/max7219.h b/os/various/devices_lib/max7219.h index 8b90260..f2bbbdf 100644 --- a/os/various/devices_lib/max7219.h +++ b/os/various/devices_lib/max7219.h @@ -36,7 +36,6 @@ #ifndef _MAX7219_H_ #define _MAX7219_H_ -#if (PLAY_USE_MAX7219) || defined (__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -182,7 +181,6 @@ extern "C" { #ifdef __cplusplus } #endif -#endif /* PLAY_USE_MAX7219 */ #endif /* _MAX7219_H_ */ /** @} */ diff --git a/os/various/devices_lib/nrf24l01.c b/os/various/devices_lib/nrf24l01.c index 31e4513..f526fbe 100644 --- a/os/various/devices_lib/nrf24l01.c +++ b/os/various/devices_lib/nrf24l01.c @@ -37,10 +37,8 @@ #include "ch.h" #include "hal.h" -#include "play.h" #include "nrf24l01.h" -#if (RF_USE_NRF24L01) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ @@ -438,6 +436,5 @@ NRF24L01_status_t nrf24l01WriteTxPlNoAck(SPIDriver *spip, uint8_t paylen, return status; } #endif /* NRF24L01_USE_FEATURE */ -#endif /* RF_USE_NRF24L01 */ /** @} */ diff --git a/os/various/devices_lib/nrf24l01.h b/os/various/devices_lib/nrf24l01.h index c56c66f..86ba127 100644 --- a/os/various/devices_lib/nrf24l01.h +++ b/os/various/devices_lib/nrf24l01.h @@ -36,9 +36,6 @@ #ifndef _NRF24L01_H_ #define _NRF24L01_H_ -#include "playconf.h" - -#if (RF_USE_NRF24L01) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -573,7 +570,6 @@ NRF24L01_status_t nrf24l01WriteTxPlNoAck(SPIDriver *spip, uint8_t paylen, } #endif -#endif /* RF_USE_NRF24L01 */ #endif /* _NRF24L01_H_ */ /** @} */ -- cgit v1.2.3 From c6474b882a3e28dabe18a12f27ba1e544e429d5c Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Tue, 14 Apr 2015 22:40:24 +0200 Subject: Tiva. EXT. Added number of GPIO pins to the registry. --- os/hal/ports/TIVA/TM4C123x/tiva_registry.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h index 09a8c75..04786e0 100644 --- a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h @@ -98,6 +98,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 56 #endif #if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ @@ -122,6 +123,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 48 #endif #if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ @@ -146,6 +148,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 88 #endif #if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) @@ -167,6 +170,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 112 #endif #if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) #define TIVA_HAS_GPIOA TRUE @@ -187,6 +191,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 120 #endif /* GPTM attributes.*/ -- cgit v1.2.3 From 1afe28e9bed89a455947f91f2059152bc047b815 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Tue, 14 Apr 2015 22:43:42 +0200 Subject: Tiva. EXT. Added ext_lld files and added ext_lld.c to platform.mk --- os/hal/ports/TIVA/LLD/ext_lld.c | 977 +++++++++++++++++++++++++++++++++ os/hal/ports/TIVA/LLD/ext_lld.h | 363 ++++++++++++ os/hal/ports/TIVA/TM4C123x/platform.mk | 3 +- os/hal/ports/TIVA/TM4C129x/platform.mk | 3 +- 4 files changed, 1344 insertions(+), 2 deletions(-) create mode 100644 os/hal/ports/TIVA/LLD/ext_lld.c create mode 100644 os/hal/ports/TIVA/LLD/ext_lld.h diff --git a/os/hal/ports/TIVA/LLD/ext_lld.c b/os/hal/ports/TIVA/LLD/ext_lld.c new file mode 100644 index 0000000..56857c2 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/ext_lld.c @@ -0,0 +1,977 @@ +/* + Copyright (C) 2014 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Tiva/ext_lld.c + * @brief Tiva EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Generic interrupt serving code for multiple pins per interrupt + * handler. + */ +#define ext_serve_port_interrupt(gpiop, start) \ + uint32_t mis = gpiop->MIS; \ + \ + gpiop->ICR = mis; \ + \ + if (mis & (1 << 0)) { \ + EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0);\ + } \ + if (mis & (1 << 1)) { \ + EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1);\ + } \ + if (mis & (1 << 2)) { \ + EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2);\ + } \ + if (mis & (1 << 3)) { \ + EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3);\ + } \ + if (mis & (1 << 4)) { \ + EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4);\ + } \ + if (mis & (1 << 5)) { \ + EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5);\ + } \ + if (mis & (1 << 6)) { \ + EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6);\ + } \ + if (mis & (1 << 7)) { \ + EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7);\ + } + +/** + * @brief Generic interrupt serving code for single pin per interrupt + * handler. + */ +#define ext_server_pin_interrupt(gpiop, start, pin) \ + gpiop->ICR = (1 << pin); \ + EXTD1.config->channels[start].cb(&EXTD1, start); + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +const ioportid_t gpio[] = +{ +#if TIVA_HAS_GPIOA + GPIOA, +#endif +#if TIVA_HAS_GPIOB + GPIOB, +#endif +#if TIVA_HAS_GPIOC + GPIOC, +#endif +#if TIVA_HAS_GPIOD + GPIOD, +#endif +#if TIVA_HAS_GPIOE + GPIOE, +#endif +#if TIVA_HAS_GPIOF + GPIOF, +#endif +#if TIVA_HAS_GPIOG + GPIOG, +#endif +#if TIVA_HAS_GPIOH + GPIOH, +#endif +#if TIVA_HAS_GPIOJ + GPIOJ, +#endif +#if TIVA_HAS_GPIOK + GPIOK, +#endif +#if TIVA_HAS_GPIOL + GPIOL, +#endif +#if TIVA_HAS_GPIOM + GPIOM, +#endif +#if TIVA_HAS_GPION + GPION, +#endif +#if TIVA_HAS_GPIOP + GPIOP, +#endif +#if TIVA_HAS_GPIOQ + GPIOQ, +#endif +#if TIVA_HAS_GPIOR + GPIOR, +#endif +#if TIVA_HAS_GPIOS + GPIOS, +#endif +#if TIVA_HAS_GPIOT + GPIOT, +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +static void ext_lld_irq_enable(void) +{ +#if TIVA_HAS_GPIOA + nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOB + nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOC + nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOD + nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOE + nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOF + nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOG + nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOH + nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOJ + nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOK + nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOL + nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOM + nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPION + nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOP + nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOQ + nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOR + nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOS + nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOT + nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY); +#endif +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +static void ext_lld_irq_disable(void) +{ +#if TIVA_HAS_GPIOA + nvicDisableVector(TIVA_GPIOA_NUMBER); +#endif +#if TIVA_HAS_GPIOB + nvicDisableVector(TIVA_GPIOB_NUMBER); +#endif +#if TIVA_HAS_GPIOC + nvicDisableVector(TIVA_GPIOC_NUMBER); +#endif +#if TIVA_HAS_GPIOD + nvicDisableVector(TIVA_GPIOD_NUMBER); +#endif +#if TIVA_HAS_GPIOE + nvicDisableVector(TIVA_GPIOE_NUMBER); +#endif +#if TIVA_HAS_GPIOF + nvicDisableVector(TIVA_GPIOF_NUMBER); +#endif +#if TIVA_HAS_GPIOG + nvicDisableVector(TIVA_GPIOG_NUMBER); +#endif +#if TIVA_HAS_GPIOH + nvicDisableVector(TIVA_GPIOH_NUMBER); +#endif +#if TIVA_HAS_GPIOJ + nvicDisableVector(TIVA_GPIOJ_NUMBER); +#endif +#if TIVA_HAS_GPIOK + nvicDisableVector(TIVA_GPIOK_NUMBER); +#endif +#if TIVA_HAS_GPIOL + nvicDisableVector(TIVA_GPIOL_NUMBER); +#endif +#if TIVA_HAS_GPIOM + nvicDisableVector(TIVA_GPIOM_NUMBER); +#endif +#if TIVA_HAS_GPION + nvicDisableVector(TIVA_GPION_NUMBER); +#endif +#if TIVA_HAS_GPIOP + nvicDisableVector(TIVA_GPIOP0_NUMBER); + nvicDisableVector(TIVA_GPIOP1_NUMBER); + nvicDisableVector(TIVA_GPIOP2_NUMBER); + nvicDisableVector(TIVA_GPIOP3_NUMBER); + nvicDisableVector(TIVA_GPIOP4_NUMBER); + nvicDisableVector(TIVA_GPIOP5_NUMBER); + nvicDisableVector(TIVA_GPIOP6_NUMBER); + nvicDisableVector(TIVA_GPIOP7_NUMBER); +#endif +#if TIVA_HAS_GPIOQ + nvicDisableVector(TIVA_GPIOQ0_NUMBER); + nvicDisableVector(TIVA_GPIOQ1_NUMBER); + nvicDisableVector(TIVA_GPIOQ2_NUMBER); + nvicDisableVector(TIVA_GPIOQ3_NUMBER); + nvicDisableVector(TIVA_GPIOQ4_NUMBER); + nvicDisableVector(TIVA_GPIOQ5_NUMBER); + nvicDisableVector(TIVA_GPIOQ6_NUMBER); + nvicDisableVector(TIVA_GPIOQ7_NUMBER); +#endif +#if TIVA_HAS_GPIOR + nvicDisableVector(TIVA_GPIOR_NUMBER); +#endif +#if TIVA_HAS_GPIOS + nvicDisableVector(TIVA_GPIOS_NUMBER); +#endif +#if TIVA_HAS_GPIOT + nvicDisableVector(TIVA_GPIOT_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) +/** + * @brief GPIOA interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(GPIOA, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) +/** + * @brief GPIOB interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(GPIOB, 8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) +/** + * @brief GPIOC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(GPIOC, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) +/** + * @brief GPIOD interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(GPIOD, 24); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) +/** + * @brief GPIOE interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(GPIOE, 32); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) +/** + * @brief GPIOF interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(GPIOF, 40); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +/** + * @brief GPIOG interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPIOG, 48); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +/** + * @brief GPIOH interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPIOH, 56); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +/** + * @brief GPIOJ interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPIOJ, 64); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +/** + * @brief GPIOK interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPIOK, 72); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +/** + * @brief GPIOL interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPIOL, 80); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +/** + * @brief GPIOM interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPIOM, 88); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +/** + * @brief GPION interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPION, 96); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +/** + * @brief GPIOP0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOP, 104, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOP, 105, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOP, 106, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOP, 107, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOP, 108, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOP, 109, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOP, 110, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOP, 111, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +/** + * @brief GPIOQ0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOQ, 112, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOQ, 113, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOQ, 114, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOQ, 115, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOQ, 116, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOQ, 117, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOQ, 118, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_pin_interrupt(&GPIOQ, 119, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +/** + * @brief GPIOR interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPIOR, 120); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +/** + * @brief GPIOS interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPIOS, 128); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +/** + * @brief GPIOT interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_serve_port_interrupt(&GPIOT, 132); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) +{ + extObjectInit(&EXTD1); +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) +{ + uint8_t i; + + if (extp->state == EXT_STOP) { + ext_lld_irq_enable(); + } + + /* Configuration of automatic channels.*/ + for (i = 0; i < EXT_MAX_CHANNELS; i++) { + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { + ext_lld_channel_enable(extp, i); + } + else { + ext_lld_channel_disable(extp, i); + } + } +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) +{ + if (extp->state == EXT_ACTIVE) { + ext_lld_irq_disable(); + } + +#if TIVA_HAS_GPIOA + GPIOA->IM = 0; +#endif +#if TIVA_HAS_GPIOB + GPIOB->IM = 0; +#endif +#if TIVA_HAS_GPIOC + GPIOC->IM = 0; +#endif +#if TIVA_HAS_GPIOD + GPIOD->IM = 0; +#endif +#if TIVA_HAS_GPIOE + GPIOE->IM = 0; +#endif +#if TIVA_HAS_GPIOF + GPIOF->IM = 0; +#endif +#if TIVA_HAS_GPIOG + GPIOG->IM = 0; +#endif +#if TIVA_HAS_GPIOH + GPIOH->IM = 0; +#endif +#if TIVA_HAS_GPIOJ + GPIOJ->IM = 0; +#endif +#if TIVA_HAS_GPIOK + GPIOK->IM = 0; +#endif +#if TIVA_HAS_GPIOL + GPIOL->IM = 0; +#endif +#if TIVA_HAS_GPIOM + GPIOM->IM = 0; +#endif +#if TIVA_HAS_GPION + GPION->IM = 0; +#endif +#if TIVA_HAS_GPIOP + GPIOP->IM = 0; +#endif +#if TIVA_HAS_GPIOQ + GPIOQ->IM = 0; +#endif +#if TIVA_HAS_GPIOR + GPIOR->IM = 0; +#endif +#if TIVA_HAS_GPIOS + GPIOS->IM = 0; +#endif +#if TIVA_HAS_GPIOT + GPIOT->IM = 0; +#endif +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) +{ + GPIO_TypeDef *gpiop; + uint8_t pin; + uint32_t im; + + pin = channel & 0x07; + gpiop = gpio[channel >> 3]; + + /* Disable interrupts */ + im = gpiop->IM; + gpiop->IM = 0; + + /* Configure pin to be edge-sensitive.*/ + gpiop->IS &= ~(1 << pin); + + /* Programming edge registers.*/ + if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == + EXT_CH_MODE_BOTH_EDGES) { + gpiop->IBE |= (1 << pin); + } + else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == + EXT_CH_MODE_FALLING_EDGE) { + gpiop->IBE &= ~(1 << pin); + gpiop->IEV &= ~(1 << pin); + } + else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == + EXT_CH_MODE_RISING_EDGE) { + gpiop->IBE &= ~(1 << pin); + gpiop->IEV |= (1 << pin); + } + + /* Programming interrupt and event registers.*/ + if ((extp->config->channels[channel].cb != NULL) && + ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) != + EXT_CH_MODE_DISABLED)) { + im |= (1 << pin); + } + else { + im &= ~(1 << pin); + } + + /* Restore interrupts */ + gpiop->IM = im; +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) +{ + (void)extp; + GPIO_TypeDef *gpiop; + uint8_t pin; + + pin = channel & 0x07; + gpiop = gpio[channel >> 3]; + + gpiop->IM &= ~(1 << pin); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/ext_lld.h b/os/hal/ports/TIVA/LLD/ext_lld.h new file mode 100644 index 0000000..15232e2 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/ext_lld.h @@ -0,0 +1,363 @@ +/* + Copyright (C) 2014 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Tiva/ext_lld.h + * @brief Tiva EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_H_ +#define _EXT_LLD_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of EXT per port. + */ +#define EXT_MAX_CHANNELS TIVA_GPIO_PINS + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPIOA interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOA_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOB interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOB_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOC interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOC_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOD interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOD_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOE interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOE_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOF interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOF_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOG interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOG_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOH interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOH_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOJ interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOJ_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOK interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOK_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOL interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOL_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOM interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOM_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPION interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPION_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP0 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP1 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP2 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP3 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP4 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP5 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP6 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP7 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP7_IRQ_PRIORITY 3 +#endif +/** @} */ + +/** + * @brief GPIOQ0 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ1 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ2 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ3 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ4 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ5 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ6 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ7 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOR interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOR_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOS interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOS_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOT interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOT_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk index 0f54c5a..e808142 100644 --- a/os/hal/ports/TIVA/TM4C123x/platform.mk +++ b/os/hal/ports/TIVA/TM4C123x/platform.mk @@ -8,7 +8,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/gpt_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pwm_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/spi_lld.c \ - ${CHISIOS}/community/os/hal/ports/TIVA/LLD/tiva_udma.c + ${CHISIOS}/community/os/hal/ports/TIVA/LLD/tiva_udma.c \ + ${CHISIOS}/community/os/hal/ports/TIVA/LLD/ext_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index 35de5ce..97a5a73 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -4,7 +4,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/st_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pal_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c \ - ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/mac_lld.c + ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/mac_lld.c \ + ${CHISIOS}/community/os/hal/ports/TIVA/LLD/ext_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ -- cgit v1.2.3 From f4e68ad23a5b61a0a87e52afd1f71ae0d593229d Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Tue, 14 Apr 2015 22:52:22 +0200 Subject: Tiva. EXT. Wrapped ext_serve_port_interrupt and ext_serve_pin_interrupt in a do{}while(0) --- os/hal/ports/TIVA/LLD/ext_lld.c | 68 ++++++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 32 deletions(-) diff --git a/os/hal/ports/TIVA/LLD/ext_lld.c b/os/hal/ports/TIVA/LLD/ext_lld.c index 56857c2..c4c7163 100644 --- a/os/hal/ports/TIVA/LLD/ext_lld.c +++ b/os/hal/ports/TIVA/LLD/ext_lld.c @@ -34,43 +34,47 @@ * @brief Generic interrupt serving code for multiple pins per interrupt * handler. */ -#define ext_serve_port_interrupt(gpiop, start) \ - uint32_t mis = gpiop->MIS; \ - \ - gpiop->ICR = mis; \ - \ - if (mis & (1 << 0)) { \ - EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0);\ - } \ - if (mis & (1 << 1)) { \ - EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1);\ - } \ - if (mis & (1 << 2)) { \ - EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2);\ - } \ - if (mis & (1 << 3)) { \ - EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3);\ - } \ - if (mis & (1 << 4)) { \ - EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4);\ - } \ - if (mis & (1 << 5)) { \ - EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5);\ - } \ - if (mis & (1 << 6)) { \ - EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6);\ - } \ - if (mis & (1 << 7)) { \ - EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7);\ - } +#define ext_serve_port_interrupt(gpiop, start) \ + do { \ + uint32_t mis = gpiop->MIS; \ + \ + gpiop->ICR = mis; \ + \ + if (mis & (1 << 0)) { \ + EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ + } \ + if (mis & (1 << 1)) { \ + EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1); \ + } \ + if (mis & (1 << 2)) { \ + EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2); \ + } \ + if (mis & (1 << 3)) { \ + EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3); \ + } \ + if (mis & (1 << 4)) { \ + EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4); \ + } \ + if (mis & (1 << 5)) { \ + EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5); \ + } \ + if (mis & (1 << 6)) { \ + EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6); \ + } \ + if (mis & (1 << 7)) { \ + EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7); \ + } \ + } while (0); /** * @brief Generic interrupt serving code for single pin per interrupt * handler. */ -#define ext_server_pin_interrupt(gpiop, start, pin) \ - gpiop->ICR = (1 << pin); \ - EXTD1.config->channels[start].cb(&EXTD1, start); +#define ext_server_pin_interrupt(gpiop, start, pin) \ + do { \ + gpiop->ICR = (1 << pin); \ + EXTD1.config->channels[start].cb(&EXTD1, start); \ + } while (0); /*===========================================================================*/ /* Driver exported variables. */ -- cgit v1.2.3 From 2c66f5477153fcbf503c8a6aca6d99e4e5da3e9d Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Tue, 14 Apr 2015 22:53:48 +0200 Subject: Tiva. EXT. Fixed typo in ext_serve_pin_interrupt macro. --- os/hal/ports/TIVA/LLD/ext_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/ports/TIVA/LLD/ext_lld.c b/os/hal/ports/TIVA/LLD/ext_lld.c index c4c7163..20a001a 100644 --- a/os/hal/ports/TIVA/LLD/ext_lld.c +++ b/os/hal/ports/TIVA/LLD/ext_lld.c @@ -70,7 +70,7 @@ * @brief Generic interrupt serving code for single pin per interrupt * handler. */ -#define ext_server_pin_interrupt(gpiop, start, pin) \ +#define ext_serve_pin_interrupt(gpiop, start, pin) \ do { \ gpiop->ICR = (1 << pin); \ EXTD1.config->channels[start].cb(&EXTD1, start); \ -- cgit v1.2.3 From a8358f2140d54e4e32fae935d94d95e3d5e03ded Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Tue, 14 Apr 2015 23:00:29 +0200 Subject: Tiva. EXT. Changed name of ext_serve_port_interrupt and ext_serve_pin_interrupt. --- os/hal/ports/TIVA/LLD/ext_lld.c | 72 ++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/os/hal/ports/TIVA/LLD/ext_lld.c b/os/hal/ports/TIVA/LLD/ext_lld.c index 20a001a..dc58d99 100644 --- a/os/hal/ports/TIVA/LLD/ext_lld.c +++ b/os/hal/ports/TIVA/LLD/ext_lld.c @@ -34,7 +34,7 @@ * @brief Generic interrupt serving code for multiple pins per interrupt * handler. */ -#define ext_serve_port_interrupt(gpiop, start) \ +#define ext_lld_serve_port_interrupt(gpiop, start) \ do { \ uint32_t mis = gpiop->MIS; \ \ @@ -70,7 +70,7 @@ * @brief Generic interrupt serving code for single pin per interrupt * handler. */ -#define ext_serve_pin_interrupt(gpiop, start, pin) \ +#define ext_lld_serve_pin_interrupt(gpiop, start, pin) \ do { \ gpiop->ICR = (1 << pin); \ EXTD1.config->channels[start].cb(&EXTD1, start); \ @@ -152,7 +152,7 @@ const ioportid_t gpio[] = /*===========================================================================*/ /** - * @brief Enables EXTI IRQ sources. + * @brief Enables GPIO IRQ sources. * * @notapi */ @@ -229,7 +229,7 @@ static void ext_lld_irq_enable(void) } /** - * @brief Disables EXTI IRQ sources. + * @brief Disables GPIO IRQ sources. * * @notapi */ @@ -319,7 +319,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(GPIOA, 0); + ext_lld_serve_port_interrupt(GPIOA, 0); OSAL_IRQ_EPILOGUE(); } @@ -335,7 +335,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(GPIOB, 8); + ext_lld_serve_port_interrupt(GPIOB, 8); OSAL_IRQ_EPILOGUE(); } @@ -351,7 +351,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(GPIOC, 16); + ext_lld_serve_port_interrupt(GPIOC, 16); OSAL_IRQ_EPILOGUE(); } @@ -367,7 +367,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(GPIOD, 24); + ext_lld_serve_port_interrupt(GPIOD, 24); OSAL_IRQ_EPILOGUE(); } @@ -383,7 +383,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(GPIOE, 32); + ext_lld_serve_port_interrupt(GPIOE, 32); OSAL_IRQ_EPILOGUE(); } @@ -399,7 +399,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(GPIOF, 40); + ext_lld_serve_port_interrupt(GPIOF, 40); OSAL_IRQ_EPILOGUE(); } @@ -415,7 +415,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPIOG, 48); + ext_lld_serve_port_interrupt(&GPIOG, 48); OSAL_IRQ_EPILOGUE(); } @@ -431,7 +431,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPIOH, 56); + ext_lld_serve_port_interrupt(&GPIOH, 56); OSAL_IRQ_EPILOGUE(); } @@ -447,7 +447,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPIOJ, 64); + ext_lld_serve_port_interrupt(&GPIOJ, 64); OSAL_IRQ_EPILOGUE(); } @@ -463,7 +463,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPIOK, 72); + ext_lld_serve_port_interrupt(&GPIOK, 72); OSAL_IRQ_EPILOGUE(); } @@ -479,7 +479,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPIOL, 80); + ext_lld_serve_port_interrupt(&GPIOL, 80); OSAL_IRQ_EPILOGUE(); } @@ -495,7 +495,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPIOM, 88); + ext_lld_serve_port_interrupt(&GPIOM, 88); OSAL_IRQ_EPILOGUE(); } @@ -511,7 +511,7 @@ OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPION, 96); + ext_lld_serve_port_interrupt(&GPION, 96); OSAL_IRQ_EPILOGUE(); } @@ -527,7 +527,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOP, 104, 0); + ext_lld_serve_pin_interrupt(&GPIOP, 104, 0); OSAL_IRQ_EPILOGUE(); } @@ -541,7 +541,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOP, 105, 1); + ext_lld_serve_pin_interrupt(&GPIOP, 105, 1); OSAL_IRQ_EPILOGUE(); } @@ -555,7 +555,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOP, 106, 2); + ext_lld_serve_pin_interrupt(&GPIOP, 106, 2); OSAL_IRQ_EPILOGUE(); } @@ -569,7 +569,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOP, 107, 3); + ext_lld_serve_pin_interrupt(&GPIOP, 107, 3); OSAL_IRQ_EPILOGUE(); } @@ -583,7 +583,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOP, 108, 4); + ext_lld_serve_pin_interrupt(&GPIOP, 108, 4); OSAL_IRQ_EPILOGUE(); } @@ -597,7 +597,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOP, 109, 5); + ext_lld_serve_pin_interrupt(&GPIOP, 109, 5); OSAL_IRQ_EPILOGUE(); } @@ -611,7 +611,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOP, 110, 6); + ext_lld_serve_pin_interrupt(&GPIOP, 110, 6); OSAL_IRQ_EPILOGUE(); } @@ -625,7 +625,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOP, 111, 7); + ext_lld_serve_pin_interrupt(&GPIOP, 111, 7); OSAL_IRQ_EPILOGUE(); } @@ -641,7 +641,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOQ, 112, 0); + ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0); OSAL_IRQ_EPILOGUE(); } @@ -655,7 +655,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOQ, 113, 1); + ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1); OSAL_IRQ_EPILOGUE(); } @@ -669,7 +669,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOQ, 114, 2); + ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2); OSAL_IRQ_EPILOGUE(); } @@ -683,7 +683,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOQ, 115, 3); + ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3); OSAL_IRQ_EPILOGUE(); } @@ -697,7 +697,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOQ, 116, 4); + ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4); OSAL_IRQ_EPILOGUE(); } @@ -711,7 +711,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOQ, 117, 5); + ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5); OSAL_IRQ_EPILOGUE(); } @@ -725,7 +725,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOQ, 118, 6); + ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6); OSAL_IRQ_EPILOGUE(); } @@ -739,7 +739,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_pin_interrupt(&GPIOQ, 119, 7); + ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7); OSAL_IRQ_EPILOGUE(); } @@ -755,7 +755,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPIOR, 120); + ext_lld_serve_port_interrupt(&GPIOR, 120); OSAL_IRQ_EPILOGUE(); } @@ -771,7 +771,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPIOS, 128); + ext_lld_serve_port_interrupt(&GPIOS, 128); OSAL_IRQ_EPILOGUE(); } @@ -787,7 +787,7 @@ OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) { OSAL_IRQ_PROLOGUE(); - ext_serve_port_interrupt(&GPIOT, 132); + ext_lld_serve_port_interrupt(&GPIOT, 132); OSAL_IRQ_EPILOGUE(); } -- cgit v1.2.3 From 246a8cc1d7e387324a8021a7490995a553607d24 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Tue, 14 Apr 2015 23:06:48 +0200 Subject: Tiva. EXT. Added EXT testhal demo for TM4C123x. --- testhal/TIVA/TM4C123x/EXT/.cproject | 51 +++ testhal/TIVA/TM4C123x/EXT/.project | 106 +++++ testhal/TIVA/TM4C123x/EXT/Makefile | 197 +++++++++ testhal/TIVA/TM4C123x/EXT/chconf.h | 468 +++++++++++++++++++++ ... (prompts for .cfg target configuration).launch | 10 + .../TM4C123x-EXT (OpenOCD, Flash and Run).launch | 52 +++ testhal/TIVA/TM4C123x/EXT/halconf.h | 278 ++++++++++++ testhal/TIVA/TM4C123x/EXT/main.c | 126 ++++++ testhal/TIVA/TM4C123x/EXT/mcuconf.h | 152 +++++++ 9 files changed, 1440 insertions(+) create mode 100644 testhal/TIVA/TM4C123x/EXT/.cproject create mode 100644 testhal/TIVA/TM4C123x/EXT/.project create mode 100644 testhal/TIVA/TM4C123x/EXT/Makefile create mode 100644 testhal/TIVA/TM4C123x/EXT/chconf.h create mode 100644 testhal/TIVA/TM4C123x/EXT/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch create mode 100644 testhal/TIVA/TM4C123x/EXT/debug/TM4C123x-EXT (OpenOCD, Flash and Run).launch create mode 100644 testhal/TIVA/TM4C123x/EXT/halconf.h create mode 100644 testhal/TIVA/TM4C123x/EXT/main.c create mode 100644 testhal/TIVA/TM4C123x/EXT/mcuconf.h diff --git a/testhal/TIVA/TM4C123x/EXT/.cproject b/testhal/TIVA/TM4C123x/EXT/.cproject new file mode 100644 index 0000000..5aa94c5 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/TIVA/TM4C123x/EXT/.project b/testhal/TIVA/TM4C123x/EXT/.project new file mode 100644 index 0000000..79bd112 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/.project @@ -0,0 +1,106 @@ + + + TM4C123x-EXT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS3/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD + + + community_os + 2 + CHIBIOS3/community/os + + + os + 2 + CHIBIOS3/os + + + test + 2 + CHIBIOS3/test + + + + + CHIBIOS3 + file:/C:/ChibiStudio/chibios3 + + + diff --git a/testhal/TIVA/TM4C123x/EXT/Makefile b/testhal/TIVA/TM4C123x/EXT/Makefile new file mode 100644 index 0000000..e3845c1 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/Makefile @@ -0,0 +1,197 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../.. +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk +include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/TM4C123xH6.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(OSALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/TIVA/TM4C123x/EXT/chconf.h b/testhal/TIVA/TM4C123x/EXT/chconf.h new file mode 100644 index 0000000..5e26c27 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/chconf.h @@ -0,0 +1,468 @@ +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 0 + +/** + * @brief Realtime Counter frequency. + * @details Frequency of the system counter used for realtime delays and + * measurements. + */ +#define CH_CFG_RTC_FREQUENCY 80000000 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_TRACE FALSE + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/TIVA/TM4C123x/EXT/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch b/testhal/TIVA/TM4C123x/EXT/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch new file mode 100644 index 0000000..8772f9c --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/testhal/TIVA/TM4C123x/EXT/debug/TM4C123x-EXT (OpenOCD, Flash and Run).launch b/testhal/TIVA/TM4C123x/EXT/debug/TM4C123x-EXT (OpenOCD, Flash and Run).launch new file mode 100644 index 0000000..d963642 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/debug/TM4C123x-EXT (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/TIVA/TM4C123x/EXT/halconf.h b/testhal/TIVA/TM4C123x/EXT/halconf.h new file mode 100644 index 0000000..bb46d6e --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/halconf.h @@ -0,0 +1,278 @@ +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT TRUE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/TIVA/TM4C123x/EXT/main.c b/testhal/TIVA/TM4C123x/EXT/main.c new file mode 100644 index 0000000..3d15451 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/main.c @@ -0,0 +1,126 @@ +/* + Copyright (C) 2014 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void extcb1(EXTDriver *extp, expchannel_t channel) +{ + (void)extp; + (void)channel; + + palTogglePad(GPIOF, GPIOF_LED_RED); +} + +static void extcb2(EXTDriver *extp, expchannel_t channel) +{ + (void)extp; + (void)channel; + + palTogglePad(GPIOF, GPIOF_LED_GREEN); +} + +static const EXTConfig extcfg = +{ + { + /* GPIOA */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOB */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOC */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOD */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOE */ + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + /* GPIOF */ + {EXT_CH_MODE_FALLING_EDGE | EXT_CH_MODE_AUTOSTART, extcb1}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART, extcb2}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL}, + {EXT_CH_MODE_DISABLED, NULL} + } +}; + +/* + * Application entry point. + */ +int main(void) +{ + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + palSetPadMode(GPIOF, GPIOF_LED_RED, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GPIOF, GPIOF_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GPIOF, GPIOF_SW1, PAL_MODE_INPUT_PULLUP); + palSetPadMode(GPIOF, GPIOF_SW2, PAL_MODE_INPUT_PULLUP); + + extStart(&EXTD1, &extcfg); + + /* + * Normal main() thread activity + */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + + return 0; +} diff --git a/testhal/TIVA/TM4C123x/EXT/mcuconf.h b/testhal/TIVA/TM4C123x/EXT/mcuconf.h new file mode 100644 index 0000000..99b4536 --- /dev/null +++ b/testhal/TIVA/TM4C123x/EXT/mcuconf.h @@ -0,0 +1,152 @@ +/* + * TM4C123x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 7...0 Lowest...Highest. + */ + +#define TM4C123x_MCUCONF + +/* + * HAL driver system settings. + */ +#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_MOSC_ENABLE TRUE +#define TIVA_DIV400_VALUE 1 +#define TIVA_SYSDIV_VALUE 2 +#define TIVA_USESYSDIV_ENABLE FALSE +#define TIVA_SYSDIV2LSB_ENABLE FALSE +#define TIVA_BYPASS_VALUE 0 +#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \ + TIVA_RCC_PWMDIV_8) + +/* + * GPIO driver system settings. + */ +#define TIVA_GPIO_GPIOA_USE_AHB TRUE +#define TIVA_GPIO_GPIOB_USE_AHB TRUE +#define TIVA_GPIO_GPIOC_USE_AHB TRUE +#define TIVA_GPIO_GPIOD_USE_AHB TRUE +#define TIVA_GPIO_GPIOE_USE_AHB TRUE +#define TIVA_GPIO_GPIOF_USE_AHB TRUE + +/* + * GPT driver system settings. + */ +#define TIVA_GPT_USE_GPT0 FALSE +#define TIVA_GPT_USE_GPT1 FALSE +#define TIVA_GPT_USE_GPT2 FALSE +#define TIVA_GPT_USE_GPT3 FALSE +#define TIVA_GPT_USE_GPT4 FALSE +#define TIVA_GPT_USE_GPT5 FALSE +#define TIVA_GPT_USE_WGPT0 FALSE +#define TIVA_GPT_USE_WGPT1 FALSE +#define TIVA_GPT_USE_WGPT2 FALSE +#define TIVA_GPT_USE_WGPT3 FALSE +#define TIVA_GPT_USE_WGPT4 FALSE +#define TIVA_GPT_USE_WGPT5 FALSE + +#define TIVA_GPT_GPT0A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT1A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT2A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT3A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT4A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT5A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT0A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT1A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT2A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT3A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT4A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT5A_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define TIVA_I2C_USE_I2C0 FALSE +#define TIVA_I2C_USE_I2C1 FALSE +#define TIVA_I2C_USE_I2C2 FALSE +#define TIVA_I2C_USE_I2C3 FALSE +#define TIVA_I2C_USE_I2C4 FALSE +#define TIVA_I2C_USE_I2C5 FALSE +#define TIVA_I2C_USE_I2C6 FALSE +#define TIVA_I2C_USE_I2C7 FALSE +#define TIVA_I2C_I2C0_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C1_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C2_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C3_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C4_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C5_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C6_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C7_IRQ_PRIORITY 4 + +/* + * PWM driver system settings. + */ +#define TIVA_PWM_USE_PWM0 FALSE +#define TIVA_PWM_USE_PWM1 FALSE +#define TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_0_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_1_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_2_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_3_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_0_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_1_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_2_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_3_IRQ_PRIORITY 4 + +/* + * SERIAL driver system settings. + */ +#define TIVA_SERIAL_USE_UART0 FALSE +#define TIVA_SERIAL_USE_UART1 FALSE +#define TIVA_SERIAL_USE_UART2 FALSE +#define TIVA_SERIAL_USE_UART3 FALSE +#define TIVA_SERIAL_USE_UART4 FALSE +#define TIVA_SERIAL_USE_UART5 FALSE +#define TIVA_SERIAL_USE_UART6 FALSE +#define TIVA_SERIAL_USE_UART7 FALSE +#define TIVA_SERIAL_UART0_PRIORITY 5 +#define TIVA_SERIAL_UART1_PRIORITY 5 +#define TIVA_SERIAL_UART2_PRIORITY 5 +#define TIVA_SERIAL_UART3_PRIORITY 5 +#define TIVA_SERIAL_UART4_PRIORITY 5 +#define TIVA_SERIAL_UART5_PRIORITY 5 +#define TIVA_SERIAL_UART6_PRIORITY 5 +#define TIVA_SERIAL_UART7_PRIORITY 5 + +/* + * SPI driver system settings. + */ +#define TIVA_SPI_USE_SSI0 TRUE +#define TIVA_SPI_USE_SSI1 FALSE +#define TIVA_SPI_USE_SSI2 FALSE +#define TIVA_SPI_USE_SSI3 FALSE +#define TIVA_SPI_SSI0_RX_UDMA_CHANNEL 10 +#define TIVA_SPI_SSI1_RX_UDMA_CHANNEL 24 +#define TIVA_SPI_SSI2_RX_UDMA_CHANNEL 12 +#define TIVA_SPI_SSI3_RX_UDMA_CHANNEL 14 +#define TIVA_SPI_SSI0_TX_UDMA_CHANNEL 11 +#define TIVA_SPI_SSI1_TX_UDMA_CHANNEL 25 +#define TIVA_SPI_SSI2_TX_UDMA_CHANNEL 13 +#define TIVA_SPI_SSI3_TX_UDMA_CHANNEL 15 +#define TIVA_SPI_SSI0_RX_UDMA_MAPPING 0 +#define TIVA_SPI_SSI1_RX_UDMA_MAPPING 0 +#define TIVA_SPI_SSI2_RX_UDMA_MAPPING 2 +#define TIVA_SPI_SSI3_RX_UDMA_MAPPING 2 +#define TIVA_SPI_SSI0_TX_UDMA_MAPPING 0 +#define TIVA_SPI_SSI1_TX_UDMA_MAPPING 0 +#define TIVA_SPI_SSI2_TX_UDMA_MAPPING 2 +#define TIVA_SPI_SSI3_TX_UDMA_MAPPING 2 + +/* + * ST driver system settings. + */ +#define TIVA_ST_IRQ_PRIORITY 2 +#define TIVA_ST_USE_WIDE_TIMER TRUE +#define TIVA_ST_TIMER_NUMBER 5 +#define TIVA_ST_TIMER_LETTER A -- cgit v1.2.3 From 8c36a9827508ff7fa9b46b1fd90c96de519bc0d7 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Wed, 15 Apr 2015 21:42:29 +0200 Subject: Tiva. Updated Tiva linker files to the new format. --- .../ports/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld | 24 +++++++++++++++++++- .../ports/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld | 24 +++++++++++++++++++- .../ports/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld | 24 +++++++++++++++++++- .../ports/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld | 23 ++++++++++++++++++- .../ports/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld | 24 +++++++++++++++++++- .../ports/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld | 26 ++++++++++++++++++++-- 6 files changed, 138 insertions(+), 7 deletions(-) diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld index 53e04bd..8f676a0 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xC3.ld @@ -20,7 +20,29 @@ MEMORY { flash : org = 0x00000000, len = 32k - ram : org = 0x20000000, len = 12k + ram0 : org = 0x20000000, len = 12k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld index 4378c41..1968cd0 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xD5.ld @@ -20,7 +20,29 @@ MEMORY { flash : org = 0x00000000, len = 64k - ram : org = 0x20000000, len = 24k + ram0 : org = 0x20000000, len = 24k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld index cad084f..7b12b53 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xE6.ld @@ -20,7 +20,29 @@ MEMORY { flash : org = 0x00000000, len = 128k - ram : org = 0x20000000, len = 32k + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld index ecdcf26..5c049b9 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C123xH6.ld @@ -20,7 +20,28 @@ MEMORY { flash : org = 0x00000000, len = 256k - ram : org = 0x20000000, len = 32k + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld index 875158e..0f3fef1 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xKC.ld @@ -20,7 +20,29 @@ MEMORY { flash : org = 0x00000000, len = 512k - ram : org = 0x20000000, len = 256k + ram0 : org = 0x20000000, len = 256k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld index f36164e..fd23266 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/TM4C129xNC.ld @@ -19,8 +19,30 @@ */ MEMORY { - flash : org = 0x00000000, len = 1024k - ram : org = 0x20000000, len = 256k + flash : org = 0x00000000, len = 1M + ram0 : org = 0x20000000, len = 256k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 } +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + + INCLUDE rules.ld -- cgit v1.2.3 From 772a39d3e99d331ab850b8fa3b78632184d88af1 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Wed, 15 Apr 2015 23:04:13 +0200 Subject: Tiva. Removed port_tm4c123x.mk and port_tm4c129x.mk files. --- os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk | 15 --------------- os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk | 15 --------------- os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk | 15 --------------- os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk | 15 --------------- 4 files changed, 60 deletions(-) delete mode 100644 os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk delete mode 100644 os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk delete mode 100644 os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk delete mode 100644 os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk deleted file mode 100644 index bd76209..0000000 --- a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M4F TM4C123x port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \ - ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \ - ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s \ - $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s - -PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \ - ${CHIBIOS}/community/os/common/ports/ARMCMx/devices/TM4C123x \ - ${CHIBIOS}/os/nil/ports/ARMCMx \ - ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC - -PORTLD = ${CHIBIOS}/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk deleted file mode 100644 index 7e55117..0000000 --- a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M4F TM4C129x port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \ - ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \ - ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s \ - $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s - -PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \ - ${CHIBIOS}/community/os/common/ports/ARMCMx/devices/TM4C129x \ - ${CHIBIOS}/os/nil/ports/ARMCMx \ - ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC - -PORTLD = ${CHIBIOS}/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk deleted file mode 100644 index 470f42d..0000000 --- a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M4F TM4C123x port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \ - ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \ - ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s \ - $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s - -PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \ - ${CHIBIOS}/community/os/common/ports/ARMCMx/devices/TM4C123x \ - ${CHIBIOS}/os/rt/ports/ARMCMx \ - ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC - -PORTLD = ${CHIBIOS}/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk deleted file mode 100644 index 0891b83..0000000 --- a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of the ChibiOS/RT Cortex-M4F TM4C129x port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \ - ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \ - ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s \ - $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s - -PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \ - ${CHIBIOS}/community/os/common/ports/ARMCMx/devices/TM4C129x \ - ${CHIBIOS}/os/rt/ports/ARMCMx \ - ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC - -PORTLD = ${CHIBIOS}/community/os/common/ports/ARMCMx/compilers/GCC/ld -- cgit v1.2.3 From 491f5ff6750717c6fdfaad368332563ba5b58ffa Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Wed, 15 Apr 2015 23:05:43 +0200 Subject: Tiva. Fixed Tiva CORTEX_MODEL definitions in cmparams.h. --- os/common/ports/ARMCMx/devices/TM4C123x/cmparams.h | 2 +- os/common/ports/ARMCMx/devices/TM4C129x/cmparams.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/os/common/ports/ARMCMx/devices/TM4C123x/cmparams.h b/os/common/ports/ARMCMx/devices/TM4C123x/cmparams.h index 3e5457c..c9e98bd 100644 --- a/os/common/ports/ARMCMx/devices/TM4C123x/cmparams.h +++ b/os/common/ports/ARMCMx/devices/TM4C123x/cmparams.h @@ -26,7 +26,7 @@ /** * @brief Cortex core model. */ -#define CORTEX_MODEL CORTEX_M4 +#define CORTEX_MODEL 4 /** * @brief Memory Protection unit presence. diff --git a/os/common/ports/ARMCMx/devices/TM4C129x/cmparams.h b/os/common/ports/ARMCMx/devices/TM4C129x/cmparams.h index ea5821f..5bd8a7b 100644 --- a/os/common/ports/ARMCMx/devices/TM4C129x/cmparams.h +++ b/os/common/ports/ARMCMx/devices/TM4C129x/cmparams.h @@ -26,7 +26,7 @@ /** * @brief Cortex core model. */ -#define CORTEX_MODEL CORTEX_M4 +#define CORTEX_MODEL 4 /** * @brief Memory Protection unit presence. -- cgit v1.2.3 From 9d14e38afea0e28e66deb5abe182751b802ceed9 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Wed, 15 Apr 2015 23:16:23 +0200 Subject: Tiva. Added new startup files. --- os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk | 10 ++++++++++ os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk | 10 ++++++++++ 2 files changed, 20 insertions(+) create mode 100644 os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk create mode 100644 os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk diff --git a/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk new file mode 100644 index 0000000..35d4fc8 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk @@ -0,0 +1,10 @@ +# List of the ChibiOS generic TM4C123x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c + +STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s + +STARTUPINC = $(CHIBIOS)/community/os/common/ports/ARMCMx/devices/TM4C123x \ + $(CHIBIOS)/os/ext/CMSIS/include + +STARTUPLD = $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/ld diff --git a/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk new file mode 100644 index 0000000..6ce72da --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk @@ -0,0 +1,10 @@ +# List of the ChibiOS generic TM4C129x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c + +STARTUPASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0_v7m.s + +STARTUPINC = $(CHIBIOS)/community/os/common/ports/ARMCMx/devices/TM4C129x \ + $(CHIBIOS)/os/ext/CMSIS/include + +STARTUPLD = $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/ld -- cgit v1.2.3 From 23c2cabf28f94fc4a32b7013f29c35cbeee31904 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 16 Apr 2015 19:19:03 +0200 Subject: Tiva. Updated makefiles for Tiva demos and testhal. --- demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile | 34 +++++++++++++------ demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile | 46 +++++++++++++++----------- demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile | 34 +++++++++++++------ testhal/TIVA/TM4C123x/EXT/Makefile | 36 +++++++++++++------- testhal/TIVA/TM4C123x/GPT/Makefile | 35 ++++++++++++++------ testhal/TIVA/TM4C123x/I2C/Makefile | 38 +++++++++++++-------- testhal/TIVA/TM4C123x/PWM/Makefile | 37 ++++++++++++++------- testhal/TIVA/TM4C123x/SPI/Makefile | 37 ++++++++++++++------- 8 files changed, 196 insertions(+), 101 deletions(-) diff --git a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile index 6a6d35e..884406a 100644 --- a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile +++ b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,26 +81,32 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -123,10 +134,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -150,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile index 2841644..12680c1 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -lm + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,31 +81,33 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C129x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk -include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C129xNC.ld +LDSCRIPT= $(STARTUPLD)/TM4C129xNC.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ - $(LWSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - main.c \ - web/web.c \ - $(CHIBIOS)/os/various/chprintf.c + $(TESTSRC) \ + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -127,10 +134,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -154,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex @@ -180,7 +188,7 @@ CPPWARN = -Wall -Wextra # # List all user C define here, like -D_DEBUG=1 -UDEFS = -DLWIP_DEBUG=0 +UDEFS = # Define ASM defines here UADEFS = diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile index 5321329..12680c1 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,26 +81,32 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C129x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C129xNC.ld +LDSCRIPT= $(STARTUPLD)/TM4C129xNC.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -123,10 +134,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -150,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/testhal/TIVA/TM4C123x/EXT/Makefile b/testhal/TIVA/TM4C123x/EXT/Makefile index e3845c1..43de29b 100644 --- a/testhal/TIVA/TM4C123x/EXT/Makefile +++ b/testhal/TIVA/TM4C123x/EXT/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,25 +81,31 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -122,10 +133,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -149,6 +160,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/testhal/TIVA/TM4C123x/GPT/Makefile b/testhal/TIVA/TM4C123x/GPT/Makefile index abbd840..dde090d 100644 --- a/testhal/TIVA/TM4C123x/GPT/Makefile +++ b/testhal/TIVA/TM4C123x/GPT/Makefile @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,25 +81,32 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -122,10 +134,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -149,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/testhal/TIVA/TM4C123x/I2C/Makefile b/testhal/TIVA/TM4C123x/I2C/Makefile index 4123eb6..dde090d 100644 --- a/testhal/TIVA/TM4C123x/I2C/Makefile +++ b/testhal/TIVA/TM4C123x/I2C/Makefile @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,27 +81,33 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ - main.c \ - $(CHIBIOS)/os/various/chprintf.c + $(TESTSRC) \ + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -123,10 +134,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -150,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/testhal/TIVA/TM4C123x/PWM/Makefile b/testhal/TIVA/TM4C123x/PWM/Makefile index e3845c1..dde090d 100644 --- a/testhal/TIVA/TM4C123x/PWM/Makefile +++ b/testhal/TIVA/TM4C123x/PWM/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,25 +81,32 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -122,10 +134,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -149,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex diff --git a/testhal/TIVA/TM4C123x/SPI/Makefile b/testhal/TIVA/TM4C123x/SPI/Makefile index e3845c1..dde090d 100644 --- a/testhal/TIVA/TM4C123x/SPI/Makefile +++ b/testhal/TIVA/TM4C123x/SPI/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). @@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = yes @@ -58,9 +63,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = no + USE_FPU = hard endif # @@ -76,25 +81,32 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. +# Startup files. +include $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS)/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c123x.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk # Define linker script file here -LDSCRIPT= $(PORTLD)/TM4C123xH6.ld +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = $(PORTSRC) \ +CSRC = $(STARTUPSRC) \ $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ + $(PORTSRC) \ $(OSALSRC) \ + $(HALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ + $(TESTSRC) \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -122,10 +134,10 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) +ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ +INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ $(CHIBIOS)/os/various # @@ -149,6 +161,7 @@ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar OD = $(TRGT)objdump SZ = $(TRGT)size HEX = $(CP) -O ihex -- cgit v1.2.3 From 6ed850b0a53659c3891a1fb41863ca741af54ef3 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 16 Apr 2015 21:16:10 +0200 Subject: Tiva. Fixed makefile for RT-TM4C1294-LAUNCHPAD-LWIP demo. --- demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile index 12680c1..ed53024 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile @@ -92,7 +92,7 @@ include $(CHIBIOS)/os/hal/osal/rt/osal.mk include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). -include $(CHIBIOS)/test/rt/test.mk +include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk # Define linker script file here LDSCRIPT= $(STARTUPLD)/TM4C129xNC.ld @@ -107,7 +107,10 @@ CSRC = $(STARTUPSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ $(TESTSRC) \ - main.c + $(LWSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + main.c \ + web/web.c \ # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -138,7 +141,7 @@ ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ - $(CHIBIOS)/os/various + $(CHIBIOS)/os/various $(LWINC) # # Project, sources and paths -- cgit v1.2.3 From b0bba2957e303f610ed9cd60a760104c70cad51a Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 16 Apr 2015 21:41:36 +0200 Subject: Tiva. Removed unnecessary include of test.mk in makefiles. --- testhal/TIVA/TM4C123x/GPT/Makefile | 1 - testhal/TIVA/TM4C123x/PWM/Makefile | 1 - testhal/TIVA/TM4C123x/SPI/Makefile | 1 - 3 files changed, 3 deletions(-) diff --git a/testhal/TIVA/TM4C123x/GPT/Makefile b/testhal/TIVA/TM4C123x/GPT/Makefile index dde090d..43de29b 100644 --- a/testhal/TIVA/TM4C123x/GPT/Makefile +++ b/testhal/TIVA/TM4C123x/GPT/Makefile @@ -92,7 +92,6 @@ include $(CHIBIOS)/os/hal/osal/rt/osal.mk include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). -include $(CHIBIOS)/test/rt/test.mk # Define linker script file here LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld diff --git a/testhal/TIVA/TM4C123x/PWM/Makefile b/testhal/TIVA/TM4C123x/PWM/Makefile index dde090d..43de29b 100644 --- a/testhal/TIVA/TM4C123x/PWM/Makefile +++ b/testhal/TIVA/TM4C123x/PWM/Makefile @@ -92,7 +92,6 @@ include $(CHIBIOS)/os/hal/osal/rt/osal.mk include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). -include $(CHIBIOS)/test/rt/test.mk # Define linker script file here LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld diff --git a/testhal/TIVA/TM4C123x/SPI/Makefile b/testhal/TIVA/TM4C123x/SPI/Makefile index dde090d..43de29b 100644 --- a/testhal/TIVA/TM4C123x/SPI/Makefile +++ b/testhal/TIVA/TM4C123x/SPI/Makefile @@ -92,7 +92,6 @@ include $(CHIBIOS)/os/hal/osal/rt/osal.mk include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). -include $(CHIBIOS)/test/rt/test.mk # Define linker script file here LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld -- cgit v1.2.3 From e62aae545ae8c1047b863911f5a880dd075dbfe8 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 16 Apr 2015 21:42:15 +0200 Subject: Tiva. Fixed I2C testhal makefile. --- testhal/TIVA/TM4C123x/I2C/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/testhal/TIVA/TM4C123x/I2C/Makefile b/testhal/TIVA/TM4C123x/I2C/Makefile index dde090d..3aa487c 100644 --- a/testhal/TIVA/TM4C123x/I2C/Makefile +++ b/testhal/TIVA/TM4C123x/I2C/Makefile @@ -92,7 +92,6 @@ include $(CHIBIOS)/os/hal/osal/rt/osal.mk include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). -include $(CHIBIOS)/test/rt/test.mk # Define linker script file here LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld @@ -107,7 +106,8 @@ CSRC = $(STARTUPSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ $(TESTSRC) \ - main.c + $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -138,7 +138,7 @@ ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ - $(CHIBIOS)/os/various + $(CHIBIOS)/os/various $(CHIBIOS)/os/hal/lib/streams # # Project, sources and paths -- cgit v1.2.3 From 7b7c6fd19853d05fe7758d074360754ec8fcf05c Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 16 Apr 2015 21:46:53 +0200 Subject: Tiva. Replaced all references to CORTEX_IS_VALID_KERNEL_PRIORITY with OSAL_IRQ_IS_VALID_PRIORITY. --- os/hal/ports/TIVA/LLD/gpt_lld.h | 24 ++++++++++++------------ os/hal/ports/TIVA/LLD/i2c_lld.h | 20 ++++++++++---------- os/hal/ports/TIVA/LLD/pwm_lld.h | 20 ++++++++++---------- os/hal/ports/TIVA/LLD/serial_lld.h | 16 ++++++++-------- os/hal/ports/TIVA/LLD/spi_lld.h | 10 +++++----- os/hal/ports/TIVA/TM4C123x/hal_lld.h | 2 +- os/hal/ports/TIVA/TM4C129x/hal_lld.h | 2 +- 7 files changed, 47 insertions(+), 47 deletions(-) diff --git a/os/hal/ports/TIVA/LLD/gpt_lld.h b/os/hal/ports/TIVA/LLD/gpt_lld.h index 0e27017..2f1f75d 100644 --- a/os/hal/ports/TIVA/LLD/gpt_lld.h +++ b/os/hal/ports/TIVA/LLD/gpt_lld.h @@ -294,62 +294,62 @@ #endif #if TIVA_GPT_USE_GPT0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT0A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT0A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT0" #endif #if TIVA_GPT_USE_GPT1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT1A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT1A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT1" #endif #if TIVA_GPT_USE_GPT2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT2A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT2A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT2" #endif #if TIVA_GPT_USE_GPT3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT3A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT3A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT3" #endif #if TIVA_GPT_USE_GPT4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT4A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT4A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT4" #endif #if TIVA_GPT_USE_GPT5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT5A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT5A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to GPT5" #endif #if TIVA_GPT_USE_WGPT0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT0A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT0A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT0" #endif #if TIVA_GPT_USE_WGPT1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT1A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT1A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT1" #endif #if TIVA_GPT_USE_WGPT2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT2A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT2A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT2" #endif #if TIVA_GPT_USE_WGPT3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT3A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT3A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT3" #endif #if TIVA_GPT_USE_WGPT4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT4A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT4A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT4" #endif #if TIVA_GPT_USE_WGPT5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT5A_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT5A_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to WGPT5" #endif diff --git a/os/hal/ports/TIVA/LLD/i2c_lld.h b/os/hal/ports/TIVA/LLD/i2c_lld.h index 9b7b743..1479600 100644 --- a/os/hal/ports/TIVA/LLD/i2c_lld.h +++ b/os/hal/ports/TIVA/LLD/i2c_lld.h @@ -300,52 +300,52 @@ #endif #if TIVA_I2C_USE_I2C0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C0_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C0" #endif #if TIVA_I2C_USE_I2C1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C1_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C1" #endif #if TIVA_I2C_USE_I2C2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C2_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C2" #endif #if TIVA_I2C_USE_I2C3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C3_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C3" #endif #if TIVA_I2C_USE_I2C4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C4_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C4_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C4" #endif #if TIVA_I2C_USE_I2C5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C5_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C5_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C5" #endif #if TIVA_I2C_USE_I2C6 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C6_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C6_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C6" #endif #if TIVA_I2C_USE_I2C7 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C7_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C7_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C7" #endif #if TIVA_I2C_USE_I2C8 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C8_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C8_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C8" #endif #if TIVA_I2C_USE_I2C9 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C9_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C9_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C9" #endif diff --git a/os/hal/ports/TIVA/LLD/pwm_lld.h b/os/hal/ports/TIVA/LLD/pwm_lld.h index 70ba97b..472bae8 100644 --- a/os/hal/ports/TIVA/LLD/pwm_lld.h +++ b/os/hal/ports/TIVA/LLD/pwm_lld.h @@ -154,52 +154,52 @@ #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 FAULT" #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_0_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 GEN0" #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_1_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 GEN1" #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_2_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 GEN2" #endif #if TIVA_PWM_USE_PWM0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_3_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM0 GEN3" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 FAULT" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_0_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 GEN0" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_1_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 GEN1" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_2_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 GEN2" #endif #if TIVA_PWM_USE_PWM1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_3_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to PWM1 GEN3" #endif diff --git a/os/hal/ports/TIVA/LLD/serial_lld.h b/os/hal/ports/TIVA/LLD/serial_lld.h index 5ba4645..535d0a5 100644 --- a/os/hal/ports/TIVA/LLD/serial_lld.h +++ b/os/hal/ports/TIVA/LLD/serial_lld.h @@ -341,42 +341,42 @@ #endif #if TIVA_SERIAL_USE_UART0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART0_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART0_PRIORITY) #error "Invalid IRQ priority assigned to UART0" #endif #if TIVA_SERIAL_USE_UART1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART1_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART1_PRIORITY) #error "Invalid IRQ priority assigned to UART1" #endif #if TIVA_SERIAL_USE_UART2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART2_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART2_PRIORITY) #error "Invalid IRQ priority assigned to UART2" #endif #if TIVA_SERIAL_USE_UART3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART3_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART3_PRIORITY) #error "Invalid IRQ priority assigned to UART3" #endif #if TIVA_SERIAL_USE_UART4 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART4_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART4_PRIORITY) #error "Invalid IRQ priority assigned to UART4" #endif #if TIVA_SERIAL_USE_UART5 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART5_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART5_PRIORITY) #error "Invalid IRQ priority assigned to UART5" #endif #if TIVA_SERIAL_USE_UART6 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART6_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART6_PRIORITY) #error "Invalid IRQ priority assigned to UART6" #endif #if TIVA_SERIAL_USE_UART7 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART7_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART7_PRIORITY) #error "Invalid IRQ priority assigned to UART7" #endif diff --git a/os/hal/ports/TIVA/LLD/spi_lld.h b/os/hal/ports/TIVA/LLD/spi_lld.h index c757a22..5c04d69 100644 --- a/os/hal/ports/TIVA/LLD/spi_lld.h +++ b/os/hal/ports/TIVA/LLD/spi_lld.h @@ -114,7 +114,7 @@ */ #define TIVA_DMACTL_RXDMAE (1 << 0) #define TIVA_DMACTL_TXDMAE (1 << 1) -/** @} +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -222,22 +222,22 @@ #endif #if TIVA_SPI_USE_SSI0 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI0_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI0_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI0" #endif #if TIVA_SPI_USE_SSI1 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI1_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI1" #endif #if TIVA_SPI_USE_SSI2 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI2_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI2" #endif #if TM4C123x_SPI_USE_SSI3 && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI3" #endif diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h index 72b53b4..b81ace8 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h @@ -330,7 +330,7 @@ #define TIVA_SYSCLK (TIVA_SRC / (((TIVA_SYSDIV_VALUE << TIVA_DIV400_VALUE /*& TIVA_BYPASS_VALUE*/) | (TIVA_SYSDIV2LSB >> 22)) + 1)) #if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_ST_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SysTick" #endif diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/os/hal/ports/TIVA/TM4C129x/hal_lld.h index a0e769b..a89a11d 100644 --- a/os/hal/ports/TIVA/TM4C129x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.h @@ -345,7 +345,7 @@ #define TIVA_SYSCLK 120000000 #if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC && \ - !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_ST_IRQ_PRIORITY) + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SysTick" #endif -- cgit v1.2.3 From cd95bc80f0ee01fe059164a072a5e51390429b8e Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 16 Apr 2015 21:56:32 +0200 Subject: Tiva. EXT. Added checks for valid interrupt priorities. --- os/hal/ports/TIVA/LLD/ext_lld.h | 160 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/os/hal/ports/TIVA/LLD/ext_lld.h b/os/hal/ports/TIVA/LLD/ext_lld.h index 15232e2..3817130 100644 --- a/os/hal/ports/TIVA/LLD/ext_lld.h +++ b/os/hal/ports/TIVA/LLD/ext_lld.h @@ -274,6 +274,166 @@ /* Derived constants and error checks. */ /*===========================================================================*/ +#if TIVA_HAS_GPIOA && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOA" +#endif + +#if TIVA_HAS_GPIOB && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOB" +#endif + +#if TIVA_HAS_GPIOC && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOC" +#endif + +#if TIVA_HAS_GPIOD && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOD" +#endif + +#if TIVA_HAS_GPIOE && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOE" +#endif + +#if TIVA_HAS_GPIOF && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOF" +#endif + +#if TIVA_HAS_GPIOG && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOG" +#endif + +#if TIVA_HAS_GPIOH && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOH" +#endif + +#if TIVA_HAS_GPIOJ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOJ" +#endif + +#if TIVA_HAS_GPIOK && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOK" +#endif + +#if TIVA_HAS_GPIOL && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOL" +#endif + +#if TIVA_HAS_GPIOM && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOM" +#endif + +#if TIVA_HAS_GPION && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPION" +#endif + +#if TIVA_HAS_GPIOP0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP0" +#endif + +#if TIVA_HAS_GPIOP1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP1" +#endif + +#if TIVA_HAS_GPIOP2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP2" +#endif + +#if TIVA_HAS_GPIOP3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP3" +#endif + +#if TIVA_HAS_GPIOP4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP4" +#endif + +#if TIVA_HAS_GPIOP5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP5" +#endif + +#if TIVA_HAS_GPIOP6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP6" +#endif + +#if TIVA_HAS_GPIOP7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP7" +#endif + +#if TIVA_HAS_GPIOQ0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ0" +#endif + +#if TIVA_HAS_GPIOQ1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ1" +#endif + +#if TIVA_HAS_GPIOQ2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ2" +#endif + +#if TIVA_HAS_GPIOQ3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ3" +#endif + +#if TIVA_HAS_GPIOQ4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ4" +#endif + +#if TIVA_HAS_GPIOQ5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ5" +#endif + +#if TIVA_HAS_GPIOQ6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ6" +#endif + +#if TIVA_HAS_GPIOQ7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ7" +#endif + +#if TIVA_HAS_GPIOR && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOR" +#endif + +#if TIVA_HAS_GPIOS && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOS" +#endif + +#if TIVA_HAS_GPIOT && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOT" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ -- cgit v1.2.3 From 5130840d32ee59d311d4875cb09edbd84facad71 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 16 Apr 2015 22:03:13 +0200 Subject: Tiva. MAC. Added check for valid interrupt priority. --- os/hal/ports/TIVA/LLD/mac_lld.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/os/hal/ports/TIVA/LLD/mac_lld.h b/os/hal/ports/TIVA/LLD/mac_lld.h index 7c86dbd..af088b0 100644 --- a/os/hal/ports/TIVA/LLD/mac_lld.h +++ b/os/hal/ports/TIVA/LLD/mac_lld.h @@ -262,6 +262,10 @@ #error "TIVA_MAC_PHY_TIMEOUT requires the realtime counter service" #endif +#if !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_MAC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to MAC" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ -- cgit v1.2.3 From e5f1b8b034f66fa3aa4dd45f6c69da191e326c03 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 16 Apr 2015 22:15:15 +0200 Subject: Tiva. ST. Moved ST interrupt priority check from hal_lld to st_lld. --- os/hal/ports/TIVA/LLD/st_lld.h | 5 +++++ os/hal/ports/TIVA/TM4C123x/hal_lld.h | 5 ----- os/hal/ports/TIVA/TM4C129x/hal_lld.h | 5 ----- 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/os/hal/ports/TIVA/LLD/st_lld.h b/os/hal/ports/TIVA/LLD/st_lld.h index bec1a36..23b3ef5 100644 --- a/os/hal/ports/TIVA/LLD/st_lld.h +++ b/os/hal/ports/TIVA/LLD/st_lld.h @@ -164,6 +164,11 @@ #error "wrong value defined for TIVA_ST_USE_WIDE_TIMER" #endif +#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ST" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h index b81ace8..5c2cd25 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h @@ -329,11 +329,6 @@ */ #define TIVA_SYSCLK (TIVA_SRC / (((TIVA_SYSDIV_VALUE << TIVA_DIV400_VALUE /*& TIVA_BYPASS_VALUE*/) | (TIVA_SYSDIV2LSB >> 22)) + 1)) -#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SysTick" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/os/hal/ports/TIVA/TM4C129x/hal_lld.h index a89a11d..dc6644f 100644 --- a/os/hal/ports/TIVA/TM4C129x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.h @@ -344,11 +344,6 @@ */ #define TIVA_SYSCLK 120000000 -#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SysTick" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ -- cgit v1.2.3 From 50398ec98ef7f07ec3adbdfa5d9f9829f092df59 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 16 Apr 2015 22:38:12 +0200 Subject: Tiva. Fixed wrong define of TIVA_ST_USE_WIDE_TIMER in mcuconf.h for TM4C129x demos. --- demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h | 2 +- demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h index a3c6b3b..00b4fe5 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h @@ -95,6 +95,6 @@ * ST driver system settings. */ #define TIVA_ST_IRQ_PRIORITY 2 -#define TIVA_ST_USE_WIDE_TIMER TRUE +#define TIVA_ST_USE_WIDE_TIMER FALSE #define TIVA_ST_TIMER_NUMBER 5 #define TIVA_ST_TIMER_LETTER A diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h index a3c6b3b..00b4fe5 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h @@ -95,6 +95,6 @@ * ST driver system settings. */ #define TIVA_ST_IRQ_PRIORITY 2 -#define TIVA_ST_USE_WIDE_TIMER TRUE +#define TIVA_ST_USE_WIDE_TIMER FALSE #define TIVA_ST_TIMER_NUMBER 5 #define TIVA_ST_TIMER_LETTER A -- cgit v1.2.3 From a67bba56af1bfc5f8c24c03ef6c9c411518e802e Mon Sep 17 00:00:00 2001 From: Rocco Marco Date: Fri, 17 Apr 2015 00:44:32 +0200 Subject: Reorganized devices_lib folder Removed some others pre-processor directives --- os/various/devices_lib/l3gd20.c | 123 ------- os/various/devices_lib/l3gd20.h | 245 ------------- os/various/devices_lib/lis3mdl.c | 151 -------- os/various/devices_lib/lis3mdl.h | 258 -------------- os/various/devices_lib/lsm303dlhc.c | 205 ----------- os/various/devices_lib/lsm303dlhc.h | 354 ------------------- os/various/devices_lib/lsm6ds0.c | 184 ---------- os/various/devices_lib/lsm6ds0.h | 485 -------------------------- os/various/devices_lib/max7219.c | 94 ----- os/various/devices_lib/max7219.h | 187 ---------- os/various/devices_lib/mems/l3gd20.c | 123 +++++++ os/various/devices_lib/mems/l3gd20.h | 243 +++++++++++++ os/various/devices_lib/mems/lis3mdl.c | 151 ++++++++ os/various/devices_lib/mems/lis3mdl.h | 258 ++++++++++++++ os/various/devices_lib/mems/lsm303dlhc.c | 205 +++++++++++ os/various/devices_lib/mems/lsm303dlhc.h | 352 +++++++++++++++++++ os/various/devices_lib/mems/lsm6ds0.c | 184 ++++++++++ os/various/devices_lib/mems/lsm6ds0.h | 482 ++++++++++++++++++++++++++ os/various/devices_lib/nrf24l01.c | 440 ----------------------- os/various/devices_lib/nrf24l01.h | 575 ------------------------------- os/various/devices_lib/others/max7219.c | 94 +++++ os/various/devices_lib/others/max7219.h | 187 ++++++++++ os/various/devices_lib/rf/nrf24l01.c | 440 +++++++++++++++++++++++ os/various/devices_lib/rf/nrf24l01.h | 575 +++++++++++++++++++++++++++++++ 24 files changed, 3294 insertions(+), 3301 deletions(-) delete mode 100644 os/various/devices_lib/l3gd20.c delete mode 100644 os/various/devices_lib/l3gd20.h delete mode 100644 os/various/devices_lib/lis3mdl.c delete mode 100644 os/various/devices_lib/lis3mdl.h delete mode 100644 os/various/devices_lib/lsm303dlhc.c delete mode 100644 os/various/devices_lib/lsm303dlhc.h delete mode 100644 os/various/devices_lib/lsm6ds0.c delete mode 100644 os/various/devices_lib/lsm6ds0.h delete mode 100644 os/various/devices_lib/max7219.c delete mode 100644 os/various/devices_lib/max7219.h create mode 100644 os/various/devices_lib/mems/l3gd20.c create mode 100644 os/various/devices_lib/mems/l3gd20.h create mode 100644 os/various/devices_lib/mems/lis3mdl.c create mode 100644 os/various/devices_lib/mems/lis3mdl.h create mode 100644 os/various/devices_lib/mems/lsm303dlhc.c create mode 100644 os/various/devices_lib/mems/lsm303dlhc.h create mode 100644 os/various/devices_lib/mems/lsm6ds0.c create mode 100644 os/various/devices_lib/mems/lsm6ds0.h delete mode 100644 os/various/devices_lib/nrf24l01.c delete mode 100644 os/various/devices_lib/nrf24l01.h create mode 100644 os/various/devices_lib/others/max7219.c create mode 100644 os/various/devices_lib/others/max7219.h create mode 100644 os/various/devices_lib/rf/nrf24l01.c create mode 100644 os/various/devices_lib/rf/nrf24l01.h diff --git a/os/various/devices_lib/l3gd20.c b/os/various/devices_lib/l3gd20.c deleted file mode 100644 index 1cc52c9..0000000 --- a/os/various/devices_lib/l3gd20.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file l3gd20.c - * @brief L3GD20 MEMS interface module code. - * - * @addtogroup l3gd20 - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "l3gd20.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic register value. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] reg register number - * @return register value. - */ -uint8_t l3gd20ReadRegister(SPIDriver *spip, uint8_t reg) { - uint8_t txbuf[2] = {L3GD20_RW | reg, 0xFF}; - uint8_t rxbuf[2] = {0x00, 0x00}; - spiSelect(spip); - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[1]; -} - - -void l3gd20WriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) { - - switch (reg) { - - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lg3d20WriteRegister(), reserved register"); - case L3GD20_AD_WHO_AM_I: - case L3GD20_AD_OUT_TEMP : - case L3GD20_AD_STATUS_REG: - case L3GD20_AD_OUT_X_L: - case L3GD20_AD_OUT_X_H: - case L3GD20_AD_OUT_Y_L: - case L3GD20_AD_OUT_Y_H: - case L3GD20_AD_OUT_Z_L: - case L3GD20_AD_OUT_Z_H: - case L3GD20_AD_FIFO_SRC_REG: - case L3GD20_AD_INT1_SRC: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case L3GD20_AD_CTRL_REG1: - case L3GD20_AD_CTRL_REG2: - case L3GD20_AD_CTRL_REG3: - case L3GD20_AD_CTRL_REG4: - case L3GD20_AD_CTRL_REG5: - case L3GD20_AD_REFERENCE: - case L3GD20_AD_FIFO_CTRL_REG: - case L3GD20_AD_INT1_CFG: - case L3GD20_AD_INT1_TSH_XH: - case L3GD20_AD_INT1_TSH_XL: - case L3GD20_AD_INT1_TSH_YH: - case L3GD20_AD_INT1_TSH_YL: - case L3GD20_AD_INT1_TSH_ZH: - case L3GD20_AD_INT1_TSH_ZL: - case L3GD20_AD_INT1_DURATION: - spiSelect(spip); - uint8_t txbuf[2] = {reg, value}; - spiSend(spip, 2, txbuf); - spiUnselect(spip); - } -} -/** @} */ diff --git a/os/various/devices_lib/l3gd20.h b/os/various/devices_lib/l3gd20.h deleted file mode 100644 index ff67b21..0000000 --- a/os/various/devices_lib/l3gd20.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file l3gd20.h - * @brief L3GD20 MEMS interface module header. - * - * @{ - */ - -#ifndef _L3GD20_H_ -#define _L3GD20_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#if (PLAY_USE_FLOAT) || defined(__DOXYGEN__) -#define L3GD20_SENS_250DPS ((float)131.072f) /*!< gyroscope sensitivity with 250 dps full scale [LSB/dps] */ -#define L3GD20_SENS_500DPS ((float)65.536f) /*!< gyroscope sensitivity with 500 dps full scale [LSB/dps] */ -#define L3GD20_SENS_2000DPS ((float)16.384f) /*!< gyroscope sensitivity with 2000 dps full scale [LSB/dps] */ -#endif /* PLAY_USE_FLOAT */ -/** - * @name L3GD20 register names - * @{ - */ -/******************************************************************************/ -/* */ -/* L3GD20 on board MEMS */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SPI communication *******************/ -#define L3GD20_DI ((uint8_t)0xFF) /*!< DI[7:0] Data input */ -#define L3GD20_DI_0 ((uint8_t)0x01) /*!< bit 0 */ -#define L3GD20_DI_1 ((uint8_t)0x02) /*!< bit 1 */ -#define L3GD20_DI_2 ((uint8_t)0x04) /*!< bit 2 */ -#define L3GD20_DI_3 ((uint8_t)0x08) /*!< bit 3 */ -#define L3GD20_DI_4 ((uint8_t)0x10) /*!< bit 4 */ -#define L3GD20_DI_5 ((uint8_t)0x20) /*!< bit 5 */ -#define L3GD20_DI_6 ((uint8_t)0x40) /*!< bit 6 */ -#define L3GD20_DI_7 ((uint8_t)0x80) /*!< bit 7 */ - -#define L3GD20_AD ((uint8_t)0x3F) /*!< AD[5:0] Address Data */ -#define L3GD20_AD_0 ((uint8_t)0x01) /*!< bit 0 */ -#define L3GD20_AD_1 ((uint8_t)0x02) /*!< bit 1 */ -#define L3GD20_AD_2 ((uint8_t)0x04) /*!< bit 2 */ -#define L3GD20_AD_3 ((uint8_t)0x08) /*!< bit 3 */ -#define L3GD20_AD_4 ((uint8_t)0x10) /*!< bit 4 */ -#define L3GD20_AD_5 ((uint8_t)0x20) /*!< bit 5 */ - -#define L3GD20_MS ((uint8_t)0x40) /*!< Multiple read write */ -#define L3GD20_RW ((uint8_t)0x80) /*!< Read Write, 1 0 */ - -/****************** Bit definition for Registers Addresses *******************/ -#define L3GD20_AD_WHO_AM_I ((uint8_t)0x0F) /*!< WHO I AM */ -#define L3GD20_AD_CTRL_REG1 ((uint8_t)0x20) /*!< CONTROL REGISTER 1 */ -#define L3GD20_AD_CTRL_REG2 ((uint8_t)0x21) /*!< CONTROL REGISTER 2 */ -#define L3GD20_AD_CTRL_REG3 ((uint8_t)0x22) /*!< CONTROL REGISTER 3 */ -#define L3GD20_AD_CTRL_REG4 ((uint8_t)0x23) /*!< CONTROL REGISTER 4 */ -#define L3GD20_AD_CTRL_REG5 ((uint8_t)0x24) /*!< CONTROL REGISTER 5 */ -#define L3GD20_AD_REFERENCE ((uint8_t)0x25) /*!< REFERENCE/DATACAPTURE */ -#define L3GD20_AD_OUT_TEMP ((uint8_t)0x26) /*!< MEMS ONBOARD TEMP SENSOR */ -#define L3GD20_AD_STATUS_REG ((uint8_t)0x27) /*!< STATUS REGISTER */ -#define L3GD20_AD_OUT_X_L ((uint8_t)0x28) /*!< OUTPUT X-AXIS LOW */ -#define L3GD20_AD_OUT_X_H ((uint8_t)0x29) /*!< OUTPUT X-AXIS HIGH */ -#define L3GD20_AD_OUT_Y_L ((uint8_t)0x2A) /*!< OUTPUT Y-AXIS LOW */ -#define L3GD20_AD_OUT_Y_H ((uint8_t)0x2B) /*!< OUTPUT Y-AXIS HIGH */ -#define L3GD20_AD_OUT_Z_L ((uint8_t)0x2C) /*!< OUTPUT Z-AXIS LOW */ -#define L3GD20_AD_OUT_Z_H ((uint8_t)0x2D) /*!< OUTPUT Z-AXIS HIGH */ -#define L3GD20_AD_FIFO_CTRL_REG ((uint8_t)0x2E) /*!< FIFO CONTROL REGISTER */ -#define L3GD20_AD_FIFO_SRC_REG ((uint8_t)0x2F) /*!< FIFO SOURCE REGISTER */ -#define L3GD20_AD_INT1_CFG ((uint8_t)0x30) /*!< INTERRUPT1 CONFIG REGISTER */ -#define L3GD20_AD_INT1_SRC ((uint8_t)0x31) /*!< INTERRUPT1 SOURCE REGISTER */ -#define L3GD20_AD_INT1_TSH_XH ((uint8_t)0x32) /*!< INTERRUPT1 THRESHOLD X-AXIS HIGH */ -#define L3GD20_AD_INT1_TSH_XL ((uint8_t)0x33) /*!< INTERRUPT1 THRESHOLD X-AXIS LOW */ -#define L3GD20_AD_INT1_TSH_YH ((uint8_t)0x34) /*!< INTERRUPT1 THRESHOLD Y-AXIS HIGH */ -#define L3GD20_AD_INT1_TSH_YL ((uint8_t)0x35) /*!< INTERRUPT1 THRESHOLD Y-AXIS LOW */ -#define L3GD20_AD_INT1_TSH_ZH ((uint8_t)0x36) /*!< INTERRUPT1 THRESHOLD Z-AXIS HIGH */ -#define L3GD20_AD_INT1_TSH_ZL ((uint8_t)0x37) /*!< INTERRUPT1 THRESHOLD Z-AXIS LOW */ -#define L3GD20_AD_INT1_DURATION ((uint8_t)0x38) /*!< INTERRUPT1 DURATION */ - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name Gyroscope data structures and types - * @{ - */ - -/** - * @brief Gyroscope Output Data Rate - */ -typedef enum { - L3GD20_ODR_95Hz_Fc_12_5 = 0x00, /*!< Output Data Rate = 95 Hz - LPF Cut-Off = 12.5 Hz */ - L3GD20_ODR_95Hz_Fc_25 = 0x10, /*!< Output Data Rate = 95 Hz - LPF Cut-Off = 25 Hz */ - L3GD20_ODR_190Hz_Fc_12_5 = 0x40, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 12.5 Hz */ - L3GD20_ODR_190Hz_Fc_25 = 0x50, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 25 Hz */ - L3GD20_ODR_190Hz_Fc_50 = 0x60, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 50 Hz */ - L3GD20_ODR_190Hz_Fc_70 = 0x70, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 70 Hz */ - L3GD20_ODR_380Hz_Fc_20 = 0x80, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 20 Hz */ - L3GD20_ODR_380Hz_Fc_25 = 0x90, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 25 Hz */ - L3GD20_ODR_380Hz_Fc_50 = 0xA0, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 50 Hz */ - L3GD20_ODR_380Hz_Fc_100 = 0xB0, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 100 Hz */ - L3GD20_ODR_760Hz_Fc_30 = 0xC0, /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 30 Hz */ - L3GD20_ODR_760Hz_Fc_35 = 0xD0, /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 35 Hz */ - L3GD20_ODR_760Hz_Fc_50 = 0xE0, /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 50 Hz */ - L3GD20_ODR_760Hz_Fc_100 = 0xF0 /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 100 Hz */ -}L3GD20_ODR_t; - -/** - * @brief Gyroscope Power Mode - */ -typedef enum { - L3GD20_PM_POWER_DOWN = 0x00, /*!< Normal mode enabled */ - L3GD20_PM_SLEEP_NORMAL = 0x08 /*!< Low Power mode enabled */ -}L3GD20_PM_t; - -/** - * @brief Gyroscope Full Scale - */ -typedef enum { - L3GD20_FS_250DPS = 0x00, /*!< ±250 dps */ - L3GD20_FS_500DPS = 0x10, /*!< ±500 dps */ - L3GD20_FS_2000DPS = 0x20 /*!< ±200 dps */ -}L3GD20_FS_t; - -/** - * @brief Gyroscope Axes Enabling - */ -typedef enum { - L3GD20_AE_DISABLED = 0x00, /*!< All disabled */ - L3GD20_AE_X = 0x01, /*!< Only X */ - L3GD20_AE_Y = 0x02, /*!< Only Y */ - L3GD20_AE_XY = 0x03, /*!< X & Y */ - L3GD20_AE_Z = 0x04, /*!< Only Z */ - L3GD20_AE_XZ = 0x05, /*!< X & Z */ - L3GD20_AE_YZ = 0x06, /*!< Y & Z */ - L3GD20_AE_XYZ = 0x07 /*!< All enabled */ -}L3GD20_AE_t; - -/** - * @brief Gyroscope Block Data Update - */ -typedef enum { - L3GD20_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ - L3GD20_BDU_BLOCKED = 0x80 /*!< Single Update: output registers not updated until MSB and LSB reading */ -}L3GD20_BDU_t; - -/** - * @brief Gyroscope Endianness - */ -typedef enum { - L3GD20_End_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ - L3GD20_End_BIG = 0x40 /*!< Big Endian: data MSB @ lower address */ -}L3GD20_End_t; - - -/** - * @brief Gyroscope configuration structure. - */ -typedef struct { - /** - * @brief Gyroscope fullscale value. - */ - L3GD20_FS_t fullscale; - /** - * @brief Gyroscope power mode selection. - */ - L3GD20_PM_t powermode; - /** - * @brief Gyroscope output data rate selection. - */ - L3GD20_ODR_t outputdatarate; - /** - * @brief Gyroscope axes enabling. - */ - L3GD20_AE_t axesenabling; - /** - * @brief Gyroscope endianess. - */ - L3GD20_End_t endianess; - /** - * @brief Gyroscope block data update. - */ - L3GD20_BDU_t blockdataupdate; -} L3GD20_Config; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - uint8_t l3gd20ReadRegister(SPIDriver *spip, uint8_t reg); - void l3gd20WriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value); -#ifdef __cplusplus -} -#endif - -#endif /* _L3GD20_H_ */ - -/** @} */ - diff --git a/os/various/devices_lib/lis3mdl.c b/os/various/devices_lib/lis3mdl.c deleted file mode 100644 index 99b71e4..0000000 --- a/os/various/devices_lib/lis3mdl.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lis3mdl.c - * @brief LIS3MDL MEMS interface module through I2C code. - * - * @addtogroup lis3mdl - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "lis3mdl.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic sub-register value. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] message pointer to message - * @return register value. - */ -uint8_t lis3mdlReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message) { - - uint8_t txbuf, rxbuf[2]; -#if defined(STM32F103_MCUCONF) - txbuf = LSM303DLHC_SUB_MSB | sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, TIME_INFINITE); - } - return rxbuf[0]; -#else - txbuf = sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, TIME_INFINITE); - } - return rxbuf[0]; -#endif -} - -/** - * @brief Writes a value into a register. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] value the value to be written - * @param[out] message pointer to message - */ -void lis3mdlWriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message) { - - uint8_t txbuf[2]; - uint8_t rxbuf; - switch (sub) { - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lis3mdlWriteRegister(), reserved register"); - case LIS3MDL_SUB_WHO_AM_I: - case LIS3MDL_SUB_STATUS_REG: - case LIS3MDL_SUB_OUT_X_L: - case LIS3MDL_SUB_OUT_X_H: - case LIS3MDL_SUB_OUT_Y_L: - case LIS3MDL_SUB_OUT_Y_H: - case LIS3MDL_SUB_OUT_Z_L: - case LIS3MDL_SUB_OUT_Z_H: - case LIS3MDL_SUB_INT_SOURCE: - case LIS3MDL_SUB_INT_THS_L: - case LIS3MDL_SUB_INT_THS_H: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LIS3MDL_SUB_CTRL_REG1: - case LIS3MDL_SUB_CTRL_REG2: - case LIS3MDL_SUB_CTRL_REG3: - case LIS3MDL_SUB_CTRL_REG4: - case LIS3MDL_SUB_CTRL_REG5: - case LIS3MDL_SUB_INT_CFG: - txbuf[0] = sub; - txbuf[1] = value; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); - } - break; - } -} -/** @} */ diff --git a/os/various/devices_lib/lis3mdl.h b/os/various/devices_lib/lis3mdl.h deleted file mode 100644 index e55978e..0000000 --- a/os/various/devices_lib/lis3mdl.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lis3mdl.h - * @brief LIS3MDL MEMS interface module header. - * - * @{ - */ - -#ifndef _LIS3MDL_H_ -#define _LIS3MDL_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define LIS3MDL_COMP_SENS_4GA ((float)6842.0f) /*!< compass sensitivity with 4 GA full scale [LSB / Ga] */ -#define LIS3MDL_COMP_SENS_8GA ((float)3421.0f) /*!< compass sensitivity with 8 GA full scale [LSB / Ga] */ -#define LIS3MDL_COMP_SENS_12GA ((float)2281.0f) /*!< compass sensitivity with 12 GA full scale [LSB / Ga] */ -#define LIS3MDL_COMP_SENS_16GA ((float)1711.0f) /*!< compass sensitivity with 16 GA full scale [LSB / Ga] */ -/** - * @name LIS3MDL register names - * @{ - */ -/******************************************************************************/ -/* */ -/* LIS3MDL on board MEMS */ -/* */ -/******************************************************************************/ -/***************** Bit definition for I2C/SPI communication *****************/ -#define LIS3MDL_SUB ((uint8_t)0x7F) /*!< SUB[6:0] Sub-registers address Mask */ -#define LIS3MDL_SUB_0 ((uint8_t)0x01) /*!< bit 0 */ -#define LIS3MDL_SUB_1 ((uint8_t)0x02) /*!< bit 1 */ -#define LIS3MDL_SUB_2 ((uint8_t)0x08) /*!< bit 3 */ -#define LIS3MDL_SUB_4 ((uint8_t)0x10) /*!< bit 4 */ -#define LIS3MDL_SUB_5 ((uint8_t)0x20) /*!< bit 5 */ -#define LIS3MDL_SUB_6 ((uint8_t)0x40) /*!< bit 6 */ - -#define LIS3MDL_SUB_MSB ((uint8_t)0x80) /*!< Multiple data read\write bit */ - -/**************** Bit definition SUB-Registers Addresses ********************/ -#define LIS3MDL_SUB_WHO_AM_I ((uint8_t)0x0F) /*!< CONTROL REGISTER 1 */ -#define LIS3MDL_SUB_CTRL_REG1 ((uint8_t)0x20) /*!< CONTROL REGISTER 1 */ -#define LIS3MDL_SUB_CTRL_REG2 ((uint8_t)0x21) /*!< CONTROL REGISTER 2 */ -#define LIS3MDL_SUB_CTRL_REG3 ((uint8_t)0x22) /*!< CONTROL REGISTER 3 */ -#define LIS3MDL_SUB_CTRL_REG4 ((uint8_t)0x23) /*!< CONTROL REGISTER 4 */ -#define LIS3MDL_SUB_CTRL_REG5 ((uint8_t)0x24) /*!< CONTROL REGISTER 5 */ -#define LIS3MDL_SUB_STATUS_REG ((uint8_t)0x27) /*!< STATUS REGISTER */ -#define LIS3MDL_SUB_OUT_X_L ((uint8_t)0x28) /*!< OUTPUT X-AXIS LOW */ -#define LIS3MDL_SUB_OUT_X_H ((uint8_t)0x29) /*!< OUTPUT X-AXIS HIGH */ -#define LIS3MDL_SUB_OUT_Y_L ((uint8_t)0x2A) /*!< OUTPUT Y-AXIS LOW */ -#define LIS3MDL_SUB_OUT_Y_H ((uint8_t)0x2B) /*!< OUTPUT Y-AXIS HIGH */ -#define LIS3MDL_SUB_OUT_Z_L ((uint8_t)0x2C) /*!< OUTPUT Z-AXIS LOW */ -#define LIS3MDL_SUB_OUT_Z_H ((uint8_t)0x2D) /*!< OUTPUT Z-AXIS HIGH */ -#define LIS3MDL_SUB_INT_CFG ((uint8_t)0x30) /*!< INTERRUPT1 CONFIG */ -#define LIS3MDL_SUB_INT_SOURCE ((uint8_t)0x31) /*!< INTERRUPT1 SOURCE */ -#define LIS3MDL_SUB_INT_THS_L ((uint8_t)0x32) /*!< INTERRUPT1 THRESHOLD */ -#define LIS3MDL_SUB_INT_THS_H ((uint8_t)0x33) /*!< INTERRUPT1 DURATION */ - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name Compass data structures and types - * @{ - */ - -/** - * @brief Compass Slave Address - */ -typedef enum { - LIS3MDL_SAD_GND = 0x1C, /*!< COMPASS Slave Address when SA1 is to GND */ - LIS3MDL_SAD_VCC = 0x1E /*!< COMPASS Slave Address when SA1 is to VCC */ -}LIS3MDL_SAD_t; - -/** - * @brief Compass Operation Mode for X and Y axes - */ -typedef enum { - LIS3MDL_OMXY_LOW_POWER = 0x00, /*!< Operation Mode XY low power */ - LIS3MDL_OMXY_MEDIUM_PERFORMANCE = 0x20, /*!< Operation Mode XY medium performance */ - LIS3MDL_OMXY_HIGH_PERFORMANCE = 0x40, /*!< Operation Mode XY high performance */ - LIS3MDL_OMXY_ULTRA_PERFORMANCE = 0x60 /*!< Operation Mode XY ultra performance */ -}LIS3MDL_OMXY_t; - -/** - * @brief Compass Output Data Rate - */ -typedef enum { - LIS3MDL_ODR_0_625Hz = 0x00, /*!< Output Data Rate = 0.625 Hz */ - LIS3MDL_ODR_1_25Hz = 0x04, /*!< Output Data Rate = 1.25 Hz */ - LIS3MDL_ODR_2_5Hz = 0x08, /*!< Output Data Rate = 2.5 Hz */ - LIS3MDL_ODR_5Hz = 0x0C, /*!< Output Data Rate = 5 Hz */ - LIS3MDL_ODR_10Hz = 0x10, /*!< Output Data Rate = 10 Hz */ - LIS3MDL_ODR_20Hz = 0x14, /*!< Output Data Rate = 20 Hz */ - LIS3MDL_ODR_40Hz = 0x18, /*!< Output Data Rate = 40 Hz */ - LIS3MDL_ODR_80Hz = 0x1C /*!< Output Data Rate = 80 Hz */ -}LIS3MDL_ODR_t; - -/** - * @brief Compass Full Scale - */ -typedef enum { - LIS3MDL_FS_4GA = 0x00, /*!< ±4 Gauss */ - LIS3MDL_FS_8GA = 0x02, /*!< ±8 Gauss */ - LIS3MDL_FS_12GA = 0x04, /*!< ±12 Gauss */ - LIS3MDL_FS_16GA = 0x0C /*!< ±16 Gauss */ -}LIS3MDL_FS_t; - -/** - * @brief Compass Low Mode configuration - */ -typedef enum { - LIS3MDL_LOW_POWER_DISABLED = 0x00, /*!< Low Power mode disabled */ - LIS3MDL_LOW_POWER_ENABLED = 0x20 /*!< Low Power mode enabled */ -}LIS3MDL_PM_t; - -/** - * @brief Compass Mode - */ -typedef enum { - LIS3MDL_MD_CONTINOUS_CONVERSION = 0x00, /*!< Continous conversion mode */ - LIS3MDL_MD_SINGLE_CONVERSION = 0x01, /*!< Single conversion mode */ - LIS3MDL_MD_POWER_DOWN = 0x02 /*!< Power down mode */ -}LIS3MDL_MD_t; - - -/** - * @brief Compass Operation Mode for Z axis - */ -typedef enum { - LIS3MDL_OMZ_LOW_POWER = 0x00, /*!< Operation Mode Z low power */ - LIS3MDL_OMZ_MEDIUM_PERFORMANCE = 0x04, /*!< Operation Mode Z medium performance */ - LIS3MDL_OMZ_HIGH_PERFORMANCE = 0x08, /*!< Operation Mode Z high performance */ - LIS3MDL_OMZ_ULTRA_PERFORMANCE = 0x0C /*!< Operation Mode Z ultra performance */ -}LIS3MDL_OMZ_t; - -/** - * @brief Compass Endianness - */ -typedef enum { - LIS3MDL_End_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ - LIS3MDL_End_BIG = 0x02 /*!< Big Endian: data MSB @ lower address */ -}LIS3MDL_End_t; - -/** - * @brief Compass Block Data Update - */ -typedef enum { - LIS3MDL_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ - LIS3MDL_BDU_BLOCKED = 0x40 /*!< Single Update: output registers not updated until MSB and LSB reading */ -}LIS3MDL_BDU_t; - - - - -/** - * @brief Gyroscope configuration structure. - */ -typedef struct { - /** - * @brief Compass Slave Address - */ - LIS3MDL_SAD_t slaveaddress; - /** - * @brief Compass Operation Mode for X and Y axes - */ - LIS3MDL_OMXY_t opmodexy; - /** - * @brief Compass Output Data Rate - */ - LIS3MDL_ODR_t outputdatarate; - /** - * @brief Compass Full Scale - */ - LIS3MDL_FS_t fullscale; - /** - * @brief Compass Low Mode configuration - */ - LIS3MDL_PM_t lowpowermode; - /** - * @brief Compass Mode - */ - LIS3MDL_MD_t mode; - /** - * @brief Compass Operation Mode for Z axis - */ - LIS3MDL_OMZ_t opmodez; - /** - * @brief Compass Endianness - */ - LIS3MDL_End_t endianess; - /** - * @brief Compass Block Data Update - */ - LIS3MDL_BDU_t blockdataupdate; -} LIS3MDL_Config; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - uint8_t lis3mdlReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message); - void lis3mdlWriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message); -#ifdef __cplusplus -} -#endif - -#endif /* _LIS3MDL_H_ */ - -/** @} */ diff --git a/os/various/devices_lib/lsm303dlhc.c b/os/various/devices_lib/lsm303dlhc.c deleted file mode 100644 index 070c49c..0000000 --- a/os/various/devices_lib/lsm303dlhc.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lsm303dlhc.c - * @brief LSM303DLHC MEMS interface module through I2C code. - * - * @addtogroup lsm303dlhc - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "lsm303dlhc.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic sub-register value. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] message pointer to message - * @return register value. - */ -uint8_t lsm303dlhcReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message) { - - uint8_t txbuf, rxbuf[2]; -#if defined(STM32F103_MCUCONF) - txbuf = LSM303DLHC_SUB_MSB | sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, TIME_INFINITE); - } - return rxbuf[0]; -#else - txbuf = sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, TIME_INFINITE); - } - return rxbuf[0]; -#endif - - -} - -/** - * @brief Writes a value into a register. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] value the value to be written - * @param[out] message pointer to message - */ -void lsm303dlhcWriteRegister(I2CDriver *i2cp,uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message) { - - uint8_t txbuf[2]; - uint8_t rxbuf; - if(sad == LSM303DLHC_SAD_ACCEL){ - switch (sub) { - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), reserved register"); - case LSM303DLHC_SUB_ACC_STATUS_REG: - case LSM303DLHC_SUB_ACC_OUT_X_L: - case LSM303DLHC_SUB_ACC_OUT_X_H: - case LSM303DLHC_SUB_ACC_OUT_Y_L: - case LSM303DLHC_SUB_ACC_OUT_Y_H: - case LSM303DLHC_SUB_ACC_OUT_Z_L: - case LSM303DLHC_SUB_ACC_OUT_Z_H: - case LSM303DLHC_SUB_ACC_FIFO_SRC_REG: - case LSM303DLHC_SUB_ACC_INT1_SOURCE: - case LSM303DLHC_SUB_ACC_INT2_SOURCE: - case LSM303DLHC_SUB_ACC_CLICK_SRC: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LSM303DLHC_SUB_ACC_CTRL_REG1: - case LSM303DLHC_SUB_ACC_CTRL_REG2: - case LSM303DLHC_SUB_ACC_CTRL_REG3: - case LSM303DLHC_SUB_ACC_CTRL_REG4: - case LSM303DLHC_SUB_ACC_CTRL_REG5: - case LSM303DLHC_SUB_ACC_CTRL_REG6: - case LSM303DLHC_SUB_ACC_REFERENCE: - case LSM303DLHC_SUB_ACC_FIFO_CTRL_REG: - case LSM303DLHC_SUB_ACC_INT1_CFG: - case LSM303DLHC_SUB_ACC_INT1_THS: - case LSM303DLHC_SUB_ACC_INT1_DURATION: - case LSM303DLHC_SUB_ACC_INT2_CFG: - case LSM303DLHC_SUB_ACC_INT2_THS: - case LSM303DLHC_SUB_ACC_INT2_DURATION: - case LSM303DLHC_SUB_ACC_CLICK_CFG: - case LSM303DLHC_SUB_ACC_CLICK_THS: - case LSM303DLHC_SUB_ACC_TIME_LIMIT: - case LSM303DLHC_SUB_ACC_TIME_LATENCY: - case LSM303DLHC_SUB_ACC_TIME_WINDOW: - txbuf[0] = sub; - txbuf[1] = value; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); - } - break; - } - } - else if(sad == LSM303DLHC_SAD_COMPASS){ - switch (sub) { - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), reserved register"); - case LSM303DLHC_SUB_COMP_OUT_X_H: - case LSM303DLHC_SUB_COMP_OUT_X_L: - case LSM303DLHC_SUB_COMP_OUT_Z_H: - case LSM303DLHC_SUB_COMP_OUT_Z_L: - case LSM303DLHC_SUB_COMP_OUT_Y_H: - case LSM303DLHC_SUB_COMP_OUT_Y_L: - case LSM303DLHC_SUB_COMP_SR_REG: - case LSM303DLHC_SUB_COMP_IRA_REG: - case LSM303DLHC_SUB_COMP_IRB_REG: - case LSM303DLHC_SUB_COMP_IRC_REG: - case LSM303DLHC_SUB_COMP_TEMP_OUT_H: - case LSM303DLHC_SUB_COMP_TEMP_OUT_L: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LSM303DLHC_SUB_COMP_CRA_REG: - case LSM303DLHC_SUB_COMP_CRB_REG: - case LSM303DLHC_SUB_COMP_MR_REG: - txbuf[0] = sub; - txbuf[1] = value; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); - } - break; - } - } -} -/** @} */ diff --git a/os/various/devices_lib/lsm303dlhc.h b/os/various/devices_lib/lsm303dlhc.h deleted file mode 100644 index ed52e68..0000000 --- a/os/various/devices_lib/lsm303dlhc.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lsm303dlhc.h - * @brief LSM303DLHC MEMS interface module through I2C header. - * - * @addtogroup lsm303dlhc - * @{ - */ - -#ifndef _LSM303DLHC_H_ -#define _LSM303DLHC_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#if (PLAY_USE_FLOAT) || defined(__DOXYGEN__) -#define LSM303DLHC_ACC_SENS_2G ((float)1671.836f) /*!< Accelerometer sensitivity with 2 G full scale [LSB * s^2 / m] */ -#define LSM303DLHC_ACC_SENS_4G ((float)835.918f) /*!< Accelerometer sensitivity with 4 G full scale [LSB * s^2 / m] */ -#define LSM303DLHC_ACC_SENS_8G ((float)417.959f) /*!< Accelerometer sensitivity with 8 G full scale [LSB * s^2 / m] */ -#define LSM303DLHC_ACC_SENS_16G ((float)208.979f) /*!< Accelerometer sensitivity with 16 G full scale [LSB * s^2 / m] */ - -#define LSM303DLHC_COMP_SENS_XY_1_3GA ((float)1100.0f) /*!< Compass sensitivity with 1.3 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_1_9GA ((float)855.0f) /*!< Compass sensitivity with 1.9 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_2_5GA ((float)670.0f) /*!< Compass sensitivity with 2.5 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_4_0GA ((float)450.0f) /*!< Compass sensitivity with 4.0 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_4_7GA ((float)400.0f) /*!< Compass sensitivity with 4.7 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_5_6GA ((float)330.0f) /*!< Compass sensitivity with 5.6 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_XY_8_1GA ((float)230.0f) /*!< Compass sensitivity with 8.1 GA full scale [LSB / Ga] */ - -#define LSM303DLHC_COMP_SENS_Z_1_3GA ((float)980.0f) /*!< Compass sensitivity with 1.3 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_1_9GA ((float)765.0f) /*!< Compass sensitivity with 1.9 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_2_5GA ((float)600.0f) /*!< Compass sensitivity with 2.5 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_4_0GA ((float)400.0f) /*!< Compass sensitivity with 4.0 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_4_7GA ((float)355.0f) /*!< Compass sensitivity with 4.7 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_5_6GA ((float)295.0f) /*!< Compass sensitivity with 5.6 GA full scale [LSB / Ga] */ -#define LSM303DLHC_COMP_SENS_Z_8_1GA ((float)205.0f) /*!< Compass sensitivity with 8.1 GA full scale [LSB / Ga] */ -#endif /* PLAY_USE_FLOAT */ -/** - * @name LSM303DLHC register names - * @{ - */ -/******************************************************************************/ -/* */ -/* LSM303DLHC on board MEMS */ -/* */ -/******************************************************************************/ -/******************* Bit definition for I2C communication *******************/ -#define LSM303DLHC_SAD ((uint8_t)0x7F) /*!< SAD[6:0] Slave Address Mask */ -#define LSM303DLHC_SAD_ACCEL ((uint8_t)0x19) /*!< ACCELEROMETER Slave Address */ -#define LSM303DLHC_SAD_COMPASS ((uint8_t)0x1E) /*!< MAGNETOMETER Slave Address */ - -#define LSM303DLHC_SUB ((uint8_t)0x7F) /*!< SUB[6:0] Sub-registers address Mask */ -#define LSM303DLHC_SUB_0 ((uint8_t)0x01) /*!< bit 0 */ -#define LSM303DLHC_SUB_1 ((uint8_t)0x02) /*!< bit 1 */ -#define LSM303DLHC_SUB_2 ((uint8_t)0x08) /*!< bit 3 */ -#define LSM303DLHC_SUB_4 ((uint8_t)0x10) /*!< bit 4 */ -#define LSM303DLHC_SUB_5 ((uint8_t)0x20) /*!< bit 5 */ -#define LSM303DLHC_SUB_6 ((uint8_t)0x40) /*!< bit 6 */ - -#define LSM303DLHC_SUB_MSB ((uint8_t)0x80) /*!< Multiple data read\write bit */ - -/******** Bit definition for Accelerometer SUB-Registers Addresses **********/ -#define LSM303DLHC_SUB_ACC_CTRL_REG1 ((uint8_t)0x20) /*!< CONTROL REGISTER 1 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG2 ((uint8_t)0x21) /*!< CONTROL REGISTER 2 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG3 ((uint8_t)0x22) /*!< CONTROL REGISTER 3 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG4 ((uint8_t)0x23) /*!< CONTROL REGISTER 4 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG5 ((uint8_t)0x24) /*!< CONTROL REGISTER 5 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CTRL_REG6 ((uint8_t)0x25) /*!< CONTROL REGISTER 6 FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_REFERENCE ((uint8_t)0x26) /*!< REFERENCE/DATACAPTURE FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_STATUS_REG ((uint8_t)0x27) /*!< STATUS REGISTER FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_X_L ((uint8_t)0x28) /*!< OUTPUT X-AXIS LOW FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_X_H ((uint8_t)0x29) /*!< OUTPUT X-AXIS HIGH FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_Y_L ((uint8_t)0x2A) /*!< OUTPUT Y-AXIS LOW FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_Y_H ((uint8_t)0x2B) /*!< OUTPUT Y-AXIS HIGH FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_Z_L ((uint8_t)0x2C) /*!< OUTPUT Z-AXIS LOW FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_OUT_Z_H ((uint8_t)0x2D) /*!< OUTPUT Z-AXIS HIGH FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_FIFO_CTRL_REG ((uint8_t)0x2E) /*!< FIFO CONTROL REGISTER FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_FIFO_SRC_REG ((uint8_t)0x2F) /*!< FIFO SOURCE REGISTER FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT1_CFG ((uint8_t)0x30) /*!< INTERRUPT1 CONFIG FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT1_SOURCE ((uint8_t)0x31) /*!< INTERRUPT1 SOURCE FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT1_THS ((uint8_t)0x32) /*!< INTERRUPT1 THRESHOLD FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT1_DURATION ((uint8_t)0x33) /*!< INTERRUPT1 DURATION FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT2_CFG ((uint8_t)0x34) /*!< INTERRUPT2 CONFIG FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT2_SOURCE ((uint8_t)0x35) /*!< INTERRUPT2 SOURCE FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT2_THS ((uint8_t)0x36) /*!< INTERRUPT2 THRESHOLD FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_INT2_DURATION ((uint8_t)0x37) /*!< INTERRUPT2 DURATION FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CLICK_CFG ((uint8_t)0x38) /*!< CLICK CONFIG FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CLICK_SRC ((uint8_t)0x39) /*!< CLICK SOURCE FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_CLICK_THS ((uint8_t)0x3A) /*!< CLICK THRESHOLD FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_TIME_LIMIT ((uint8_t)0x3B) /*!< TIME LIMIT FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_TIME_LATENCY ((uint8_t)0x3C) /*!< TIME LATENCY FOR ACCELEROMETER */ -#define LSM303DLHC_SUB_ACC_TIME_WINDOW ((uint8_t)0x3D) /*!< TIME WINDOW FOR ACCELEROMETER */ - -/********* Bit definition for Compass SUB-Registers Addresses **********/ -#define LSM303DLHC_SUB_COMP_CRA_REG ((uint8_t)0x00) /*!< CONTROL REGISTER A FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_CRB_REG ((uint8_t)0x01) /*!< CONTROL REGISTER B FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_MR_REG ((uint8_t)0x02) /*!< STATUS REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_X_H ((uint8_t)0x03) /*!< OUTPUT X-AXIS HIGH FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_X_L ((uint8_t)0x04) /*!< OUTPUT X-AXIS LOW FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_Z_H ((uint8_t)0x05) /*!< OUTPUT Z-AXIS HIGH FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_Z_L ((uint8_t)0x06) /*!< OUTPUT Z-AXIS LOW FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_Y_H ((uint8_t)0x07) /*!< OUTPUT Y-AXIS HIGH FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_OUT_Y_L ((uint8_t)0x08) /*!< OUTPUT Y-AXIS LOW FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_SR_REG ((uint8_t)0x09) /*!< SR REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_IRA_REG ((uint8_t)0x0A) /*!< IR A REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_IRB_REG ((uint8_t)0x0B) /*!< IR B REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_IRC_REG ((uint8_t)0x0C) /*!< IR C REGISTER FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_TEMP_OUT_H ((uint8_t)0x31) /*!< OUTPUT TEMP HIGH FOR MAGNETOMETER */ -#define LSM303DLHC_SUB_COMP_TEMP_OUT_L ((uint8_t)0x32) /*!< OUTPUT TEMP LOW FOR MAGNETOMETER */ - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name Accelerometer data structures and types - * @{ - */ - -/** - * @brief Accelerometer Output Data Rate - */ -typedef enum -{ - LSM303DLHC_ACC_ODR_PD = 0x00, /*!< Power down */ - LSM303DLHC_ACC_ODR_1Hz = 0x10, /*!< Output Data Rate = 1 Hz */ - LSM303DLHC_ACC_ODR_10Hz = 0x20, /*!< Output Data Rate = 10 Hz */ - LSM303DLHC_ACC_ODR_25Hz = 0x30, /*!< Output Data Rate = 25 Hz */ - LSM303DLHC_ACC_ODR_50Hz = 0x40, /*!< Output Data Rate = 50 Hz */ - LSM303DLHC_ACC_ODR_100Hz = 0x50, /*!< Output Data Rate = 100 Hz */ - LSM303DLHC_ACC_ODR_200Hz = 0x60, /*!< Output Data Rate = 200 Hz */ - LSM303DLHC_ACC_ODR_400Hz = 0x70, /*!< Output Data Rate = 400 Hz */ - LSM303DLHC_ACC_ODR_1620Hz = 0x80, /*!< Output Data Rate = 1620 Hz Low Power mode only */ - LSM303DLHC_ACC_ODR_1344Hz = 0x90 /*!< Output Data Rate = 1344 Hz in Normal mode and 5376 Hz in Low Power Mode */ -}LSM303DLHC_ACC_ODR_t; - -/** - * @brief Accelerometer Power Mode - */ -typedef enum -{ - LSM303DLHC_ACC_PM_NORMAL = 0x00, /*!< Normal mode enabled */ - LSM303DLHC_ACC_PM_LOW_POWER = 0x08 /*!< Low Power mode enabled */ -}LSM303DLHC_ACC_PM_t; - -/** - * @brief Accelerometer Full Scale - */ -typedef enum -{ - LSM303DLHC_ACC_FS_2G = 0x00, /*!< ±2 g m/s^2 */ - LSM303DLHC_ACC_FS_4G = 0x10, /*!< ±4 g m/s^2 */ - LSM303DLHC_ACC_FS_8G = 0x20, /*!< ±8 g m/s^2 */ - LSM303DLHC_ACC_FS_16G = 0x30 /*!< ±16 g m/s^2 */ -}LSM303DLHC_ACC_FS_t; - -/** - * @brief Accelerometer Axes Enabling - */ -typedef enum{ - LSM303DLHC_ACC_AE_DISABLED = 0x00, /*!< Axes all disabled */ - LSM303DLHC_ACC_AE_X = 0x01, /*!< Only X-axis enabled */ - LSM303DLHC_ACC_AE_Y = 0x02, /*!< Only Y-axis enabled */ - LSM303DLHC_ACC_AE_XY = 0x03, /*!< X & Y axes enabled */ - LSM303DLHC_ACC_AE_Z = 0x04, /*!< Only Z-axis enabled */ - LSM303DLHC_ACC_AE_XZ = 0x05, /*!< X & Z axes enabled */ - LSM303DLHC_ACC_AE_YZ = 0x06, /*!< Y & Z axes enabled */ - LSM303DLHC_ACC_AE_XYZ = 0x07 /*!< All axes enabled */ -}LSM303DLHC_ACC_AE_t; - -/** - * @brief Accelerometer Block Data Update - */ -typedef enum -{ - LSM303DLHC_ACC_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ - LSM303DLHC_ACC_BDU_BLOCKED = 0x80 /*!< Single Update: output registers not updated until MSB and LSB reading */ -}LSM303DLHC_ACC_BDU_t; - -/** - * @brief Accelerometer Endianness - */ -typedef enum -{ - LSM303DLHC_ACC_End_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ - LSM303DLHC_ACC_End_BIG = 0x40 /*!< Big Endian: data MSB @ lower address */ -}LSM303DLHC_ACC_End_t; - -/** - * @brief Accelerometer High Resolution mode - */ -typedef enum -{ - LSM303DLHC_ACC_HR_Enabled = 0x08, /*!< High resolution output mode enabled */ - LSM303DLHC_ACC_HR_Disabled = 0x00 /*!< High resolution output mode disabled */ -}LSM303DLHC_ACC_HR_t; - -/** - * @brief Accelerometer configuration structure. - */ -typedef struct { - /** - * @brief Accelerometer fullscale value. - */ - LSM303DLHC_ACC_FS_t fullscale; - /** - * @brief Accelerometer power mode selection. - */ - LSM303DLHC_ACC_PM_t powermode; - /** - * @brief Accelerometer output data rate selection. - */ - LSM303DLHC_ACC_ODR_t outputdatarate; - /** - * @brief Accelerometer axes enabling. - */ - LSM303DLHC_ACC_AE_t axesenabling; - /** - * @brief Accelerometer block data update. - */ - LSM303DLHC_ACC_BDU_t blockdataupdate; - /** - * @brief Accelerometer block data update. - */ - LSM303DLHC_ACC_HR_t highresmode; -} LSM303DLHC_ACC_Config; -/** @} */ - - -/** - * @name Compass data types - * @{ - */ - -/** - * @brief Compass Output Data Rate - */ -typedef enum -{ - LSM303DLHC_COMP_ODR_0_75_Hz = 0x00, /*!< Output Data Rate = 0.75 Hz */ - LSM303DLHC_COMP_ODR_1_5_Hz = 0x04, /*!< Output Data Rate = 1.5 Hz */ - LSM303DLHC_COMP_ODR_3_0_Hz = 0x08, /*!< Output Data Rate = 3 Hz */ - LSM303DLHC_COMP_ODR_7_5_Hz = 0x0C, /*!< Output Data Rate = 7.5 Hz */ - LSM303DLHC_COMP_ODR_15_Hz = 0x10, /*!< Output Data Rate = 15 Hz */ - LSM303DLHC_COMP_ODR_30_Hz = 0x14, /*!< Output Data Rate = 30 Hz */ - LSM303DLHC_COMP_ODR_75_Hz = 0x18, /*!< Output Data Rate = 75 Hz */ - LSM303DLHC_COMP_ODR_220_Hz = 0x1C /*!< Output Data Rate = 220 Hz */ -}LSM303DLHC_COMP_ODR_t; - - -/** - * @brief Compass Full Scale - */ -typedef enum -{ - LSM303DLHC_COMP_FS_1_3_GA = 0x20, /*!< Full scale = ±1.3 Gauss */ - LSM303DLHC_COMP_FS_1_9_GA = 0x40, /*!< Full scale = ±1.9 Gauss */ - LSM303DLHC_COMP_FS_2_5_GA = 0x60, /*!< Full scale = ±2.5 Gauss */ - LSM303DLHC_COMP_FS_4_0_GA = 0x80, /*!< Full scale = ±4.0 Gauss */ - LSM303DLHC_COMP_FS_4_7_GA = 0xA0, /*!< Full scale = ±4.7 Gauss */ - LSM303DLHC_COMP_FS_5_6_GA = 0xC0, /*!< Full scale = ±5.6 Gauss */ - LSM303DLHC_COMP_FS_8_1_GA = 0xE0 /*!< Full scale = ±8.1 Gauss */ -}LSM303DLHC_COMP_FS_t; - - -/** - * @brief Compass Working Mode - */ -typedef enum -{ - LSM303DLHC_COMP_WM_CONTINUOS = 0x00, /*!< Continuous-Conversion Mode */ - LSM303DLHC_COMP_WM_BLOCKED = 0x01, /*!< Single-Conversion Mode */ - LSM303DLHC_COMP_WM_SLEEP = 0x02 /*!< Sleep Mode */ -}LSM303DLHC_COMP_WM_t; - -/** - * @brief Compass configuration structure. - */ -typedef struct { - /** - * @brief Compass fullscale value. - */ - LSM303DLHC_COMP_FS_t fullscale; - /** - * @brief Compass output data rate selection. - */ - LSM303DLHC_COMP_ODR_t outputdatarate; - /** - * @brief Compass working mode. - */ - LSM303DLHC_COMP_WM_t workingmode; -} LSM303DLHC_COMP_Config; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - uint8_t lsm303dlhcReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message); - void lsm303dlhcWriteRegister(I2CDriver *i2cp,uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message); - -#ifdef __cplusplus -} -#endif -#endif /* _LSM303DLHC_H_ */ -/** @} */ - diff --git a/os/various/devices_lib/lsm6ds0.c b/os/various/devices_lib/lsm6ds0.c deleted file mode 100644 index da67f12..0000000 --- a/os/various/devices_lib/lsm6ds0.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lsm6ds0.c - * @brief LSM6DS0 MEMS interface module through I2C code. - * - * @addtogroup lsm6ds0 - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "lsm6ds0.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic sub-register value. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] message pointer to message - * @return register value. - */ -uint8_t lsm6ds0ReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message) { - - uint8_t txbuf, rxbuf[2]; -#if defined(STM32F103_MCUCONF) - txbuf = LSM303DLHC_SUB_MSB | sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, TIME_INFINITE); - } - return rxbuf[0]; -#else - txbuf = sub; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, TIME_INFINITE); - } - return rxbuf[0]; -#endif -} - -/** - * @brief Writes a value into a register. - * @pre The I2C interface must be initialized and the driver started. - * - * @param[in] i2cp pointer to the I2C interface - * @param[in] sad slave address without R bit - * @param[in] sub sub-register address - * @param[in] value the value to be written - * @param[out] message pointer to message - */ -void lsm6ds0WriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message) { - - uint8_t txbuf[2]; - uint8_t rxbuf; - switch (sub) { - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lsm6ds0WriteRegister(), reserved register"); - case LSM6DS0_SUB_WHO_AM_I: - case LSM6DS0_SUB_INT_GEN_SRC_G: - case LSM6DS0_SUB_OUT_TEMP_L: - case LSM6DS0_SUB_OUT_TEMP_H: - case LSM6DS0_SUB_STATUS_REG1: - case LSM6DS0_SUB_OUT_X_L_G: - case LSM6DS0_SUB_OUT_X_H_G: - case LSM6DS0_SUB_OUT_Y_L_G: - case LSM6DS0_SUB_OUT_Y_H_G: - case LSM6DS0_SUB_OUT_Z_L_G: - case LSM6DS0_SUB_OUT_Z_H_G: - case LSM6DS0_SUB_INT_GEN_SRC_XL: - case LSM6DS0_SUB_STATUS_REG2: - case LSM6DS0_SUB_OUT_X_L_XL: - case LSM6DS0_SUB_OUT_X_H_XL: - case LSM6DS0_SUB_OUT_Y_L_XL: - case LSM6DS0_SUB_OUT_Y_H_XL: - case LSM6DS0_SUB_OUT_Z_L_XL: - case LSM6DS0_SUB_OUT_Z_H_XL: - case LSM6DS0_SUB_FIFO_SRC: - /* Read only registers cannot be written, the command is ignored.*/ - return; - case LSM6DS0_SUB_ACT_THS: - case LSM6DS0_SUB_ACT_DUR: - case LSM6DS0_SUB_INT_GEN_CFG_XL: - case LSM6DS0_SUB_INT_GEN_THS_X_XL: - case LSM6DS0_SUB_INT_GEN_THS_Y_XL: - case LSM6DS0_SUB_INT_GEN_THS_Z_XL: - case LSM6DS0_SUB_INT_GEN_DUR_XL: - case LSM6DS0_SUB_REFERENCE_G: - case LSM6DS0_SUB_INT_CTRL: - case LSM6DS0_SUB_CTRL_REG1_G: - case LSM6DS0_SUB_CTRL_REG2_G: - case LSM6DS0_SUB_CTRL_REG3_G: - case LSM6DS0_SUB_ORIENT_CFG_G: - case LSM6DS0_SUB_CTRL_REG4: - case LSM6DS0_SUB_CTRL_REG5_XL: - case LSM6DS0_SUB_CTRL_REG6_XL: - case LSM6DS0_SUB_CTRL_REG7_XL: - case LSM6DS0_SUB_CTRL_REG8: - case LSM6DS0_SUB_CTRL_REG9: - case LSM6DS0_SUB_CTRL_REG10: - case LSM6DS0_SUB_FIFO_CTRL: - case LSM6DS0_SUB_INT_GEN_CFG_G: - case LSM6DS0_SUB_INT_GEN_THS_XH_G: - case LSM6DS0_SUB_INT_GEN_THS_XL_G: - case LSM6DS0_SUB_INT_GEN_THS_YH_G: - case LSM6DS0_SUB_INT_GEN_THS_YL_G: - case LSM6DS0_SUB_INT_GEN_THS_ZH_G: - case LSM6DS0_SUB_INT_GEN_THS_ZL_G: - case LSM6DS0_SUB_INT_GEN_DUR_G: - txbuf[0] = sub; - txbuf[1] = value; - if(message != NULL){ - *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, - TIME_INFINITE); - } - else{ - i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); - } - break; - } -} - -/** @} */ diff --git a/os/various/devices_lib/lsm6ds0.h b/os/various/devices_lib/lsm6ds0.h deleted file mode 100644 index 3631493..0000000 --- a/os/various/devices_lib/lsm6ds0.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file lsm6ds0.h - * @brief LSM6DS0 MEMS interface module header. - * - * @{ - */ - -#ifndef _LSM6DS0_H_ -#define _LSM6DS0_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#if (PLAY_USE_FLOAT) || defined(__DOXYGEN__) -#define LSM6DS0_ACC_SENS_2G ((float)1671.095f) /*!< Accelerometer sensitivity with 2 G full scale [LSB * s^2 / m] */ -#define LSM6DS0_ACC_SENS_4G ((float)835.547f) /*!< Accelerometer sensitivity with 4 G full scale [LSB * s^2 / m] */ -#define LSM6DS0_ACC_SENS_8G ((float)417.774) /*!< Accelerometer sensitivity with 8 G full scale [LSB * s^2 / m] */ -#define LSM6DS0_ACC_SENS_16G ((float)139.258f) /*!< Accelerometer sensitivity with 16 G full scale [LSB * s^2 / m] */ - -#define LSM6DS0_GYRO_SENS_245DPS ((float)114.286f) /*!< Gyroscope sensitivity with 245 dps full scale [LSB * s / °] */ -#define LSM6DS0_GYRO_SENS_500DPS ((float)57.143f) /*!< Gyroscope sensitivity with 500 dps full scale [LSB * s / °] */ -#define LSM6DS0_GYRO_SENS_2000DPS ((float)14.286f) /*!< Gyroscope sensitivity with 2000 dps full scale [LSB * s / °] */ - -#endif /* PLAY_USE_FLOAT */ -/** - * @name LSM6DS0 register names - * @{ - */ -/******************************************************************************/ -/* */ -/* LSM6DS0 on board MEMS */ -/* */ -/******************************************************************************/ -/***************** Bit definition for I2C/SPI communication *****************/ -#define LSM6DS0_SUB ((uint8_t)0x7F) /*!< SUB[6:0] Sub-registers address Mask */ -#define LSM6DS0_SUB_0 ((uint8_t)0x01) /*!< bit 0 */ -#define LSM6DS0_SUB_1 ((uint8_t)0x02) /*!< bit 1 */ -#define LSM6DS0_SUB_2 ((uint8_t)0x08) /*!< bit 3 */ -#define LSM6DS0_SUB_4 ((uint8_t)0x10) /*!< bit 4 */ -#define LSM6DS0_SUB_5 ((uint8_t)0x20) /*!< bit 5 */ -#define LSM6DS0_SUB_6 ((uint8_t)0x40) /*!< bit 6 */ - -#define LSM6DS0_SUB_MSB ((uint8_t)0x80) /*!< Multiple data read\write bit */ - -/***************** Bit definition for Registers Addresses *******************/ -#define LSM6DS0_SUB_ACT_THS ((uint8_t)0x04) /*!< Activity threshold register */ -#define LSM6DS0_SUB_ACT_DUR ((uint8_t)0x05) /*!< Inactivity duration register */ -#define LSM6DS0_SUB_INT_GEN_CFG_XL ((uint8_t)0x06) /*!< Accelerometer interrupt generator configuration register */ -#define LSM6DS0_SUB_INT_GEN_THS_X_XL ((uint8_t)0x07) /*!< Accelerometer X-axis interrupt threshold register */ -#define LSM6DS0_SUB_INT_GEN_THS_Y_XL ((uint8_t)0x08) /*!< Accelerometer Y-axis interrupt threshold register */ -#define LSM6DS0_SUB_INT_GEN_THS_Z_XL ((uint8_t)0x09) /*!< Accelerometer Z-axis interrupt threshold register */ -#define LSM6DS0_SUB_INT_GEN_DUR_XL ((uint8_t)0x0A) /*!< Accelerometer interrupt duration register */ -#define LSM6DS0_SUB_REFERENCE_G ((uint8_t)0x0B) /*!< Gyroscope reference value register for digital high-pass filter */ -#define LSM6DS0_SUB_INT_CTRL ((uint8_t)0x0C) /*!< INT pin control register */ -#define LSM6DS0_SUB_WHO_AM_I ((uint8_t)0x0F) /*!< Who_AM_I register */ -#define LSM6DS0_SUB_CTRL_REG1_G ((uint8_t)0x10) /*!< Gyroscope control register 1 */ -#define LSM6DS0_SUB_CTRL_REG2_G ((uint8_t)0x11) /*!< Gyroscope control register 2 */ -#define LSM6DS0_SUB_CTRL_REG3_G ((uint8_t)0x12) /*!< Gyroscope control register 3 */ -#define LSM6DS0_SUB_ORIENT_CFG_G ((uint8_t)0x13) /*!< Gyroscope sign and orientation register */ -#define LSM6DS0_SUB_INT_GEN_SRC_G ((uint8_t)0x14) /*!< Gyroscope interrupt source register */ -#define LSM6DS0_SUB_OUT_TEMP_L ((uint8_t)0x15) /*!< Temperature data output low register */ -#define LSM6DS0_SUB_OUT_TEMP_H ((uint8_t)0x16) /*!< Temperature data output high register */ -#define LSM6DS0_SUB_STATUS_REG1 ((uint8_t)0x17) /*!< Status register 1 */ -#define LSM6DS0_SUB_OUT_X_L_G ((uint8_t)0x18) /*!< Gyroscope X-axis low output register */ -#define LSM6DS0_SUB_OUT_X_H_G ((uint8_t)0x19) /*!< Gyroscope X-axis high output register */ -#define LSM6DS0_SUB_OUT_Y_L_G ((uint8_t)0x1A) /*!< Gyroscope Y-axis low output register */ -#define LSM6DS0_SUB_OUT_Y_H_G ((uint8_t)0x1B) /*!< Gyroscope Y-axis high output register */ -#define LSM6DS0_SUB_OUT_Z_L_G ((uint8_t)0x1C) /*!< Gyroscope Z-axis low output register */ -#define LSM6DS0_SUB_OUT_Z_H_G ((uint8_t)0x1D) /*!< Gyroscope Z-axis high output register */ -#define LSM6DS0_SUB_CTRL_REG4 ((uint8_t)0x1E) /*!< Control register 4 */ -#define LSM6DS0_SUB_CTRL_REG5_XL ((uint8_t)0x1F) /*!< Accelerometer Control Register 5 */ -#define LSM6DS0_SUB_CTRL_REG6_XL ((uint8_t)0x20) /*!< Accelerometer Control Register 6 */ -#define LSM6DS0_SUB_CTRL_REG7_XL ((uint8_t)0x21) /*!< Accelerometer Control Register 7 */ -#define LSM6DS0_SUB_CTRL_REG8 ((uint8_t)0x22) /*!< Control register 8 */ -#define LSM6DS0_SUB_CTRL_REG9 ((uint8_t)0x23) /*!< Control register 9 */ -#define LSM6DS0_SUB_CTRL_REG10 ((uint8_t)0x24) /*!< Control register 10 */ -#define LSM6DS0_SUB_INT_GEN_SRC_XL ((uint8_t)0x26) /*!< Accelerometer interrupt source register */ -#define LSM6DS0_SUB_STATUS_REG2 ((uint8_t)0x27) /*!< Status register */ -#define LSM6DS0_SUB_OUT_X_L_XL ((uint8_t)0x28) /*!< Accelerometer X-axis low output register */ -#define LSM6DS0_SUB_OUT_X_H_XL ((uint8_t)0x29) /*!< Accelerometer X-axis high output register */ -#define LSM6DS0_SUB_OUT_Y_L_XL ((uint8_t)0x2A) /*!< Accelerometer Y-axis low output register */ -#define LSM6DS0_SUB_OUT_Y_H_XL ((uint8_t)0x2B) /*!< Accelerometer Y-axis high output register */ -#define LSM6DS0_SUB_OUT_Z_L_XL ((uint8_t)0x2C) /*!< Accelerometer Z-axis low output register */ -#define LSM6DS0_SUB_OUT_Z_H_XL ((uint8_t)0x2D) /*!< Accelerometer Z-axis high output register */ -#define LSM6DS0_SUB_FIFO_CTRL ((uint8_t)0x2E) /*!< FIFO control register */ -#define LSM6DS0_SUB_FIFO_SRC ((uint8_t)0x2F) /*!< FIFO status control register */ -#define LSM6DS0_SUB_INT_GEN_CFG_G ((uint8_t)0x30) /*!< Gyroscope interrupt generator configuration register */ -#define LSM6DS0_SUB_INT_GEN_THS_XH_G ((uint8_t)0x31) /*!< Gyroscope X-axis low interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_XL_G ((uint8_t)0x32) /*!< Gyroscope X-axis high interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_YH_G ((uint8_t)0x33) /*!< Gyroscope Y-axis low interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_YL_G ((uint8_t)0x34) /*!< Gyroscope Y-axis high interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_ZH_G ((uint8_t)0x35) /*!< Gyroscope Z-axis low interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_THS_ZL_G ((uint8_t)0x36) /*!< Gyroscope Z-axis high interrupt generator threshold registers */ -#define LSM6DS0_SUB_INT_GEN_DUR_G ((uint8_t)0x37) /*!< Gyroscope interrupt generator duration register */ - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name Generic LSM6DS0 data structures and types - * @{ - */ - -/** - * @brief Accelerometer and Gyroscope Slave Address - */ -typedef enum { - LSM6DS0_SAD_GND = 0x6A, /*!< LSM6DS0 Slave Address when SA1 is to GND */ - LSM6DS0_SAD_VCC = 0x6B /*!< LSM6DS0 Slave Address when SA1 is to VCC */ -}LSM6DS0_SAD_t; - -/** - * @brief Accelerometer and Gyroscope Block Data Update - */ -typedef enum -{ - LSM6DS0_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ - LSM6DS0_BDU_BLOCKED = 0x40 /*!< Single Update: output registers not updated until MSB and LSB reading */ -}LSM6DS0_BDU_t; - -/** - * @brief Accelerometer and Gyroscope Endianness - */ -typedef enum -{ - LSM6DS0_END_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ - LSM6DS0_END_BIG = 0x20 /*!< Big Endian: data MSB @ lower address */ -}LSM6DS0_END_t; -/** @} */ - -/** - * @name Accelerometer data structures and types - * @{ - */ - -/** - * @brief Accelerometer Decimation Mode - */ -typedef enum { - LSM6DS0_ACC_DEC_DISABLED = 0x00, /*!< NO decimation */ - LSM6DS0_ACC_DEC_X2 = 0x40, /*!< Decimation update every 2 sample */ - LSM6DS0_ACC_DEC_X4 = 0x80, /*!< Decimation update every 4 sample */ - LSM6DS0_ACC_DEC_X8 = 0xC0 /*!< Decimation update every 8 sample */ -}LSM6DS0_ACC_DEC_t; - -/** - * @brief Accelerometer Axes Enabling - */ -typedef enum{ - LSM6DS0_ACC_AE_DISABLED = 0x00, /*!< Axes all disabled */ - LSM6DS0_ACC_AE_X = 0x08, /*!< Only X-axis enabled */ - LSM6DS0_ACC_AE_Y = 0x10, /*!< Only Y-axis enabled */ - LSM6DS0_ACC_AE_XY = 0x18, /*!< X & Y axes enabled */ - LSM6DS0_ACC_AE_Z = 0x20, /*!< Only Z-axis enabled */ - LSM6DS0_ACC_AE_XZ = 0x28, /*!< X & Z axes enabled */ - LSM6DS0_ACC_AE_YZ = 0x30, /*!< Y & Z axes enabled */ - LSM6DS0_ACC_AE_XYZ = 0x38 /*!< All axes enabled */ -}LSM6DS0_ACC_AE_t; - -/** - * @brief Accelerometer Output Data Rate - */ -typedef enum { - LSM6DS0_ACC_ODR_PD = 0x00, /*!< Power down */ - LSM6DS0_ACC_ODR_10Hz = 0x20, /*!< Output Data Rate = 10 Hz */ - LSM6DS0_ACC_ODR_50Hz = 0x40, /*!< Output Data Rate = 50 Hz */ - LSM6DS0_ACC_ODR_119Hz = 0x60, /*!< Output Data Rate = 119 Hz */ - LSM6DS0_ACC_ODR_238Hz = 0x80, /*!< Output Data Rate = 238 Hz */ - LSM6DS0_ACC_ODR_476Hz = 0xA0, /*!< Output Data Rate = 476 Hz */ - LSM6DS0_ACC_ODR_952Hz = 0xC0 /*!< Output Data Rate = 952 Hz */ -}LSM6DS0_ACC_ODR_t; - -/** - * @brief Accelerometer Full Scale - */ -typedef enum { - LSM6DS0_ACC_FS_2G = 0x00, /*!< ±2 g m/s^2 */ - LSM6DS0_ACC_FS_4G = 0x10, /*!< ±4 g m/s^2 */ - LSM6DS0_ACC_FS_8G = 0x18, /*!< ±8 g m/s^2 */ - LSM6DS0_ACC_FS_16G = 0x08 /*!< ±16 g m/s^2 */ -}LSM6DS0_ACC_FS_t; - -/** - * @brief Accelerometer Antialiasing filter Bandwidth Selection - */ -typedef enum { - LSM6DS0_ACC_BW_408Hz = 0x00, /*!< AA filter bandwidth = 408 Hz */ - LSM6DS0_ACC_BW_211Hz = 0x01, /*!< AA filter bandwidth = 211 Hz */ - LSM6DS0_ACC_BW_105Hz = 0x02, /*!< AA filter bandwidth = 105 Hz */ - LSM6DS0_ACC_BW_50Hz = 0x03, /*!< AA filter bandwidth = 50 Hz */ - LSM6DS0_ACC_BW_ACCORDED = 0x04, /*!< AA filter bandwidth chosen by ODR selection */ -}LSM6DS0_ACC_BW_t; - -/** - * @brief Accelerometer High Resolution mode - */ -typedef enum -{ - LSM6DS0_ACC_HR_Disabled = 0x00, /*!< High resolution output mode disabled, FDS bypassed */ - LSM6DS0_ACC_HR_EN_9 = 0xC4, /*!< High resolution output mode enabled, LP cutoff = ODR/9, FDS enabled */ - LSM6DS0_ACC_HR_EN_50 = 0x84, /*!< High resolution output mode enabled, LP cutoff = ODR/50, FDS enabled */ - LSM6DS0_ACC_HR_EN_100 = 0xA4, /*!< High resolution output mode enabled, LP cutoff = ODR/100, FDS enabled */ - LSM6DS0_ACC_HR_EN_400 = 0xE4, /*!< High resolution output mode enabled, LP cutoff = ODR/400, FDS enabled */ -}LSM6DS0_ACC_HR_t; - -/** - * @brief HP filter for interrupt - */ -typedef enum -{ - LSM6DS0_ACC_HPIS1_BYPASSED = 0x00, /*!< High-pass filter bypassed */ - LSM6DS0_ACC_HPIS1_ENABLED = 0x01 /*!< High-pass filter enabled for accelerometer interrupt function on interrupt */ -}LSM6DS0_ACC_HPIS1_t; - -/** - * @brief Accelerometer configuration structure. - */ -typedef struct { - - /** - * @brief LSM6DS0 Slave Address - */ - LSM6DS0_SAD_t slaveaddress; - /** - * @brief Accelerometer Decimation Mode - */ - LSM6DS0_ACC_DEC_t decimation; - /** - * @brief Accelerometer Output Data Rate - */ - LSM6DS0_ACC_ODR_t outputdatarate; - /** - * @brief Accelerometer Antialiasing filter Bandwidth Selection - */ - LSM6DS0_ACC_BW_t bandwidth; - /** - * @brief Accelerometer Full Scale - */ - LSM6DS0_ACC_FS_t fullscale; - /** - * @brief Accelerometer Axes Enabling - */ - LSM6DS0_ACC_AE_t axesenabling; - /** - * @brief Accelerometer High Resolution mode - */ - LSM6DS0_ACC_HR_t highresmode; - /** - * @brief HP filter for interrupt - */ - LSM6DS0_ACC_HPIS1_t hpfirq; - /** - * @brief LSM6DS0 Endianness - */ - LSM6DS0_END_t endianess; - /** - * @brief LSM6DS0 Block Data Update - */ - LSM6DS0_BDU_t blockdataupdate; -} LSM6DS0_ACC_Config; -/** @} */ - -/** - * @name Gyroscope data structures and types - * @{ - */ - -/** - * @brief Gyroscope Output Data Rate - */ -typedef enum { - LSM6DS0_GYRO_ODR_PD = 0x00, /*!< Power down */ - LSM6DS0_GYRO_ODR_14_9Hz_CO_5Hz = 0x20, /*!< Output Data Rate = 14.9 Hz, CutOff = 5Hz */ - LSM6DS0_GYRO_ODR_59_5Hz_CO_16Hz = 0x40, /*!< Output Data Rate = 59.5 Hz, CutOff = 16Hz */ - LSM6DS0_GYRO_ODR_119Hz_CO_14Hz = 0x60, /*!< Output Data Rate = 119 Hz, CutOff = 14Hz */ - LSM6DS0_GYRO_ODR_119Hz_CO_31Hz = 0x61, /*!< Output Data Rate = 119 Hz, CutOff = 31Hz */ - LSM6DS0_GYRO_ODR_238Hz_CO_14Hz = 0x80, /*!< Output Data Rate = 238 Hz, CutOff = 14Hz */ - LSM6DS0_GYRO_ODR_238Hz_CO_29Hz = 0x81, /*!< Output Data Rate = 328 Hz, CutOff = 29Hz */ - LSM6DS0_GYRO_ODR_238Hz_CO_63Hz = 0x82, /*!< Output Data Rate = 238 Hz, CutOff = 63Hz */ - LSM6DS0_GYRO_ODR_238Hz_CO_78Hz = 0x83, /*!< Output Data Rate = 476 Hz, CutOff = 78Hz */ - LSM6DS0_GYRO_ODR_476Hz_CO_21Hz = 0xA0, /*!< Output Data Rate = 476 Hz, CutOff = 21Hz */ - LSM6DS0_GYRO_ODR_476Hz_CO_28Hz = 0xA1, /*!< Output Data Rate = 238 Hz, CutOff = 28Hz */ - LSM6DS0_GYRO_ODR_476Hz_CO_57Hz = 0xA2, /*!< Output Data Rate = 476 Hz, CutOff = 57Hz */ - LSM6DS0_GYRO_ODR_476Hz_CO_100Hz = 0xA3, /*!< Output Data Rate = 476 Hz, CutOff = 100Hz */ - LSM6DS0_GYRO_ODR_952Hz_CO_33Hz = 0xC0, /*!< Output Data Rate = 952 Hz, CutOff = 33Hz */ - LSM6DS0_GYRO_ODR_952Hz_CO_40Hz = 0xC1, /*!< Output Data Rate = 952 Hz, CutOff = 40Hz */ - LSM6DS0_GYRO_ODR_952Hz_CO_58Hz = 0xC2, /*!< Output Data Rate = 952 Hz, CutOff = 58Hz */ - LSM6DS0_GYRO_ODR_952Hz_CO_100Hz = 0xC3 /*!< Output Data Rate = 952 Hz, CutOff = 100Hz */ -}LSM6DS0_GYRO_ODR_t; - -/** - * @brief Gyroscope Full Scale - */ -typedef enum { - LSM6DS0_GYRO_FS_245DSP = 0x00, /*!< ±245 degrees per second */ - LSM6DS0_GYRO_FS_500DSP = 0x08, /*!< ±500 degrees per second */ - LSM6DS0_GYRO_FS_2000DSP = 0x18 /*!< ±2000 degrees per second */ -}LSM6DS0_GYRO_FS_t; - -/** - * @brief Gyroscope Output Selection - */ -typedef enum { - LSM6DS0_GYRO_OUT_SEL_BYPASS = 0x00, /*!< Output not filtered */ - LSM6DS0_GYRO_OUT_SEL_FILTERED = 0x01, /*!< Output filtered */ -}LSM6DS0_GYRO_OUT_SEL_t; - -/** - * @brief Gyroscope Interrupt Selection - */ -typedef enum { - LSM6DS0_GYRO_INT_SEL_BYPASS = 0x00, /*!< Interrupt generator signal not filtered */ - LSM6DS0_GYRO_INT_SEL_FILTERED = 0x08, /*!< Interrupt generator signal filtered */ -}LSM6DS0_GYRO_INT_SEL_t; - -/** - * @brief Gyroscope Low Power Mode - */ -typedef enum { - LSM6DS0_GYRO_LP_MODE_HIGH_PERFORMANCE = 0x00, /*!< High performance */ - LSM6DS0_GYRO_LP_MODE_LOW_POWER = 0x80, /*!< Low power */ -}LSM6DS0_GYRO_LP_MODE_t; - -/** - * @brief Gyroscope High Pass Filter Cutoff Selection - */ -typedef enum { - LSM6DS0_GYRO_HPCF_DISABLED = 0x00, /*!< HP filter disabled */ - LSM6DS0_GYRO_HPCF_0 = 0x40, /*!< Config 0 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_1 = 0x41, /*!< Config 1 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_2 = 0x42, /*!< Config 2 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_3 = 0x43, /*!< Config 3 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_4 = 0x44, /*!< Config 4 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_5 = 0x45, /*!< Config 5 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_6 = 0x46, /*!< Config 6 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_7 = 0x47, /*!< Config 7 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_8 = 0x48, /*!< Config 8 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_9 = 0x49, /*!< Config 9 refer to table 48 of DOcID025604 Rev 3 */ - LSM6DS0_GYRO_HPCF_10 = 0x4A /*!< Config 10 refer to table 48 of DOcID025604 Rev 3 */ -}LSM6DS0_GYRO_HPCF_t; - -/** - * @brief Gyroscope Axes Enabling - */ -typedef enum{ - LSM6DS0_GYRO_AE_DISABLED = 0x00, /*!< Axes all disabled */ - LSM6DS0_GYRO_AE_X = 0x08, /*!< Only X-axis enabled */ - LSM6DS0_GYRO_AE_Y = 0x10, /*!< Only Y-axis enabled */ - LSM6DS0_GYRO_AE_XY = 0x18, /*!< X & Y axes enabled */ - LSM6DS0_GYRO_AE_Z = 0x20, /*!< Only Z-axis enabled */ - LSM6DS0_GYRO_AE_XZ = 0x28, /*!< X & Z axes enabled */ - LSM6DS0_GYRO_AE_YZ = 0x30, /*!< Y & Z axes enabled */ - LSM6DS0_GYRO_AE_XYZ = 0x38 /*!< All axes enabled */ -}LSM6DS0_GYRO_AE_t; - -/** - * @brief Gyroscope Decimation Mode - */ -typedef enum { - LSM6DS0_GYRO_DEC_DISABLED = 0x00, /*!< NO decimation */ - LSM6DS0_GYRO_DEC_X2 = 0x40, /*!< Decimation update every 2 sample */ - LSM6DS0_GYRO_DEC_X4 = 0x80, /*!< Decimation update every 4 sample */ - LSM6DS0_GYRO_DEC_X8 = 0xC0 /*!< Decimation update every 8 sample */ -}LSM6DS0_GYRO_DEC_t; - -/** - * @brief Gyroscope Sleep Mode - */ -typedef enum { - LSM6DS0_GYRO_SLP_DISABLED = 0x00, /*!< Gyroscope sleep mode disabled */ - LSM6DS0_GYRO_SLP_ENABLED = 0x40 /*!< Gyroscope sleep mode enabled */ -}LSM6DS0_GYRO_SLP_t; -/** - * @brief Gyroscope configuration structure. - */ -typedef struct { - /** - * @brief LSM6DS0 Slave Address - */ - LSM6DS0_SAD_t slaveaddress; - /** - * @brief Gyroscope Output Data Rate - */ - LSM6DS0_GYRO_ODR_t outputdatarate; - /** - * @brief Gyroscope Full Scale - */ - LSM6DS0_GYRO_FS_t fullscale; - /** - * @brief Gyroscope Output Selection - */ - LSM6DS0_GYRO_OUT_SEL_t outputselect; - /** - * @brief Gyroscope Interrupt Selection - */ - LSM6DS0_GYRO_INT_SEL_t irqselect; - /** - * @brief Gyroscope Low Power Mode - */ - LSM6DS0_GYRO_LP_MODE_t lowpowermode; - /** - * @brief Gyroscope High Pass Filter Cutoff Selection - */ - LSM6DS0_GYRO_HPCF_t HPCfrequency; - /** - * @brief Gyroscope Axes Enabling - */ - LSM6DS0_GYRO_AE_t axesenabling; - /** - * @brief Gyroscope Decimation Mode - */ - LSM6DS0_GYRO_DEC_t decimation; - /** - * @brief LSM6DS0 Endianness - */ - LSM6DS0_END_t endianess; - /** - * @brief LSM6DS0 Block Data Update - */ - LSM6DS0_BDU_t blockdataupdate; -} LSM6DS0_GYRO_Config; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - uint8_t lsm6ds0ReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - msg_t* message); - void lsm6ds0WriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, - uint8_t value, msg_t* message); -#ifdef __cplusplus -} -#endif - -#endif /* _LSM6DS0_H_ */ - -/** @} */ diff --git a/os/various/devices_lib/max7219.c b/os/various/devices_lib/max7219.c deleted file mode 100644 index 0e51167..0000000 --- a/os/various/devices_lib/max7219.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file max7219.c - * @brief MAX7219 display driver module code. - * - * @addtogroup max7219 - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "max7219.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Reads a generic register value. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] adr address number - * @param[in] data data value. - */ -void max7219WriteRegister(SPIDriver *spip, uint16_t adr, uint8_t data) { - - switch (adr) { - default: - return; - case MAX7219_AD_DIGIT_0: - case MAX7219_AD_DIGIT_1: - case MAX7219_AD_DIGIT_2: - case MAX7219_AD_DIGIT_3: - case MAX7219_AD_DIGIT_4: - case MAX7219_AD_DIGIT_5: - case MAX7219_AD_DIGIT_6: - case MAX7219_AD_DIGIT_7: - case MAX7219_AD_DECODE_MODE: - case MAX7219_AD_INTENSITY: - case MAX7219_AD_SCAN_LIMIT: - case MAX7219_AD_SHUTDOWN: - case MAX7219_AD_DISPLAY_TEST: - spiSelect(spip); - uint16_t txbuf = {adr | data}; - spiSend(spip, 1, &txbuf); - spiUnselect(spip); - } -} -/** @} */ diff --git a/os/various/devices_lib/max7219.h b/os/various/devices_lib/max7219.h deleted file mode 100644 index f2bbbdf..0000000 --- a/os/various/devices_lib/max7219.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file MAX7219.h - * @brief MAX7219 display driver module header. - * - * @{ - */ - -#ifndef _MAX7219_H_ -#define _MAX7219_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name MAX7219 register names - * @{ - */ -/******************************************************************************/ -/* */ -/* MAX7219 display driver */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SPI communication *******************/ -#define MAX7219_DI ((uint16_t)0x00FF) /*!< DI[7:0] Data input */ -#define MAX7219_DI_0 ((uint16_t)0x0001) /*!< bit 0 */ -#define MAX7219_DI_1 ((uint16_t)0x0002) /*!< bit 1 */ -#define MAX7219_DI_2 ((uint16_t)0x0004) /*!< bit 2 */ -#define MAX7219_DI_3 ((uint16_t)0x0008) /*!< bit 3 */ -#define MAX7219_DI_4 ((uint16_t)0x0010) /*!< bit 4 */ -#define MAX7219_DI_5 ((uint16_t)0x0020) /*!< bit 5 */ -#define MAX7219_DI_6 ((uint16_t)0x0040) /*!< bit 6 */ -#define MAX7219_DI_7 ((uint16_t)0x0080) /*!< bit 7 */ - -#define MAX7219_AD ((uint16_t)0x0F00) /*!< AD[11:8] Data input */ -#define MAX7219_AD_0 ((uint16_t)0x0100) /*!< bit 8 */ -#define MAX7219_AD_1 ((uint16_t)0x0200) /*!< bit 9 */ -#define MAX7219_AD_2 ((uint16_t)0x0400) /*!< bit 10 */ -#define MAX7219_AD_3 ((uint16_t)0x0800) /*!< bit 11 */ - -/****************** Bit definition for Registers Addresses *******************/ -#define MAX7219_AD_NOP ((uint16_t)0x0000) /*!< No operation */ -#define MAX7219_AD_DIGIT_0 ((uint16_t)0x0100) /*!< Digit 0 */ -#define MAX7219_AD_DIGIT_1 ((uint16_t)0x0200) /*!< Digit 1 */ -#define MAX7219_AD_DIGIT_2 ((uint16_t)0x0300) /*!< Digit 2 */ -#define MAX7219_AD_DIGIT_3 ((uint16_t)0x0400) /*!< Digit 3 */ -#define MAX7219_AD_DIGIT_4 ((uint16_t)0x0500) /*!< Digit 4 */ -#define MAX7219_AD_DIGIT_5 ((uint16_t)0x0600) /*!< Digit 5 */ -#define MAX7219_AD_DIGIT_6 ((uint16_t)0x0700) /*!< Digit 6 */ -#define MAX7219_AD_DIGIT_7 ((uint16_t)0x0800) /*!< Digit 7 */ -#define MAX7219_AD_DECODE_MODE ((uint16_t)0x0900) /*!< Decode mode */ -#define MAX7219_AD_INTENSITY ((uint16_t)0x0A00) /*!< Intensity */ -#define MAX7219_AD_SCAN_LIMIT ((uint16_t)0x0B00) /*!< Scan limit */ -#define MAX7219_AD_SHUTDOWN ((uint16_t)0x0C00) /*!< Shutdown */ -#define MAX7219_AD_DISPLAY_TEST ((uint16_t)0x0F00) /*!< Display test */ - -/*************** Bit definition for Registers Configuration *****************/ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !HAL_USE_SPI -#error "MAX7219 requires HAL_USE_SPI" -#endif -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name MAX7219 data structures and types - * @{ - * - */ - -/** - * @brief MAX7219 operation mode - */ -typedef enum { - MAX7219_OM_Shutdown = 0x00, /*!< Shutdown mode */ - MAX7219_OM_Normal = 0x01 /*!< Normal mode */ -} MAX7219_OM_t; - -/** - * @brief MAX7219 decoder mode - */ -typedef enum { - MAX7219_DM_No_decode = 0x00, /*!< No decode */ - MAX7219_DM_CodeB_0 = 0x01, /*!< Code B on Digit 0 */ - MAX7219_DM_CodeB_1 = 0x02, /*!< Code B on Digit 1 */ - MAX7219_DM_CodeB_2 = 0x04, /*!< Code B on Digit 2 */ - MAX7219_DM_CodeB_3 = 0x08, /*!< Code B on Digit 3 */ - MAX7219_DM_CodeB_4 = 0x10, /*!< Code B on Digit 4 */ - MAX7219_DM_CodeB_5 = 0x20, /*!< Code B on Digit 5 */ - MAX7219_DM_CodeB_6 = 0x40, /*!< Code B on Digit 6 */ - MAX7219_DM_CodeB_7 = 0x80 /*!< Code B on Digit 7 */ -} MAX7219_DM_t; - -/** - * @brief MAX7219 intensity mode - */ -typedef enum { - MAX7219_IM_1_32 = 0x00, /*!< 1/32 intensity */ - MAX7219_IM_3_32 = 0x01, /*!< 3/32 intensity */ - MAX7219_IM_5_32 = 0x02, /*!< 5/32 intensity */ - MAX7219_IM_7_32 = 0x03, /*!< 7/32 intensity */ - MAX7219_IM_9_32 = 0x04, /*!< 9/32 intensity */ - MAX7219_IM_11_32 = 0x05, /*!< 11/32 intensity */ - MAX7219_IM_13_32 = 0x06, /*!< 13/32 intensity */ - MAX7219_IM_15_32 = 0x07, /*!< 15/32 intensity */ - MAX7219_IM_17_32 = 0x08, /*!< 17/32 intensity */ - MAX7219_IM_19_32 = 0x09, /*!< 19/32 intensity */ - MAX7219_IM_21_32 = 0x0A, /*!< 21/32 intensity */ - MAX7219_IM_23_32 = 0x0B, /*!< 23/32 intensity */ - MAX7219_IM_25_32 = 0x0C, /*!< 25/32 intensity */ - MAX7219_IM_27_32 = 0x0D, /*!< 27/32 intensity */ - MAX7219_IM_29_32 = 0x0E, /*!< 29/32 intensity */ - MAX7219_IM_31_32 = 0x0F /*!< 31/32 intensity */ -} MAX7219_IM_t; - -/** - * @brief MAX7219 scan line mode - */ -typedef enum { - MAX7219_SL_0 = 0x00, /*!< Scanned digit 0 only */ - MAX7219_SL_1 = 0x01, /*!< Scanned digit 0 & 1 */ - MAX7219_SL_2 = 0x02, /*!< Scanned digit 0 - 2 */ - MAX7219_SL_3 = 0x03, /*!< Scanned digit 0 - 3 */ - MAX7219_SL_4 = 0x04, /*!< Scanned digit 0 - 4 */ - MAX7219_SL_5 = 0x05, /*!< Scanned digit 0 - 5 */ - MAX7219_SL_6 = 0x06, /*!< Scanned digit 0 - 6 */ - MAX7219_SL_7 = 0x07 /*!< Scanned digit 0 - 7 */ -} MAX7219_SL_t; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - - void max7219WriteRegister(SPIDriver *spip, uint16_t adr, uint8_t data); -#ifdef __cplusplus -} -#endif -#endif /* _MAX7219_H_ */ - -/** @} */ - diff --git a/os/various/devices_lib/mems/l3gd20.c b/os/various/devices_lib/mems/l3gd20.c new file mode 100644 index 0000000..1cc52c9 --- /dev/null +++ b/os/various/devices_lib/mems/l3gd20.c @@ -0,0 +1,123 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file l3gd20.c + * @brief L3GD20 MEMS interface module code. + * + * @addtogroup l3gd20 + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "l3gd20.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Reads a generic register value. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] reg register number + * @return register value. + */ +uint8_t l3gd20ReadRegister(SPIDriver *spip, uint8_t reg) { + uint8_t txbuf[2] = {L3GD20_RW | reg, 0xFF}; + uint8_t rxbuf[2] = {0x00, 0x00}; + spiSelect(spip); + spiExchange(spip, 2, txbuf, rxbuf); + spiUnselect(spip); + return rxbuf[1]; +} + + +void l3gd20WriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value) { + + switch (reg) { + + default: + /* Reserved register must not be written, according to the datasheet + * this could permanently damage the device. + */ + chDbgAssert(FALSE, "lg3d20WriteRegister(), reserved register"); + case L3GD20_AD_WHO_AM_I: + case L3GD20_AD_OUT_TEMP : + case L3GD20_AD_STATUS_REG: + case L3GD20_AD_OUT_X_L: + case L3GD20_AD_OUT_X_H: + case L3GD20_AD_OUT_Y_L: + case L3GD20_AD_OUT_Y_H: + case L3GD20_AD_OUT_Z_L: + case L3GD20_AD_OUT_Z_H: + case L3GD20_AD_FIFO_SRC_REG: + case L3GD20_AD_INT1_SRC: + /* Read only registers cannot be written, the command is ignored.*/ + return; + case L3GD20_AD_CTRL_REG1: + case L3GD20_AD_CTRL_REG2: + case L3GD20_AD_CTRL_REG3: + case L3GD20_AD_CTRL_REG4: + case L3GD20_AD_CTRL_REG5: + case L3GD20_AD_REFERENCE: + case L3GD20_AD_FIFO_CTRL_REG: + case L3GD20_AD_INT1_CFG: + case L3GD20_AD_INT1_TSH_XH: + case L3GD20_AD_INT1_TSH_XL: + case L3GD20_AD_INT1_TSH_YH: + case L3GD20_AD_INT1_TSH_YL: + case L3GD20_AD_INT1_TSH_ZH: + case L3GD20_AD_INT1_TSH_ZL: + case L3GD20_AD_INT1_DURATION: + spiSelect(spip); + uint8_t txbuf[2] = {reg, value}; + spiSend(spip, 2, txbuf); + spiUnselect(spip); + } +} +/** @} */ diff --git a/os/various/devices_lib/mems/l3gd20.h b/os/various/devices_lib/mems/l3gd20.h new file mode 100644 index 0000000..08d9092 --- /dev/null +++ b/os/various/devices_lib/mems/l3gd20.h @@ -0,0 +1,243 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file l3gd20.h + * @brief L3GD20 MEMS interface module header. + * + * @{ + */ + +#ifndef _L3GD20_H_ +#define _L3GD20_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define L3GD20_SENS_250DPS ((float)131.072f) /*!< gyroscope sensitivity with 250 dps full scale [LSB/dps] */ +#define L3GD20_SENS_500DPS ((float)65.536f) /*!< gyroscope sensitivity with 500 dps full scale [LSB/dps] */ +#define L3GD20_SENS_2000DPS ((float)16.384f) /*!< gyroscope sensitivity with 2000 dps full scale [LSB/dps] */ +/** + * @name L3GD20 register names + * @{ + */ +/******************************************************************************/ +/* */ +/* L3GD20 on board MEMS */ +/* */ +/******************************************************************************/ +/******************* Bit definition for SPI communication *******************/ +#define L3GD20_DI ((uint8_t)0xFF) /*!< DI[7:0] Data input */ +#define L3GD20_DI_0 ((uint8_t)0x01) /*!< bit 0 */ +#define L3GD20_DI_1 ((uint8_t)0x02) /*!< bit 1 */ +#define L3GD20_DI_2 ((uint8_t)0x04) /*!< bit 2 */ +#define L3GD20_DI_3 ((uint8_t)0x08) /*!< bit 3 */ +#define L3GD20_DI_4 ((uint8_t)0x10) /*!< bit 4 */ +#define L3GD20_DI_5 ((uint8_t)0x20) /*!< bit 5 */ +#define L3GD20_DI_6 ((uint8_t)0x40) /*!< bit 6 */ +#define L3GD20_DI_7 ((uint8_t)0x80) /*!< bit 7 */ + +#define L3GD20_AD ((uint8_t)0x3F) /*!< AD[5:0] Address Data */ +#define L3GD20_AD_0 ((uint8_t)0x01) /*!< bit 0 */ +#define L3GD20_AD_1 ((uint8_t)0x02) /*!< bit 1 */ +#define L3GD20_AD_2 ((uint8_t)0x04) /*!< bit 2 */ +#define L3GD20_AD_3 ((uint8_t)0x08) /*!< bit 3 */ +#define L3GD20_AD_4 ((uint8_t)0x10) /*!< bit 4 */ +#define L3GD20_AD_5 ((uint8_t)0x20) /*!< bit 5 */ + +#define L3GD20_MS ((uint8_t)0x40) /*!< Multiple read write */ +#define L3GD20_RW ((uint8_t)0x80) /*!< Read Write, 1 0 */ + +/****************** Bit definition for Registers Addresses *******************/ +#define L3GD20_AD_WHO_AM_I ((uint8_t)0x0F) /*!< WHO I AM */ +#define L3GD20_AD_CTRL_REG1 ((uint8_t)0x20) /*!< CONTROL REGISTER 1 */ +#define L3GD20_AD_CTRL_REG2 ((uint8_t)0x21) /*!< CONTROL REGISTER 2 */ +#define L3GD20_AD_CTRL_REG3 ((uint8_t)0x22) /*!< CONTROL REGISTER 3 */ +#define L3GD20_AD_CTRL_REG4 ((uint8_t)0x23) /*!< CONTROL REGISTER 4 */ +#define L3GD20_AD_CTRL_REG5 ((uint8_t)0x24) /*!< CONTROL REGISTER 5 */ +#define L3GD20_AD_REFERENCE ((uint8_t)0x25) /*!< REFERENCE/DATACAPTURE */ +#define L3GD20_AD_OUT_TEMP ((uint8_t)0x26) /*!< MEMS ONBOARD TEMP SENSOR */ +#define L3GD20_AD_STATUS_REG ((uint8_t)0x27) /*!< STATUS REGISTER */ +#define L3GD20_AD_OUT_X_L ((uint8_t)0x28) /*!< OUTPUT X-AXIS LOW */ +#define L3GD20_AD_OUT_X_H ((uint8_t)0x29) /*!< OUTPUT X-AXIS HIGH */ +#define L3GD20_AD_OUT_Y_L ((uint8_t)0x2A) /*!< OUTPUT Y-AXIS LOW */ +#define L3GD20_AD_OUT_Y_H ((uint8_t)0x2B) /*!< OUTPUT Y-AXIS HIGH */ +#define L3GD20_AD_OUT_Z_L ((uint8_t)0x2C) /*!< OUTPUT Z-AXIS LOW */ +#define L3GD20_AD_OUT_Z_H ((uint8_t)0x2D) /*!< OUTPUT Z-AXIS HIGH */ +#define L3GD20_AD_FIFO_CTRL_REG ((uint8_t)0x2E) /*!< FIFO CONTROL REGISTER */ +#define L3GD20_AD_FIFO_SRC_REG ((uint8_t)0x2F) /*!< FIFO SOURCE REGISTER */ +#define L3GD20_AD_INT1_CFG ((uint8_t)0x30) /*!< INTERRUPT1 CONFIG REGISTER */ +#define L3GD20_AD_INT1_SRC ((uint8_t)0x31) /*!< INTERRUPT1 SOURCE REGISTER */ +#define L3GD20_AD_INT1_TSH_XH ((uint8_t)0x32) /*!< INTERRUPT1 THRESHOLD X-AXIS HIGH */ +#define L3GD20_AD_INT1_TSH_XL ((uint8_t)0x33) /*!< INTERRUPT1 THRESHOLD X-AXIS LOW */ +#define L3GD20_AD_INT1_TSH_YH ((uint8_t)0x34) /*!< INTERRUPT1 THRESHOLD Y-AXIS HIGH */ +#define L3GD20_AD_INT1_TSH_YL ((uint8_t)0x35) /*!< INTERRUPT1 THRESHOLD Y-AXIS LOW */ +#define L3GD20_AD_INT1_TSH_ZH ((uint8_t)0x36) /*!< INTERRUPT1 THRESHOLD Z-AXIS HIGH */ +#define L3GD20_AD_INT1_TSH_ZL ((uint8_t)0x37) /*!< INTERRUPT1 THRESHOLD Z-AXIS LOW */ +#define L3GD20_AD_INT1_DURATION ((uint8_t)0x38) /*!< INTERRUPT1 DURATION */ + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @name Gyroscope data structures and types + * @{ + */ + +/** + * @brief Gyroscope Output Data Rate + */ +typedef enum { + L3GD20_ODR_95Hz_Fc_12_5 = 0x00, /*!< Output Data Rate = 95 Hz - LPF Cut-Off = 12.5 Hz */ + L3GD20_ODR_95Hz_Fc_25 = 0x10, /*!< Output Data Rate = 95 Hz - LPF Cut-Off = 25 Hz */ + L3GD20_ODR_190Hz_Fc_12_5 = 0x40, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 12.5 Hz */ + L3GD20_ODR_190Hz_Fc_25 = 0x50, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 25 Hz */ + L3GD20_ODR_190Hz_Fc_50 = 0x60, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 50 Hz */ + L3GD20_ODR_190Hz_Fc_70 = 0x70, /*!< Output Data Rate = 190 Hz - LPF Cut-Off = 70 Hz */ + L3GD20_ODR_380Hz_Fc_20 = 0x80, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 20 Hz */ + L3GD20_ODR_380Hz_Fc_25 = 0x90, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 25 Hz */ + L3GD20_ODR_380Hz_Fc_50 = 0xA0, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 50 Hz */ + L3GD20_ODR_380Hz_Fc_100 = 0xB0, /*!< Output Data Rate = 380 Hz - LPF Cut-Off = 100 Hz */ + L3GD20_ODR_760Hz_Fc_30 = 0xC0, /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 30 Hz */ + L3GD20_ODR_760Hz_Fc_35 = 0xD0, /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 35 Hz */ + L3GD20_ODR_760Hz_Fc_50 = 0xE0, /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 50 Hz */ + L3GD20_ODR_760Hz_Fc_100 = 0xF0 /*!< Output Data Rate = 760 Hz - LPF Cut-Off = 100 Hz */ +}L3GD20_ODR_t; + +/** + * @brief Gyroscope Power Mode + */ +typedef enum { + L3GD20_PM_POWER_DOWN = 0x00, /*!< Normal mode enabled */ + L3GD20_PM_SLEEP_NORMAL = 0x08 /*!< Low Power mode enabled */ +}L3GD20_PM_t; + +/** + * @brief Gyroscope Full Scale + */ +typedef enum { + L3GD20_FS_250DPS = 0x00, /*!< ±250 dps */ + L3GD20_FS_500DPS = 0x10, /*!< ±500 dps */ + L3GD20_FS_2000DPS = 0x20 /*!< ±200 dps */ +}L3GD20_FS_t; + +/** + * @brief Gyroscope Axes Enabling + */ +typedef enum { + L3GD20_AE_DISABLED = 0x00, /*!< All disabled */ + L3GD20_AE_X = 0x01, /*!< Only X */ + L3GD20_AE_Y = 0x02, /*!< Only Y */ + L3GD20_AE_XY = 0x03, /*!< X & Y */ + L3GD20_AE_Z = 0x04, /*!< Only Z */ + L3GD20_AE_XZ = 0x05, /*!< X & Z */ + L3GD20_AE_YZ = 0x06, /*!< Y & Z */ + L3GD20_AE_XYZ = 0x07 /*!< All enabled */ +}L3GD20_AE_t; + +/** + * @brief Gyroscope Block Data Update + */ +typedef enum { + L3GD20_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ + L3GD20_BDU_BLOCKED = 0x80 /*!< Single Update: output registers not updated until MSB and LSB reading */ +}L3GD20_BDU_t; + +/** + * @brief Gyroscope Endianness + */ +typedef enum { + L3GD20_End_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ + L3GD20_End_BIG = 0x40 /*!< Big Endian: data MSB @ lower address */ +}L3GD20_End_t; + + +/** + * @brief Gyroscope configuration structure. + */ +typedef struct { + /** + * @brief Gyroscope fullscale value. + */ + L3GD20_FS_t fullscale; + /** + * @brief Gyroscope power mode selection. + */ + L3GD20_PM_t powermode; + /** + * @brief Gyroscope output data rate selection. + */ + L3GD20_ODR_t outputdatarate; + /** + * @brief Gyroscope axes enabling. + */ + L3GD20_AE_t axesenabling; + /** + * @brief Gyroscope endianess. + */ + L3GD20_End_t endianess; + /** + * @brief Gyroscope block data update. + */ + L3GD20_BDU_t blockdataupdate; +} L3GD20_Config; +/** @} */ +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + + uint8_t l3gd20ReadRegister(SPIDriver *spip, uint8_t reg); + void l3gd20WriteRegister(SPIDriver *spip, uint8_t reg, uint8_t value); +#ifdef __cplusplus +} +#endif + +#endif /* _L3GD20_H_ */ + +/** @} */ + diff --git a/os/various/devices_lib/mems/lis3mdl.c b/os/various/devices_lib/mems/lis3mdl.c new file mode 100644 index 0000000..99b71e4 --- /dev/null +++ b/os/various/devices_lib/mems/lis3mdl.c @@ -0,0 +1,151 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file lis3mdl.c + * @brief LIS3MDL MEMS interface module through I2C code. + * + * @addtogroup lis3mdl + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "lis3mdl.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Reads a generic sub-register value. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] sub sub-register address + * @param[in] message pointer to message + * @return register value. + */ +uint8_t lis3mdlReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + msg_t* message) { + + uint8_t txbuf, rxbuf[2]; +#if defined(STM32F103_MCUCONF) + txbuf = LSM303DLHC_SUB_MSB | sub; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, TIME_INFINITE); + } + return rxbuf[0]; +#else + txbuf = sub; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, TIME_INFINITE); + } + return rxbuf[0]; +#endif +} + +/** + * @brief Writes a value into a register. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] sub sub-register address + * @param[in] value the value to be written + * @param[out] message pointer to message + */ +void lis3mdlWriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + uint8_t value, msg_t* message) { + + uint8_t txbuf[2]; + uint8_t rxbuf; + switch (sub) { + default: + /* Reserved register must not be written, according to the datasheet + * this could permanently damage the device. + */ + chDbgAssert(FALSE, "lis3mdlWriteRegister(), reserved register"); + case LIS3MDL_SUB_WHO_AM_I: + case LIS3MDL_SUB_STATUS_REG: + case LIS3MDL_SUB_OUT_X_L: + case LIS3MDL_SUB_OUT_X_H: + case LIS3MDL_SUB_OUT_Y_L: + case LIS3MDL_SUB_OUT_Y_H: + case LIS3MDL_SUB_OUT_Z_L: + case LIS3MDL_SUB_OUT_Z_H: + case LIS3MDL_SUB_INT_SOURCE: + case LIS3MDL_SUB_INT_THS_L: + case LIS3MDL_SUB_INT_THS_H: + /* Read only registers cannot be written, the command is ignored.*/ + return; + case LIS3MDL_SUB_CTRL_REG1: + case LIS3MDL_SUB_CTRL_REG2: + case LIS3MDL_SUB_CTRL_REG3: + case LIS3MDL_SUB_CTRL_REG4: + case LIS3MDL_SUB_CTRL_REG5: + case LIS3MDL_SUB_INT_CFG: + txbuf[0] = sub; + txbuf[1] = value; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); + } + break; + } +} +/** @} */ diff --git a/os/various/devices_lib/mems/lis3mdl.h b/os/various/devices_lib/mems/lis3mdl.h new file mode 100644 index 0000000..e55978e --- /dev/null +++ b/os/various/devices_lib/mems/lis3mdl.h @@ -0,0 +1,258 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file lis3mdl.h + * @brief LIS3MDL MEMS interface module header. + * + * @{ + */ + +#ifndef _LIS3MDL_H_ +#define _LIS3MDL_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define LIS3MDL_COMP_SENS_4GA ((float)6842.0f) /*!< compass sensitivity with 4 GA full scale [LSB / Ga] */ +#define LIS3MDL_COMP_SENS_8GA ((float)3421.0f) /*!< compass sensitivity with 8 GA full scale [LSB / Ga] */ +#define LIS3MDL_COMP_SENS_12GA ((float)2281.0f) /*!< compass sensitivity with 12 GA full scale [LSB / Ga] */ +#define LIS3MDL_COMP_SENS_16GA ((float)1711.0f) /*!< compass sensitivity with 16 GA full scale [LSB / Ga] */ +/** + * @name LIS3MDL register names + * @{ + */ +/******************************************************************************/ +/* */ +/* LIS3MDL on board MEMS */ +/* */ +/******************************************************************************/ +/***************** Bit definition for I2C/SPI communication *****************/ +#define LIS3MDL_SUB ((uint8_t)0x7F) /*!< SUB[6:0] Sub-registers address Mask */ +#define LIS3MDL_SUB_0 ((uint8_t)0x01) /*!< bit 0 */ +#define LIS3MDL_SUB_1 ((uint8_t)0x02) /*!< bit 1 */ +#define LIS3MDL_SUB_2 ((uint8_t)0x08) /*!< bit 3 */ +#define LIS3MDL_SUB_4 ((uint8_t)0x10) /*!< bit 4 */ +#define LIS3MDL_SUB_5 ((uint8_t)0x20) /*!< bit 5 */ +#define LIS3MDL_SUB_6 ((uint8_t)0x40) /*!< bit 6 */ + +#define LIS3MDL_SUB_MSB ((uint8_t)0x80) /*!< Multiple data read\write bit */ + +/**************** Bit definition SUB-Registers Addresses ********************/ +#define LIS3MDL_SUB_WHO_AM_I ((uint8_t)0x0F) /*!< CONTROL REGISTER 1 */ +#define LIS3MDL_SUB_CTRL_REG1 ((uint8_t)0x20) /*!< CONTROL REGISTER 1 */ +#define LIS3MDL_SUB_CTRL_REG2 ((uint8_t)0x21) /*!< CONTROL REGISTER 2 */ +#define LIS3MDL_SUB_CTRL_REG3 ((uint8_t)0x22) /*!< CONTROL REGISTER 3 */ +#define LIS3MDL_SUB_CTRL_REG4 ((uint8_t)0x23) /*!< CONTROL REGISTER 4 */ +#define LIS3MDL_SUB_CTRL_REG5 ((uint8_t)0x24) /*!< CONTROL REGISTER 5 */ +#define LIS3MDL_SUB_STATUS_REG ((uint8_t)0x27) /*!< STATUS REGISTER */ +#define LIS3MDL_SUB_OUT_X_L ((uint8_t)0x28) /*!< OUTPUT X-AXIS LOW */ +#define LIS3MDL_SUB_OUT_X_H ((uint8_t)0x29) /*!< OUTPUT X-AXIS HIGH */ +#define LIS3MDL_SUB_OUT_Y_L ((uint8_t)0x2A) /*!< OUTPUT Y-AXIS LOW */ +#define LIS3MDL_SUB_OUT_Y_H ((uint8_t)0x2B) /*!< OUTPUT Y-AXIS HIGH */ +#define LIS3MDL_SUB_OUT_Z_L ((uint8_t)0x2C) /*!< OUTPUT Z-AXIS LOW */ +#define LIS3MDL_SUB_OUT_Z_H ((uint8_t)0x2D) /*!< OUTPUT Z-AXIS HIGH */ +#define LIS3MDL_SUB_INT_CFG ((uint8_t)0x30) /*!< INTERRUPT1 CONFIG */ +#define LIS3MDL_SUB_INT_SOURCE ((uint8_t)0x31) /*!< INTERRUPT1 SOURCE */ +#define LIS3MDL_SUB_INT_THS_L ((uint8_t)0x32) /*!< INTERRUPT1 THRESHOLD */ +#define LIS3MDL_SUB_INT_THS_H ((uint8_t)0x33) /*!< INTERRUPT1 DURATION */ + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @name Compass data structures and types + * @{ + */ + +/** + * @brief Compass Slave Address + */ +typedef enum { + LIS3MDL_SAD_GND = 0x1C, /*!< COMPASS Slave Address when SA1 is to GND */ + LIS3MDL_SAD_VCC = 0x1E /*!< COMPASS Slave Address when SA1 is to VCC */ +}LIS3MDL_SAD_t; + +/** + * @brief Compass Operation Mode for X and Y axes + */ +typedef enum { + LIS3MDL_OMXY_LOW_POWER = 0x00, /*!< Operation Mode XY low power */ + LIS3MDL_OMXY_MEDIUM_PERFORMANCE = 0x20, /*!< Operation Mode XY medium performance */ + LIS3MDL_OMXY_HIGH_PERFORMANCE = 0x40, /*!< Operation Mode XY high performance */ + LIS3MDL_OMXY_ULTRA_PERFORMANCE = 0x60 /*!< Operation Mode XY ultra performance */ +}LIS3MDL_OMXY_t; + +/** + * @brief Compass Output Data Rate + */ +typedef enum { + LIS3MDL_ODR_0_625Hz = 0x00, /*!< Output Data Rate = 0.625 Hz */ + LIS3MDL_ODR_1_25Hz = 0x04, /*!< Output Data Rate = 1.25 Hz */ + LIS3MDL_ODR_2_5Hz = 0x08, /*!< Output Data Rate = 2.5 Hz */ + LIS3MDL_ODR_5Hz = 0x0C, /*!< Output Data Rate = 5 Hz */ + LIS3MDL_ODR_10Hz = 0x10, /*!< Output Data Rate = 10 Hz */ + LIS3MDL_ODR_20Hz = 0x14, /*!< Output Data Rate = 20 Hz */ + LIS3MDL_ODR_40Hz = 0x18, /*!< Output Data Rate = 40 Hz */ + LIS3MDL_ODR_80Hz = 0x1C /*!< Output Data Rate = 80 Hz */ +}LIS3MDL_ODR_t; + +/** + * @brief Compass Full Scale + */ +typedef enum { + LIS3MDL_FS_4GA = 0x00, /*!< ±4 Gauss */ + LIS3MDL_FS_8GA = 0x02, /*!< ±8 Gauss */ + LIS3MDL_FS_12GA = 0x04, /*!< ±12 Gauss */ + LIS3MDL_FS_16GA = 0x0C /*!< ±16 Gauss */ +}LIS3MDL_FS_t; + +/** + * @brief Compass Low Mode configuration + */ +typedef enum { + LIS3MDL_LOW_POWER_DISABLED = 0x00, /*!< Low Power mode disabled */ + LIS3MDL_LOW_POWER_ENABLED = 0x20 /*!< Low Power mode enabled */ +}LIS3MDL_PM_t; + +/** + * @brief Compass Mode + */ +typedef enum { + LIS3MDL_MD_CONTINOUS_CONVERSION = 0x00, /*!< Continous conversion mode */ + LIS3MDL_MD_SINGLE_CONVERSION = 0x01, /*!< Single conversion mode */ + LIS3MDL_MD_POWER_DOWN = 0x02 /*!< Power down mode */ +}LIS3MDL_MD_t; + + +/** + * @brief Compass Operation Mode for Z axis + */ +typedef enum { + LIS3MDL_OMZ_LOW_POWER = 0x00, /*!< Operation Mode Z low power */ + LIS3MDL_OMZ_MEDIUM_PERFORMANCE = 0x04, /*!< Operation Mode Z medium performance */ + LIS3MDL_OMZ_HIGH_PERFORMANCE = 0x08, /*!< Operation Mode Z high performance */ + LIS3MDL_OMZ_ULTRA_PERFORMANCE = 0x0C /*!< Operation Mode Z ultra performance */ +}LIS3MDL_OMZ_t; + +/** + * @brief Compass Endianness + */ +typedef enum { + LIS3MDL_End_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ + LIS3MDL_End_BIG = 0x02 /*!< Big Endian: data MSB @ lower address */ +}LIS3MDL_End_t; + +/** + * @brief Compass Block Data Update + */ +typedef enum { + LIS3MDL_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ + LIS3MDL_BDU_BLOCKED = 0x40 /*!< Single Update: output registers not updated until MSB and LSB reading */ +}LIS3MDL_BDU_t; + + + + +/** + * @brief Gyroscope configuration structure. + */ +typedef struct { + /** + * @brief Compass Slave Address + */ + LIS3MDL_SAD_t slaveaddress; + /** + * @brief Compass Operation Mode for X and Y axes + */ + LIS3MDL_OMXY_t opmodexy; + /** + * @brief Compass Output Data Rate + */ + LIS3MDL_ODR_t outputdatarate; + /** + * @brief Compass Full Scale + */ + LIS3MDL_FS_t fullscale; + /** + * @brief Compass Low Mode configuration + */ + LIS3MDL_PM_t lowpowermode; + /** + * @brief Compass Mode + */ + LIS3MDL_MD_t mode; + /** + * @brief Compass Operation Mode for Z axis + */ + LIS3MDL_OMZ_t opmodez; + /** + * @brief Compass Endianness + */ + LIS3MDL_End_t endianess; + /** + * @brief Compass Block Data Update + */ + LIS3MDL_BDU_t blockdataupdate; +} LIS3MDL_Config; +/** @} */ +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + + uint8_t lis3mdlReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + msg_t* message); + void lis3mdlWriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + uint8_t value, msg_t* message); +#ifdef __cplusplus +} +#endif + +#endif /* _LIS3MDL_H_ */ + +/** @} */ diff --git a/os/various/devices_lib/mems/lsm303dlhc.c b/os/various/devices_lib/mems/lsm303dlhc.c new file mode 100644 index 0000000..070c49c --- /dev/null +++ b/os/various/devices_lib/mems/lsm303dlhc.c @@ -0,0 +1,205 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file lsm303dlhc.c + * @brief LSM303DLHC MEMS interface module through I2C code. + * + * @addtogroup lsm303dlhc + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "lsm303dlhc.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Reads a generic sub-register value. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] sub sub-register address + * @param[in] message pointer to message + * @return register value. + */ +uint8_t lsm303dlhcReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + msg_t* message) { + + uint8_t txbuf, rxbuf[2]; +#if defined(STM32F103_MCUCONF) + txbuf = LSM303DLHC_SUB_MSB | sub; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, TIME_INFINITE); + } + return rxbuf[0]; +#else + txbuf = sub; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, TIME_INFINITE); + } + return rxbuf[0]; +#endif + + +} + +/** + * @brief Writes a value into a register. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] sub sub-register address + * @param[in] value the value to be written + * @param[out] message pointer to message + */ +void lsm303dlhcWriteRegister(I2CDriver *i2cp,uint8_t sad, uint8_t sub, + uint8_t value, msg_t* message) { + + uint8_t txbuf[2]; + uint8_t rxbuf; + if(sad == LSM303DLHC_SAD_ACCEL){ + switch (sub) { + default: + /* Reserved register must not be written, according to the datasheet + * this could permanently damage the device. + */ + chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), reserved register"); + case LSM303DLHC_SUB_ACC_STATUS_REG: + case LSM303DLHC_SUB_ACC_OUT_X_L: + case LSM303DLHC_SUB_ACC_OUT_X_H: + case LSM303DLHC_SUB_ACC_OUT_Y_L: + case LSM303DLHC_SUB_ACC_OUT_Y_H: + case LSM303DLHC_SUB_ACC_OUT_Z_L: + case LSM303DLHC_SUB_ACC_OUT_Z_H: + case LSM303DLHC_SUB_ACC_FIFO_SRC_REG: + case LSM303DLHC_SUB_ACC_INT1_SOURCE: + case LSM303DLHC_SUB_ACC_INT2_SOURCE: + case LSM303DLHC_SUB_ACC_CLICK_SRC: + /* Read only registers cannot be written, the command is ignored.*/ + return; + case LSM303DLHC_SUB_ACC_CTRL_REG1: + case LSM303DLHC_SUB_ACC_CTRL_REG2: + case LSM303DLHC_SUB_ACC_CTRL_REG3: + case LSM303DLHC_SUB_ACC_CTRL_REG4: + case LSM303DLHC_SUB_ACC_CTRL_REG5: + case LSM303DLHC_SUB_ACC_CTRL_REG6: + case LSM303DLHC_SUB_ACC_REFERENCE: + case LSM303DLHC_SUB_ACC_FIFO_CTRL_REG: + case LSM303DLHC_SUB_ACC_INT1_CFG: + case LSM303DLHC_SUB_ACC_INT1_THS: + case LSM303DLHC_SUB_ACC_INT1_DURATION: + case LSM303DLHC_SUB_ACC_INT2_CFG: + case LSM303DLHC_SUB_ACC_INT2_THS: + case LSM303DLHC_SUB_ACC_INT2_DURATION: + case LSM303DLHC_SUB_ACC_CLICK_CFG: + case LSM303DLHC_SUB_ACC_CLICK_THS: + case LSM303DLHC_SUB_ACC_TIME_LIMIT: + case LSM303DLHC_SUB_ACC_TIME_LATENCY: + case LSM303DLHC_SUB_ACC_TIME_WINDOW: + txbuf[0] = sub; + txbuf[1] = value; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); + } + break; + } + } + else if(sad == LSM303DLHC_SAD_COMPASS){ + switch (sub) { + default: + /* Reserved register must not be written, according to the datasheet + * this could permanently damage the device. + */ + chDbgAssert(FALSE, "lsm303dlhcWriteRegister(), reserved register"); + case LSM303DLHC_SUB_COMP_OUT_X_H: + case LSM303DLHC_SUB_COMP_OUT_X_L: + case LSM303DLHC_SUB_COMP_OUT_Z_H: + case LSM303DLHC_SUB_COMP_OUT_Z_L: + case LSM303DLHC_SUB_COMP_OUT_Y_H: + case LSM303DLHC_SUB_COMP_OUT_Y_L: + case LSM303DLHC_SUB_COMP_SR_REG: + case LSM303DLHC_SUB_COMP_IRA_REG: + case LSM303DLHC_SUB_COMP_IRB_REG: + case LSM303DLHC_SUB_COMP_IRC_REG: + case LSM303DLHC_SUB_COMP_TEMP_OUT_H: + case LSM303DLHC_SUB_COMP_TEMP_OUT_L: + /* Read only registers cannot be written, the command is ignored.*/ + return; + case LSM303DLHC_SUB_COMP_CRA_REG: + case LSM303DLHC_SUB_COMP_CRB_REG: + case LSM303DLHC_SUB_COMP_MR_REG: + txbuf[0] = sub; + txbuf[1] = value; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); + } + break; + } + } +} +/** @} */ diff --git a/os/various/devices_lib/mems/lsm303dlhc.h b/os/various/devices_lib/mems/lsm303dlhc.h new file mode 100644 index 0000000..46b51bc --- /dev/null +++ b/os/various/devices_lib/mems/lsm303dlhc.h @@ -0,0 +1,352 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file lsm303dlhc.h + * @brief LSM303DLHC MEMS interface module through I2C header. + * + * @addtogroup lsm303dlhc + * @{ + */ + +#ifndef _LSM303DLHC_H_ +#define _LSM303DLHC_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define LSM303DLHC_ACC_SENS_2G ((float)1671.836f) /*!< Accelerometer sensitivity with 2 G full scale [LSB * s^2 / m] */ +#define LSM303DLHC_ACC_SENS_4G ((float)835.918f) /*!< Accelerometer sensitivity with 4 G full scale [LSB * s^2 / m] */ +#define LSM303DLHC_ACC_SENS_8G ((float)417.959f) /*!< Accelerometer sensitivity with 8 G full scale [LSB * s^2 / m] */ +#define LSM303DLHC_ACC_SENS_16G ((float)208.979f) /*!< Accelerometer sensitivity with 16 G full scale [LSB * s^2 / m] */ + +#define LSM303DLHC_COMP_SENS_XY_1_3GA ((float)1100.0f) /*!< Compass sensitivity with 1.3 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_XY_1_9GA ((float)855.0f) /*!< Compass sensitivity with 1.9 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_XY_2_5GA ((float)670.0f) /*!< Compass sensitivity with 2.5 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_XY_4_0GA ((float)450.0f) /*!< Compass sensitivity with 4.0 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_XY_4_7GA ((float)400.0f) /*!< Compass sensitivity with 4.7 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_XY_5_6GA ((float)330.0f) /*!< Compass sensitivity with 5.6 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_XY_8_1GA ((float)230.0f) /*!< Compass sensitivity with 8.1 GA full scale [LSB / Ga] */ + +#define LSM303DLHC_COMP_SENS_Z_1_3GA ((float)980.0f) /*!< Compass sensitivity with 1.3 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_Z_1_9GA ((float)765.0f) /*!< Compass sensitivity with 1.9 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_Z_2_5GA ((float)600.0f) /*!< Compass sensitivity with 2.5 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_Z_4_0GA ((float)400.0f) /*!< Compass sensitivity with 4.0 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_Z_4_7GA ((float)355.0f) /*!< Compass sensitivity with 4.7 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_Z_5_6GA ((float)295.0f) /*!< Compass sensitivity with 5.6 GA full scale [LSB / Ga] */ +#define LSM303DLHC_COMP_SENS_Z_8_1GA ((float)205.0f) /*!< Compass sensitivity with 8.1 GA full scale [LSB / Ga] */ +/** + * @name LSM303DLHC register names + * @{ + */ +/******************************************************************************/ +/* */ +/* LSM303DLHC on board MEMS */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C communication *******************/ +#define LSM303DLHC_SAD ((uint8_t)0x7F) /*!< SAD[6:0] Slave Address Mask */ +#define LSM303DLHC_SAD_ACCEL ((uint8_t)0x19) /*!< ACCELEROMETER Slave Address */ +#define LSM303DLHC_SAD_COMPASS ((uint8_t)0x1E) /*!< MAGNETOMETER Slave Address */ + +#define LSM303DLHC_SUB ((uint8_t)0x7F) /*!< SUB[6:0] Sub-registers address Mask */ +#define LSM303DLHC_SUB_0 ((uint8_t)0x01) /*!< bit 0 */ +#define LSM303DLHC_SUB_1 ((uint8_t)0x02) /*!< bit 1 */ +#define LSM303DLHC_SUB_2 ((uint8_t)0x08) /*!< bit 3 */ +#define LSM303DLHC_SUB_4 ((uint8_t)0x10) /*!< bit 4 */ +#define LSM303DLHC_SUB_5 ((uint8_t)0x20) /*!< bit 5 */ +#define LSM303DLHC_SUB_6 ((uint8_t)0x40) /*!< bit 6 */ + +#define LSM303DLHC_SUB_MSB ((uint8_t)0x80) /*!< Multiple data read\write bit */ + +/******** Bit definition for Accelerometer SUB-Registers Addresses **********/ +#define LSM303DLHC_SUB_ACC_CTRL_REG1 ((uint8_t)0x20) /*!< CONTROL REGISTER 1 FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_CTRL_REG2 ((uint8_t)0x21) /*!< CONTROL REGISTER 2 FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_CTRL_REG3 ((uint8_t)0x22) /*!< CONTROL REGISTER 3 FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_CTRL_REG4 ((uint8_t)0x23) /*!< CONTROL REGISTER 4 FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_CTRL_REG5 ((uint8_t)0x24) /*!< CONTROL REGISTER 5 FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_CTRL_REG6 ((uint8_t)0x25) /*!< CONTROL REGISTER 6 FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_REFERENCE ((uint8_t)0x26) /*!< REFERENCE/DATACAPTURE FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_STATUS_REG ((uint8_t)0x27) /*!< STATUS REGISTER FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_OUT_X_L ((uint8_t)0x28) /*!< OUTPUT X-AXIS LOW FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_OUT_X_H ((uint8_t)0x29) /*!< OUTPUT X-AXIS HIGH FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_OUT_Y_L ((uint8_t)0x2A) /*!< OUTPUT Y-AXIS LOW FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_OUT_Y_H ((uint8_t)0x2B) /*!< OUTPUT Y-AXIS HIGH FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_OUT_Z_L ((uint8_t)0x2C) /*!< OUTPUT Z-AXIS LOW FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_OUT_Z_H ((uint8_t)0x2D) /*!< OUTPUT Z-AXIS HIGH FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_FIFO_CTRL_REG ((uint8_t)0x2E) /*!< FIFO CONTROL REGISTER FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_FIFO_SRC_REG ((uint8_t)0x2F) /*!< FIFO SOURCE REGISTER FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_INT1_CFG ((uint8_t)0x30) /*!< INTERRUPT1 CONFIG FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_INT1_SOURCE ((uint8_t)0x31) /*!< INTERRUPT1 SOURCE FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_INT1_THS ((uint8_t)0x32) /*!< INTERRUPT1 THRESHOLD FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_INT1_DURATION ((uint8_t)0x33) /*!< INTERRUPT1 DURATION FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_INT2_CFG ((uint8_t)0x34) /*!< INTERRUPT2 CONFIG FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_INT2_SOURCE ((uint8_t)0x35) /*!< INTERRUPT2 SOURCE FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_INT2_THS ((uint8_t)0x36) /*!< INTERRUPT2 THRESHOLD FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_INT2_DURATION ((uint8_t)0x37) /*!< INTERRUPT2 DURATION FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_CLICK_CFG ((uint8_t)0x38) /*!< CLICK CONFIG FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_CLICK_SRC ((uint8_t)0x39) /*!< CLICK SOURCE FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_CLICK_THS ((uint8_t)0x3A) /*!< CLICK THRESHOLD FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_TIME_LIMIT ((uint8_t)0x3B) /*!< TIME LIMIT FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_TIME_LATENCY ((uint8_t)0x3C) /*!< TIME LATENCY FOR ACCELEROMETER */ +#define LSM303DLHC_SUB_ACC_TIME_WINDOW ((uint8_t)0x3D) /*!< TIME WINDOW FOR ACCELEROMETER */ + +/********* Bit definition for Compass SUB-Registers Addresses **********/ +#define LSM303DLHC_SUB_COMP_CRA_REG ((uint8_t)0x00) /*!< CONTROL REGISTER A FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_CRB_REG ((uint8_t)0x01) /*!< CONTROL REGISTER B FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_MR_REG ((uint8_t)0x02) /*!< STATUS REGISTER FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_OUT_X_H ((uint8_t)0x03) /*!< OUTPUT X-AXIS HIGH FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_OUT_X_L ((uint8_t)0x04) /*!< OUTPUT X-AXIS LOW FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_OUT_Z_H ((uint8_t)0x05) /*!< OUTPUT Z-AXIS HIGH FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_OUT_Z_L ((uint8_t)0x06) /*!< OUTPUT Z-AXIS LOW FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_OUT_Y_H ((uint8_t)0x07) /*!< OUTPUT Y-AXIS HIGH FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_OUT_Y_L ((uint8_t)0x08) /*!< OUTPUT Y-AXIS LOW FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_SR_REG ((uint8_t)0x09) /*!< SR REGISTER FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_IRA_REG ((uint8_t)0x0A) /*!< IR A REGISTER FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_IRB_REG ((uint8_t)0x0B) /*!< IR B REGISTER FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_IRC_REG ((uint8_t)0x0C) /*!< IR C REGISTER FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_TEMP_OUT_H ((uint8_t)0x31) /*!< OUTPUT TEMP HIGH FOR MAGNETOMETER */ +#define LSM303DLHC_SUB_COMP_TEMP_OUT_L ((uint8_t)0x32) /*!< OUTPUT TEMP LOW FOR MAGNETOMETER */ + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @name Accelerometer data structures and types + * @{ + */ + +/** + * @brief Accelerometer Output Data Rate + */ +typedef enum +{ + LSM303DLHC_ACC_ODR_PD = 0x00, /*!< Power down */ + LSM303DLHC_ACC_ODR_1Hz = 0x10, /*!< Output Data Rate = 1 Hz */ + LSM303DLHC_ACC_ODR_10Hz = 0x20, /*!< Output Data Rate = 10 Hz */ + LSM303DLHC_ACC_ODR_25Hz = 0x30, /*!< Output Data Rate = 25 Hz */ + LSM303DLHC_ACC_ODR_50Hz = 0x40, /*!< Output Data Rate = 50 Hz */ + LSM303DLHC_ACC_ODR_100Hz = 0x50, /*!< Output Data Rate = 100 Hz */ + LSM303DLHC_ACC_ODR_200Hz = 0x60, /*!< Output Data Rate = 200 Hz */ + LSM303DLHC_ACC_ODR_400Hz = 0x70, /*!< Output Data Rate = 400 Hz */ + LSM303DLHC_ACC_ODR_1620Hz = 0x80, /*!< Output Data Rate = 1620 Hz Low Power mode only */ + LSM303DLHC_ACC_ODR_1344Hz = 0x90 /*!< Output Data Rate = 1344 Hz in Normal mode and 5376 Hz in Low Power Mode */ +}LSM303DLHC_ACC_ODR_t; + +/** + * @brief Accelerometer Power Mode + */ +typedef enum +{ + LSM303DLHC_ACC_PM_NORMAL = 0x00, /*!< Normal mode enabled */ + LSM303DLHC_ACC_PM_LOW_POWER = 0x08 /*!< Low Power mode enabled */ +}LSM303DLHC_ACC_PM_t; + +/** + * @brief Accelerometer Full Scale + */ +typedef enum +{ + LSM303DLHC_ACC_FS_2G = 0x00, /*!< ±2 g m/s^2 */ + LSM303DLHC_ACC_FS_4G = 0x10, /*!< ±4 g m/s^2 */ + LSM303DLHC_ACC_FS_8G = 0x20, /*!< ±8 g m/s^2 */ + LSM303DLHC_ACC_FS_16G = 0x30 /*!< ±16 g m/s^2 */ +}LSM303DLHC_ACC_FS_t; + +/** + * @brief Accelerometer Axes Enabling + */ +typedef enum{ + LSM303DLHC_ACC_AE_DISABLED = 0x00, /*!< Axes all disabled */ + LSM303DLHC_ACC_AE_X = 0x01, /*!< Only X-axis enabled */ + LSM303DLHC_ACC_AE_Y = 0x02, /*!< Only Y-axis enabled */ + LSM303DLHC_ACC_AE_XY = 0x03, /*!< X & Y axes enabled */ + LSM303DLHC_ACC_AE_Z = 0x04, /*!< Only Z-axis enabled */ + LSM303DLHC_ACC_AE_XZ = 0x05, /*!< X & Z axes enabled */ + LSM303DLHC_ACC_AE_YZ = 0x06, /*!< Y & Z axes enabled */ + LSM303DLHC_ACC_AE_XYZ = 0x07 /*!< All axes enabled */ +}LSM303DLHC_ACC_AE_t; + +/** + * @brief Accelerometer Block Data Update + */ +typedef enum +{ + LSM303DLHC_ACC_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ + LSM303DLHC_ACC_BDU_BLOCKED = 0x80 /*!< Single Update: output registers not updated until MSB and LSB reading */ +}LSM303DLHC_ACC_BDU_t; + +/** + * @brief Accelerometer Endianness + */ +typedef enum +{ + LSM303DLHC_ACC_End_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ + LSM303DLHC_ACC_End_BIG = 0x40 /*!< Big Endian: data MSB @ lower address */ +}LSM303DLHC_ACC_End_t; + +/** + * @brief Accelerometer High Resolution mode + */ +typedef enum +{ + LSM303DLHC_ACC_HR_Enabled = 0x08, /*!< High resolution output mode enabled */ + LSM303DLHC_ACC_HR_Disabled = 0x00 /*!< High resolution output mode disabled */ +}LSM303DLHC_ACC_HR_t; + +/** + * @brief Accelerometer configuration structure. + */ +typedef struct { + /** + * @brief Accelerometer fullscale value. + */ + LSM303DLHC_ACC_FS_t fullscale; + /** + * @brief Accelerometer power mode selection. + */ + LSM303DLHC_ACC_PM_t powermode; + /** + * @brief Accelerometer output data rate selection. + */ + LSM303DLHC_ACC_ODR_t outputdatarate; + /** + * @brief Accelerometer axes enabling. + */ + LSM303DLHC_ACC_AE_t axesenabling; + /** + * @brief Accelerometer block data update. + */ + LSM303DLHC_ACC_BDU_t blockdataupdate; + /** + * @brief Accelerometer block data update. + */ + LSM303DLHC_ACC_HR_t highresmode; +} LSM303DLHC_ACC_Config; +/** @} */ + + +/** + * @name Compass data types + * @{ + */ + +/** + * @brief Compass Output Data Rate + */ +typedef enum +{ + LSM303DLHC_COMP_ODR_0_75_Hz = 0x00, /*!< Output Data Rate = 0.75 Hz */ + LSM303DLHC_COMP_ODR_1_5_Hz = 0x04, /*!< Output Data Rate = 1.5 Hz */ + LSM303DLHC_COMP_ODR_3_0_Hz = 0x08, /*!< Output Data Rate = 3 Hz */ + LSM303DLHC_COMP_ODR_7_5_Hz = 0x0C, /*!< Output Data Rate = 7.5 Hz */ + LSM303DLHC_COMP_ODR_15_Hz = 0x10, /*!< Output Data Rate = 15 Hz */ + LSM303DLHC_COMP_ODR_30_Hz = 0x14, /*!< Output Data Rate = 30 Hz */ + LSM303DLHC_COMP_ODR_75_Hz = 0x18, /*!< Output Data Rate = 75 Hz */ + LSM303DLHC_COMP_ODR_220_Hz = 0x1C /*!< Output Data Rate = 220 Hz */ +}LSM303DLHC_COMP_ODR_t; + + +/** + * @brief Compass Full Scale + */ +typedef enum +{ + LSM303DLHC_COMP_FS_1_3_GA = 0x20, /*!< Full scale = ±1.3 Gauss */ + LSM303DLHC_COMP_FS_1_9_GA = 0x40, /*!< Full scale = ±1.9 Gauss */ + LSM303DLHC_COMP_FS_2_5_GA = 0x60, /*!< Full scale = ±2.5 Gauss */ + LSM303DLHC_COMP_FS_4_0_GA = 0x80, /*!< Full scale = ±4.0 Gauss */ + LSM303DLHC_COMP_FS_4_7_GA = 0xA0, /*!< Full scale = ±4.7 Gauss */ + LSM303DLHC_COMP_FS_5_6_GA = 0xC0, /*!< Full scale = ±5.6 Gauss */ + LSM303DLHC_COMP_FS_8_1_GA = 0xE0 /*!< Full scale = ±8.1 Gauss */ +}LSM303DLHC_COMP_FS_t; + + +/** + * @brief Compass Working Mode + */ +typedef enum +{ + LSM303DLHC_COMP_WM_CONTINUOS = 0x00, /*!< Continuous-Conversion Mode */ + LSM303DLHC_COMP_WM_BLOCKED = 0x01, /*!< Single-Conversion Mode */ + LSM303DLHC_COMP_WM_SLEEP = 0x02 /*!< Sleep Mode */ +}LSM303DLHC_COMP_WM_t; + +/** + * @brief Compass configuration structure. + */ +typedef struct { + /** + * @brief Compass fullscale value. + */ + LSM303DLHC_COMP_FS_t fullscale; + /** + * @brief Compass output data rate selection. + */ + LSM303DLHC_COMP_ODR_t outputdatarate; + /** + * @brief Compass working mode. + */ + LSM303DLHC_COMP_WM_t workingmode; +} LSM303DLHC_COMP_Config; +/** @} */ +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + + uint8_t lsm303dlhcReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + msg_t* message); + void lsm303dlhcWriteRegister(I2CDriver *i2cp,uint8_t sad, uint8_t sub, + uint8_t value, msg_t* message); + +#ifdef __cplusplus +} +#endif +#endif /* _LSM303DLHC_H_ */ +/** @} */ + diff --git a/os/various/devices_lib/mems/lsm6ds0.c b/os/various/devices_lib/mems/lsm6ds0.c new file mode 100644 index 0000000..da67f12 --- /dev/null +++ b/os/various/devices_lib/mems/lsm6ds0.c @@ -0,0 +1,184 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file lsm6ds0.c + * @brief LSM6DS0 MEMS interface module through I2C code. + * + * @addtogroup lsm6ds0 + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "lsm6ds0.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Reads a generic sub-register value. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] sub sub-register address + * @param[in] message pointer to message + * @return register value. + */ +uint8_t lsm6ds0ReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + msg_t* message) { + + uint8_t txbuf, rxbuf[2]; +#if defined(STM32F103_MCUCONF) + txbuf = LSM303DLHC_SUB_MSB | sub; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 2, TIME_INFINITE); + } + return rxbuf[0]; +#else + txbuf = sub; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, &txbuf, 1, rxbuf, 1, TIME_INFINITE); + } + return rxbuf[0]; +#endif +} + +/** + * @brief Writes a value into a register. + * @pre The I2C interface must be initialized and the driver started. + * + * @param[in] i2cp pointer to the I2C interface + * @param[in] sad slave address without R bit + * @param[in] sub sub-register address + * @param[in] value the value to be written + * @param[out] message pointer to message + */ +void lsm6ds0WriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + uint8_t value, msg_t* message) { + + uint8_t txbuf[2]; + uint8_t rxbuf; + switch (sub) { + default: + /* Reserved register must not be written, according to the datasheet + * this could permanently damage the device. + */ + chDbgAssert(FALSE, "lsm6ds0WriteRegister(), reserved register"); + case LSM6DS0_SUB_WHO_AM_I: + case LSM6DS0_SUB_INT_GEN_SRC_G: + case LSM6DS0_SUB_OUT_TEMP_L: + case LSM6DS0_SUB_OUT_TEMP_H: + case LSM6DS0_SUB_STATUS_REG1: + case LSM6DS0_SUB_OUT_X_L_G: + case LSM6DS0_SUB_OUT_X_H_G: + case LSM6DS0_SUB_OUT_Y_L_G: + case LSM6DS0_SUB_OUT_Y_H_G: + case LSM6DS0_SUB_OUT_Z_L_G: + case LSM6DS0_SUB_OUT_Z_H_G: + case LSM6DS0_SUB_INT_GEN_SRC_XL: + case LSM6DS0_SUB_STATUS_REG2: + case LSM6DS0_SUB_OUT_X_L_XL: + case LSM6DS0_SUB_OUT_X_H_XL: + case LSM6DS0_SUB_OUT_Y_L_XL: + case LSM6DS0_SUB_OUT_Y_H_XL: + case LSM6DS0_SUB_OUT_Z_L_XL: + case LSM6DS0_SUB_OUT_Z_H_XL: + case LSM6DS0_SUB_FIFO_SRC: + /* Read only registers cannot be written, the command is ignored.*/ + return; + case LSM6DS0_SUB_ACT_THS: + case LSM6DS0_SUB_ACT_DUR: + case LSM6DS0_SUB_INT_GEN_CFG_XL: + case LSM6DS0_SUB_INT_GEN_THS_X_XL: + case LSM6DS0_SUB_INT_GEN_THS_Y_XL: + case LSM6DS0_SUB_INT_GEN_THS_Z_XL: + case LSM6DS0_SUB_INT_GEN_DUR_XL: + case LSM6DS0_SUB_REFERENCE_G: + case LSM6DS0_SUB_INT_CTRL: + case LSM6DS0_SUB_CTRL_REG1_G: + case LSM6DS0_SUB_CTRL_REG2_G: + case LSM6DS0_SUB_CTRL_REG3_G: + case LSM6DS0_SUB_ORIENT_CFG_G: + case LSM6DS0_SUB_CTRL_REG4: + case LSM6DS0_SUB_CTRL_REG5_XL: + case LSM6DS0_SUB_CTRL_REG6_XL: + case LSM6DS0_SUB_CTRL_REG7_XL: + case LSM6DS0_SUB_CTRL_REG8: + case LSM6DS0_SUB_CTRL_REG9: + case LSM6DS0_SUB_CTRL_REG10: + case LSM6DS0_SUB_FIFO_CTRL: + case LSM6DS0_SUB_INT_GEN_CFG_G: + case LSM6DS0_SUB_INT_GEN_THS_XH_G: + case LSM6DS0_SUB_INT_GEN_THS_XL_G: + case LSM6DS0_SUB_INT_GEN_THS_YH_G: + case LSM6DS0_SUB_INT_GEN_THS_YL_G: + case LSM6DS0_SUB_INT_GEN_THS_ZH_G: + case LSM6DS0_SUB_INT_GEN_THS_ZL_G: + case LSM6DS0_SUB_INT_GEN_DUR_G: + txbuf[0] = sub; + txbuf[1] = value; + if(message != NULL){ + *message = i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, + TIME_INFINITE); + } + else{ + i2cMasterTransmitTimeout(i2cp, sad, txbuf, 2, &rxbuf, 0, TIME_INFINITE); + } + break; + } +} + +/** @} */ diff --git a/os/various/devices_lib/mems/lsm6ds0.h b/os/various/devices_lib/mems/lsm6ds0.h new file mode 100644 index 0000000..57e2057 --- /dev/null +++ b/os/various/devices_lib/mems/lsm6ds0.h @@ -0,0 +1,482 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file lsm6ds0.h + * @brief LSM6DS0 MEMS interface module header. + * + * @{ + */ + +#ifndef _LSM6DS0_H_ +#define _LSM6DS0_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define LSM6DS0_ACC_SENS_2G ((float)1671.095f) /*!< Accelerometer sensitivity with 2 G full scale [LSB * s^2 / m] */ +#define LSM6DS0_ACC_SENS_4G ((float)835.547f) /*!< Accelerometer sensitivity with 4 G full scale [LSB * s^2 / m] */ +#define LSM6DS0_ACC_SENS_8G ((float)417.774) /*!< Accelerometer sensitivity with 8 G full scale [LSB * s^2 / m] */ +#define LSM6DS0_ACC_SENS_16G ((float)139.258f) /*!< Accelerometer sensitivity with 16 G full scale [LSB * s^2 / m] */ + +#define LSM6DS0_GYRO_SENS_245DPS ((float)114.286f) /*!< Gyroscope sensitivity with 245 dps full scale [LSB * s / °] */ +#define LSM6DS0_GYRO_SENS_500DPS ((float)57.143f) /*!< Gyroscope sensitivity with 500 dps full scale [LSB * s / °] */ +#define LSM6DS0_GYRO_SENS_2000DPS ((float)14.286f) /*!< Gyroscope sensitivity with 2000 dps full scale [LSB * s / °] */ +/** + * @name LSM6DS0 register names + * @{ + */ +/******************************************************************************/ +/* */ +/* LSM6DS0 on board MEMS */ +/* */ +/******************************************************************************/ +/***************** Bit definition for I2C/SPI communication *****************/ +#define LSM6DS0_SUB ((uint8_t)0x7F) /*!< SUB[6:0] Sub-registers address Mask */ +#define LSM6DS0_SUB_0 ((uint8_t)0x01) /*!< bit 0 */ +#define LSM6DS0_SUB_1 ((uint8_t)0x02) /*!< bit 1 */ +#define LSM6DS0_SUB_2 ((uint8_t)0x08) /*!< bit 3 */ +#define LSM6DS0_SUB_4 ((uint8_t)0x10) /*!< bit 4 */ +#define LSM6DS0_SUB_5 ((uint8_t)0x20) /*!< bit 5 */ +#define LSM6DS0_SUB_6 ((uint8_t)0x40) /*!< bit 6 */ + +#define LSM6DS0_SUB_MSB ((uint8_t)0x80) /*!< Multiple data read\write bit */ + +/***************** Bit definition for Registers Addresses *******************/ +#define LSM6DS0_SUB_ACT_THS ((uint8_t)0x04) /*!< Activity threshold register */ +#define LSM6DS0_SUB_ACT_DUR ((uint8_t)0x05) /*!< Inactivity duration register */ +#define LSM6DS0_SUB_INT_GEN_CFG_XL ((uint8_t)0x06) /*!< Accelerometer interrupt generator configuration register */ +#define LSM6DS0_SUB_INT_GEN_THS_X_XL ((uint8_t)0x07) /*!< Accelerometer X-axis interrupt threshold register */ +#define LSM6DS0_SUB_INT_GEN_THS_Y_XL ((uint8_t)0x08) /*!< Accelerometer Y-axis interrupt threshold register */ +#define LSM6DS0_SUB_INT_GEN_THS_Z_XL ((uint8_t)0x09) /*!< Accelerometer Z-axis interrupt threshold register */ +#define LSM6DS0_SUB_INT_GEN_DUR_XL ((uint8_t)0x0A) /*!< Accelerometer interrupt duration register */ +#define LSM6DS0_SUB_REFERENCE_G ((uint8_t)0x0B) /*!< Gyroscope reference value register for digital high-pass filter */ +#define LSM6DS0_SUB_INT_CTRL ((uint8_t)0x0C) /*!< INT pin control register */ +#define LSM6DS0_SUB_WHO_AM_I ((uint8_t)0x0F) /*!< Who_AM_I register */ +#define LSM6DS0_SUB_CTRL_REG1_G ((uint8_t)0x10) /*!< Gyroscope control register 1 */ +#define LSM6DS0_SUB_CTRL_REG2_G ((uint8_t)0x11) /*!< Gyroscope control register 2 */ +#define LSM6DS0_SUB_CTRL_REG3_G ((uint8_t)0x12) /*!< Gyroscope control register 3 */ +#define LSM6DS0_SUB_ORIENT_CFG_G ((uint8_t)0x13) /*!< Gyroscope sign and orientation register */ +#define LSM6DS0_SUB_INT_GEN_SRC_G ((uint8_t)0x14) /*!< Gyroscope interrupt source register */ +#define LSM6DS0_SUB_OUT_TEMP_L ((uint8_t)0x15) /*!< Temperature data output low register */ +#define LSM6DS0_SUB_OUT_TEMP_H ((uint8_t)0x16) /*!< Temperature data output high register */ +#define LSM6DS0_SUB_STATUS_REG1 ((uint8_t)0x17) /*!< Status register 1 */ +#define LSM6DS0_SUB_OUT_X_L_G ((uint8_t)0x18) /*!< Gyroscope X-axis low output register */ +#define LSM6DS0_SUB_OUT_X_H_G ((uint8_t)0x19) /*!< Gyroscope X-axis high output register */ +#define LSM6DS0_SUB_OUT_Y_L_G ((uint8_t)0x1A) /*!< Gyroscope Y-axis low output register */ +#define LSM6DS0_SUB_OUT_Y_H_G ((uint8_t)0x1B) /*!< Gyroscope Y-axis high output register */ +#define LSM6DS0_SUB_OUT_Z_L_G ((uint8_t)0x1C) /*!< Gyroscope Z-axis low output register */ +#define LSM6DS0_SUB_OUT_Z_H_G ((uint8_t)0x1D) /*!< Gyroscope Z-axis high output register */ +#define LSM6DS0_SUB_CTRL_REG4 ((uint8_t)0x1E) /*!< Control register 4 */ +#define LSM6DS0_SUB_CTRL_REG5_XL ((uint8_t)0x1F) /*!< Accelerometer Control Register 5 */ +#define LSM6DS0_SUB_CTRL_REG6_XL ((uint8_t)0x20) /*!< Accelerometer Control Register 6 */ +#define LSM6DS0_SUB_CTRL_REG7_XL ((uint8_t)0x21) /*!< Accelerometer Control Register 7 */ +#define LSM6DS0_SUB_CTRL_REG8 ((uint8_t)0x22) /*!< Control register 8 */ +#define LSM6DS0_SUB_CTRL_REG9 ((uint8_t)0x23) /*!< Control register 9 */ +#define LSM6DS0_SUB_CTRL_REG10 ((uint8_t)0x24) /*!< Control register 10 */ +#define LSM6DS0_SUB_INT_GEN_SRC_XL ((uint8_t)0x26) /*!< Accelerometer interrupt source register */ +#define LSM6DS0_SUB_STATUS_REG2 ((uint8_t)0x27) /*!< Status register */ +#define LSM6DS0_SUB_OUT_X_L_XL ((uint8_t)0x28) /*!< Accelerometer X-axis low output register */ +#define LSM6DS0_SUB_OUT_X_H_XL ((uint8_t)0x29) /*!< Accelerometer X-axis high output register */ +#define LSM6DS0_SUB_OUT_Y_L_XL ((uint8_t)0x2A) /*!< Accelerometer Y-axis low output register */ +#define LSM6DS0_SUB_OUT_Y_H_XL ((uint8_t)0x2B) /*!< Accelerometer Y-axis high output register */ +#define LSM6DS0_SUB_OUT_Z_L_XL ((uint8_t)0x2C) /*!< Accelerometer Z-axis low output register */ +#define LSM6DS0_SUB_OUT_Z_H_XL ((uint8_t)0x2D) /*!< Accelerometer Z-axis high output register */ +#define LSM6DS0_SUB_FIFO_CTRL ((uint8_t)0x2E) /*!< FIFO control register */ +#define LSM6DS0_SUB_FIFO_SRC ((uint8_t)0x2F) /*!< FIFO status control register */ +#define LSM6DS0_SUB_INT_GEN_CFG_G ((uint8_t)0x30) /*!< Gyroscope interrupt generator configuration register */ +#define LSM6DS0_SUB_INT_GEN_THS_XH_G ((uint8_t)0x31) /*!< Gyroscope X-axis low interrupt generator threshold registers */ +#define LSM6DS0_SUB_INT_GEN_THS_XL_G ((uint8_t)0x32) /*!< Gyroscope X-axis high interrupt generator threshold registers */ +#define LSM6DS0_SUB_INT_GEN_THS_YH_G ((uint8_t)0x33) /*!< Gyroscope Y-axis low interrupt generator threshold registers */ +#define LSM6DS0_SUB_INT_GEN_THS_YL_G ((uint8_t)0x34) /*!< Gyroscope Y-axis high interrupt generator threshold registers */ +#define LSM6DS0_SUB_INT_GEN_THS_ZH_G ((uint8_t)0x35) /*!< Gyroscope Z-axis low interrupt generator threshold registers */ +#define LSM6DS0_SUB_INT_GEN_THS_ZL_G ((uint8_t)0x36) /*!< Gyroscope Z-axis high interrupt generator threshold registers */ +#define LSM6DS0_SUB_INT_GEN_DUR_G ((uint8_t)0x37) /*!< Gyroscope interrupt generator duration register */ + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @name Generic LSM6DS0 data structures and types + * @{ + */ + +/** + * @brief Accelerometer and Gyroscope Slave Address + */ +typedef enum { + LSM6DS0_SAD_GND = 0x6A, /*!< LSM6DS0 Slave Address when SA1 is to GND */ + LSM6DS0_SAD_VCC = 0x6B /*!< LSM6DS0 Slave Address when SA1 is to VCC */ +}LSM6DS0_SAD_t; + +/** + * @brief Accelerometer and Gyroscope Block Data Update + */ +typedef enum +{ + LSM6DS0_BDU_CONTINOUS = 0x00, /*!< Continuos Update */ + LSM6DS0_BDU_BLOCKED = 0x40 /*!< Single Update: output registers not updated until MSB and LSB reading */ +}LSM6DS0_BDU_t; + +/** + * @brief Accelerometer and Gyroscope Endianness + */ +typedef enum +{ + LSM6DS0_END_LITTLE = 0x00, /*!< Little Endian: data LSB @ lower address */ + LSM6DS0_END_BIG = 0x20 /*!< Big Endian: data MSB @ lower address */ +}LSM6DS0_END_t; +/** @} */ + +/** + * @name Accelerometer data structures and types + * @{ + */ + +/** + * @brief Accelerometer Decimation Mode + */ +typedef enum { + LSM6DS0_ACC_DEC_DISABLED = 0x00, /*!< NO decimation */ + LSM6DS0_ACC_DEC_X2 = 0x40, /*!< Decimation update every 2 sample */ + LSM6DS0_ACC_DEC_X4 = 0x80, /*!< Decimation update every 4 sample */ + LSM6DS0_ACC_DEC_X8 = 0xC0 /*!< Decimation update every 8 sample */ +}LSM6DS0_ACC_DEC_t; + +/** + * @brief Accelerometer Axes Enabling + */ +typedef enum{ + LSM6DS0_ACC_AE_DISABLED = 0x00, /*!< Axes all disabled */ + LSM6DS0_ACC_AE_X = 0x08, /*!< Only X-axis enabled */ + LSM6DS0_ACC_AE_Y = 0x10, /*!< Only Y-axis enabled */ + LSM6DS0_ACC_AE_XY = 0x18, /*!< X & Y axes enabled */ + LSM6DS0_ACC_AE_Z = 0x20, /*!< Only Z-axis enabled */ + LSM6DS0_ACC_AE_XZ = 0x28, /*!< X & Z axes enabled */ + LSM6DS0_ACC_AE_YZ = 0x30, /*!< Y & Z axes enabled */ + LSM6DS0_ACC_AE_XYZ = 0x38 /*!< All axes enabled */ +}LSM6DS0_ACC_AE_t; + +/** + * @brief Accelerometer Output Data Rate + */ +typedef enum { + LSM6DS0_ACC_ODR_PD = 0x00, /*!< Power down */ + LSM6DS0_ACC_ODR_10Hz = 0x20, /*!< Output Data Rate = 10 Hz */ + LSM6DS0_ACC_ODR_50Hz = 0x40, /*!< Output Data Rate = 50 Hz */ + LSM6DS0_ACC_ODR_119Hz = 0x60, /*!< Output Data Rate = 119 Hz */ + LSM6DS0_ACC_ODR_238Hz = 0x80, /*!< Output Data Rate = 238 Hz */ + LSM6DS0_ACC_ODR_476Hz = 0xA0, /*!< Output Data Rate = 476 Hz */ + LSM6DS0_ACC_ODR_952Hz = 0xC0 /*!< Output Data Rate = 952 Hz */ +}LSM6DS0_ACC_ODR_t; + +/** + * @brief Accelerometer Full Scale + */ +typedef enum { + LSM6DS0_ACC_FS_2G = 0x00, /*!< ±2 g m/s^2 */ + LSM6DS0_ACC_FS_4G = 0x10, /*!< ±4 g m/s^2 */ + LSM6DS0_ACC_FS_8G = 0x18, /*!< ±8 g m/s^2 */ + LSM6DS0_ACC_FS_16G = 0x08 /*!< ±16 g m/s^2 */ +}LSM6DS0_ACC_FS_t; + +/** + * @brief Accelerometer Antialiasing filter Bandwidth Selection + */ +typedef enum { + LSM6DS0_ACC_BW_408Hz = 0x00, /*!< AA filter bandwidth = 408 Hz */ + LSM6DS0_ACC_BW_211Hz = 0x01, /*!< AA filter bandwidth = 211 Hz */ + LSM6DS0_ACC_BW_105Hz = 0x02, /*!< AA filter bandwidth = 105 Hz */ + LSM6DS0_ACC_BW_50Hz = 0x03, /*!< AA filter bandwidth = 50 Hz */ + LSM6DS0_ACC_BW_ACCORDED = 0x04, /*!< AA filter bandwidth chosen by ODR selection */ +}LSM6DS0_ACC_BW_t; + +/** + * @brief Accelerometer High Resolution mode + */ +typedef enum +{ + LSM6DS0_ACC_HR_Disabled = 0x00, /*!< High resolution output mode disabled, FDS bypassed */ + LSM6DS0_ACC_HR_EN_9 = 0xC4, /*!< High resolution output mode enabled, LP cutoff = ODR/9, FDS enabled */ + LSM6DS0_ACC_HR_EN_50 = 0x84, /*!< High resolution output mode enabled, LP cutoff = ODR/50, FDS enabled */ + LSM6DS0_ACC_HR_EN_100 = 0xA4, /*!< High resolution output mode enabled, LP cutoff = ODR/100, FDS enabled */ + LSM6DS0_ACC_HR_EN_400 = 0xE4, /*!< High resolution output mode enabled, LP cutoff = ODR/400, FDS enabled */ +}LSM6DS0_ACC_HR_t; + +/** + * @brief HP filter for interrupt + */ +typedef enum +{ + LSM6DS0_ACC_HPIS1_BYPASSED = 0x00, /*!< High-pass filter bypassed */ + LSM6DS0_ACC_HPIS1_ENABLED = 0x01 /*!< High-pass filter enabled for accelerometer interrupt function on interrupt */ +}LSM6DS0_ACC_HPIS1_t; + +/** + * @brief Accelerometer configuration structure. + */ +typedef struct { + + /** + * @brief LSM6DS0 Slave Address + */ + LSM6DS0_SAD_t slaveaddress; + /** + * @brief Accelerometer Decimation Mode + */ + LSM6DS0_ACC_DEC_t decimation; + /** + * @brief Accelerometer Output Data Rate + */ + LSM6DS0_ACC_ODR_t outputdatarate; + /** + * @brief Accelerometer Antialiasing filter Bandwidth Selection + */ + LSM6DS0_ACC_BW_t bandwidth; + /** + * @brief Accelerometer Full Scale + */ + LSM6DS0_ACC_FS_t fullscale; + /** + * @brief Accelerometer Axes Enabling + */ + LSM6DS0_ACC_AE_t axesenabling; + /** + * @brief Accelerometer High Resolution mode + */ + LSM6DS0_ACC_HR_t highresmode; + /** + * @brief HP filter for interrupt + */ + LSM6DS0_ACC_HPIS1_t hpfirq; + /** + * @brief LSM6DS0 Endianness + */ + LSM6DS0_END_t endianess; + /** + * @brief LSM6DS0 Block Data Update + */ + LSM6DS0_BDU_t blockdataupdate; +} LSM6DS0_ACC_Config; +/** @} */ + +/** + * @name Gyroscope data structures and types + * @{ + */ + +/** + * @brief Gyroscope Output Data Rate + */ +typedef enum { + LSM6DS0_GYRO_ODR_PD = 0x00, /*!< Power down */ + LSM6DS0_GYRO_ODR_14_9Hz_CO_5Hz = 0x20, /*!< Output Data Rate = 14.9 Hz, CutOff = 5Hz */ + LSM6DS0_GYRO_ODR_59_5Hz_CO_16Hz = 0x40, /*!< Output Data Rate = 59.5 Hz, CutOff = 16Hz */ + LSM6DS0_GYRO_ODR_119Hz_CO_14Hz = 0x60, /*!< Output Data Rate = 119 Hz, CutOff = 14Hz */ + LSM6DS0_GYRO_ODR_119Hz_CO_31Hz = 0x61, /*!< Output Data Rate = 119 Hz, CutOff = 31Hz */ + LSM6DS0_GYRO_ODR_238Hz_CO_14Hz = 0x80, /*!< Output Data Rate = 238 Hz, CutOff = 14Hz */ + LSM6DS0_GYRO_ODR_238Hz_CO_29Hz = 0x81, /*!< Output Data Rate = 328 Hz, CutOff = 29Hz */ + LSM6DS0_GYRO_ODR_238Hz_CO_63Hz = 0x82, /*!< Output Data Rate = 238 Hz, CutOff = 63Hz */ + LSM6DS0_GYRO_ODR_238Hz_CO_78Hz = 0x83, /*!< Output Data Rate = 476 Hz, CutOff = 78Hz */ + LSM6DS0_GYRO_ODR_476Hz_CO_21Hz = 0xA0, /*!< Output Data Rate = 476 Hz, CutOff = 21Hz */ + LSM6DS0_GYRO_ODR_476Hz_CO_28Hz = 0xA1, /*!< Output Data Rate = 238 Hz, CutOff = 28Hz */ + LSM6DS0_GYRO_ODR_476Hz_CO_57Hz = 0xA2, /*!< Output Data Rate = 476 Hz, CutOff = 57Hz */ + LSM6DS0_GYRO_ODR_476Hz_CO_100Hz = 0xA3, /*!< Output Data Rate = 476 Hz, CutOff = 100Hz */ + LSM6DS0_GYRO_ODR_952Hz_CO_33Hz = 0xC0, /*!< Output Data Rate = 952 Hz, CutOff = 33Hz */ + LSM6DS0_GYRO_ODR_952Hz_CO_40Hz = 0xC1, /*!< Output Data Rate = 952 Hz, CutOff = 40Hz */ + LSM6DS0_GYRO_ODR_952Hz_CO_58Hz = 0xC2, /*!< Output Data Rate = 952 Hz, CutOff = 58Hz */ + LSM6DS0_GYRO_ODR_952Hz_CO_100Hz = 0xC3 /*!< Output Data Rate = 952 Hz, CutOff = 100Hz */ +}LSM6DS0_GYRO_ODR_t; + +/** + * @brief Gyroscope Full Scale + */ +typedef enum { + LSM6DS0_GYRO_FS_245DSP = 0x00, /*!< ±245 degrees per second */ + LSM6DS0_GYRO_FS_500DSP = 0x08, /*!< ±500 degrees per second */ + LSM6DS0_GYRO_FS_2000DSP = 0x18 /*!< ±2000 degrees per second */ +}LSM6DS0_GYRO_FS_t; + +/** + * @brief Gyroscope Output Selection + */ +typedef enum { + LSM6DS0_GYRO_OUT_SEL_BYPASS = 0x00, /*!< Output not filtered */ + LSM6DS0_GYRO_OUT_SEL_FILTERED = 0x01, /*!< Output filtered */ +}LSM6DS0_GYRO_OUT_SEL_t; + +/** + * @brief Gyroscope Interrupt Selection + */ +typedef enum { + LSM6DS0_GYRO_INT_SEL_BYPASS = 0x00, /*!< Interrupt generator signal not filtered */ + LSM6DS0_GYRO_INT_SEL_FILTERED = 0x08, /*!< Interrupt generator signal filtered */ +}LSM6DS0_GYRO_INT_SEL_t; + +/** + * @brief Gyroscope Low Power Mode + */ +typedef enum { + LSM6DS0_GYRO_LP_MODE_HIGH_PERFORMANCE = 0x00, /*!< High performance */ + LSM6DS0_GYRO_LP_MODE_LOW_POWER = 0x80, /*!< Low power */ +}LSM6DS0_GYRO_LP_MODE_t; + +/** + * @brief Gyroscope High Pass Filter Cutoff Selection + */ +typedef enum { + LSM6DS0_GYRO_HPCF_DISABLED = 0x00, /*!< HP filter disabled */ + LSM6DS0_GYRO_HPCF_0 = 0x40, /*!< Config 0 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_1 = 0x41, /*!< Config 1 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_2 = 0x42, /*!< Config 2 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_3 = 0x43, /*!< Config 3 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_4 = 0x44, /*!< Config 4 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_5 = 0x45, /*!< Config 5 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_6 = 0x46, /*!< Config 6 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_7 = 0x47, /*!< Config 7 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_8 = 0x48, /*!< Config 8 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_9 = 0x49, /*!< Config 9 refer to table 48 of DOcID025604 Rev 3 */ + LSM6DS0_GYRO_HPCF_10 = 0x4A /*!< Config 10 refer to table 48 of DOcID025604 Rev 3 */ +}LSM6DS0_GYRO_HPCF_t; + +/** + * @brief Gyroscope Axes Enabling + */ +typedef enum{ + LSM6DS0_GYRO_AE_DISABLED = 0x00, /*!< Axes all disabled */ + LSM6DS0_GYRO_AE_X = 0x08, /*!< Only X-axis enabled */ + LSM6DS0_GYRO_AE_Y = 0x10, /*!< Only Y-axis enabled */ + LSM6DS0_GYRO_AE_XY = 0x18, /*!< X & Y axes enabled */ + LSM6DS0_GYRO_AE_Z = 0x20, /*!< Only Z-axis enabled */ + LSM6DS0_GYRO_AE_XZ = 0x28, /*!< X & Z axes enabled */ + LSM6DS0_GYRO_AE_YZ = 0x30, /*!< Y & Z axes enabled */ + LSM6DS0_GYRO_AE_XYZ = 0x38 /*!< All axes enabled */ +}LSM6DS0_GYRO_AE_t; + +/** + * @brief Gyroscope Decimation Mode + */ +typedef enum { + LSM6DS0_GYRO_DEC_DISABLED = 0x00, /*!< NO decimation */ + LSM6DS0_GYRO_DEC_X2 = 0x40, /*!< Decimation update every 2 sample */ + LSM6DS0_GYRO_DEC_X4 = 0x80, /*!< Decimation update every 4 sample */ + LSM6DS0_GYRO_DEC_X8 = 0xC0 /*!< Decimation update every 8 sample */ +}LSM6DS0_GYRO_DEC_t; + +/** + * @brief Gyroscope Sleep Mode + */ +typedef enum { + LSM6DS0_GYRO_SLP_DISABLED = 0x00, /*!< Gyroscope sleep mode disabled */ + LSM6DS0_GYRO_SLP_ENABLED = 0x40 /*!< Gyroscope sleep mode enabled */ +}LSM6DS0_GYRO_SLP_t; +/** + * @brief Gyroscope configuration structure. + */ +typedef struct { + /** + * @brief LSM6DS0 Slave Address + */ + LSM6DS0_SAD_t slaveaddress; + /** + * @brief Gyroscope Output Data Rate + */ + LSM6DS0_GYRO_ODR_t outputdatarate; + /** + * @brief Gyroscope Full Scale + */ + LSM6DS0_GYRO_FS_t fullscale; + /** + * @brief Gyroscope Output Selection + */ + LSM6DS0_GYRO_OUT_SEL_t outputselect; + /** + * @brief Gyroscope Interrupt Selection + */ + LSM6DS0_GYRO_INT_SEL_t irqselect; + /** + * @brief Gyroscope Low Power Mode + */ + LSM6DS0_GYRO_LP_MODE_t lowpowermode; + /** + * @brief Gyroscope High Pass Filter Cutoff Selection + */ + LSM6DS0_GYRO_HPCF_t HPCfrequency; + /** + * @brief Gyroscope Axes Enabling + */ + LSM6DS0_GYRO_AE_t axesenabling; + /** + * @brief Gyroscope Decimation Mode + */ + LSM6DS0_GYRO_DEC_t decimation; + /** + * @brief LSM6DS0 Endianness + */ + LSM6DS0_END_t endianess; + /** + * @brief LSM6DS0 Block Data Update + */ + LSM6DS0_BDU_t blockdataupdate; +} LSM6DS0_GYRO_Config; +/** @} */ +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + + uint8_t lsm6ds0ReadRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + msg_t* message); + void lsm6ds0WriteRegister(I2CDriver *i2cp, uint8_t sad, uint8_t sub, + uint8_t value, msg_t* message); +#ifdef __cplusplus +} +#endif + +#endif /* _LSM6DS0_H_ */ + +/** @} */ diff --git a/os/various/devices_lib/nrf24l01.c b/os/various/devices_lib/nrf24l01.c deleted file mode 100644 index f526fbe..0000000 --- a/os/various/devices_lib/nrf24l01.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file nrf24l01.c - * @brief NRF24L01 interface module code. - * - * @addtogroup nrf24l01 - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#include "nrf24l01.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define ACTIVATE 0x73 -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Gets the status register value. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01GetStatus(SPIDriver *spip) { - uint8_t txbuf = NRF24L01_CMD_NOP; - uint8_t status; - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiUnselect(spip); - return status; -} - -/** - * @brief Reads a generic register value. - * - * @note Cannot be used to set addresses - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] reg register number - * @param[out] pvalue pointer to a data buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01ReadRegister(SPIDriver *spip, uint8_t reg, - uint8_t* pvalue) { - uint8_t txbuf = (NRF24L01_CMD_READ | reg); - uint8_t status = 0xFF; - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiReceive(spip, 1, pvalue); - spiUnselect(spip); - return status; -} - -/** - * @brief Writes a generic register value. - * - * @note Cannot be used to set addresses - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] reg register number - * @param[in] value data value - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteRegister(SPIDriver *spip, uint8_t reg, - uint8_t value) { - - uint8_t txbuf[2] = {(NRF24L01_CMD_WRITE | reg), value}; - uint8_t rxbuf[2] = {0xFF, 0xFF}; - switch (reg) { - - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "lg3d20WriteRegister(), reserved register"); - case NRF24L01_AD_OBSERVE_TX: - case NRF24L01_AD_CD: - case NRF24L01_AD_RX_ADDR_P0: - case NRF24L01_AD_RX_ADDR_P1: - case NRF24L01_AD_RX_ADDR_P2: - case NRF24L01_AD_RX_ADDR_P3: - case NRF24L01_AD_RX_ADDR_P4: - case NRF24L01_AD_RX_ADDR_P5: - case NRF24L01_AD_TX_ADDR: - /* Read only or addresses registers cannot be written, - * the command is ignored. - */ - return 0; - case NRF24L01_AD_CONFIG: - case NRF24L01_AD_EN_AA: - case NRF24L01_AD_EN_RXADDR: - case NRF24L01_AD_SETUP_AW: - case NRF24L01_AD_SETUP_RETR: - case NRF24L01_AD_RF_CH: - case NRF24L01_AD_RF_SETUP: - case NRF24L01_AD_STATUS: - case NRF24L01_AD_RX_PW_P0: - case NRF24L01_AD_RX_PW_P1: - case NRF24L01_AD_RX_PW_P2: - case NRF24L01_AD_RX_PW_P3: - case NRF24L01_AD_RX_PW_P4: - case NRF24L01_AD_RX_PW_P5: - case NRF24L01_AD_FIFO_STATUS: - case NRF24L01_AD_DYNPD: - case NRF24L01_AD_FEATURE: - spiSelect(spip); - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[0]; - } -} - - -/** - * @brief Writes an address. - * - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] reg register number - * @param[in] pvalue pointer to address value - * @param[in] addlen address len - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteAddress(SPIDriver *spip, uint8_t reg, - uint8_t *pvalue, uint8_t addlen) { - - uint8_t txbuf[NRF24L01_MAX_ADD_LENGHT + 1]; - uint8_t rxbuf[NRF24L01_MAX_ADD_LENGHT + 1]; - unsigned i; - - if(addlen > NRF24L01_MAX_ADD_LENGHT) { - chDbgAssert(FALSE, "nrf24l01WriteAddress(), wrong address length"); - return 0; - } - txbuf[0] = (NRF24L01_CMD_WRITE | reg); - rxbuf[0] = 0xFF; - for(i = 1; i <= addlen; i++) { - txbuf[i] = *(pvalue + (i - 1)); - rxbuf[i] = 0xFF; - } - switch (reg) { - - default: - /* Reserved register must not be written, according to the datasheet - * this could permanently damage the device. - */ - chDbgAssert(FALSE, "nrf24l01WriteAddress(), reserved register"); - case NRF24L01_AD_OBSERVE_TX: - case NRF24L01_AD_CD: - case NRF24L01_AD_CONFIG: - case NRF24L01_AD_EN_AA: - case NRF24L01_AD_EN_RXADDR: - case NRF24L01_AD_SETUP_AW: - case NRF24L01_AD_SETUP_RETR: - case NRF24L01_AD_RF_CH: - case NRF24L01_AD_RF_SETUP: - case NRF24L01_AD_STATUS: - case NRF24L01_AD_RX_PW_P0: - case NRF24L01_AD_RX_PW_P1: - case NRF24L01_AD_RX_PW_P2: - case NRF24L01_AD_RX_PW_P3: - case NRF24L01_AD_RX_PW_P4: - case NRF24L01_AD_RX_PW_P5: - case NRF24L01_AD_FIFO_STATUS: - case NRF24L01_AD_DYNPD: - case NRF24L01_AD_FEATURE: - /* Not address registers cannot be written, the command is ignored.*/ - return 0; - case NRF24L01_AD_RX_ADDR_P0: - case NRF24L01_AD_RX_ADDR_P1: - case NRF24L01_AD_RX_ADDR_P2: - case NRF24L01_AD_RX_ADDR_P3: - case NRF24L01_AD_RX_ADDR_P4: - case NRF24L01_AD_RX_ADDR_P5: - case NRF24L01_AD_TX_ADDR: - spiSelect(spip); - spiExchange(spip, addlen + 1, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[0]; - } -} -/** - * @brief Reads RX payload from FIFO. - * - * @note Payload is deleted from FIFO after it is read. Used in RX mode. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] paylen payload length - * @param[in] rxbuf pointer to a buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01GetRxPl(SPIDriver *spip, uint8_t paylen, - uint8_t* rxbuf) { - - uint8_t txbuf = NRF24L01_CMD_R_RX_PAYLOAD; - uint8_t status; - if(paylen > NRF24L01_MAX_PL_LENGHT) { - return 0; - } - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiReceive(spip, paylen, rxbuf); - spiUnselect(spip); - return status; -} - -/** - * @brief Writes TX payload on FIFO. - * - * @note Used in TX mode. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] paylen payload length - * @param[in] rxbuf pointer to a buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteTxPl(SPIDriver *spip, uint8_t paylen, - uint8_t* txbuf) { - - uint8_t cmd = NRF24L01_CMD_W_TX_PAYLOAD; - uint8_t status; - if(paylen > NRF24L01_MAX_PL_LENGHT) { - return 0; - } - spiSelect(spip); - spiExchange(spip, 1, &cmd, &status); - spiSend(spip, paylen, txbuf); - spiUnselect(spip); - return status; -} - -/** - * @brief Flush TX FIFO. - * - * @note Used in TX mode. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01FlushTx(SPIDriver *spip) { - - uint8_t txbuf = NRF24L01_CMD_FLUSH_TX; - uint8_t status; - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiUnselect(spip); - return status; -} - -/** - * @brief Flush RX FIFO. - * - * @note Used in RX mode. Should not be executed during transmission of - acknowledge, that is, acknowledge package will not be completed. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01FlushRx(SPIDriver *spip) { - - uint8_t txbuf = NRF24L01_CMD_FLUSH_RX; - uint8_t status; - spiSelect(spip); - spiExchange(spip, 1, &txbuf, &status); - spiUnselect(spip); - return status; -} - -#if NRF24L01_USE_FEATURE || defined(__DOXYGEN__) -/** - * @brief Activates the following features: - * R_RX_PL_WID -> (In order to enable DPL the EN_DPL bit in the - * FEATURE register must be set) - * W_ACK_PAYLOAD -> (In order to enable PL with ACK the EN_ACK_PAY - * bit in the FEATURE register must be set) - * W_TX_PAYLOAD_NOACK -> (In order to send a PL without ACK - * the EN_DYN_ACK it in the FEATURE register - * must be set) - * - * @note A new ACTIVATE command with the same data deactivates them again. - * This is executable in power down or stand by modes only. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01Activate(SPIDriver *spip) { - - uint8_t txbuf[2] = {NRF24L01_CMD_FLUSH_RX, ACTIVATE}; - uint8_t rxbuf[2]; - spiSelect(spip); - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - return rxbuf[0]; -} - -/** - * @brief Reads RX payload lenght for the top R_RX_PAYLOAD - * in the RX FIFO when Dynamic Payload Length is activated. - * - * @note R_RX_PL_WID must be set and activated. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] ppaylen pointer to the payload length variable - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01ReadRxPlWid(SPIDriver *spip, uint8_t *ppaylen) { - - uint8_t txbuf[2] = {NRF24L01_CMD_R_RX_PL_WID, 0xFF}; - uint8_t rxbuf[2]; - spiSelect(spip); - spiExchange(spip, 2, txbuf, rxbuf); - spiUnselect(spip); - *ppaylen = rxbuf[1]; - return rxbuf[0]; -} - -/** - * @brief Writes TX payload associateted to ACK. - * - * @note Used in RX mode. Write Payload to be transmitted together with - * ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101). - * @note EN_ACK_PAY must be set and activated. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] paylen payload length - * @param[in] rxbuf pointer to a buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteAckPl(SPIDriver *spip, uint8_t ppp, uint8_t paylen, - uint8_t* payload){ - - payload[0] = NRF24L01_CMD_W_ACK_PAYLOAD | NRF24L01_MAX_PPP; - uint8_t status; - if((paylen > NRF24L01_MAX_PL_LENGHT) || (ppp > NRF24L01_MAX_PPP)) { - return 0; - } - spiSelect(spip); - spiExchange(spip, 1, payload, &status); - spiSend(spip, paylen, payload); - spiUnselect(spip); - return status; -} - -/** - * @brief Writes next TX payload without ACK. - * - * @note Used in TX mode. - * @note EN_DYN_ACK must be set and activated. - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * @param[in] paylen payload length - * @param[in] rxbuf pointer to a buffer - * - * @return the status register value - */ -NRF24L01_status_t nrf24l01WriteTxPlNoAck(SPIDriver *spip, uint8_t paylen, - uint8_t* txbuf) { - - txbuf[0] = NRF24L01_CMD_W_TX_PAYLOAD_NOACK; - uint8_t status; - if(paylen > NRF24L01_MAX_PL_LENGHT) { - return 0; - } - spiSelect(spip); - spiExchange(spip, 1, txbuf, &status); - spiSend(spip, paylen, txbuf); - spiUnselect(spip); - return status; -} -#endif /* NRF24L01_USE_FEATURE */ - -/** @} */ diff --git a/os/various/devices_lib/nrf24l01.h b/os/various/devices_lib/nrf24l01.h deleted file mode 100644 index 86ba127..0000000 --- a/os/various/devices_lib/nrf24l01.h +++ /dev/null @@ -1,575 +0,0 @@ -/* - Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi - - This file is part of PLAY for ChibiOS/RT. - - PLAY is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - PLAY is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - Special thanks to Giovanni Di Sirio for teachings, his moral support and - friendship. Note that some or every piece of this file could be part of - the ChibiOS project that is intellectual property of Giovanni Di Sirio. - Please refer to ChibiOS/RT license before use this file. - - For suggestion or Bug report - roccomarco.guglielmi@playembedded.org - */ - -/** - * @file nrf24l01.h - * @brief NRF24L01 Radio frequency module interface module header. - * - * @{ - */ - -#ifndef _NRF24L01_H_ -#define _NRF24L01_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define NRF24L01_MAX_ADD_LENGHT ((uint8_t) 5) -#define NRF24L01_MAX_PL_LENGHT ((uint8_t) 32) -#define NRF24L01_MAX_PPP ((uint8_t) 5) - -/** - * @brief Enables Advanced Features. - */ -#if !defined(NRF24L01_USE_FEATURE) || defined(__DOXYGEN__) -#define NRF24L01_USE_FEATURE TRUE -#endif - -/** - * @name NRF24L01 register names - * @{ - */ -/******************************************************************************/ -/* */ -/* NRF24L01 RF Transceiver */ -/* */ -/******************************************************************************/ -/****************** Bit definition for SPI communication ********************/ -#define NRF24L01_DI ((uint8_t)0xFF) /*!< DI[7:0] Data input */ -#define NRF24L01_DI_0 ((uint8_t)0x01) /*!< bit 0 */ -#define NRF24L01_DI_1 ((uint8_t)0x02) /*!< bit 1 */ -#define NRF24L01_DI_2 ((uint8_t)0x04) /*!< bit 2 */ -#define NRF24L01_DI_3 ((uint8_t)0x08) /*!< bit 3 */ -#define NRF24L01_DI_4 ((uint8_t)0x10) /*!< bit 4 */ -#define NRF24L01_DI_5 ((uint8_t)0x20) /*!< bit 5 */ -#define NRF24L01_DI_6 ((uint8_t)0x40) /*!< bit 6 */ -#define NRF24L01_DI_7 ((uint8_t)0x80) /*!< bit 7 */ - -#define NRF24L01_AD ((uint8_t)0x1F) /*!< AD[4:0] Address Data */ -#define NRF24L01_AD_0 ((uint8_t)0x01) /*!< bit 0 */ -#define NRF24L01_AD_1 ((uint8_t)0x02) /*!< bit 1 */ -#define NRF24L01_AD_2 ((uint8_t)0x04) /*!< bit 2 */ -#define NRF24L01_AD_3 ((uint8_t)0x08) /*!< bit 3 */ -#define NRF24L01_AD_4 ((uint8_t)0x10) /*!< bit 4 */ - -#define NRF24L01_CMD_READ ((uint8_t)0x00) /*!< Read command */ -#define NRF24L01_CMD_WRITE ((uint8_t)0x20) /*!< Write command */ -#define NRF24L01_CMD_R_RX_PAYLOAD ((uint8_t)0x61) /*!< Read RX-payload*/ -#define NRF24L01_CMD_W_TX_PAYLOAD ((uint8_t)0xA0) /*!< Write TX-payload */ -#define NRF24L01_CMD_FLUSH_TX ((uint8_t)0xE1) /*!< Flush TX FIFO */ -#define NRF24L01_CMD_FLUSH_RX ((uint8_t)0xE2) /*!< Flush RX FIFO */ -#define NRF24L01_CMD_REUSE_TX_PL ((uint8_t)0xE3) /*!< Used for a PTX device */ -#define NRF24L01_CMD_ACTIVATE ((uint8_t)0x50) /*!< Activate command */ -#define NRF24L01_CMD_R_RX_PL_WID ((uint8_t)0x60) /*!< Read RX-payload width */ -#define NRF24L01_CMD_W_ACK_PAYLOAD ((uint8_t)0xA8) /*!< Write Payload for ACK */ -#define NRF24L01_CMD_W_TX_PAYLOAD_NOACK ((uint8_t)0xB0) /*!< Disables AUTOACK*/ -#define NRF24L01_CMD_NOP ((uint8_t)0xFF) /*!< No Operation */ - -/****************** Bit definition for Registers Addresses *******************/ -#define NRF24L01_AD_CONFIG ((uint8_t)0x00) /*!< Configuration Register */ -#define NRF24L01_AD_EN_AA ((uint8_t)0x01) /*!< Enable ‘Auto Acknowledgment’ */ -#define NRF24L01_AD_EN_RXADDR ((uint8_t)0x02) /*!< Enabled RX Addresses */ -#define NRF24L01_AD_SETUP_AW ((uint8_t)0x03) /*!< Setup of Address Widths */ -#define NRF24L01_AD_SETUP_RETR ((uint8_t)0x04) /*!< Setup of Automatic Retransmission */ -#define NRF24L01_AD_RF_CH ((uint8_t)0x05) /*!< RF Channel */ -#define NRF24L01_AD_RF_SETUP ((uint8_t)0x06) /*!< RF Setup Register */ -#define NRF24L01_AD_STATUS ((uint8_t)0x07) /*!< Status Register */ -#define NRF24L01_AD_OBSERVE_TX ((uint8_t)0x08) /*!< Transmit observe register */ -#define NRF24L01_AD_CD ((uint8_t)0x09) /*!< CD */ -#define NRF24L01_AD_RX_ADDR_P0 ((uint8_t)0x0A) /*!< Receive address data pipe 0 */ -#define NRF24L01_AD_RX_ADDR_P1 ((uint8_t)0x0B) /*!< Receive address data pipe 1 */ -#define NRF24L01_AD_RX_ADDR_P2 ((uint8_t)0x0C) /*!< Receive address data pipe 2 */ -#define NRF24L01_AD_RX_ADDR_P3 ((uint8_t)0x0D) /*!< Receive address data pipe 3 */ -#define NRF24L01_AD_RX_ADDR_P4 ((uint8_t)0x0E) /*!< Receive address data pipe 4 */ -#define NRF24L01_AD_RX_ADDR_P5 ((uint8_t)0x0F) /*!< Receive address data pipe 5 */ -#define NRF24L01_AD_TX_ADDR ((uint8_t)0x10) /*!< Transmit address */ -#define NRF24L01_AD_RX_PW_P0 ((uint8_t)0x11) /*!< Number of bytes in RX payload in data pipe 0 */ -#define NRF24L01_AD_RX_PW_P1 ((uint8_t)0x12) /*!< Number of bytes in RX payload in data pipe 1 */ -#define NRF24L01_AD_RX_PW_P2 ((uint8_t)0x13) /*!< Number of bytes in RX payload in data pipe 2 */ -#define NRF24L01_AD_RX_PW_P3 ((uint8_t)0x14) /*!< Number of bytes in RX payload in data pipe 3 */ -#define NRF24L01_AD_RX_PW_P4 ((uint8_t)0x15) /*!< Number of bytes in RX payload in data pipe 4 */ -#define NRF24L01_AD_RX_PW_P5 ((uint8_t)0x16) /*!< Number of bytes in RX payload in data pipe 5 */ -#define NRF24L01_AD_FIFO_STATUS ((uint8_t)0x17) /*!< FIFO Status Register */ -#define NRF24L01_AD_DYNPD ((uint8_t)0x1C) /*!< Enable dynamic payload length */ -#define NRF24L01_AD_FEATURE ((uint8_t)0x1D) /*!< Feature Register */ - -/*************** Bit definition for Registers Configuration *****************/ -#define NRF24L01_DI_CONFIG ((uint8_t)0x7F) /*!< CONTROL REGISTER BIT MASK*/ -#define NRF24L01_DI_CONFIG_PRIM_RX ((uint8_t)0x01) /*!< RX/TX control - 1: PRX, 0: PTX */ -#define NRF24L01_DI_CONFIG_PWR_UP ((uint8_t)0x02) /*!< 1: POWER UP, 0:POWER DOWN */ -#define NRF24L01_DI_CONFIG_CRCO ((uint8_t)0x04) /*!< CRC encoding scheme - 1:two bytes, 0:one byte */ -#define NRF24L01_DI_CONFIG_EN_CRC ((uint8_t)0x08) /*!< Enable CRC. Forced high if one of the bits in the EN_AA is high */ -#define NRF24L01_DI_CONFIG_MASK_MAX_RT ((uint8_t)0x10) /*!< Mask interrupt caused by MAX_RT - 1: Interrupt disabled, 0: Interrupt reflected on IRQ pin */ -#define NRF24L01_DI_CONFIG_MASK_TX_DS ((uint8_t)0x20) /*!< Mask interrupt caused by TX_DS - 1: Interrupt disabled, 0: Interrupt reflected on IRQ pin */ -#define NRF24L01_DI_CONFIG_MASK_RX_DR ((uint8_t)0x40) /*!< Mask interrupt caused by RX_DR - 1: Interrupt disabled, 0: Interrupt reflected on IRQ pin */ - -#define NRF24L01_DI_EN_AA ((uint8_t)0x3F) /*!< ENABLE AUTO ACKNOLEDGMENT REGISTER BIT MASK */ -#define NRF24L01_DI_EN_AA_P0 ((uint8_t)0x01) /*!< Enable auto acknowledgement data pipe 0 */ -#define NRF24L01_DI_EN_AA_P1 ((uint8_t)0x02) /*!< Enable auto acknowledgement data pipe 1 */ -#define NRF24L01_DI_EN_AA_P2 ((uint8_t)0x04) /*!< Enable auto acknowledgement data pipe 2 */ -#define NRF24L01_DI_EN_AA_P3 ((uint8_t)0x08) /*!< Enable auto acknowledgement data pipe 3 */ -#define NRF24L01_DI_EN_AA_P4 ((uint8_t)0x10) /*!< Enable auto acknowledgement data pipe 4 */ -#define NRF24L01_DI_EN_AA_P5 ((uint8_t)0x20) /*!< Enable auto acknowledgement data pipe 5 */ - -#define NRF24L01_DI_EN_RXADDR ((uint8_t)0x3F) /*!< ENABLE RX ADDRESSES REGISTER BIT MASK */ -#define NRF24L01_DI_EN_RXADDR_P0 ((uint8_t)0x01) /*!< Enable data pipe 0 */ -#define NRF24L01_DI_EN_RXADDR_P1 ((uint8_t)0x02) /*!< Enable data pipe 1 */ -#define NRF24L01_DI_EN_RXADDR_P2 ((uint8_t)0x04) /*!< Enable data pipe 2 */ -#define NRF24L01_DI_EN_RXADDR_P3 ((uint8_t)0x08) /*!< Enable data pipe 3 */ -#define NRF24L01_DI_EN_RXADDR_P4 ((uint8_t)0x10) /*!< Enable data pipe 4 */ -#define NRF24L01_DI_EN_RXADDR_P5 ((uint8_t)0x20) /*!< Enable data pipe 5 */ - -#define NRF24L01_DI_SETUP_AW ((uint8_t)0x03) /*!< SETUP OF ADDRESSES WIDTHS REGISTER BIT MASK */ -#define NRF24L01_DI_SETUP_AW_0 ((uint8_t)0x01) /*!< Addressed widths bit 0 */ -#define NRF24L01_DI_SETUP_AW_1 ((uint8_t)0x02) /*!< Addressed widths bit 1 */ - -#define NRF24L01_DI_SETUP_RETR ((uint8_t)0xFF) /*!< SETUP OF AUTOMATIC RETRANSMISSION REGISTER BIT MASK */ -#define NRF24L01_DI_SETUP_RETR_ARC_0 ((uint8_t)0x01) /*!< Auto Retransmit Count bit 0 */ -#define NRF24L01_DI_SETUP_RETR_ARC_1 ((uint8_t)0x02) /*!< Auto Retransmit Count bit 1 */ -#define NRF24L01_DI_SETUP_RETR_ARC_2 ((uint8_t)0x04) /*!< Auto Retransmit Count bit 2 */ -#define NRF24L01_DI_SETUP_RETR_ARC_3 ((uint8_t)0x08) /*!< Auto Retransmit Count bit 3 */ -#define NRF24L01_DI_SETUP_RETR_ARD_0 ((uint8_t)0x10) /*!< Auto Retransmit Delay bit 0 */ -#define NRF24L01_DI_SETUP_RETR_ARD_1 ((uint8_t)0x20) /*!< Auto Retransmit Delay bit 1 */ -#define NRF24L01_DI_SETUP_RETR_ARD_2 ((uint8_t)0x40) /*!< Auto Retransmit Delay bit 2 */ -#define NRF24L01_DI_SETUP_RETR_ARD_3 ((uint8_t)0x80) /*!< Auto Retransmit Delay bit 3 */ - - -#define NRF24L01_DI_RF_CH ((uint8_t)0x7F) /*!< RF CHANNEL REGISTER BIT MASK */ -#define NRF24L01_DI_RF_CH_0 ((uint8_t)0x01) /*!< RF channel bit 0 */ -#define NRF24L01_DI_RF_CH_1 ((uint8_t)0x02) /*!< RF channel bit 1 */ -#define NRF24L01_DI_RF_CH_2 ((uint8_t)0x04) /*!< RF channel bit 2 */ -#define NRF24L01_DI_RF_CH_3 ((uint8_t)0x08) /*!< RF channel bit 3 */ -#define NRF24L01_DI_RF_CH_4 ((uint8_t)0x10) /*!< RF channel bit 4 */ -#define NRF24L01_DI_RF_CH_5 ((uint8_t)0x20) /*!< RF channel bit 5 */ -#define NRF24L01_DI_RF_CH_6 ((uint8_t)0x40) /*!< RF channel bit 6 */ - - -#define NRF24L01_DI_RF_SETUP ((uint8_t)0x1F) /*!< RF SETUP REGISTER BIT MASK */ -#define NRF24L01_DI_RF_SETUP_LNA_HCURR ((uint8_t)0x01) /*!< Setup LNA gain */ -#define NRF24L01_DI_RF_SETUP_RF_PWR_0 ((uint8_t)0x02) /*!< RF output power bit 0 */ -#define NRF24L01_DI_RF_SETUP_RF_PWR_1 ((uint8_t)0x04) /*!< RF output power bit 1 */ -#define NRF24L01_DI_RF_SETUP_RF_DR ((uint8_t)0x08) /*!< Air Data rate - 0: 1Mbps, 1: 2Mbps */ -#define NRF24L01_DI_RF_SETUP_PLL_LOCK ((uint8_t)0x10) /*!< Force PLL lock signal */ - -#define NRF24L01_DI_STATUS ((uint8_t)0x7F) /*!< STATUS REGISTER BIT MASK */ -#define NRF24L01_DI_STATUS_TX_FULL ((uint8_t)0x01) /*!< TX FIFO full flag - 0: Available locations, 1: Full */ -#define NRF24L01_DI_STATUS_RX_P_NO_0 ((uint8_t)0x02) /*!< RX payload number bit 0 */ -#define NRF24L01_DI_STATUS_RX_P_NO_1 ((uint8_t)0x04) /*!< RX payload number bit 1 */ -#define NRF24L01_DI_STATUS_RX_P_NO_2 ((uint8_t)0x08) /*!< RX payload number bit 2 */ -#define NRF24L01_DI_STATUS_MAX_RT ((uint8_t)0x10) /*!< Maximum number of TX retransmits interrupt */ -#define NRF24L01_DI_STATUS_TX_DS ((uint8_t)0x20) /*!< Data Sent TX FIFO interrupt */ -#define NRF24L01_DI_STATUS_RX_DR ((uint8_t)0x40) /*!< Data Ready RX FIFO interrupt */ - -#define NRF24L01_DI_OBSERVE_TX ((uint8_t)0xFF) /*!< TRANSMIT OBSERVE REGISTER BIT MASK */ -#define NRF24L01_DI_ARC_CNT_0 ((uint8_t)0x01) /*!< Count retransmitted packets bit 0 */ -#define NRF24L01_DI_ARC_CNT_1 ((uint8_t)0x02) /*!< Count retransmitted packets bit 1 */ -#define NRF24L01_DI_ARC_CNT_2 ((uint8_t)0x04) /*!< Count retransmitted packets bit 2 */ -#define NRF24L01_DI_ARC_CNT_3 ((uint8_t)0x08) /*!< Count retransmitted packets bit 3 */ -#define NRF24L01_DI_PLOS_CNT_0 ((uint8_t)0x10) /*!< Count lost packets bit 0 */ -#define NRF24L01_DI_PLOS_CNT_1 ((uint8_t)0x20) /*!< Count lost packets bit 1 */ -#define NRF24L01_DI_PLOS_CNT_2 ((uint8_t)0x40) /*!< Count lost packets bit 2 */ -#define NRF24L01_DI_PLOS_CNT_3 ((uint8_t)0x80) /*!< Count lost packets bit 3 */ - -#define NRF24L01_DI_CD ((uint8_t)0x01) /*!< REGISTER BIT MASK */ -#define NRF24L01_DI_CARRIER_DETECT ((uint8_t)0x01) /*!< Carrier detect */ - -#define NRF24L01_DI_RX_PW_P0 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 0 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P0_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P0_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P0_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P0_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P0_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P0_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P1 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 1 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P1_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P1_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P1_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P1_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P1_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P1_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P2 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 2 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P2_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P2_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P2_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P2_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P2_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P2_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P3 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 3 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P3_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P3_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P3_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P3_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P3_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P3_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P4 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 4 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P4_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P4_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P4_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P4_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P4_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P4_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_RX_PW_P5 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 5 REGISTER BIT MASK */ -#define NRF24L01_DI_RX_PW_P5_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define NRF24L01_DI_RX_PW_P5_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define NRF24L01_DI_RX_PW_P5_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define NRF24L01_DI_RX_PW_P5_3 ((uint8_t)0x08) /*!< Bit 3 */ -#define NRF24L01_DI_RX_PW_P5_4 ((uint8_t)0x10) /*!< Bit 4 */ -#define NRF24L01_DI_RX_PW_P5_5 ((uint8_t)0x20) /*!< Bit 5 */ - -#define NRF24L01_DI_FIFO_STATUS ((uint8_t)0x73) /*!< FIFO STATUS REGISTER BIT MASK*/ -#define NRF24L01_DI_FIFO_STATUS_RX_EMPTY ((uint8_t)0x01) /*!< RX FIFO empty flag - 0:Data in RX FIFO, 1:RX FIFO empty */ -#define NRF24L01_DI_FIFO_STATUS_RX_FULL ((uint8_t)0x02) /*!< RX FIFO full flag - 0:Available locations in RX FIFO, 1:RX FIFO empty */ -#define NRF24L01_DI_FIFO_STATUS_TX_EMPTY ((uint8_t)0x10) /*!< TX FIFO empty flag - 0:Data in TX FIFO, 1:TX FIFO empty */ -#define NRF24L01_DI_FIFO_STATUS_TX_FULL ((uint8_t)0x20) /*!< TX FIFO full flag - 0:Available locations in TX FIFO, 1:TX FIFO empty */ -#define NRF24L01_DI_FIFO_STATUS_TX_REUSE ((uint8_t)0x40) /*!< Reuse last transmitted data packet if set high */ - -#define NRF24L01_DI_DYNPD ((uint8_t)0x3F) /*!< ENABLE DYNAMIC PAYLOAD LENGHT REGISTER BIT MASK */ -#define NRF24L01_DI_DYNPD_DPL_P0 ((uint8_t)0x01) /*!< Enable dyn. payload length data pipe 0 */ -#define NRF24L01_DI_DYNPD_DPL_P1 ((uint8_t)0x02) /*!< Enable dyn. payload length data pipe 1 */ -#define NRF24L01_DI_DYNPD_DPL_P2 ((uint8_t)0x04) /*!< Enable dyn. payload length data pipe 2 */ -#define NRF24L01_DI_DYNPD_DPL_P3 ((uint8_t)0x08) /*!< Enable dyn. payload length data pipe 3 */ -#define NRF24L01_DI_DYNPD_DPL_P4 ((uint8_t)0x10) /*!< Enable dyn. payload length data pipe 4 */ -#define NRF24L01_DI_DYNPD_DPL_P5 ((uint8_t)0x20) /*!< Enable dyn. payload length data pipe 5 */ - -#define NRF24L01_DI_FEATURE ((uint8_t)0x07) /*!< FEATURE REGISTER REGISTER BIT MASK */ -#define NRF24L01_DI_FEATURE_EN_DYN_ACK ((uint8_t)0x01) /*!< Enables the W_TX_PAYLOAD_NOACK command */ -#define NRF24L01_DI_FEATURE_EN_ACK_PAY ((uint8_t)0x02) /*!< Enables Payload with ACK */ -#define NRF24L01_DI_FEATURE_EN_DPL ((uint8_t)0x04) /*!< Enables Dynamic Payload Length */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !(HAL_USE_SPI) -#error "RF_NRF24L01 requires HAL_USE_SPI." -#endif - -#if !(HAL_USE_EXT) -#error "RF_NRF24L01 requires HAL_USE_EXT." -#endif -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @name RF Transceiver data structures and types - * @{ - */ - -/** - * @brief RF Transceiver RX/TX Address field width - */ -typedef enum { - - NRF24L01_AW_3_bytes = 0x01, /*!< 3 bytes width */ - NRF24L01_AW_4_bytes = 0x02, /*!< 4 bytes width */ - NRF24L01_AW_5_bytes = 0x03 /*!< 5 bytes width */ -} NRF24L01_AW_t; - -/** - * @brief RF Transceiver Auto Retransmit Delay - */ -typedef enum { - - NRF24L01_ARD_250us = 0x00, /*!< Wait 250us */ - NRF24L01_ARD_500us = 0x10, /*!< Wait 500us */ - NRF24L01_ARD_750us = 0x20, /*!< Wait 750us */ - NRF24L01_ARD_1000us = 0x30, /*!< Wait 1000us */ - NRF24L01_ARD_1250us = 0x40, /*!< Wait 1250us */ - NRF24L01_ARD_1500us = 0x50, /*!< Wait 1500us */ - NRF24L01_ARD_1750us = 0x60, /*!< Wait 1750us */ - NRF24L01_ARD_2000us = 0x70, /*!< Wait 2000us */ - NRF24L01_ARD_2250us = 0x80, /*!< Wait 2250us */ - NRF24L01_ARD_2500us = 0x90, /*!< Wait 2500us */ - NRF24L01_ARD_2750us = 0xA0, /*!< Wait 2750us */ - NRF24L01_ARD_3000us = 0xB0, /*!< Wait 3000us */ - NRF24L01_ARD_3250us = 0xC0, /*!< Wait 3250us */ - NRF24L01_ARD_3500us = 0xD0, /*!< Wait 3500us */ - NRF24L01_ARD_3750us = 0xE0, /*!< Wait 3750us */ - NRF24L01_ARD_4000us = 0xF0 /*!< Wait 4000us */ -} NRF24L01_ARD_t; - -/** - * @brief RF Transceiver Auto Retransmit Count - */ -typedef enum { - - NRF24L01_ARC_disabled = 0x00, /*!< Re-Transmit disabled */ - NRF24L01_ARC_1_time = 0x01, /*!< Up to 1 Re-Transmit on fail of AA */ - NRF24L01_ARC_2_times = 0x02, /*!< Up to 2 Re-Transmit on fail of AA */ - NRF24L01_ARC_3_times = 0x03, /*!< Up to 3 Re-Transmit on fail of AA */ - NRF24L01_ARC_4_times = 0x04, /*!< Up to 4 Re-Transmit on fail of AA */ - NRF24L01_ARC_5_times = 0x05, /*!< Up to 5 Re-Transmit on fail of AAs */ - NRF24L01_ARC_6_times = 0x06, /*!< Up to 6 Re-Transmit on fail of AA */ - NRF24L01_ARC_7_times = 0x07, /*!< Up to 7 Re-Transmit on fail of AA */ - NRF24L01_ARC_8_times = 0x08, /*!< Up to 8 Re-Transmit on fail of AA */ - NRF24L01_ARC_9_times = 0x09, /*!< Up to 9 Re-Transmit on fail of AA */ - NRF24L01_ARC_10_times = 0x0A, /*!< Up to 10 Re-Transmit on fail of AA */ - NRF24L01_ARC_11_times = 0x0B, /*!< Up to 11 Re-Transmit on fail of AA */ - NRF24L01_ARC_12_times = 0x0C, /*!< Up to 12 Re-Transmit on fail of AA */ - NRF24L01_ARC_13_times = 0x0D, /*!< Up to 13 Re-Transmit on fail of AA */ - NRF24L01_ARC_14_times = 0x0E, /*!< Up to 14 Re-Transmit on fail of AA */ - NRF24L01_ARC_15_times = 0x0F /*!< Up to 15 Re-Transmit on fail of AA */ -} NRF24L01_ARC_t; - - -/** - * @brief RF Transceiver configuration typedef. - * - * @detail This will select frequency channel beetween 2,4 GHz and 2,525 GHz - * @detail according to formula 2,4GHz + RF_CH[MHz]. This value must be included - * @detail between 0 and 125. - */ -typedef uint8_t NRF24L01_RF_CH_t; - -/** - * @brief RF Transceiver Air Data Rate - */ -typedef enum { - - NRF24L01_ADR_1Mbps = 0x00, /*!< Air data rate 1 Mbps */ - NRF24L01_ADR_2Mbps = 0x08 /*!< Air data rate 2 Mbps */ -} NRF24L01_ADR_t; - -/** - * @brief RF Transceiver Output Power - */ -typedef enum { - - NRF24L01_PWR_0dBm = 0x06, /*!< RF output power 0 dBm */ - NRF24L01_PWR_neg6dBm = 0x04, /*!< RF output power -6 dBm */ - NRF24L01_PWR_neg12dBm = 0x02, /*!< RF output power -12 dBm */ - NRF24L01_PWR_neg18dBm = 0x00 /*!< RF output power -18 dBm */ -} NRF24L01_PWR_t; - -/** - * @brief RF Transceiver Low Noise Amplifier - * - * @details Reduce current consumption in RX mode with 0.8 mA at cost of 1.5dB - * reduction in receiver sensitivity. - */ -typedef enum { - NRF24L01_LNA_enabled = 0x01, /*!< LNA_CURR enabled */ - NRF24L01_LNA_disabled = 0x00 /*!< LNA_CURR disabled */ -} NRF24L01_LNA_t; - -/** - * @brief RF Transceiver Backward Compatibility - * - * @details This type specifies if trasmission must be compatible to receive - * from an nRF2401/nRF2402/nRF24E1/nRF24E. - */ -typedef bool_t NRF24L01_bckwrdcmp_t; - -#if NRF24L01_USE_FEATURE || defined(__doxigen__) -/** - * @brief RF Transceiver Dynamic Payload enabler - * - * @details Enables Dynamic Payload Length - */ -typedef enum { - NRF24L01_DPL_enabled = 0x04, /*!< EN_DPL enabled */ - NRF24L01_DPL_disabled = 0x00 /*!< EN_DPL disabled */ -} NRF24L01_DPL_t; - -/** - * @brief RF Transceiver Dynamic Acknowledge with Payload enabler - * - * @details Enables Payload with ACK - */ -typedef enum { - NRF24L01_ACK_PAY_enabled = 0x02, /*!< EN_ACK_PAY enabled */ - NRF24L01_ACK_PAY_disabled = 0x00 /*!< EN_ACK_PAY disabled */ -} NRF24L01_ACK_PAY_t; - -/** - * @brief RF Transceiver Dynamic Acknowledge enabler - * - * @details Enables the W_TX_PAYLOAD_NOACK command - */ -typedef enum { - NRF24L01_DYN_ACK_enabled = 0x01, /*!< EN_DYN_ACK enabled */ - NRF24L01_DYN_ACK_disabled = 0x00 /*!< EN_DYN_ACK disabled */ -} NRF24L01_DYN_ACK_t; -#endif /* NRF24L01_USE_FEATURE */ - -/** - * @brief RF Transceiver configuration structure. - */ -typedef struct { - - /** - * @brief The chip enable line port. - */ - ioportid_t ceport; - /** - * @brief The chip enable line pad number. - */ - uint16_t cepad; - /** - * @brief The interrupt line port. - */ - ioportid_t irqport; - /** - * @brief The interrupt line pad number. - */ - uint16_t irqpad; - /** - * @brief Pointer to the SPI driver associated to this RF. - */ - SPIDriver *spip; - /** - * @brief Pointer to the SPI configuration . - */ - const SPIConfig *spicfg; - /** - * @brief Pointer to the EXT driver associated to this RF. - */ - EXTDriver *extp; - /** - * @brief EXT configuration. - */ - EXTConfig *extcfg; - /** - * @brief RF Transceiver auto retransmit count. - */ - NRF24L01_ARC_t auto_retr_count; - /** - * @brief RF Transceiver auto retransmit delay. - */ - NRF24L01_ARD_t auto_retr_delay; - /** - * @brief RF Transceiver address width. - */ - NRF24L01_AW_t address_width; - /** - * @brief RF Transceiver channel frequency. - */ - NRF24L01_RF_CH_t channel_freq; - /** - * @brief RF Transceiver air data rate. - */ - NRF24L01_ADR_t data_rate; - /** - * @brief RF Transceiver output power. - */ - NRF24L01_PWR_t out_pwr; - /** - * @brief RF Transceiver Low Noise Amplifier - */ - NRF24L01_LNA_t lna; -#if NRF24L01_USE_FEATURE || defined(__doxigen__) - /** - * @brief RF Transceiver Dynamic Payload enabler - */ - NRF24L01_DPL_t en_dpl; - - /** - * @brief RF Transceiver Dynamic Acknowledge with Payload enabler - */ - NRF24L01_ACK_PAY_t en_ack_pay; - - /** - * @brief RF Transceiver Dynamic Acknowledge enabler - */ - NRF24L01_DYN_ACK_t en_dyn_ack; -#endif /* NRF24L01_USE_FEATURE */ -} NRF24L01_Config; - -/** - * @brief RF Transceiver status register value. - */ -typedef uint8_t NRF24L01_status_t; -/** @} */ -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/** - * @brief Flushes FIFOs and resets all Status flags. - * - * @pre The SPI interface must be initialized and the driver started. - * - * @param[in] spip pointer to the SPI interface - * - * @return the status register value - */ -#define nrf24l01Reset(spip) { \ - \ - nrf24l01WriteRegister(spip, NRF24L01_AD_STATUS, \ - NRF24L01_DI_STATUS_MAX_RT | \ - NRF24L01_DI_STATUS_RX_DR | \ - NRF24L01_DI_STATUS_TX_DS); \ -} - -#ifdef __cplusplus -extern "C" { -#endif -NRF24L01_status_t nrf24l01GetStatus(SPIDriver *spip); -NRF24L01_status_t nrf24l01ReadRegister(SPIDriver *spip, uint8_t reg, - uint8_t* pvalue); -NRF24L01_status_t nrf24l01WriteRegister(SPIDriver *spip, uint8_t reg, - uint8_t value); -NRF24L01_status_t nrf24l01WriteAddress(SPIDriver *spip, uint8_t reg, - uint8_t *pvalue, uint8_t addlen); -NRF24L01_status_t nrf24l01GetRxPl(SPIDriver *spip, uint8_t paylen, - uint8_t* rxbuf); -NRF24L01_status_t nrf24l01WriteTxPl(SPIDriver *spip, uint8_t paylen, - uint8_t* txbuf); -NRF24L01_status_t nrf24l01FlushTx(SPIDriver *spip); -NRF24L01_status_t nrf24l01FlushRx(SPIDriver *spip); -#if NRF24L01_USE_FEATURE || defined(__DOXYGEN__) -NRF24L01_status_t nrf24l01Activate(SPIDriver *spip); -NRF24L01_status_t nrf24l01ReadRxPlWid(SPIDriver *spip, uint8_t* ppaylen); -NRF24L01_status_t nrf24l01WriteAckPl(SPIDriver *spip, uint8_t ppp, uint8_t paylen, - uint8_t* payload); -NRF24L01_status_t nrf24l01WriteTxPlNoAck(SPIDriver *spip, uint8_t paylen, - uint8_t* txbuf); -#endif /* NRF24L01_USE_FEATURE */ -#ifdef __cplusplus -} -#endif - -#endif /* _NRF24L01_H_ */ - -/** @} */ diff --git a/os/various/devices_lib/others/max7219.c b/os/various/devices_lib/others/max7219.c new file mode 100644 index 0000000..0e51167 --- /dev/null +++ b/os/various/devices_lib/others/max7219.c @@ -0,0 +1,94 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file max7219.c + * @brief MAX7219 display driver module code. + * + * @addtogroup max7219 + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "max7219.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Reads a generic register value. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] adr address number + * @param[in] data data value. + */ +void max7219WriteRegister(SPIDriver *spip, uint16_t adr, uint8_t data) { + + switch (adr) { + default: + return; + case MAX7219_AD_DIGIT_0: + case MAX7219_AD_DIGIT_1: + case MAX7219_AD_DIGIT_2: + case MAX7219_AD_DIGIT_3: + case MAX7219_AD_DIGIT_4: + case MAX7219_AD_DIGIT_5: + case MAX7219_AD_DIGIT_6: + case MAX7219_AD_DIGIT_7: + case MAX7219_AD_DECODE_MODE: + case MAX7219_AD_INTENSITY: + case MAX7219_AD_SCAN_LIMIT: + case MAX7219_AD_SHUTDOWN: + case MAX7219_AD_DISPLAY_TEST: + spiSelect(spip); + uint16_t txbuf = {adr | data}; + spiSend(spip, 1, &txbuf); + spiUnselect(spip); + } +} +/** @} */ diff --git a/os/various/devices_lib/others/max7219.h b/os/various/devices_lib/others/max7219.h new file mode 100644 index 0000000..f2bbbdf --- /dev/null +++ b/os/various/devices_lib/others/max7219.h @@ -0,0 +1,187 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file MAX7219.h + * @brief MAX7219 display driver module header. + * + * @{ + */ + +#ifndef _MAX7219_H_ +#define _MAX7219_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name MAX7219 register names + * @{ + */ +/******************************************************************************/ +/* */ +/* MAX7219 display driver */ +/* */ +/******************************************************************************/ +/******************* Bit definition for SPI communication *******************/ +#define MAX7219_DI ((uint16_t)0x00FF) /*!< DI[7:0] Data input */ +#define MAX7219_DI_0 ((uint16_t)0x0001) /*!< bit 0 */ +#define MAX7219_DI_1 ((uint16_t)0x0002) /*!< bit 1 */ +#define MAX7219_DI_2 ((uint16_t)0x0004) /*!< bit 2 */ +#define MAX7219_DI_3 ((uint16_t)0x0008) /*!< bit 3 */ +#define MAX7219_DI_4 ((uint16_t)0x0010) /*!< bit 4 */ +#define MAX7219_DI_5 ((uint16_t)0x0020) /*!< bit 5 */ +#define MAX7219_DI_6 ((uint16_t)0x0040) /*!< bit 6 */ +#define MAX7219_DI_7 ((uint16_t)0x0080) /*!< bit 7 */ + +#define MAX7219_AD ((uint16_t)0x0F00) /*!< AD[11:8] Data input */ +#define MAX7219_AD_0 ((uint16_t)0x0100) /*!< bit 8 */ +#define MAX7219_AD_1 ((uint16_t)0x0200) /*!< bit 9 */ +#define MAX7219_AD_2 ((uint16_t)0x0400) /*!< bit 10 */ +#define MAX7219_AD_3 ((uint16_t)0x0800) /*!< bit 11 */ + +/****************** Bit definition for Registers Addresses *******************/ +#define MAX7219_AD_NOP ((uint16_t)0x0000) /*!< No operation */ +#define MAX7219_AD_DIGIT_0 ((uint16_t)0x0100) /*!< Digit 0 */ +#define MAX7219_AD_DIGIT_1 ((uint16_t)0x0200) /*!< Digit 1 */ +#define MAX7219_AD_DIGIT_2 ((uint16_t)0x0300) /*!< Digit 2 */ +#define MAX7219_AD_DIGIT_3 ((uint16_t)0x0400) /*!< Digit 3 */ +#define MAX7219_AD_DIGIT_4 ((uint16_t)0x0500) /*!< Digit 4 */ +#define MAX7219_AD_DIGIT_5 ((uint16_t)0x0600) /*!< Digit 5 */ +#define MAX7219_AD_DIGIT_6 ((uint16_t)0x0700) /*!< Digit 6 */ +#define MAX7219_AD_DIGIT_7 ((uint16_t)0x0800) /*!< Digit 7 */ +#define MAX7219_AD_DECODE_MODE ((uint16_t)0x0900) /*!< Decode mode */ +#define MAX7219_AD_INTENSITY ((uint16_t)0x0A00) /*!< Intensity */ +#define MAX7219_AD_SCAN_LIMIT ((uint16_t)0x0B00) /*!< Scan limit */ +#define MAX7219_AD_SHUTDOWN ((uint16_t)0x0C00) /*!< Shutdown */ +#define MAX7219_AD_DISPLAY_TEST ((uint16_t)0x0F00) /*!< Display test */ + +/*************** Bit definition for Registers Configuration *****************/ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !HAL_USE_SPI +#error "MAX7219 requires HAL_USE_SPI" +#endif +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @name MAX7219 data structures and types + * @{ + * + */ + +/** + * @brief MAX7219 operation mode + */ +typedef enum { + MAX7219_OM_Shutdown = 0x00, /*!< Shutdown mode */ + MAX7219_OM_Normal = 0x01 /*!< Normal mode */ +} MAX7219_OM_t; + +/** + * @brief MAX7219 decoder mode + */ +typedef enum { + MAX7219_DM_No_decode = 0x00, /*!< No decode */ + MAX7219_DM_CodeB_0 = 0x01, /*!< Code B on Digit 0 */ + MAX7219_DM_CodeB_1 = 0x02, /*!< Code B on Digit 1 */ + MAX7219_DM_CodeB_2 = 0x04, /*!< Code B on Digit 2 */ + MAX7219_DM_CodeB_3 = 0x08, /*!< Code B on Digit 3 */ + MAX7219_DM_CodeB_4 = 0x10, /*!< Code B on Digit 4 */ + MAX7219_DM_CodeB_5 = 0x20, /*!< Code B on Digit 5 */ + MAX7219_DM_CodeB_6 = 0x40, /*!< Code B on Digit 6 */ + MAX7219_DM_CodeB_7 = 0x80 /*!< Code B on Digit 7 */ +} MAX7219_DM_t; + +/** + * @brief MAX7219 intensity mode + */ +typedef enum { + MAX7219_IM_1_32 = 0x00, /*!< 1/32 intensity */ + MAX7219_IM_3_32 = 0x01, /*!< 3/32 intensity */ + MAX7219_IM_5_32 = 0x02, /*!< 5/32 intensity */ + MAX7219_IM_7_32 = 0x03, /*!< 7/32 intensity */ + MAX7219_IM_9_32 = 0x04, /*!< 9/32 intensity */ + MAX7219_IM_11_32 = 0x05, /*!< 11/32 intensity */ + MAX7219_IM_13_32 = 0x06, /*!< 13/32 intensity */ + MAX7219_IM_15_32 = 0x07, /*!< 15/32 intensity */ + MAX7219_IM_17_32 = 0x08, /*!< 17/32 intensity */ + MAX7219_IM_19_32 = 0x09, /*!< 19/32 intensity */ + MAX7219_IM_21_32 = 0x0A, /*!< 21/32 intensity */ + MAX7219_IM_23_32 = 0x0B, /*!< 23/32 intensity */ + MAX7219_IM_25_32 = 0x0C, /*!< 25/32 intensity */ + MAX7219_IM_27_32 = 0x0D, /*!< 27/32 intensity */ + MAX7219_IM_29_32 = 0x0E, /*!< 29/32 intensity */ + MAX7219_IM_31_32 = 0x0F /*!< 31/32 intensity */ +} MAX7219_IM_t; + +/** + * @brief MAX7219 scan line mode + */ +typedef enum { + MAX7219_SL_0 = 0x00, /*!< Scanned digit 0 only */ + MAX7219_SL_1 = 0x01, /*!< Scanned digit 0 & 1 */ + MAX7219_SL_2 = 0x02, /*!< Scanned digit 0 - 2 */ + MAX7219_SL_3 = 0x03, /*!< Scanned digit 0 - 3 */ + MAX7219_SL_4 = 0x04, /*!< Scanned digit 0 - 4 */ + MAX7219_SL_5 = 0x05, /*!< Scanned digit 0 - 5 */ + MAX7219_SL_6 = 0x06, /*!< Scanned digit 0 - 6 */ + MAX7219_SL_7 = 0x07 /*!< Scanned digit 0 - 7 */ +} MAX7219_SL_t; +/** @} */ +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + + void max7219WriteRegister(SPIDriver *spip, uint16_t adr, uint8_t data); +#ifdef __cplusplus +} +#endif +#endif /* _MAX7219_H_ */ + +/** @} */ + diff --git a/os/various/devices_lib/rf/nrf24l01.c b/os/various/devices_lib/rf/nrf24l01.c new file mode 100644 index 0000000..f526fbe --- /dev/null +++ b/os/various/devices_lib/rf/nrf24l01.c @@ -0,0 +1,440 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file nrf24l01.c + * @brief NRF24L01 interface module code. + * + * @addtogroup nrf24l01 + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#include "nrf24l01.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define ACTIVATE 0x73 +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Gets the status register value. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01GetStatus(SPIDriver *spip) { + uint8_t txbuf = NRF24L01_CMD_NOP; + uint8_t status; + spiSelect(spip); + spiExchange(spip, 1, &txbuf, &status); + spiUnselect(spip); + return status; +} + +/** + * @brief Reads a generic register value. + * + * @note Cannot be used to set addresses + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] reg register number + * @param[out] pvalue pointer to a data buffer + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01ReadRegister(SPIDriver *spip, uint8_t reg, + uint8_t* pvalue) { + uint8_t txbuf = (NRF24L01_CMD_READ | reg); + uint8_t status = 0xFF; + spiSelect(spip); + spiExchange(spip, 1, &txbuf, &status); + spiReceive(spip, 1, pvalue); + spiUnselect(spip); + return status; +} + +/** + * @brief Writes a generic register value. + * + * @note Cannot be used to set addresses + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] reg register number + * @param[in] value data value + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01WriteRegister(SPIDriver *spip, uint8_t reg, + uint8_t value) { + + uint8_t txbuf[2] = {(NRF24L01_CMD_WRITE | reg), value}; + uint8_t rxbuf[2] = {0xFF, 0xFF}; + switch (reg) { + + default: + /* Reserved register must not be written, according to the datasheet + * this could permanently damage the device. + */ + chDbgAssert(FALSE, "lg3d20WriteRegister(), reserved register"); + case NRF24L01_AD_OBSERVE_TX: + case NRF24L01_AD_CD: + case NRF24L01_AD_RX_ADDR_P0: + case NRF24L01_AD_RX_ADDR_P1: + case NRF24L01_AD_RX_ADDR_P2: + case NRF24L01_AD_RX_ADDR_P3: + case NRF24L01_AD_RX_ADDR_P4: + case NRF24L01_AD_RX_ADDR_P5: + case NRF24L01_AD_TX_ADDR: + /* Read only or addresses registers cannot be written, + * the command is ignored. + */ + return 0; + case NRF24L01_AD_CONFIG: + case NRF24L01_AD_EN_AA: + case NRF24L01_AD_EN_RXADDR: + case NRF24L01_AD_SETUP_AW: + case NRF24L01_AD_SETUP_RETR: + case NRF24L01_AD_RF_CH: + case NRF24L01_AD_RF_SETUP: + case NRF24L01_AD_STATUS: + case NRF24L01_AD_RX_PW_P0: + case NRF24L01_AD_RX_PW_P1: + case NRF24L01_AD_RX_PW_P2: + case NRF24L01_AD_RX_PW_P3: + case NRF24L01_AD_RX_PW_P4: + case NRF24L01_AD_RX_PW_P5: + case NRF24L01_AD_FIFO_STATUS: + case NRF24L01_AD_DYNPD: + case NRF24L01_AD_FEATURE: + spiSelect(spip); + spiExchange(spip, 2, txbuf, rxbuf); + spiUnselect(spip); + return rxbuf[0]; + } +} + + +/** + * @brief Writes an address. + * + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] reg register number + * @param[in] pvalue pointer to address value + * @param[in] addlen address len + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01WriteAddress(SPIDriver *spip, uint8_t reg, + uint8_t *pvalue, uint8_t addlen) { + + uint8_t txbuf[NRF24L01_MAX_ADD_LENGHT + 1]; + uint8_t rxbuf[NRF24L01_MAX_ADD_LENGHT + 1]; + unsigned i; + + if(addlen > NRF24L01_MAX_ADD_LENGHT) { + chDbgAssert(FALSE, "nrf24l01WriteAddress(), wrong address length"); + return 0; + } + txbuf[0] = (NRF24L01_CMD_WRITE | reg); + rxbuf[0] = 0xFF; + for(i = 1; i <= addlen; i++) { + txbuf[i] = *(pvalue + (i - 1)); + rxbuf[i] = 0xFF; + } + switch (reg) { + + default: + /* Reserved register must not be written, according to the datasheet + * this could permanently damage the device. + */ + chDbgAssert(FALSE, "nrf24l01WriteAddress(), reserved register"); + case NRF24L01_AD_OBSERVE_TX: + case NRF24L01_AD_CD: + case NRF24L01_AD_CONFIG: + case NRF24L01_AD_EN_AA: + case NRF24L01_AD_EN_RXADDR: + case NRF24L01_AD_SETUP_AW: + case NRF24L01_AD_SETUP_RETR: + case NRF24L01_AD_RF_CH: + case NRF24L01_AD_RF_SETUP: + case NRF24L01_AD_STATUS: + case NRF24L01_AD_RX_PW_P0: + case NRF24L01_AD_RX_PW_P1: + case NRF24L01_AD_RX_PW_P2: + case NRF24L01_AD_RX_PW_P3: + case NRF24L01_AD_RX_PW_P4: + case NRF24L01_AD_RX_PW_P5: + case NRF24L01_AD_FIFO_STATUS: + case NRF24L01_AD_DYNPD: + case NRF24L01_AD_FEATURE: + /* Not address registers cannot be written, the command is ignored.*/ + return 0; + case NRF24L01_AD_RX_ADDR_P0: + case NRF24L01_AD_RX_ADDR_P1: + case NRF24L01_AD_RX_ADDR_P2: + case NRF24L01_AD_RX_ADDR_P3: + case NRF24L01_AD_RX_ADDR_P4: + case NRF24L01_AD_RX_ADDR_P5: + case NRF24L01_AD_TX_ADDR: + spiSelect(spip); + spiExchange(spip, addlen + 1, txbuf, rxbuf); + spiUnselect(spip); + return rxbuf[0]; + } +} +/** + * @brief Reads RX payload from FIFO. + * + * @note Payload is deleted from FIFO after it is read. Used in RX mode. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] paylen payload length + * @param[in] rxbuf pointer to a buffer + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01GetRxPl(SPIDriver *spip, uint8_t paylen, + uint8_t* rxbuf) { + + uint8_t txbuf = NRF24L01_CMD_R_RX_PAYLOAD; + uint8_t status; + if(paylen > NRF24L01_MAX_PL_LENGHT) { + return 0; + } + spiSelect(spip); + spiExchange(spip, 1, &txbuf, &status); + spiReceive(spip, paylen, rxbuf); + spiUnselect(spip); + return status; +} + +/** + * @brief Writes TX payload on FIFO. + * + * @note Used in TX mode. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] paylen payload length + * @param[in] rxbuf pointer to a buffer + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01WriteTxPl(SPIDriver *spip, uint8_t paylen, + uint8_t* txbuf) { + + uint8_t cmd = NRF24L01_CMD_W_TX_PAYLOAD; + uint8_t status; + if(paylen > NRF24L01_MAX_PL_LENGHT) { + return 0; + } + spiSelect(spip); + spiExchange(spip, 1, &cmd, &status); + spiSend(spip, paylen, txbuf); + spiUnselect(spip); + return status; +} + +/** + * @brief Flush TX FIFO. + * + * @note Used in TX mode. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01FlushTx(SPIDriver *spip) { + + uint8_t txbuf = NRF24L01_CMD_FLUSH_TX; + uint8_t status; + spiSelect(spip); + spiExchange(spip, 1, &txbuf, &status); + spiUnselect(spip); + return status; +} + +/** + * @brief Flush RX FIFO. + * + * @note Used in RX mode. Should not be executed during transmission of + acknowledge, that is, acknowledge package will not be completed. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01FlushRx(SPIDriver *spip) { + + uint8_t txbuf = NRF24L01_CMD_FLUSH_RX; + uint8_t status; + spiSelect(spip); + spiExchange(spip, 1, &txbuf, &status); + spiUnselect(spip); + return status; +} + +#if NRF24L01_USE_FEATURE || defined(__DOXYGEN__) +/** + * @brief Activates the following features: + * R_RX_PL_WID -> (In order to enable DPL the EN_DPL bit in the + * FEATURE register must be set) + * W_ACK_PAYLOAD -> (In order to enable PL with ACK the EN_ACK_PAY + * bit in the FEATURE register must be set) + * W_TX_PAYLOAD_NOACK -> (In order to send a PL without ACK + * the EN_DYN_ACK it in the FEATURE register + * must be set) + * + * @note A new ACTIVATE command with the same data deactivates them again. + * This is executable in power down or stand by modes only. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01Activate(SPIDriver *spip) { + + uint8_t txbuf[2] = {NRF24L01_CMD_FLUSH_RX, ACTIVATE}; + uint8_t rxbuf[2]; + spiSelect(spip); + spiExchange(spip, 2, txbuf, rxbuf); + spiUnselect(spip); + return rxbuf[0]; +} + +/** + * @brief Reads RX payload lenght for the top R_RX_PAYLOAD + * in the RX FIFO when Dynamic Payload Length is activated. + * + * @note R_RX_PL_WID must be set and activated. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] ppaylen pointer to the payload length variable + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01ReadRxPlWid(SPIDriver *spip, uint8_t *ppaylen) { + + uint8_t txbuf[2] = {NRF24L01_CMD_R_RX_PL_WID, 0xFF}; + uint8_t rxbuf[2]; + spiSelect(spip); + spiExchange(spip, 2, txbuf, rxbuf); + spiUnselect(spip); + *ppaylen = rxbuf[1]; + return rxbuf[0]; +} + +/** + * @brief Writes TX payload associateted to ACK. + * + * @note Used in RX mode. Write Payload to be transmitted together with + * ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101). + * @note EN_ACK_PAY must be set and activated. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] paylen payload length + * @param[in] rxbuf pointer to a buffer + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01WriteAckPl(SPIDriver *spip, uint8_t ppp, uint8_t paylen, + uint8_t* payload){ + + payload[0] = NRF24L01_CMD_W_ACK_PAYLOAD | NRF24L01_MAX_PPP; + uint8_t status; + if((paylen > NRF24L01_MAX_PL_LENGHT) || (ppp > NRF24L01_MAX_PPP)) { + return 0; + } + spiSelect(spip); + spiExchange(spip, 1, payload, &status); + spiSend(spip, paylen, payload); + spiUnselect(spip); + return status; +} + +/** + * @brief Writes next TX payload without ACK. + * + * @note Used in TX mode. + * @note EN_DYN_ACK must be set and activated. + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * @param[in] paylen payload length + * @param[in] rxbuf pointer to a buffer + * + * @return the status register value + */ +NRF24L01_status_t nrf24l01WriteTxPlNoAck(SPIDriver *spip, uint8_t paylen, + uint8_t* txbuf) { + + txbuf[0] = NRF24L01_CMD_W_TX_PAYLOAD_NOACK; + uint8_t status; + if(paylen > NRF24L01_MAX_PL_LENGHT) { + return 0; + } + spiSelect(spip); + spiExchange(spip, 1, txbuf, &status); + spiSend(spip, paylen, txbuf); + spiUnselect(spip); + return status; +} +#endif /* NRF24L01_USE_FEATURE */ + +/** @} */ diff --git a/os/various/devices_lib/rf/nrf24l01.h b/os/various/devices_lib/rf/nrf24l01.h new file mode 100644 index 0000000..86ba127 --- /dev/null +++ b/os/various/devices_lib/rf/nrf24l01.h @@ -0,0 +1,575 @@ +/* + Pretty LAYer for ChibiOS/RT - Copyright (C) 2015 Rocco Marco Guglielmi + + This file is part of PLAY for ChibiOS/RT. + + PLAY is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + PLAY is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + Special thanks to Giovanni Di Sirio for teachings, his moral support and + friendship. Note that some or every piece of this file could be part of + the ChibiOS project that is intellectual property of Giovanni Di Sirio. + Please refer to ChibiOS/RT license before use this file. + + For suggestion or Bug report - roccomarco.guglielmi@playembedded.org + */ + +/** + * @file nrf24l01.h + * @brief NRF24L01 Radio frequency module interface module header. + * + * @{ + */ + +#ifndef _NRF24L01_H_ +#define _NRF24L01_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define NRF24L01_MAX_ADD_LENGHT ((uint8_t) 5) +#define NRF24L01_MAX_PL_LENGHT ((uint8_t) 32) +#define NRF24L01_MAX_PPP ((uint8_t) 5) + +/** + * @brief Enables Advanced Features. + */ +#if !defined(NRF24L01_USE_FEATURE) || defined(__DOXYGEN__) +#define NRF24L01_USE_FEATURE TRUE +#endif + +/** + * @name NRF24L01 register names + * @{ + */ +/******************************************************************************/ +/* */ +/* NRF24L01 RF Transceiver */ +/* */ +/******************************************************************************/ +/****************** Bit definition for SPI communication ********************/ +#define NRF24L01_DI ((uint8_t)0xFF) /*!< DI[7:0] Data input */ +#define NRF24L01_DI_0 ((uint8_t)0x01) /*!< bit 0 */ +#define NRF24L01_DI_1 ((uint8_t)0x02) /*!< bit 1 */ +#define NRF24L01_DI_2 ((uint8_t)0x04) /*!< bit 2 */ +#define NRF24L01_DI_3 ((uint8_t)0x08) /*!< bit 3 */ +#define NRF24L01_DI_4 ((uint8_t)0x10) /*!< bit 4 */ +#define NRF24L01_DI_5 ((uint8_t)0x20) /*!< bit 5 */ +#define NRF24L01_DI_6 ((uint8_t)0x40) /*!< bit 6 */ +#define NRF24L01_DI_7 ((uint8_t)0x80) /*!< bit 7 */ + +#define NRF24L01_AD ((uint8_t)0x1F) /*!< AD[4:0] Address Data */ +#define NRF24L01_AD_0 ((uint8_t)0x01) /*!< bit 0 */ +#define NRF24L01_AD_1 ((uint8_t)0x02) /*!< bit 1 */ +#define NRF24L01_AD_2 ((uint8_t)0x04) /*!< bit 2 */ +#define NRF24L01_AD_3 ((uint8_t)0x08) /*!< bit 3 */ +#define NRF24L01_AD_4 ((uint8_t)0x10) /*!< bit 4 */ + +#define NRF24L01_CMD_READ ((uint8_t)0x00) /*!< Read command */ +#define NRF24L01_CMD_WRITE ((uint8_t)0x20) /*!< Write command */ +#define NRF24L01_CMD_R_RX_PAYLOAD ((uint8_t)0x61) /*!< Read RX-payload*/ +#define NRF24L01_CMD_W_TX_PAYLOAD ((uint8_t)0xA0) /*!< Write TX-payload */ +#define NRF24L01_CMD_FLUSH_TX ((uint8_t)0xE1) /*!< Flush TX FIFO */ +#define NRF24L01_CMD_FLUSH_RX ((uint8_t)0xE2) /*!< Flush RX FIFO */ +#define NRF24L01_CMD_REUSE_TX_PL ((uint8_t)0xE3) /*!< Used for a PTX device */ +#define NRF24L01_CMD_ACTIVATE ((uint8_t)0x50) /*!< Activate command */ +#define NRF24L01_CMD_R_RX_PL_WID ((uint8_t)0x60) /*!< Read RX-payload width */ +#define NRF24L01_CMD_W_ACK_PAYLOAD ((uint8_t)0xA8) /*!< Write Payload for ACK */ +#define NRF24L01_CMD_W_TX_PAYLOAD_NOACK ((uint8_t)0xB0) /*!< Disables AUTOACK*/ +#define NRF24L01_CMD_NOP ((uint8_t)0xFF) /*!< No Operation */ + +/****************** Bit definition for Registers Addresses *******************/ +#define NRF24L01_AD_CONFIG ((uint8_t)0x00) /*!< Configuration Register */ +#define NRF24L01_AD_EN_AA ((uint8_t)0x01) /*!< Enable ‘Auto Acknowledgment’ */ +#define NRF24L01_AD_EN_RXADDR ((uint8_t)0x02) /*!< Enabled RX Addresses */ +#define NRF24L01_AD_SETUP_AW ((uint8_t)0x03) /*!< Setup of Address Widths */ +#define NRF24L01_AD_SETUP_RETR ((uint8_t)0x04) /*!< Setup of Automatic Retransmission */ +#define NRF24L01_AD_RF_CH ((uint8_t)0x05) /*!< RF Channel */ +#define NRF24L01_AD_RF_SETUP ((uint8_t)0x06) /*!< RF Setup Register */ +#define NRF24L01_AD_STATUS ((uint8_t)0x07) /*!< Status Register */ +#define NRF24L01_AD_OBSERVE_TX ((uint8_t)0x08) /*!< Transmit observe register */ +#define NRF24L01_AD_CD ((uint8_t)0x09) /*!< CD */ +#define NRF24L01_AD_RX_ADDR_P0 ((uint8_t)0x0A) /*!< Receive address data pipe 0 */ +#define NRF24L01_AD_RX_ADDR_P1 ((uint8_t)0x0B) /*!< Receive address data pipe 1 */ +#define NRF24L01_AD_RX_ADDR_P2 ((uint8_t)0x0C) /*!< Receive address data pipe 2 */ +#define NRF24L01_AD_RX_ADDR_P3 ((uint8_t)0x0D) /*!< Receive address data pipe 3 */ +#define NRF24L01_AD_RX_ADDR_P4 ((uint8_t)0x0E) /*!< Receive address data pipe 4 */ +#define NRF24L01_AD_RX_ADDR_P5 ((uint8_t)0x0F) /*!< Receive address data pipe 5 */ +#define NRF24L01_AD_TX_ADDR ((uint8_t)0x10) /*!< Transmit address */ +#define NRF24L01_AD_RX_PW_P0 ((uint8_t)0x11) /*!< Number of bytes in RX payload in data pipe 0 */ +#define NRF24L01_AD_RX_PW_P1 ((uint8_t)0x12) /*!< Number of bytes in RX payload in data pipe 1 */ +#define NRF24L01_AD_RX_PW_P2 ((uint8_t)0x13) /*!< Number of bytes in RX payload in data pipe 2 */ +#define NRF24L01_AD_RX_PW_P3 ((uint8_t)0x14) /*!< Number of bytes in RX payload in data pipe 3 */ +#define NRF24L01_AD_RX_PW_P4 ((uint8_t)0x15) /*!< Number of bytes in RX payload in data pipe 4 */ +#define NRF24L01_AD_RX_PW_P5 ((uint8_t)0x16) /*!< Number of bytes in RX payload in data pipe 5 */ +#define NRF24L01_AD_FIFO_STATUS ((uint8_t)0x17) /*!< FIFO Status Register */ +#define NRF24L01_AD_DYNPD ((uint8_t)0x1C) /*!< Enable dynamic payload length */ +#define NRF24L01_AD_FEATURE ((uint8_t)0x1D) /*!< Feature Register */ + +/*************** Bit definition for Registers Configuration *****************/ +#define NRF24L01_DI_CONFIG ((uint8_t)0x7F) /*!< CONTROL REGISTER BIT MASK*/ +#define NRF24L01_DI_CONFIG_PRIM_RX ((uint8_t)0x01) /*!< RX/TX control - 1: PRX, 0: PTX */ +#define NRF24L01_DI_CONFIG_PWR_UP ((uint8_t)0x02) /*!< 1: POWER UP, 0:POWER DOWN */ +#define NRF24L01_DI_CONFIG_CRCO ((uint8_t)0x04) /*!< CRC encoding scheme - 1:two bytes, 0:one byte */ +#define NRF24L01_DI_CONFIG_EN_CRC ((uint8_t)0x08) /*!< Enable CRC. Forced high if one of the bits in the EN_AA is high */ +#define NRF24L01_DI_CONFIG_MASK_MAX_RT ((uint8_t)0x10) /*!< Mask interrupt caused by MAX_RT - 1: Interrupt disabled, 0: Interrupt reflected on IRQ pin */ +#define NRF24L01_DI_CONFIG_MASK_TX_DS ((uint8_t)0x20) /*!< Mask interrupt caused by TX_DS - 1: Interrupt disabled, 0: Interrupt reflected on IRQ pin */ +#define NRF24L01_DI_CONFIG_MASK_RX_DR ((uint8_t)0x40) /*!< Mask interrupt caused by RX_DR - 1: Interrupt disabled, 0: Interrupt reflected on IRQ pin */ + +#define NRF24L01_DI_EN_AA ((uint8_t)0x3F) /*!< ENABLE AUTO ACKNOLEDGMENT REGISTER BIT MASK */ +#define NRF24L01_DI_EN_AA_P0 ((uint8_t)0x01) /*!< Enable auto acknowledgement data pipe 0 */ +#define NRF24L01_DI_EN_AA_P1 ((uint8_t)0x02) /*!< Enable auto acknowledgement data pipe 1 */ +#define NRF24L01_DI_EN_AA_P2 ((uint8_t)0x04) /*!< Enable auto acknowledgement data pipe 2 */ +#define NRF24L01_DI_EN_AA_P3 ((uint8_t)0x08) /*!< Enable auto acknowledgement data pipe 3 */ +#define NRF24L01_DI_EN_AA_P4 ((uint8_t)0x10) /*!< Enable auto acknowledgement data pipe 4 */ +#define NRF24L01_DI_EN_AA_P5 ((uint8_t)0x20) /*!< Enable auto acknowledgement data pipe 5 */ + +#define NRF24L01_DI_EN_RXADDR ((uint8_t)0x3F) /*!< ENABLE RX ADDRESSES REGISTER BIT MASK */ +#define NRF24L01_DI_EN_RXADDR_P0 ((uint8_t)0x01) /*!< Enable data pipe 0 */ +#define NRF24L01_DI_EN_RXADDR_P1 ((uint8_t)0x02) /*!< Enable data pipe 1 */ +#define NRF24L01_DI_EN_RXADDR_P2 ((uint8_t)0x04) /*!< Enable data pipe 2 */ +#define NRF24L01_DI_EN_RXADDR_P3 ((uint8_t)0x08) /*!< Enable data pipe 3 */ +#define NRF24L01_DI_EN_RXADDR_P4 ((uint8_t)0x10) /*!< Enable data pipe 4 */ +#define NRF24L01_DI_EN_RXADDR_P5 ((uint8_t)0x20) /*!< Enable data pipe 5 */ + +#define NRF24L01_DI_SETUP_AW ((uint8_t)0x03) /*!< SETUP OF ADDRESSES WIDTHS REGISTER BIT MASK */ +#define NRF24L01_DI_SETUP_AW_0 ((uint8_t)0x01) /*!< Addressed widths bit 0 */ +#define NRF24L01_DI_SETUP_AW_1 ((uint8_t)0x02) /*!< Addressed widths bit 1 */ + +#define NRF24L01_DI_SETUP_RETR ((uint8_t)0xFF) /*!< SETUP OF AUTOMATIC RETRANSMISSION REGISTER BIT MASK */ +#define NRF24L01_DI_SETUP_RETR_ARC_0 ((uint8_t)0x01) /*!< Auto Retransmit Count bit 0 */ +#define NRF24L01_DI_SETUP_RETR_ARC_1 ((uint8_t)0x02) /*!< Auto Retransmit Count bit 1 */ +#define NRF24L01_DI_SETUP_RETR_ARC_2 ((uint8_t)0x04) /*!< Auto Retransmit Count bit 2 */ +#define NRF24L01_DI_SETUP_RETR_ARC_3 ((uint8_t)0x08) /*!< Auto Retransmit Count bit 3 */ +#define NRF24L01_DI_SETUP_RETR_ARD_0 ((uint8_t)0x10) /*!< Auto Retransmit Delay bit 0 */ +#define NRF24L01_DI_SETUP_RETR_ARD_1 ((uint8_t)0x20) /*!< Auto Retransmit Delay bit 1 */ +#define NRF24L01_DI_SETUP_RETR_ARD_2 ((uint8_t)0x40) /*!< Auto Retransmit Delay bit 2 */ +#define NRF24L01_DI_SETUP_RETR_ARD_3 ((uint8_t)0x80) /*!< Auto Retransmit Delay bit 3 */ + + +#define NRF24L01_DI_RF_CH ((uint8_t)0x7F) /*!< RF CHANNEL REGISTER BIT MASK */ +#define NRF24L01_DI_RF_CH_0 ((uint8_t)0x01) /*!< RF channel bit 0 */ +#define NRF24L01_DI_RF_CH_1 ((uint8_t)0x02) /*!< RF channel bit 1 */ +#define NRF24L01_DI_RF_CH_2 ((uint8_t)0x04) /*!< RF channel bit 2 */ +#define NRF24L01_DI_RF_CH_3 ((uint8_t)0x08) /*!< RF channel bit 3 */ +#define NRF24L01_DI_RF_CH_4 ((uint8_t)0x10) /*!< RF channel bit 4 */ +#define NRF24L01_DI_RF_CH_5 ((uint8_t)0x20) /*!< RF channel bit 5 */ +#define NRF24L01_DI_RF_CH_6 ((uint8_t)0x40) /*!< RF channel bit 6 */ + + +#define NRF24L01_DI_RF_SETUP ((uint8_t)0x1F) /*!< RF SETUP REGISTER BIT MASK */ +#define NRF24L01_DI_RF_SETUP_LNA_HCURR ((uint8_t)0x01) /*!< Setup LNA gain */ +#define NRF24L01_DI_RF_SETUP_RF_PWR_0 ((uint8_t)0x02) /*!< RF output power bit 0 */ +#define NRF24L01_DI_RF_SETUP_RF_PWR_1 ((uint8_t)0x04) /*!< RF output power bit 1 */ +#define NRF24L01_DI_RF_SETUP_RF_DR ((uint8_t)0x08) /*!< Air Data rate - 0: 1Mbps, 1: 2Mbps */ +#define NRF24L01_DI_RF_SETUP_PLL_LOCK ((uint8_t)0x10) /*!< Force PLL lock signal */ + +#define NRF24L01_DI_STATUS ((uint8_t)0x7F) /*!< STATUS REGISTER BIT MASK */ +#define NRF24L01_DI_STATUS_TX_FULL ((uint8_t)0x01) /*!< TX FIFO full flag - 0: Available locations, 1: Full */ +#define NRF24L01_DI_STATUS_RX_P_NO_0 ((uint8_t)0x02) /*!< RX payload number bit 0 */ +#define NRF24L01_DI_STATUS_RX_P_NO_1 ((uint8_t)0x04) /*!< RX payload number bit 1 */ +#define NRF24L01_DI_STATUS_RX_P_NO_2 ((uint8_t)0x08) /*!< RX payload number bit 2 */ +#define NRF24L01_DI_STATUS_MAX_RT ((uint8_t)0x10) /*!< Maximum number of TX retransmits interrupt */ +#define NRF24L01_DI_STATUS_TX_DS ((uint8_t)0x20) /*!< Data Sent TX FIFO interrupt */ +#define NRF24L01_DI_STATUS_RX_DR ((uint8_t)0x40) /*!< Data Ready RX FIFO interrupt */ + +#define NRF24L01_DI_OBSERVE_TX ((uint8_t)0xFF) /*!< TRANSMIT OBSERVE REGISTER BIT MASK */ +#define NRF24L01_DI_ARC_CNT_0 ((uint8_t)0x01) /*!< Count retransmitted packets bit 0 */ +#define NRF24L01_DI_ARC_CNT_1 ((uint8_t)0x02) /*!< Count retransmitted packets bit 1 */ +#define NRF24L01_DI_ARC_CNT_2 ((uint8_t)0x04) /*!< Count retransmitted packets bit 2 */ +#define NRF24L01_DI_ARC_CNT_3 ((uint8_t)0x08) /*!< Count retransmitted packets bit 3 */ +#define NRF24L01_DI_PLOS_CNT_0 ((uint8_t)0x10) /*!< Count lost packets bit 0 */ +#define NRF24L01_DI_PLOS_CNT_1 ((uint8_t)0x20) /*!< Count lost packets bit 1 */ +#define NRF24L01_DI_PLOS_CNT_2 ((uint8_t)0x40) /*!< Count lost packets bit 2 */ +#define NRF24L01_DI_PLOS_CNT_3 ((uint8_t)0x80) /*!< Count lost packets bit 3 */ + +#define NRF24L01_DI_CD ((uint8_t)0x01) /*!< REGISTER BIT MASK */ +#define NRF24L01_DI_CARRIER_DETECT ((uint8_t)0x01) /*!< Carrier detect */ + +#define NRF24L01_DI_RX_PW_P0 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 0 REGISTER BIT MASK */ +#define NRF24L01_DI_RX_PW_P0_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define NRF24L01_DI_RX_PW_P0_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define NRF24L01_DI_RX_PW_P0_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define NRF24L01_DI_RX_PW_P0_3 ((uint8_t)0x08) /*!< Bit 3 */ +#define NRF24L01_DI_RX_PW_P0_4 ((uint8_t)0x10) /*!< Bit 4 */ +#define NRF24L01_DI_RX_PW_P0_5 ((uint8_t)0x20) /*!< Bit 5 */ + +#define NRF24L01_DI_RX_PW_P1 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 1 REGISTER BIT MASK */ +#define NRF24L01_DI_RX_PW_P1_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define NRF24L01_DI_RX_PW_P1_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define NRF24L01_DI_RX_PW_P1_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define NRF24L01_DI_RX_PW_P1_3 ((uint8_t)0x08) /*!< Bit 3 */ +#define NRF24L01_DI_RX_PW_P1_4 ((uint8_t)0x10) /*!< Bit 4 */ +#define NRF24L01_DI_RX_PW_P1_5 ((uint8_t)0x20) /*!< Bit 5 */ + +#define NRF24L01_DI_RX_PW_P2 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 2 REGISTER BIT MASK */ +#define NRF24L01_DI_RX_PW_P2_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define NRF24L01_DI_RX_PW_P2_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define NRF24L01_DI_RX_PW_P2_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define NRF24L01_DI_RX_PW_P2_3 ((uint8_t)0x08) /*!< Bit 3 */ +#define NRF24L01_DI_RX_PW_P2_4 ((uint8_t)0x10) /*!< Bit 4 */ +#define NRF24L01_DI_RX_PW_P2_5 ((uint8_t)0x20) /*!< Bit 5 */ + +#define NRF24L01_DI_RX_PW_P3 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 3 REGISTER BIT MASK */ +#define NRF24L01_DI_RX_PW_P3_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define NRF24L01_DI_RX_PW_P3_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define NRF24L01_DI_RX_PW_P3_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define NRF24L01_DI_RX_PW_P3_3 ((uint8_t)0x08) /*!< Bit 3 */ +#define NRF24L01_DI_RX_PW_P3_4 ((uint8_t)0x10) /*!< Bit 4 */ +#define NRF24L01_DI_RX_PW_P3_5 ((uint8_t)0x20) /*!< Bit 5 */ + +#define NRF24L01_DI_RX_PW_P4 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 4 REGISTER BIT MASK */ +#define NRF24L01_DI_RX_PW_P4_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define NRF24L01_DI_RX_PW_P4_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define NRF24L01_DI_RX_PW_P4_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define NRF24L01_DI_RX_PW_P4_3 ((uint8_t)0x08) /*!< Bit 3 */ +#define NRF24L01_DI_RX_PW_P4_4 ((uint8_t)0x10) /*!< Bit 4 */ +#define NRF24L01_DI_RX_PW_P4_5 ((uint8_t)0x20) /*!< Bit 5 */ + +#define NRF24L01_DI_RX_PW_P5 ((uint8_t)0x3F) /*!< RX PAYLOAD WIDTH FOR PIPE 5 REGISTER BIT MASK */ +#define NRF24L01_DI_RX_PW_P5_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define NRF24L01_DI_RX_PW_P5_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define NRF24L01_DI_RX_PW_P5_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define NRF24L01_DI_RX_PW_P5_3 ((uint8_t)0x08) /*!< Bit 3 */ +#define NRF24L01_DI_RX_PW_P5_4 ((uint8_t)0x10) /*!< Bit 4 */ +#define NRF24L01_DI_RX_PW_P5_5 ((uint8_t)0x20) /*!< Bit 5 */ + +#define NRF24L01_DI_FIFO_STATUS ((uint8_t)0x73) /*!< FIFO STATUS REGISTER BIT MASK*/ +#define NRF24L01_DI_FIFO_STATUS_RX_EMPTY ((uint8_t)0x01) /*!< RX FIFO empty flag - 0:Data in RX FIFO, 1:RX FIFO empty */ +#define NRF24L01_DI_FIFO_STATUS_RX_FULL ((uint8_t)0x02) /*!< RX FIFO full flag - 0:Available locations in RX FIFO, 1:RX FIFO empty */ +#define NRF24L01_DI_FIFO_STATUS_TX_EMPTY ((uint8_t)0x10) /*!< TX FIFO empty flag - 0:Data in TX FIFO, 1:TX FIFO empty */ +#define NRF24L01_DI_FIFO_STATUS_TX_FULL ((uint8_t)0x20) /*!< TX FIFO full flag - 0:Available locations in TX FIFO, 1:TX FIFO empty */ +#define NRF24L01_DI_FIFO_STATUS_TX_REUSE ((uint8_t)0x40) /*!< Reuse last transmitted data packet if set high */ + +#define NRF24L01_DI_DYNPD ((uint8_t)0x3F) /*!< ENABLE DYNAMIC PAYLOAD LENGHT REGISTER BIT MASK */ +#define NRF24L01_DI_DYNPD_DPL_P0 ((uint8_t)0x01) /*!< Enable dyn. payload length data pipe 0 */ +#define NRF24L01_DI_DYNPD_DPL_P1 ((uint8_t)0x02) /*!< Enable dyn. payload length data pipe 1 */ +#define NRF24L01_DI_DYNPD_DPL_P2 ((uint8_t)0x04) /*!< Enable dyn. payload length data pipe 2 */ +#define NRF24L01_DI_DYNPD_DPL_P3 ((uint8_t)0x08) /*!< Enable dyn. payload length data pipe 3 */ +#define NRF24L01_DI_DYNPD_DPL_P4 ((uint8_t)0x10) /*!< Enable dyn. payload length data pipe 4 */ +#define NRF24L01_DI_DYNPD_DPL_P5 ((uint8_t)0x20) /*!< Enable dyn. payload length data pipe 5 */ + +#define NRF24L01_DI_FEATURE ((uint8_t)0x07) /*!< FEATURE REGISTER REGISTER BIT MASK */ +#define NRF24L01_DI_FEATURE_EN_DYN_ACK ((uint8_t)0x01) /*!< Enables the W_TX_PAYLOAD_NOACK command */ +#define NRF24L01_DI_FEATURE_EN_ACK_PAY ((uint8_t)0x02) /*!< Enables Payload with ACK */ +#define NRF24L01_DI_FEATURE_EN_DPL ((uint8_t)0x04) /*!< Enables Dynamic Payload Length */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !(HAL_USE_SPI) +#error "RF_NRF24L01 requires HAL_USE_SPI." +#endif + +#if !(HAL_USE_EXT) +#error "RF_NRF24L01 requires HAL_USE_EXT." +#endif +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @name RF Transceiver data structures and types + * @{ + */ + +/** + * @brief RF Transceiver RX/TX Address field width + */ +typedef enum { + + NRF24L01_AW_3_bytes = 0x01, /*!< 3 bytes width */ + NRF24L01_AW_4_bytes = 0x02, /*!< 4 bytes width */ + NRF24L01_AW_5_bytes = 0x03 /*!< 5 bytes width */ +} NRF24L01_AW_t; + +/** + * @brief RF Transceiver Auto Retransmit Delay + */ +typedef enum { + + NRF24L01_ARD_250us = 0x00, /*!< Wait 250us */ + NRF24L01_ARD_500us = 0x10, /*!< Wait 500us */ + NRF24L01_ARD_750us = 0x20, /*!< Wait 750us */ + NRF24L01_ARD_1000us = 0x30, /*!< Wait 1000us */ + NRF24L01_ARD_1250us = 0x40, /*!< Wait 1250us */ + NRF24L01_ARD_1500us = 0x50, /*!< Wait 1500us */ + NRF24L01_ARD_1750us = 0x60, /*!< Wait 1750us */ + NRF24L01_ARD_2000us = 0x70, /*!< Wait 2000us */ + NRF24L01_ARD_2250us = 0x80, /*!< Wait 2250us */ + NRF24L01_ARD_2500us = 0x90, /*!< Wait 2500us */ + NRF24L01_ARD_2750us = 0xA0, /*!< Wait 2750us */ + NRF24L01_ARD_3000us = 0xB0, /*!< Wait 3000us */ + NRF24L01_ARD_3250us = 0xC0, /*!< Wait 3250us */ + NRF24L01_ARD_3500us = 0xD0, /*!< Wait 3500us */ + NRF24L01_ARD_3750us = 0xE0, /*!< Wait 3750us */ + NRF24L01_ARD_4000us = 0xF0 /*!< Wait 4000us */ +} NRF24L01_ARD_t; + +/** + * @brief RF Transceiver Auto Retransmit Count + */ +typedef enum { + + NRF24L01_ARC_disabled = 0x00, /*!< Re-Transmit disabled */ + NRF24L01_ARC_1_time = 0x01, /*!< Up to 1 Re-Transmit on fail of AA */ + NRF24L01_ARC_2_times = 0x02, /*!< Up to 2 Re-Transmit on fail of AA */ + NRF24L01_ARC_3_times = 0x03, /*!< Up to 3 Re-Transmit on fail of AA */ + NRF24L01_ARC_4_times = 0x04, /*!< Up to 4 Re-Transmit on fail of AA */ + NRF24L01_ARC_5_times = 0x05, /*!< Up to 5 Re-Transmit on fail of AAs */ + NRF24L01_ARC_6_times = 0x06, /*!< Up to 6 Re-Transmit on fail of AA */ + NRF24L01_ARC_7_times = 0x07, /*!< Up to 7 Re-Transmit on fail of AA */ + NRF24L01_ARC_8_times = 0x08, /*!< Up to 8 Re-Transmit on fail of AA */ + NRF24L01_ARC_9_times = 0x09, /*!< Up to 9 Re-Transmit on fail of AA */ + NRF24L01_ARC_10_times = 0x0A, /*!< Up to 10 Re-Transmit on fail of AA */ + NRF24L01_ARC_11_times = 0x0B, /*!< Up to 11 Re-Transmit on fail of AA */ + NRF24L01_ARC_12_times = 0x0C, /*!< Up to 12 Re-Transmit on fail of AA */ + NRF24L01_ARC_13_times = 0x0D, /*!< Up to 13 Re-Transmit on fail of AA */ + NRF24L01_ARC_14_times = 0x0E, /*!< Up to 14 Re-Transmit on fail of AA */ + NRF24L01_ARC_15_times = 0x0F /*!< Up to 15 Re-Transmit on fail of AA */ +} NRF24L01_ARC_t; + + +/** + * @brief RF Transceiver configuration typedef. + * + * @detail This will select frequency channel beetween 2,4 GHz and 2,525 GHz + * @detail according to formula 2,4GHz + RF_CH[MHz]. This value must be included + * @detail between 0 and 125. + */ +typedef uint8_t NRF24L01_RF_CH_t; + +/** + * @brief RF Transceiver Air Data Rate + */ +typedef enum { + + NRF24L01_ADR_1Mbps = 0x00, /*!< Air data rate 1 Mbps */ + NRF24L01_ADR_2Mbps = 0x08 /*!< Air data rate 2 Mbps */ +} NRF24L01_ADR_t; + +/** + * @brief RF Transceiver Output Power + */ +typedef enum { + + NRF24L01_PWR_0dBm = 0x06, /*!< RF output power 0 dBm */ + NRF24L01_PWR_neg6dBm = 0x04, /*!< RF output power -6 dBm */ + NRF24L01_PWR_neg12dBm = 0x02, /*!< RF output power -12 dBm */ + NRF24L01_PWR_neg18dBm = 0x00 /*!< RF output power -18 dBm */ +} NRF24L01_PWR_t; + +/** + * @brief RF Transceiver Low Noise Amplifier + * + * @details Reduce current consumption in RX mode with 0.8 mA at cost of 1.5dB + * reduction in receiver sensitivity. + */ +typedef enum { + NRF24L01_LNA_enabled = 0x01, /*!< LNA_CURR enabled */ + NRF24L01_LNA_disabled = 0x00 /*!< LNA_CURR disabled */ +} NRF24L01_LNA_t; + +/** + * @brief RF Transceiver Backward Compatibility + * + * @details This type specifies if trasmission must be compatible to receive + * from an nRF2401/nRF2402/nRF24E1/nRF24E. + */ +typedef bool_t NRF24L01_bckwrdcmp_t; + +#if NRF24L01_USE_FEATURE || defined(__doxigen__) +/** + * @brief RF Transceiver Dynamic Payload enabler + * + * @details Enables Dynamic Payload Length + */ +typedef enum { + NRF24L01_DPL_enabled = 0x04, /*!< EN_DPL enabled */ + NRF24L01_DPL_disabled = 0x00 /*!< EN_DPL disabled */ +} NRF24L01_DPL_t; + +/** + * @brief RF Transceiver Dynamic Acknowledge with Payload enabler + * + * @details Enables Payload with ACK + */ +typedef enum { + NRF24L01_ACK_PAY_enabled = 0x02, /*!< EN_ACK_PAY enabled */ + NRF24L01_ACK_PAY_disabled = 0x00 /*!< EN_ACK_PAY disabled */ +} NRF24L01_ACK_PAY_t; + +/** + * @brief RF Transceiver Dynamic Acknowledge enabler + * + * @details Enables the W_TX_PAYLOAD_NOACK command + */ +typedef enum { + NRF24L01_DYN_ACK_enabled = 0x01, /*!< EN_DYN_ACK enabled */ + NRF24L01_DYN_ACK_disabled = 0x00 /*!< EN_DYN_ACK disabled */ +} NRF24L01_DYN_ACK_t; +#endif /* NRF24L01_USE_FEATURE */ + +/** + * @brief RF Transceiver configuration structure. + */ +typedef struct { + + /** + * @brief The chip enable line port. + */ + ioportid_t ceport; + /** + * @brief The chip enable line pad number. + */ + uint16_t cepad; + /** + * @brief The interrupt line port. + */ + ioportid_t irqport; + /** + * @brief The interrupt line pad number. + */ + uint16_t irqpad; + /** + * @brief Pointer to the SPI driver associated to this RF. + */ + SPIDriver *spip; + /** + * @brief Pointer to the SPI configuration . + */ + const SPIConfig *spicfg; + /** + * @brief Pointer to the EXT driver associated to this RF. + */ + EXTDriver *extp; + /** + * @brief EXT configuration. + */ + EXTConfig *extcfg; + /** + * @brief RF Transceiver auto retransmit count. + */ + NRF24L01_ARC_t auto_retr_count; + /** + * @brief RF Transceiver auto retransmit delay. + */ + NRF24L01_ARD_t auto_retr_delay; + /** + * @brief RF Transceiver address width. + */ + NRF24L01_AW_t address_width; + /** + * @brief RF Transceiver channel frequency. + */ + NRF24L01_RF_CH_t channel_freq; + /** + * @brief RF Transceiver air data rate. + */ + NRF24L01_ADR_t data_rate; + /** + * @brief RF Transceiver output power. + */ + NRF24L01_PWR_t out_pwr; + /** + * @brief RF Transceiver Low Noise Amplifier + */ + NRF24L01_LNA_t lna; +#if NRF24L01_USE_FEATURE || defined(__doxigen__) + /** + * @brief RF Transceiver Dynamic Payload enabler + */ + NRF24L01_DPL_t en_dpl; + + /** + * @brief RF Transceiver Dynamic Acknowledge with Payload enabler + */ + NRF24L01_ACK_PAY_t en_ack_pay; + + /** + * @brief RF Transceiver Dynamic Acknowledge enabler + */ + NRF24L01_DYN_ACK_t en_dyn_ack; +#endif /* NRF24L01_USE_FEATURE */ +} NRF24L01_Config; + +/** + * @brief RF Transceiver status register value. + */ +typedef uint8_t NRF24L01_status_t; +/** @} */ +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/** + * @brief Flushes FIFOs and resets all Status flags. + * + * @pre The SPI interface must be initialized and the driver started. + * + * @param[in] spip pointer to the SPI interface + * + * @return the status register value + */ +#define nrf24l01Reset(spip) { \ + \ + nrf24l01WriteRegister(spip, NRF24L01_AD_STATUS, \ + NRF24L01_DI_STATUS_MAX_RT | \ + NRF24L01_DI_STATUS_RX_DR | \ + NRF24L01_DI_STATUS_TX_DS); \ +} + +#ifdef __cplusplus +extern "C" { +#endif +NRF24L01_status_t nrf24l01GetStatus(SPIDriver *spip); +NRF24L01_status_t nrf24l01ReadRegister(SPIDriver *spip, uint8_t reg, + uint8_t* pvalue); +NRF24L01_status_t nrf24l01WriteRegister(SPIDriver *spip, uint8_t reg, + uint8_t value); +NRF24L01_status_t nrf24l01WriteAddress(SPIDriver *spip, uint8_t reg, + uint8_t *pvalue, uint8_t addlen); +NRF24L01_status_t nrf24l01GetRxPl(SPIDriver *spip, uint8_t paylen, + uint8_t* rxbuf); +NRF24L01_status_t nrf24l01WriteTxPl(SPIDriver *spip, uint8_t paylen, + uint8_t* txbuf); +NRF24L01_status_t nrf24l01FlushTx(SPIDriver *spip); +NRF24L01_status_t nrf24l01FlushRx(SPIDriver *spip); +#if NRF24L01_USE_FEATURE || defined(__DOXYGEN__) +NRF24L01_status_t nrf24l01Activate(SPIDriver *spip); +NRF24L01_status_t nrf24l01ReadRxPlWid(SPIDriver *spip, uint8_t* ppaylen); +NRF24L01_status_t nrf24l01WriteAckPl(SPIDriver *spip, uint8_t ppp, uint8_t paylen, + uint8_t* payload); +NRF24L01_status_t nrf24l01WriteTxPlNoAck(SPIDriver *spip, uint8_t paylen, + uint8_t* txbuf); +#endif /* NRF24L01_USE_FEATURE */ +#ifdef __cplusplus +} +#endif + +#endif /* _NRF24L01_H_ */ + +/** @} */ -- cgit v1.2.3