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-rw-r--r--os/hal/hal.mk3
-rw-r--r--os/hal/include/eicu.h187
-rw-r--r--os/hal/include/hal_community.h1
-rw-r--r--os/hal/ports/STM32/LLD/eicu_lld.c964
-rw-r--r--os/hal/ports/STM32/LLD/eicu_lld.h452
-rw-r--r--os/hal/ports/STM32/STM32F4xx/platform.mk4
-rw-r--r--os/hal/src/eicu.c149
-rw-r--r--os/hal/src/hal_community.c4
-rw-r--r--testhal/STM32/STM32F0xx/onewire/.project8
-rw-r--r--testhal/STM32/STM32F1xx/onewire/.project8
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/.cproject6
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/.project8
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_SDRAM/.cproject6
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_SDRAM/.project8
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_SRAM/.cproject6
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_SRAM/.project8
-rw-r--r--testhal/STM32/STM32F4xx/onewire/.project8
17 files changed, 1795 insertions, 35 deletions
diff --git a/os/hal/hal.mk b/os/hal/hal.mk
index 38868b6..2508c90 100644
--- a/os/hal/hal.mk
+++ b/os/hal/hal.mk
@@ -2,6 +2,7 @@ include ${CHIBIOS}/os/hal/hal.mk
HALSRC += ${CHIBIOS}/community/os/hal/src/hal_community.c \
${CHIBIOS}/community/os/hal/src/nand.c \
- ${CHIBIOS}/community/os/hal/src/onewire.c
+ ${CHIBIOS}/community/os/hal/src/onewire.c \
+ ${CHIBIOS}/community/os/hal/src/eicu.c
HALINC += ${CHIBIOS}/community/os/hal/include
diff --git a/os/hal/include/eicu.h b/os/hal/include/eicu.h
new file mode 100644
index 0000000..a4ab30f
--- /dev/null
+++ b/os/hal/include/eicu.h
@@ -0,0 +1,187 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Rewritten by Emil Fresk (1/5 - 2014) for extended input capture
+ functionality. And fix for spurious callbacks in the interrupt handler.
+*/
+
+#ifndef _EICU_H_
+#define _EICU_H_
+
+#if HAL_USE_EICU || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ EICU_UNINIT, /* Not initialized. */
+ EICU_STOP, /* Stopped. */
+ EICU_READY, /* Ready. */
+ EICU_WAITING, /* Waiting for first edge. */
+ EICU_ACTIVE, /* Active cycle phase. */
+ EICU_IDLE /* Idle cycle phase. */
+} eicustate_t;
+
+/**
+ * @brief Channel state machine possible states.
+ */
+typedef enum {
+ EICU_CH_IDLE, /* Idle cycle phase. */
+ EICU_CH_ACTIVE /* Active cycle phase. */
+} eicuchannelstate_t;
+
+/**
+ * @brief EICU channel selection definition
+ */
+typedef enum {
+ EICU_CHANNEL_1,
+ EICU_CHANNEL_2,
+ EICU_CHANNEL_3,
+ EICU_CHANNEL_4,
+ EICU_CHANNEL_ENUM_END
+} eicuchannel_t;
+
+/**
+ * @brief Type of a structure representing an EICU driver.
+ */
+typedef struct EICUDriver EICUDriver;
+
+/**
+ * @brief EICU notification callback type.
+ *
+ * @param[in] eicup Pointer to a EICUDriver object
+ * @param[in] channel EICU channel that fired the interrupt
+ * @param[in] width Pulse width
+ * @param[in] period Pulse period
+ */
+typedef void (*eicucallback_t)(EICUDriver *eicup, eicuchannel_t channel,
+ uint32_t width, uint32_t period);
+
+#include "eicu_lld.h"
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Enables the extended input capture.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @iclass
+ */
+#define eicuEnableI(eicup) eicu_lld_enable(eicup)
+
+/**
+ * @brief Disables the extended input capture.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @iclass
+ */
+#define eicuDisableI(eicup) eicu_lld_disable(eicup)
+/** @} */
+
+/**
+ * @name Low Level driver helper macros
+ * @{
+ */
+/**
+ * @brief Common ISR code, EICU PWM width event.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ * @param[in] channel The timer channel that fired the interrupt.
+ *
+ * @notapi
+ */
+static inline void _eicu_isr_invoke_pwm_width_cb(EICUDriver *eicup,
+ eicuchannel_t channel) {
+ if (eicup->state != EICU_WAITING) {
+ eicup->state = EICU_IDLE;
+ eicup->config->iccfgp[channel]->capture_cb(eicup, channel, 0, 0);
+ }
+}
+
+/**
+ * @brief Common ISR code, EICU PWM period event.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ * @param[in] channel The timer channel that fired the interrupt.
+ *
+ * @notapi
+ */
+static inline void _eicu_isr_invoke_pwm_period_cb(EICUDriver *eicup,
+ eicuchannel_t channel) {
+ eicustate_t previous_state = eicup->state;
+ eicup->state = EICU_ACTIVE;
+ if (previous_state != EICU_WAITING)
+ eicup->channel[channel].config->capture_cb(eicup, channel, 0, 0);
+}
+
+/**
+ * @brief Common ISR code, EICU timer overflow event.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @notapi
+ */
+#define _eicu_isr_invoke_overflow_cb(icup) do { \
+ (eicup)->config->overflow_cb(eicup, 0, 0, 0); \
+} while (0)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void eicuInit(void);
+ void eicuObjectInit(EICUDriver *eicup);
+ void eicuStart(EICUDriver *eicup, const EICUConfig *config);
+ void eicuStop(EICUDriver *eicup);
+ void eicuEnable(EICUDriver *eicup);
+ void eicuDisable(EICUDriver *eicup);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EICU */
+
+#endif /* _EICU_H_ */
+
+/** @} */
diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h
index bf645ae..6a60491 100644
--- a/os/hal/include/hal_community.h
+++ b/os/hal/include/hal_community.h
@@ -34,6 +34,7 @@
/* Normal drivers.*/
#include "nand.h"
+#include "eicu.h"
/* Complex drivers.*/
#include "onewire.h"
diff --git a/os/hal/ports/STM32/LLD/eicu_lld.c b/os/hal/ports/STM32/LLD/eicu_lld.c
new file mode 100644
index 0000000..0245128
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/eicu_lld.c
@@ -0,0 +1,964 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Fabio Utzig and
+ Xo Wang.
+*/
+/*
+ Rewritten by Emil Fresk (1/5 - 2014) for extended input capture
+ functionality. And fix for spurious callbacks in the interrupt handler.
+*/
+
+/*
+ * Hardware Abstraction Layer for Extended Input Capture Unit
+ */
+#include "hal.h"
+
+#if HAL_USE_EICU || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+/**
+ * @brief Inverts the polarity for the given channel.
+ *
+ * @param[in] eicup Pointer to the EICUDriver object.
+ * @param[in] channel The timer channel to invert.
+ *
+ * @notapi
+ */
+#define eicu_lld_invert_polarity(eicup, channel) \
+ (eicup)->tim->CCER ^= ((uint16_t)(STM32_TIM_CCER_CC1P << ((channel) * 4)))
+
+/**
+ * @brief Returns the compare value of the latest cycle.
+ *
+ * @param[in] chp Pointer to channel structure that fired the interrupt.
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+#define eicu_lld_get_compare(chp) (*((chp)->ccrp) + 1)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+/**
+ * @brief EICUD1 driver identifier.
+ * @note The driver EICUD1 allocates the complex timer TIM1 when enabled.
+ */
+#if STM32_EICU_USE_TIM1 && !defined(__DOXYGEN__)
+EICUDriver EICUD1;
+#endif
+
+/**
+ * @brief EICUD2 driver identifier.
+ * @note The driver EICUD2 allocates the timer TIM2 when enabled.
+ */
+#if STM32_EICU_USE_TIM2 && !defined(__DOXYGEN__)
+EICUDriver EICUD2;
+#endif
+
+/**
+ * @brief EICUD3 driver identifier.
+ * @note The driver EICUD3 allocates the timer TIM3 when enabled.
+ */
+#if STM32_EICU_USE_TIM3 && !defined(__DOXYGEN__)
+EICUDriver EICUD3;
+#endif
+
+/**
+ * @brief EICUD4 driver identifier.
+ * @note The driver EICUD4 allocates the timer TIM4 when enabled.
+ */
+#if STM32_EICU_USE_TIM4 && !defined(__DOXYGEN__)
+EICUDriver EICUD4;
+#endif
+
+/**
+ * @brief EICUD5 driver identifier.
+ * @note The driver EICUD5 allocates the timer TIM5 when enabled.
+ */
+#if STM32_EICU_USE_TIM5 && !defined(__DOXYGEN__)
+EICUDriver EICUD5;
+#endif
+
+/**
+ * @brief EICUD8 driver identifier.
+ * @note The driver EICUD8 allocates the timer TIM8 when enabled.
+ */
+#if STM32_EICU_USE_TIM8 && !defined(__DOXYGEN__)
+EICUDriver EICUD8;
+#endif
+
+/**
+ * @brief EICUD9 driver identifier.
+ * @note The driver EICUD9 allocates the timer TIM9 when enabled.
+ */
+#if STM32_EICU_USE_TIM9 && !defined(__DOXYGEN__)
+EICUDriver EICUD9;
+#endif
+
+/**
+ * @brief EICUD12 driver identifier.
+ * @note The driver EICUD12 allocates the timer TIM12 when enabled.
+ */
+#if STM32_EICU_USE_TIM12 && !defined(__DOXYGEN__)
+EICUDriver EICUD12;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+/**
+ * @brief Returns both pulse width and period.
+ * @details The time is defined as number of ticks.
+ *
+ * @param[in] eicup Pointer to the EICUDriver object.
+ * @param[in] channel The timer channel that fired the interrupt.
+ * @param[in] compare Content of the CCR register.
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+static eicuresult_t get_time_both(EICUDriver *eicup,
+ eicuchannel_t channel,
+ eicucnt_t compare) {
+
+ const EICUChannel *chp = &eicup->channel[channel];
+ eicuresult_t ret;
+
+ /* Note! there is no overflow check because it handles under the hood of
+ unsigned subtraction math.*/
+
+ /* 16-bit timer */
+ if (0xFFFF == eicup->tim->ARR) {
+ uint16_t cmp = compare;
+ uint16_t la = chp->last_active;
+ uint16_t li = chp->last_idle;
+ uint16_t w = li - la;
+ uint16_t p = cmp - la;
+ ret.width = w;
+ ret.period = p;
+ }
+ /* 32-bit timer */
+ else if (0xFFFFFFFF == eicup->tim->ARR) {
+ ret.width = chp->last_idle - chp->last_active;
+ ret.period = compare - chp->last_active;
+ return ret;
+ }
+ /* error trap */
+ else {
+ osalSysHalt("ARR register must be loaded with maximum possible value");
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Returns pulse width.
+ * @details The time is defined as number of ticks.
+ *
+ * @param[in] eicup Pointer to the EICUDriver object.
+ * @param[in] channel The timer channel that fired the interrupt.
+ * @param[in] compare Content of the CCR register.
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+static eicucnt_t get_time_width(EICUDriver *eicup,
+ eicuchannel_t channel,
+ eicucnt_t compare) {
+
+ const EICUChannel *chp = &eicup->channel[channel];
+
+ /* Note! there is no overflow check because it handles under the hood of
+ unsigned subtraction math.*/
+
+ /* 16-bit timer */
+ if (0xFFFF == eicup->tim->ARR) {
+ uint16_t cmp = compare;
+ uint16_t la = chp->last_active;
+ uint16_t ret = cmp - la;
+ return ret;
+ }
+ /* 32-bit timer */
+ else if (0xFFFFFFFF == eicup->tim->ARR) {
+ return compare - chp->last_active;
+ }
+ /* error trap */
+ else {
+ osalSysHalt("ARR register must be loaded with maximum possible value");
+ return 0;
+ }
+}
+
+/**
+ * @brief Returns both pulse period.
+ * @details The time is defined as number of ticks.
+ *
+ * @param[in] eicup Pointer to the EICUDriver object.
+ * @param[in] channel The timer channel that fired the interrupt.
+ * @param[in] compare Content of the CCR register.
+ * @return The number of ticks.
+ *
+ * @notapi
+ */
+static eicucnt_t get_time_period(EICUDriver *eicup,
+ eicuchannel_t channel,
+ eicucnt_t compare) {
+
+ const EICUChannel *chp = &eicup->channel[channel];
+
+ /* Note! there is no overflow check because it handles under the hood of
+ unsigned subtraction math.*/
+
+ /* 16-bit timer */
+ if (0xFFFF == eicup->tim->ARR) {
+ uint16_t cmp = compare;
+ uint16_t li = chp->last_idle;
+ uint16_t ret = cmp - li;
+ return ret;
+ }
+ /* 32-bit timer */
+ else if (0xFFFFFFFF == eicup->tim->ARR) {
+ return compare - chp->last_idle;
+ }
+ /* error trap */
+ else {
+ osalSysHalt("ARR register must be loaded with maximum possible value");
+ return 0;
+ }
+}
+
+/**
+ * @brief EICU width or (width + period) event.
+ * @note Needs special care since it needs to invert the
+ * correct polarity bit to detect pulses.
+ * @note Assumes that the polarity is not changed by some
+ * external user. It must only be changed using the HAL.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ * @param[in] channel The timer channel that fired the interrupt.
+ *
+ * @notapi
+ */
+static void isr_invoke_pulse_cb(EICUDriver *eicup, eicuchannel_t channel) {
+ EICUChannel *chp = &eicup->channel[channel];
+ eicucnt_t compare = eicu_lld_get_compare(chp);
+
+ if (EICU_CH_ACTIVE == chp->state) {
+ chp->state = EICU_CH_IDLE;
+ eicu_lld_invert_polarity(eicup, channel);
+ if (EICU_INPUT_PULSE == chp->config->mode) {
+ uint32_t width = get_time_width(eicup, channel, compare);
+ chp->config->capture_cb(eicup, channel, width, 0);
+ }
+ chp->last_idle = compare;
+ }
+ else {
+ chp->state = EICU_CH_ACTIVE;
+ eicu_lld_invert_polarity(eicup, channel);
+ if (EICU_INPUT_BOTH == chp->config->mode) {
+ eicuresult_t both = get_time_both(eicup, channel, compare);
+ chp->config->capture_cb(eicup, channel, both.width, both.period);
+ }
+ chp->last_active = compare;
+ }
+}
+
+/**
+ * @brief EICU Edge detect event.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ * @param[in] channel The timer channel that fired the interrupt.
+ *
+ * @notapi
+ */
+static void isr_invoke_edge_cb(EICUDriver *eicup, eicuchannel_t channel) {
+ EICUChannel *chp = &eicup->channel[channel];
+ eicucnt_t compare = eicu_lld_get_compare(chp);
+ uint32_t period = get_time_period(eicup, channel, compare);
+
+ chp->config->capture_cb(eicup, channel, 0, period);
+ chp->last_idle = compare;
+}
+
+/**
+ * @brief Common EICU detect call.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ * @param[in] channel The timer channel that fired the interrupt.
+ *
+ * @notapi
+ */
+static void eicu_isr_invoke_cb(EICUDriver *eicup, eicuchannel_t channel) {
+
+ if (EICU_INPUT_EDGE == eicup->channel[channel].config->mode)
+ isr_invoke_edge_cb(eicup, channel);
+ else /* EICU_INPUT_PULSE || EICU_INPUT_BOTH */
+ isr_invoke_pulse_cb(eicup, channel);
+}
+
+/**
+ * @brief Shared IRQ handler.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ */
+static void eicu_lld_serve_interrupt(EICUDriver *eicup) {
+ uint16_t sr;
+ sr = eicup->tim->SR;
+
+ /* Pick out the interrupts we are interested in by using
+ the interrupt enable bits as mask */
+ sr &= (eicup->tim->DIER & STM32_TIM_DIER_IRQ_MASK);
+
+ /* Clear interrupts */
+ eicup->tim->SR = ~sr;
+
+ if ((sr & STM32_TIM_SR_CC1IF) != 0)
+ eicu_isr_invoke_cb(eicup, EICU_CHANNEL_1);
+ if ((sr & STM32_TIM_SR_CC2IF) != 0)
+ eicu_isr_invoke_cb(eicup, EICU_CHANNEL_2);
+ if ((sr & STM32_TIM_SR_CC3IF) != 0)
+ eicu_isr_invoke_cb(eicup, EICU_CHANNEL_3);
+ if ((sr & STM32_TIM_SR_CC4IF) != 0)
+ eicu_isr_invoke_cb(eicup, EICU_CHANNEL_4);
+}
+
+/**
+ * @brief Starts every channel.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ */
+static void start_channels(EICUDriver *eicup) {
+
+ /* Set each input channel that is used as: a normal input capture channel,
+ link the corresponding CCR register and set polarity. */
+
+ /* Input capture channel 1 */
+ if (eicup->config->iccfgp[0] != NULL) {
+ /* Normal capture input input */
+ eicup->tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(1);
+
+ /* Link CCR register */
+ eicup->channel[0].ccrp = &eicup->tim->CCR[0];
+
+ /* Set input polarity */
+ if (eicup->config->iccfgp[0]->alvl == EICU_INPUT_ACTIVE_HIGH)
+ eicup->tim->CCER |= STM32_TIM_CCER_CC1E;
+ else
+ eicup->tim->CCER |= STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P;
+ }
+
+ /* Input capture channel 2 */
+ if (eicup->config->iccfgp[1] != NULL) {
+ /* Normal capture input input */
+ eicup->tim->CCMR1 |= STM32_TIM_CCMR1_CC2S(1);
+
+ /* Link CCR register */
+ eicup->channel[1].ccrp = &eicup->tim->CCR[1];
+
+ /* Set input polarity */
+ if (eicup->config->iccfgp[1]->alvl == EICU_INPUT_ACTIVE_HIGH)
+ eicup->tim->CCER |= STM32_TIM_CCER_CC2E;
+ else
+ eicup->tim->CCER |= STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P;
+ }
+
+ /* Input capture channel 3 (not for TIM 9 and 12) */
+ if (eicup->config->iccfgp[2] != NULL) {
+ /* Normal capture input input */
+ eicup->tim->CCMR2 |= STM32_TIM_CCMR2_CC3S(1);
+
+ /* Link CCR register */
+ eicup->channel[2].ccrp = &eicup->tim->CCR[2];
+
+ /* Set input polarity */
+ if (eicup->config->iccfgp[2]->alvl == EICU_INPUT_ACTIVE_HIGH)
+ eicup->tim->CCER |= STM32_TIM_CCER_CC3E;
+ else
+ eicup->tim->CCER |= STM32_TIM_CCER_CC3E | STM32_TIM_CCER_CC3P;
+ }
+
+ /* Input capture channel 4 (not for TIM 9 and 12) */
+ if (eicup->config->iccfgp[3] != NULL) {
+ /* Normal capture input input */
+ eicup->tim->CCMR2 |= STM32_TIM_CCMR2_CC4S(1);
+
+ /* Link CCR register */
+ eicup->channel[3].ccrp = &eicup->tim->CCR[3];
+
+ /* Set input polarity */
+ if (eicup->config->iccfgp[3]->alvl == EICU_INPUT_ACTIVE_HIGH)
+ eicup->tim->CCER |= STM32_TIM_CCER_CC4E;
+ else
+ eicup->tim->CCER |= STM32_TIM_CCER_CC4E | STM32_TIM_CCER_CC4P;
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if STM32_EICU_USE_TIM1
+#if !defined(STM32_TIM1_UP_HANDLER)
+#error "STM32_TIM1_UP_HANDLER not defined"
+#endif
+/**
+ * @brief TIM1 compare interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(STM32_TIM1_CC_HANDLER)
+#error "STM32_TIM1_CC_HANDLER not defined"
+#endif
+/**
+ * @brief TIM1 compare interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM1 */
+
+#if STM32_EICU_USE_TIM2
+
+#if !defined(STM32_TIM2_HANDLER)
+#error "STM32_TIM2_HANDLER not defined"
+#endif
+/**
+ * @brief TIM2 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM2 */
+
+#if STM32_EICU_USE_TIM3
+#if !defined(STM32_TIM3_HANDLER)
+#error "STM32_TIM3_HANDLER not defined"
+#endif
+/**
+ * @brief TIM3 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM3 */
+
+#if STM32_EICU_USE_TIM4
+#if !defined(STM32_TIM4_HANDLER)
+#error "STM32_TIM4_HANDLER not defined"
+#endif
+/**
+ * @brief TIM4 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM4 */
+
+#if STM32_EICU_USE_TIM5
+#if !defined(STM32_TIM5_HANDLER)
+#error "STM32_TIM5_HANDLER not defined"
+#endif
+/**
+ * @brief TIM5 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM5 */
+
+#if STM32_EICU_USE_TIM8
+#if !defined(STM32_TIM8_UP_HANDLER)
+#error "STM32_TIM8_UP_HANDLER not defined"
+#endif
+/**
+ * @brief TIM8 compare interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD8);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(STM32_TIM8_CC_HANDLER)
+#error "STM32_TIM8_CC_HANDLER not defined"
+#endif
+/**
+ * @brief TIM8 compare interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD8);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM8 */
+
+#if STM32_EICU_USE_TIM9
+#if !defined(STM32_TIM9_HANDLER)
+#error "STM32_TIM9_HANDLER not defined"
+#endif
+/**
+ * @brief TIM9 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM9 */
+
+#if STM32_EICU_USE_TIM12
+#if !defined(STM32_TIM12_HANDLER)
+#error "STM32_TIM12_HANDLER not defined"
+#endif
+/**
+ * @brief TIM12 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD12);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM12 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level EICU driver initialization.
+ *
+ * @notapi
+ */
+void eicu_lld_init(void) {
+#if STM32_EICU_USE_TIM1
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD1);
+ EICUD1.tim = STM32_TIM1;
+#endif
+
+#if STM32_EICU_USE_TIM2
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD2);
+ EICUD2.tim = STM32_TIM2;
+#endif
+
+#if STM32_EICU_USE_TIM3
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD3);
+ EICUD3.tim = STM32_TIM3;
+#endif
+
+#if STM32_EICU_USE_TIM4
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD4);
+ EICUD4.tim = STM32_TIM4;
+#endif
+
+#if STM32_EICU_USE_TIM5
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD5);
+ EICUD5.tim = STM32_TIM5;
+#endif
+
+#if STM32_EICU_USE_TIM8
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD8);
+ EICUD8.tim = STM32_TIM8;
+#endif
+
+#if STM32_EICU_USE_TIM9
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD9);
+ EICUD9.tim = STM32_TIM9;
+#endif
+
+#if STM32_EICU_USE_TIM12
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD12);
+ EICUD12.tim = STM32_TIM12;
+#endif
+}
+
+/**
+ * @brief Configures and activates the EICU peripheral.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @notapi
+ */
+void eicu_lld_start(EICUDriver *eicup) {
+ uint32_t psc;
+ size_t ch;
+
+ osalDbgAssert((eicup->config->iccfgp[0] != NULL) ||
+ (eicup->config->iccfgp[1] != NULL) ||
+ (eicup->config->iccfgp[2] != NULL) ||
+ (eicup->config->iccfgp[3] != NULL),
+ "invalid input configuration");
+
+ if (eicup->state == EICU_STOP) {
+ /* Clock activation and timer reset.*/
+#if STM32_EICU_USE_TIM1
+ if (&EICUD1 == eicup) {
+ rccEnableTIM1(FALSE);
+ rccResetTIM1();
+ nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY);
+#if defined(STM32_TIM1CLK)
+ eicup->clock = STM32_TIM1CLK;
+#else
+ eicup->clock = STM32_TIMCLK2;
+#endif
+ }
+#endif
+#if STM32_EICU_USE_TIM2
+ if (&EICUD2 == eicup) {
+ rccEnableTIM2(FALSE);
+ rccResetTIM2();
+ nvicEnableVector(STM32_TIM2_NUMBER, STM32_EICU_TIM2_IRQ_PRIORITY);
+ eicup->clock = STM32_TIMCLK1;
+ }
+#endif
+#if STM32_EICU_USE_TIM3
+ if (&EICUD3 == eicup) {
+ rccEnableTIM3(FALSE);
+ rccResetTIM3();
+ nvicEnableVector(STM32_TIM3_NUMBER, STM32_EICU_TIM3_IRQ_PRIORITY);
+ eicup->clock = STM32_TIMCLK1;
+ }
+#endif
+#if STM32_EICU_USE_TIM4
+ if (&EICUD4 == eicup) {
+ rccEnableTIM4(FALSE);
+ rccResetTIM4();
+ nvicEnableVector(STM32_TIM4_NUMBER, STM32_EICU_TIM4_IRQ_PRIORITY);
+ eicup->clock = STM32_TIMCLK1;
+ }
+#endif
+#if STM32_EICU_USE_TIM5
+ if (&EICUD5 == eicup) {
+ rccEnableTIM5(FALSE);
+ rccResetTIM5();
+ nvicEnableVector(STM32_TIM5_NUMBER, STM32_EICU_TIM5_IRQ_PRIORITY);
+ eicup->clock = STM32_TIMCLK1;
+ }
+#endif
+#if STM32_EICU_USE_TIM8
+ if (&EICUD8 == eicup) {
+ rccEnableTIM8(FALSE);
+ rccResetTIM8();
+ nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY);
+ nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY);
+#if defined(STM32_TIM8CLK)
+ eicup->clock = STM32_TIM8CLK;
+#else
+ eicup->clock = STM32_TIMCLK2;
+#endif
+ }
+#endif
+#if STM32_EICU_USE_TIM9
+ if (&EICUD9 == eicup) {
+ rccEnableTIM9(FALSE);
+ rccResetTIM9();
+ nvicEnableVector(STM32_TIM9_NUMBER, STM32_EICU_TIM9_IRQ_PRIORITY);
+ eicup->clock = STM32_TIMCLK2;
+ }
+#endif
+#if STM32_EICU_USE_TIM12
+ if (&EICUD12 == eicup) {
+ rccEnableTIM12(FALSE);
+ rccResetTIM12();
+ nvicEnableVector(STM32_TIM12_NUMBER, STM32_EICU_TIM12_IRQ_PRIORITY);
+ eicup->clock = STM32_TIMCLK1;
+ }
+#endif
+ }
+ else {
+ /* Driver re-configuration scenario, it must be stopped first.*/
+ eicup->tim->CR1 = 0; /* Timer disabled. */
+ eicup->tim->DIER = eicup->config->dier &/* DMA-related DIER settings. */
+ ~STM32_TIM_DIER_IRQ_MASK;
+ eicup->tim->SR = 0; /* Clear eventual pending IRQs. */
+ eicup->tim->CCR[0] = 0; /* Comparator 1 disabled. */
+ eicup->tim->CCR[1] = 0; /* Comparator 2 disabled. */
+ eicup->tim->CNT = 0; /* Counter reset to zero. */
+ }
+
+ /* Timer configuration.*/
+ psc = (eicup->clock / eicup->config->frequency) - 1;
+ chDbgAssert((psc <= 0xFFFF) &&
+ ((psc + 1) * eicup->config->frequency) == eicup->clock,
+ "invalid frequency");
+ eicup->tim->PSC = (uint16_t)psc;
+ eicup->tim->ARR = (eicucnt_t)-1;
+
+ /* Reset registers */
+ eicup->tim->SMCR = 0;
+ eicup->tim->CCMR1 = 0;
+
+ /* clean channel structures and set pointers to channel configs */
+ for (ch=0; ch<EICU_CHANNEL_ENUM_END; ch++) {
+ eicup->channel[ch].last_active = 0;
+ eicup->channel[ch].last_idle = 0;
+ eicup->channel[ch].config = eicup->config->iccfgp[ch];
+ eicup->channel[ch].state = EICU_CH_IDLE;
+ }
+
+#if STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12
+ if (eicup != &EICUD9)
+ eicup->tim->CCMR2 = 0;
+#elif !STM32_EICU_USE_TIM9 && STM32_EICU_USE_TIM12
+ if (eicup != &EICUD12)
+ eicup->tim->CCMR2 = 0;
+#elif STM32_EICU_USE_TIM9 && STM32_EICU_USE_TIM12
+ if ((eicup != &EICUD9) && (eicup != &EICUD12))
+ eicup->tim->CCMR2 = 0;
+#else
+ eicup->tim->CCMR2 = 0;
+#endif
+
+ /* TIM9 and TIM12 have only 2 channels.*/
+#if STM32_EICU_USE_TIM9
+ if (eicup == &EICUD9) {
+ osalDbgCheck((eicup->config->iccfgp[2] == NULL) &&
+ (eicup->config->iccfgp[3] == NULL));
+ }
+#endif
+#if STM32_EICU_USE_TIM12
+ if (eicup == &EICUD12) {
+ osalDbgCheck((eicup->config->iccfgp[2] == NULL) &&
+ (eicup->config->iccfgp[3] == NULL));
+ }
+#endif
+
+ start_channels(eicup);
+}
+
+/**
+ * @brief Deactivates the EICU peripheral.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @notapi
+ */
+void eicu_lld_stop(EICUDriver *eicup) {
+
+ if (eicup->state == EICU_READY) {
+
+ /* Clock deactivation.*/
+ eicup->tim->CR1 = 0; /* Timer disabled. */
+ eicup->tim->DIER = 0; /* All IRQs disabled. */
+ eicup->tim->SR = 0; /* Clear eventual pending IRQs. */
+
+#if STM32_EICU_USE_TIM1
+ if (&EICUD1 == eicup) {
+ nvicDisableVector(STM32_TIM1_UP_NUMBER);
+ nvicDisableVector(STM32_TIM1_CC_NUMBER);
+ rccDisableTIM1(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM2
+ if (&EICUD2 == eicup) {
+ nvicDisableVector(STM32_TIM2_NUMBER);
+ rccDisableTIM2(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM3
+ if (&EICUD3 == eicup) {
+ nvicDisableVector(STM32_TIM3_NUMBER);
+ rccDisableTIM3(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM4
+ if (&EICUD4 == eicup) {
+ nvicDisableVector(STM32_TIM4_NUMBER);
+ rccDisableTIM4(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM5
+ if (&EICUD5 == eicup) {
+ nvicDisableVector(STM32_TIM5_NUMBER);
+ rccDisableTIM5(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM8
+ if (&EICUD8 == eicup) {
+ nvicDisableVector(STM32_TIM8_UP_NUMBER);
+ nvicDisableVector(STM32_TIM8_CC_NUMBER);
+ rccDisableTIM8(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM9
+ if (&EICUD9 == eicup) {
+ nvicDisableVector(STM32_TIM9_NUMBER);
+ rccDisableTIM9(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM12
+ if (&EICUD12 == eicup) {
+ nvicDisableVector(STM32_TIM12_NUMBER);
+ rccDisableTIM12(FALSE);
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Enables the EICU.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @notapi
+ */
+void eicu_lld_enable(EICUDriver *eicup) {
+
+ eicup->tim->EGR = STM32_TIM_EGR_UG;
+ eicup->tim->SR = 0; /* Clear pending IRQs (if any). */
+
+ if ((eicup->config->iccfgp[EICU_CHANNEL_1] != NULL) &&
+ (eicup->config->iccfgp[EICU_CHANNEL_1]->capture_cb != NULL))
+ eicup->tim->DIER |= STM32_TIM_DIER_CC1IE;
+ if ((eicup->config->iccfgp[EICU_CHANNEL_2] != NULL) &&
+ (eicup->config->iccfgp[EICU_CHANNEL_2]->capture_cb != NULL))
+ eicup->tim->DIER |= STM32_TIM_DIER_CC2IE;
+ if ((eicup->config->iccfgp[EICU_CHANNEL_3] != NULL) &&
+ (eicup->config->iccfgp[EICU_CHANNEL_3]->capture_cb != NULL))
+ eicup->tim->DIER |= STM32_TIM_DIER_CC3IE;
+ if ((eicup->config->iccfgp[EICU_CHANNEL_4] != NULL) &&
+ (eicup->config->iccfgp[EICU_CHANNEL_4]->capture_cb != NULL))
+ eicup->tim->DIER |= STM32_TIM_DIER_CC4IE;
+
+ eicup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
+}
+
+/**
+ * @brief Disables the EICU.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @notapi
+ */
+void eicu_lld_disable(EICUDriver *eicup) {
+ eicup->tim->CR1 = 0; /* Initially stopped. */
+ eicup->tim->SR = 0; /* Clear pending IRQs (if any). */
+
+ /* All interrupts disabled.*/
+ eicup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
+}
+
+#endif /* HAL_USE_EICU */
diff --git a/os/hal/ports/STM32/LLD/eicu_lld.h b/os/hal/ports/STM32/LLD/eicu_lld.h
new file mode 100644
index 0000000..4f10893
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/eicu_lld.h
@@ -0,0 +1,452 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Rewritten by Emil Fresk (1/5 - 2014) for extended input capture
+ functionality. And fix for spurious callbacks in the interrupt handler.
+*/
+
+#ifndef __EICU_LLD_H
+#define __EICU_LLD_H
+
+#include "stm32_tim.h"
+
+#if HAL_USE_EICU || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EICUD1 driver enable switch.
+ * @details If set to @p TRUE the support for EICUD1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_EICU_USE_TIM1) || defined(__DOXYGEN__)
+#define STM32_EICU_USE_TIM1 FALSE
+#endif
+
+/**
+ * @brief EICUD2 driver enable switch.
+ * @details If set to @p TRUE the support for EICUD2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_EICU_USE_TIM2) || defined(__DOXYGEN__)
+#define STM32_EICU_USE_TIM2 FALSE
+#endif
+
+/**
+ * @brief EICUD3 driver enable switch.
+ * @details If set to @p TRUE the support for EICUD3 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_EICU_USE_TIM3) || defined(__DOXYGEN__)
+#define STM32_EICU_USE_TIM3 FALSE
+#endif
+
+/**
+ * @brief EICUD4 driver enable switch.
+ * @details If set to @p TRUE the support for EICUD4 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_EICU_USE_TIM4) || defined(__DOXYGEN__)
+#define STM32_EICU_USE_TIM4 FALSE
+#endif
+
+/**
+ * @brief EICUD5 driver enable switch.
+ * @details If set to @p TRUE the support for EICUD5 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_EICU_USE_TIM5) || defined(__DOXYGEN__)
+#define STM32_EICU_USE_TIM5 FALSE
+#endif
+
+/**
+ * @brief EICUD8 driver enable switch.
+ * @details If set to @p TRUE the support for EICUD8 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_EICU_USE_TIM8) || defined(__DOXYGEN__)
+#define STM32_EICU_USE_TIM8 FALSE
+#endif
+
+/**
+ * @brief EICUD9 driver enable switch.
+ * @details If set to @p TRUE the support for EICUD9 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_EICU_USE_TIM9) || defined(__DOXYGEN__)
+#define STM32_EICU_USE_TIM9 FALSE
+#endif
+
+/**
+ * @brief EICUD12 driver enable switch.
+ * @details If set to @p TRUE the support for EICUD12 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_EICU_USE_TIM12) || defined(__DOXYGEN__)
+#define STM32_EICU_USE_TIM12 FALSE
+#endif
+
+/**
+ * @brief EICUD1 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM1_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD2 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM2_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD3 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM3_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD4 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM4_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD5 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM5_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD8 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM8_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD9 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM9_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD12 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM12_IRQ_PRIORITY 7
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_EICU_USE_TIM1 && !STM32_HAS_TIM1
+#error "TIM1 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM2 && !STM32_HAS_TIM2
+#error "TIM2 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM3 && !STM32_HAS_TIM3
+#error "TIM3 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM4 && !STM32_HAS_TIM4
+#error "TIM4 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM5 && !STM32_HAS_TIM5
+#error "TIM5 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM8 && !STM32_HAS_TIM8
+#error "TIM8 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM9 && !STM32_HAS_TIM9
+#error "TIM9 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM12 && !STM32_HAS_TIM12
+#error "TIM12 not present in the selected device"
+#endif
+
+#if !STM32_EICU_USE_TIM1 && !STM32_EICU_USE_TIM2 && \
+ !STM32_EICU_USE_TIM3 && !STM32_EICU_USE_TIM4 && \
+ !STM32_EICU_USE_TIM5 && !STM32_EICU_USE_TIM8 && \
+ !STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12
+#error "EICU driver activated but no TIM peripheral assigned"
+#endif
+
+#if STM32_EICU_USE_TIM1 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM1"
+#endif
+
+#if STM32_EICU_USE_TIM2 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM2"
+#endif
+
+#if STM32_EICU_USE_TIM3 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM3"
+#endif
+
+#if STM32_EICU_USE_TIM4 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM4"
+#endif
+
+#if STM32_EICU_USE_TIM5 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM5"
+#endif
+
+#if STM32_EICU_USE_TIM8 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM8_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM8"
+#endif
+
+#if STM32_EICU_USE_TIM9 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM9_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM9"
+#endif
+
+#if STM32_EICU_USE_TIM12 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM12_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM12"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+/**
+ * @brief Active level selector.
+ */
+typedef enum {
+ EICU_INPUT_ACTIVE_HIGH, /**< Trigger on rising edge. */
+ EICU_INPUT_ACTIVE_LOW, /**< Trigger on falling edge. */
+} eicuactivelevel_t;
+
+/**
+ * @brief Input type selector.
+ */
+typedef enum {
+ /**
+ * @brief Measures time between consequent edges.
+ * @details Callback fires on every _active_ edge.
+ */
+ EICU_INPUT_EDGE,
+ /**
+ * @brief Measures pulse width.
+ * @details Callback fires on _idle_ edge of pulse.
+ */
+ EICU_INPUT_PULSE,
+ /**
+ * @brief Measures both period and width..
+ * @details Callback fires on _active_ edge of pulse.
+ */
+ EICU_INPUT_BOTH
+} eicucapturemode_t;
+
+/**
+ * @brief EICU frequency type.
+ */
+typedef uint32_t eicufreq_t;
+
+/**
+ * @brief EICU counter type.
+ */
+typedef uint32_t eicucnt_t;
+
+/**
+ * @brief EICU captured width and (or) period.
+ */
+typedef struct {
+ /**
+ * @brief Pulse width.
+ */
+ eicucnt_t width;
+ /**
+ * @brief Pulse period.
+ */
+ eicucnt_t period;
+} eicuresult_t;
+
+/**
+ * @brief EICU Capture Channel Config structure definition.
+ */
+typedef struct {
+ /**
+ * @brief Specifies the active level of the input signal.
+ */
+ eicuactivelevel_t alvl;
+ /**
+ * @brief Specifies the channel capture mode.
+ */
+ eicucapturemode_t mode;
+ /**
+ * @brief Capture event callback. Used for PWM width, pulse width and
+ * pulse period capture event.
+ */
+ eicucallback_t capture_cb;
+} EICUChannelConfig;
+
+/**
+ * @brief EICU Capture Channel structure definition.
+ */
+typedef struct {
+ /**
+ * @brief Channel state for the internal state machine.
+ */
+ eicuchannelstate_t state;
+ /**
+ * @brief Cached value for pulse width calculation.
+ */
+ eicucnt_t last_active;
+ /**
+ * @brief Cached value for period calculation.
+ */
+ eicucnt_t last_idle;
+ /**
+ * @brief Pointer to Input Capture channel configuration.
+ */
+ const EICUChannelConfig *config;
+ /**
+ * @brief CCR register pointer for faster access.
+ */
+ volatile uint32_t *ccrp;
+} EICUChannel;
+
+/**
+ * @brief EICU Config structure definition.
+ */
+typedef struct {
+ /**
+ * @brief Specifies the Timer clock in Hz.
+ */
+ eicufreq_t frequency;
+ /**
+ * @brief Pointer to each Input Capture channel configuration.
+ * @note A NULL parameter indicates the channel as unused.
+ * @note In PWM mode, only Channel 1 OR Channel 2 may be used.
+ */
+ const EICUChannelConfig *iccfgp[EICU_CHANNEL_ENUM_END];
+ /**
+ * @brief TIM DIER register initialization data.
+ */
+ uint32_t dier;
+} EICUConfig;
+
+/**
+ * @brief EICU Driver structure definition
+ */
+struct EICUDriver {
+ /**
+ * @brief STM32 timer peripheral for Input Capture.
+ */
+ stm32_tim_t *tim;
+ /**
+ * @brief Driver state for the internal state machine.
+ */
+ eicustate_t state;
+ /**
+ * @brief Channels' data structures.
+ */
+ EICUChannel channel[EICU_CHANNEL_ENUM_END];
+ /**
+ * @brief Timer base clock.
+ */
+ uint32_t clock;
+ /**
+ * @brief Pointer to configuration for the driver.
+ */
+ const EICUConfig *config;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+#if STM32_EICU_USE_TIM1 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD1;
+#endif
+
+#if STM32_EICU_USE_TIM2 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD2;
+#endif
+
+#if STM32_EICU_USE_TIM3 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD3;
+#endif
+
+#if STM32_EICU_USE_TIM4 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD4;
+#endif
+
+#if STM32_EICU_USE_TIM5 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD5;
+#endif
+
+#if STM32_EICU_USE_TIM8 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD8;
+#endif
+
+#if STM32_EICU_USE_TIM9 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD9;
+#endif
+
+#if STM32_EICU_USE_TIM12 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD12;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void eicu_lld_init(void);
+ void eicu_lld_start(EICUDriver *eicup);
+ void eicu_lld_stop(EICUDriver *eicup);
+ void eicu_lld_enable(EICUDriver *eicup);
+ void eicu_lld_disable(EICUDriver *eicup);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EICU */
+
+#endif /* __EICU_LLD_H */
diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk
index 2ede59d..cd25988 100644
--- a/os/hal/ports/STM32/STM32F4xx/platform.mk
+++ b/os/hal/ports/STM32/STM32F4xx/platform.mk
@@ -3,6 +3,8 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/platform.mk
PLATFORMSRC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c \
+ ${CHIBIOS}/community/os/hal/ports/STM32/LLD/eicu_lld.c \
${CHIBIOS}/community/os/hal/src/fsmc_sdram.c
-PLATFORMINC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1
+PLATFORMINC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1 \
+ ${CHIBIOS}/community/os/hal/ports/STM32/LLD
diff --git a/os/hal/src/eicu.c b/os/hal/src/eicu.c
new file mode 100644
index 0000000..6088b8f
--- /dev/null
+++ b/os/hal/src/eicu.c
@@ -0,0 +1,149 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Rewritten by Emil Fresk (1/5 - 2014) for extended input capture
+ functionality. And fix for spurious callbacks in the interrupt handler.
+*/
+
+/*
+ * Hardware Abstraction Layer for Extended Input Capture Unit
+ */
+#include "hal.h"
+
+#if HAL_USE_EICU || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief EICU Driver initialization.
+ *
+ * @init
+ */
+void eicuInit(void) {
+
+ eicu_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p EICUDriver structure.
+ *
+ * @param[out] eicup Pointer to the @p EICUDriver object
+ *
+ * @init
+ */
+void eicuObjectInit(EICUDriver *eicup) {
+
+ eicup->state = EICU_STOP;
+ eicup->config = NULL;
+}
+
+/**
+ * @brief Configures and activates the EICU peripheral.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ * @param[in] config Pointer to the @p EICUConfig object
+ *
+ * @api
+ */
+void eicuStart(EICUDriver *eicup, const EICUConfig *config) {
+
+ osalDbgCheck((eicup != NULL) && (config != NULL));
+
+ osalSysLock();
+ osalDbgAssert((eicup->state == EICU_STOP) || (eicup->state == EICU_READY),
+ "invalid state");
+ eicup->config = config;
+ eicu_lld_start(eicup);
+ eicup->state = EICU_READY;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Deactivates the EICU peripheral.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @api
+ */
+void eicuStop(EICUDriver *eicup) {
+
+ osalDbgCheck(eicup != NULL);
+
+ osalSysLock();
+ osalDbgAssert((eicup->state == EICU_STOP) || (eicup->state == EICU_READY),
+ "invalid state");
+ eicu_lld_stop(eicup);
+ eicup->state = EICU_STOP;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Enables the extended input capture.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @api
+ */
+void eicuEnable(EICUDriver *eicup) {
+
+ osalDbgCheck(eicup != NULL);
+
+ osalSysLock();
+ osalDbgAssert(eicup->state == EICU_READY, "invalid state");
+ eicu_lld_enable(eicup);
+ eicup->state = EICU_WAITING;
+ osalSysUnlock();
+}
+
+/**
+ * @brief Disables the extended input capture.
+ *
+ * @param[in] eicup Pointer to the @p EICUDriver object
+ *
+ * @api
+ */
+void eicuDisable(EICUDriver *eicup) {
+
+ osalDbgCheck(eicup != NULL);
+
+ osalSysLock();
+ osalDbgAssert((eicup->state == EICU_READY) || (eicup->state == EICU_IDLE) ||
+ (eicup->state == EICU_ACTIVE) || (eicup->state == EICU_WAITING),
+ "invalid state");
+ eicu_lld_disable(eicup);
+ eicup->state = EICU_READY;
+ osalSysUnlock();
+}
+
+#endif /* HAL_USE_EICU */
diff --git a/os/hal/src/hal_community.c b/os/hal/src/hal_community.c
index b1e13e6..fc0cf85 100644
--- a/os/hal/src/hal_community.c
+++ b/os/hal/src/hal_community.c
@@ -59,6 +59,10 @@ void halCommunityInit(void) {
#if HAL_USE_NAND || defined(__DOXYGEN__)
nandInit();
#endif
+
+#if HAL_USE_EICU || defined(__DOXYGEN__)
+ eicuInit();
+#endif
}
#endif /* HAL_USE_COMMUNITY */
diff --git a/testhal/STM32/STM32F0xx/onewire/.project b/testhal/STM32/STM32F0xx/onewire/.project
index 33bcb82..856b65d 100644
--- a/testhal/STM32/STM32F0xx/onewire/.project
+++ b/testhal/STM32/STM32F0xx/onewire/.project
@@ -77,14 +77,14 @@
</natures>
<linkedResources>
<link>
- <name>os</name>
+ <name>os-community</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
</link>
<link>
- <name>os_community</name>
+ <name>os-git</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
</link>
</linkedResources>
</projectDescription>
diff --git a/testhal/STM32/STM32F1xx/onewire/.project b/testhal/STM32/STM32F1xx/onewire/.project
index 3eb5f6b..8f7973b 100644
--- a/testhal/STM32/STM32F1xx/onewire/.project
+++ b/testhal/STM32/STM32F1xx/onewire/.project
@@ -77,14 +77,14 @@
</natures>
<linkedResources>
<link>
- <name>os</name>
+ <name>os-community</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
</link>
<link>
- <name>os_community</name>
+ <name>os-git</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
</link>
</linkedResources>
</projectDescription>
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject b/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject
index 5915dc0..9dcfe77 100644
--- a/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject
@@ -21,15 +21,15 @@
<builder id="org.eclipse.cdt.build.core.settings.default.builder.681215945" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1913618182" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.1359024970" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
- <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.648690541" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.648690541" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.865562104" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.321395526" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
- <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.76286563" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.76286563" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1168908150" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.1390938668" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
- <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.684710851" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.684710851" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.645908401" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
</toolChain>
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/.project b/testhal/STM32/STM32F4xx/FSMC_NAND/.project
index 1f4f15b..c141077 100644
--- a/testhal/STM32/STM32F4xx/FSMC_NAND/.project
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/.project
@@ -25,14 +25,14 @@
</natures>
<linkedResources>
<link>
- <name>os</name>
+ <name>os-community</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
</link>
<link>
- <name>os_community</name>
+ <name>os-git</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
</link>
</linkedResources>
</projectDescription>
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/.cproject b/testhal/STM32/STM32F4xx/FSMC_SDRAM/.cproject
index 527852a..f9f2751 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/.cproject
+++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/.cproject
@@ -21,15 +21,15 @@
<builder id="org.eclipse.cdt.build.core.settings.default.builder.681215945" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1913618182" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.1359024970" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
- <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.648690541" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.648690541" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.865562104" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.321395526" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
- <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.76286563" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.76286563" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1168908150" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.1390938668" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
- <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.684710851" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.684710851" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.645908401" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
</toolChain>
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/.project b/testhal/STM32/STM32F4xx/FSMC_SDRAM/.project
index c8f9f20..e0391df 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/.project
+++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/.project
@@ -25,14 +25,14 @@
</natures>
<linkedResources>
<link>
- <name>os</name>
+ <name>os-community</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
</link>
<link>
- <name>os_community</name>
+ <name>os-git</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
</link>
</linkedResources>
</projectDescription>
diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/.cproject b/testhal/STM32/STM32F4xx/FSMC_SRAM/.cproject
index e658cfa..9ba3e1a 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SRAM/.cproject
+++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/.cproject
@@ -21,15 +21,15 @@
<builder id="org.eclipse.cdt.build.core.settings.default.builder.681215945" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1913618182" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.1359024970" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
- <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.648690541" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.648690541" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.865562104" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.321395526" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
- <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.76286563" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.76286563" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1168908150" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.1390938668" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
- <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.684710851" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
+ <option id="org.eclipse.cdt.build.core.settings.holder.incpaths.684710851" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.645908401" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
</toolChain>
diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/.project b/testhal/STM32/STM32F4xx/FSMC_SRAM/.project
index 2ae708b..b25c098 100644
--- a/testhal/STM32/STM32F4xx/FSMC_SRAM/.project
+++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/.project
@@ -25,14 +25,14 @@
</natures>
<linkedResources>
<link>
- <name>os</name>
+ <name>os-community</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
</link>
<link>
- <name>os_community</name>
+ <name>os-git</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
</link>
</linkedResources>
</projectDescription>
diff --git a/testhal/STM32/STM32F4xx/onewire/.project b/testhal/STM32/STM32F4xx/onewire/.project
index cf8a277..cb64a53 100644
--- a/testhal/STM32/STM32F4xx/onewire/.project
+++ b/testhal/STM32/STM32F4xx/onewire/.project
@@ -77,14 +77,14 @@
</natures>
<linkedResources>
<link>
- <name>os</name>
+ <name>os-community</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
</link>
<link>
- <name>os_community</name>
+ <name>os-git</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>PARENT-5-PROJECT_LOC/os</locationURI>
</link>
</linkedResources>
</projectDescription>
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-23 17:21:59 +0000