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-rw-r--r--os/hal/include/eicu.h4
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c (renamed from os/hal/ports/STM32/LLD/eicu_lld.c)278
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/eicu_lld.h (renamed from os/hal/ports/STM32/LLD/eicu_lld.h)128
-rw-r--r--os/hal/ports/STM32/STM32F4xx/platform.mk3
-rw-r--r--os/hal/src/eicu.c4
5 files changed, 370 insertions, 47 deletions
diff --git a/os/hal/include/eicu.h b/os/hal/include/eicu.h
index a4ab30f..a4fb342 100644
--- a/os/hal/include/eicu.h
+++ b/os/hal/include/eicu.h
@@ -17,6 +17,10 @@
Rewritten by Emil Fresk (1/5 - 2014) for extended input capture
functionality. And fix for spurious callbacks in the interrupt handler.
*/
+/*
+ Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of
+ 32-bit timers and timers with single capture/compare channels.
+*/
#ifndef _EICU_H_
#define _EICU_H_
diff --git a/os/hal/ports/STM32/LLD/eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c
index 0245128..ff62928 100644
--- a/os/hal/ports/STM32/LLD/eicu_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c
@@ -21,6 +21,10 @@
Rewritten by Emil Fresk (1/5 - 2014) for extended input capture
functionality. And fix for spurious callbacks in the interrupt handler.
*/
+/*
+ Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of
+ 32-bit timers and timers with single capture/compare channels.
+*/
/*
* Hardware Abstraction Layer for Extended Input Capture Unit
@@ -56,6 +60,7 @@
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
+
/**
* @brief EICUD1 driver identifier.
* @note The driver EICUD1 allocates the complex timer TIM1 when enabled.
@@ -120,6 +125,38 @@ EICUDriver EICUD9;
EICUDriver EICUD12;
#endif
+/**
+ * @brief EICUD10 driver identifier.
+ * @note The driver EICUD10 allocates the timer TIM10 when enabled.
+ */
+#if STM32_EICU_USE_TIM10 && !defined(__DOXYGEN__)
+EICUDriver EICUD10;
+#endif
+
+/**
+ * @brief EICUD11 driver identifier.
+ * @note The driver EICUD11 allocates the timer TIM11 when enabled.
+ */
+#if STM32_EICU_USE_TIM11 && !defined(__DOXYGEN__)
+EICUDriver EICUD11;
+#endif
+
+/**
+ * @brief EICUD13 driver identifier.
+ * @note The driver EICUD13 allocates the timer TIM13 when enabled.
+ */
+#if STM32_EICU_USE_TIM13 && !defined(__DOXYGEN__)
+EICUDriver EICUD13;
+#endif
+
+/**
+ * @brief EICUD14 driver identifier.
+ * @note The driver EICUD14 allocates the timer TIM14 when enabled.
+ */
+#if STM32_EICU_USE_TIM14 && !defined(__DOXYGEN__)
+EICUDriver EICUD14;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -138,7 +175,7 @@ EICUDriver EICUD12;
*
* @notapi
*/
-static eicuresult_t get_time_both(EICUDriver *eicup,
+static eicuresult_t get_time_both(const EICUDriver *eicup,
eicuchannel_t channel,
eicucnt_t compare) {
@@ -149,7 +186,7 @@ static eicuresult_t get_time_both(EICUDriver *eicup,
unsigned subtraction math.*/
/* 16-bit timer */
- if (0xFFFF == eicup->tim->ARR) {
+ if (EICU_WIDTH_16 == eicup->width) {
uint16_t cmp = compare;
uint16_t la = chp->last_active;
uint16_t li = chp->last_idle;
@@ -159,14 +196,13 @@ static eicuresult_t get_time_both(EICUDriver *eicup,
ret.period = p;
}
/* 32-bit timer */
- else if (0xFFFFFFFF == eicup->tim->ARR) {
+ else if (EICU_WIDTH_32 == eicup->width) {
ret.width = chp->last_idle - chp->last_active;
ret.period = compare - chp->last_active;
- return ret;
}
/* error trap */
else {
- osalSysHalt("ARR register must be loaded with maximum possible value");
+ osalSysHalt("Unhandled width value");
}
return ret;
@@ -183,7 +219,7 @@ static eicuresult_t get_time_both(EICUDriver *eicup,
*
* @notapi
*/
-static eicucnt_t get_time_width(EICUDriver *eicup,
+static eicucnt_t get_time_width(const EICUDriver *eicup,
eicuchannel_t channel,
eicucnt_t compare) {
@@ -193,19 +229,19 @@ static eicucnt_t get_time_width(EICUDriver *eicup,
unsigned subtraction math.*/
/* 16-bit timer */
- if (0xFFFF == eicup->tim->ARR) {
+ if (EICU_WIDTH_16 == eicup->width) {
uint16_t cmp = compare;
uint16_t la = chp->last_active;
uint16_t ret = cmp - la;
return ret;
}
/* 32-bit timer */
- else if (0xFFFFFFFF == eicup->tim->ARR) {
+ else if (EICU_WIDTH_32 == eicup->width) {
return compare - chp->last_active;
}
/* error trap */
else {
- osalSysHalt("ARR register must be loaded with maximum possible value");
+ osalSysHalt("Unhandled width value");
return 0;
}
}
@@ -221,7 +257,7 @@ static eicucnt_t get_time_width(EICUDriver *eicup,
*
* @notapi
*/
-static eicucnt_t get_time_period(EICUDriver *eicup,
+static eicucnt_t get_time_period(const EICUDriver *eicup,
eicuchannel_t channel,
eicucnt_t compare) {
@@ -231,19 +267,19 @@ static eicucnt_t get_time_period(EICUDriver *eicup,
unsigned subtraction math.*/
/* 16-bit timer */
- if (0xFFFF == eicup->tim->ARR) {
+ if (EICU_WIDTH_16 == eicup->width) {
uint16_t cmp = compare;
uint16_t li = chp->last_idle;
uint16_t ret = cmp - li;
return ret;
}
/* 32-bit timer */
- else if (0xFFFFFFFF == eicup->tim->ARR) {
+ else if (EICU_WIDTH_32 == eicup->width) {
return compare - chp->last_idle;
}
/* error trap */
else {
- osalSysHalt("ARR register must be loaded with maximum possible value");
+ osalSysHalt("Unhandled width value");
return 0;
}
}
@@ -635,6 +671,94 @@ OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) {
}
#endif /* STM32_EICU_USE_TIM12 */
+#if STM32_EICU_USE_TIM10
+#if !defined(STM32_TIM10_HANDLER)
+#error "STM32_TIM10_HANDLER not defined"
+#endif
+/**
+ * @brief TIM10 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM10_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD10);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM10 */
+
+#if STM32_EICU_USE_TIM11
+#if !defined(STM32_TIM11_HANDLER)
+#error "STM32_TIM11_HANDLER not defined"
+#endif
+/**
+ * @brief TIM11 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM11_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD11);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM11 */
+
+#if STM32_EICU_USE_TIM13
+#if !defined(STM32_TIM13_HANDLER)
+#error "STM32_TIM13_HANDLER not defined"
+#endif
+/**
+ * @brief TIM13 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM13_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD13);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM13 */
+
+#if STM32_EICU_USE_TIM14
+#if !defined(STM32_TIM14_HANDLER)
+#error "STM32_TIM14_HANDLER not defined"
+#endif
+/**
+ * @brief TIM14 interrupt handler.
+ * @note It is assumed that the various sources are only activated if the
+ * associated callback pointer is not equal to @p NULL in order to not
+ * perform an extra check in a potentially critical interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM14_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ eicu_lld_serve_interrupt(&EICUD14);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_EICU_USE_TIM14 */
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -692,6 +816,30 @@ void eicu_lld_init(void) {
eicuObjectInit(&EICUD12);
EICUD12.tim = STM32_TIM12;
#endif
+
+#if STM32_EICU_USE_TIM10
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD10);
+ EICUD10.tim = STM32_TIM10;
+#endif
+
+#if STM32_EICU_USE_TIM11
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD11);
+ EICUD11.tim = STM32_TIM11;
+#endif
+
+#if STM32_EICU_USE_TIM13
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD13);
+ EICUD13.tim = STM32_TIM13;
+#endif
+
+#if STM32_EICU_USE_TIM14
+ /* Driver initialization.*/
+ eicuObjectInit(&EICUD14);
+ EICUD14.tim = STM32_TIM14;
+#endif
}
/**
@@ -719,6 +867,7 @@ void eicu_lld_start(EICUDriver *eicup) {
rccResetTIM1();
nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY);
nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY);
+ eicup->channels = 4;
#if defined(STM32_TIM1CLK)
eicup->clock = STM32_TIM1CLK;
#else
@@ -731,6 +880,7 @@ void eicu_lld_start(EICUDriver *eicup) {
rccEnableTIM2(FALSE);
rccResetTIM2();
nvicEnableVector(STM32_TIM2_NUMBER, STM32_EICU_TIM2_IRQ_PRIORITY);
+ eicup->channels = 4;
eicup->clock = STM32_TIMCLK1;
}
#endif
@@ -739,6 +889,7 @@ void eicu_lld_start(EICUDriver *eicup) {
rccEnableTIM3(FALSE);
rccResetTIM3();
nvicEnableVector(STM32_TIM3_NUMBER, STM32_EICU_TIM3_IRQ_PRIORITY);
+ eicup->channels = 4;
eicup->clock = STM32_TIMCLK1;
}
#endif
@@ -747,6 +898,7 @@ void eicu_lld_start(EICUDriver *eicup) {
rccEnableTIM4(FALSE);
rccResetTIM4();
nvicEnableVector(STM32_TIM4_NUMBER, STM32_EICU_TIM4_IRQ_PRIORITY);
+ eicup->channels = 4;
eicup->clock = STM32_TIMCLK1;
}
#endif
@@ -755,6 +907,7 @@ void eicu_lld_start(EICUDriver *eicup) {
rccEnableTIM5(FALSE);
rccResetTIM5();
nvicEnableVector(STM32_TIM5_NUMBER, STM32_EICU_TIM5_IRQ_PRIORITY);
+ eicup->channels = 4;
eicup->clock = STM32_TIMCLK1;
}
#endif
@@ -764,6 +917,7 @@ void eicu_lld_start(EICUDriver *eicup) {
rccResetTIM8();
nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY);
nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY);
+ eicup->channels = 4;
#if defined(STM32_TIM8CLK)
eicup->clock = STM32_TIM8CLK;
#else
@@ -776,6 +930,7 @@ void eicu_lld_start(EICUDriver *eicup) {
rccEnableTIM9(FALSE);
rccResetTIM9();
nvicEnableVector(STM32_TIM9_NUMBER, STM32_EICU_TIM9_IRQ_PRIORITY);
+ eicup->channels = 2;
eicup->clock = STM32_TIMCLK2;
}
#endif
@@ -784,6 +939,43 @@ void eicu_lld_start(EICUDriver *eicup) {
rccEnableTIM12(FALSE);
rccResetTIM12();
nvicEnableVector(STM32_TIM12_NUMBER, STM32_EICU_TIM12_IRQ_PRIORITY);
+ eicup->channels = 2;
+ eicup->clock = STM32_TIMCLK1;
+ }
+#endif
+#if STM32_EICU_USE_TIM10
+ if (&EICUD10 == eicup) {
+ rccEnableTIM10(FALSE);
+ rccResetTIM10();
+ nvicEnableVector(STM32_TIM10_NUMBER, STM32_EICU_TIM10_IRQ_PRIORITY);
+ eicup->channels = 1;
+ eicup->clock = STM32_TIMCLK1;
+ }
+#endif
+#if STM32_EICU_USE_TIM11
+ if (&EICUD11 == eicup) {
+ rccEnableTIM11(FALSE);
+ rccResetTIM11();
+ nvicEnableVector(STM32_TIM11_NUMBER, STM32_EICU_TIM11_IRQ_PRIORITY);
+ eicup->channels = 1;
+ eicup->clock = STM32_TIMCLK1;
+ }
+#endif
+#if STM32_EICU_USE_TIM13
+ if (&EICUD13 == eicup) {
+ rccEnableTIM13(FALSE);
+ rccResetTIM13();
+ nvicEnableVector(STM32_TIM13_NUMBER, STM32_EICU_TIM13_IRQ_PRIORITY);
+ eicup->channels = 1;
+ eicup->clock = STM32_TIMCLK1;
+ }
+#endif
+#if STM32_EICU_USE_TIM14
+ if (&EICUD14 == eicup) {
+ rccEnableTIM14(FALSE);
+ rccResetTIM14();
+ nvicEnableVector(STM32_TIM14_NUMBER, STM32_EICU_TIM14_IRQ_PRIORITY);
+ eicup->channels = 1;
eicup->clock = STM32_TIMCLK1;
}
#endif
@@ -807,9 +999,19 @@ void eicu_lld_start(EICUDriver *eicup) {
eicup->tim->PSC = (uint16_t)psc;
eicup->tim->ARR = (eicucnt_t)-1;
+ /* Detect width.*/
+ if (0xFFFFFFFF == eicup->tim->ARR)
+ eicup->width = EICU_WIDTH_32;
+ else if (0xFFFF == eicup->tim->ARR)
+ eicup->width = EICU_WIDTH_16;
+ else
+ osalSysHalt("Unsupported width");
+
/* Reset registers */
eicup->tim->SMCR = 0;
eicup->tim->CCMR1 = 0;
+ if (eicup->channels > 2)
+ eicup->tim->CCMR2 = 0;
/* clean channel structures and set pointers to channel configs */
for (ch=0; ch<EICU_CHANNEL_ENUM_END; ch++) {
@@ -819,32 +1021,18 @@ void eicu_lld_start(EICUDriver *eicup) {
eicup->channel[ch].state = EICU_CH_IDLE;
}
-#if STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12
- if (eicup != &EICUD9)
- eicup->tim->CCMR2 = 0;
-#elif !STM32_EICU_USE_TIM9 && STM32_EICU_USE_TIM12
- if (eicup != &EICUD12)
- eicup->tim->CCMR2 = 0;
-#elif STM32_EICU_USE_TIM9 && STM32_EICU_USE_TIM12
- if ((eicup != &EICUD9) && (eicup != &EICUD12))
- eicup->tim->CCMR2 = 0;
-#else
- eicup->tim->CCMR2 = 0;
-#endif
-
/* TIM9 and TIM12 have only 2 channels.*/
-#if STM32_EICU_USE_TIM9
- if (eicup == &EICUD9) {
+ if (eicup->channels == 2) {
osalDbgCheck((eicup->config->iccfgp[2] == NULL) &&
(eicup->config->iccfgp[3] == NULL));
}
-#endif
-#if STM32_EICU_USE_TIM12
- if (eicup == &EICUD12) {
- osalDbgCheck((eicup->config->iccfgp[2] == NULL) &&
+
+ /* TIM10, TIM11, TIM13 and TIM14 have only 1 channel.*/
+ if (eicup->channels == 1) {
+ osalDbgCheck((eicup->config->iccfgp[1] == NULL) &&
+ (eicup->config->iccfgp[2] == NULL) &&
(eicup->config->iccfgp[3] == NULL));
}
-#endif
start_channels(eicup);
}
@@ -916,6 +1104,30 @@ void eicu_lld_stop(EICUDriver *eicup) {
}
#endif
}
+#if STM32_EICU_USE_TIM10
+ if (&EICUD10 == eicup) {
+ nvicDisableVector(STM32_TIM10_NUMBER);
+ rccDisableTIM10(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM11
+ if (&EICUD11 == eicup) {
+ nvicDisableVector(STM32_TIM11_NUMBER);
+ rccDisableTIM11(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM13
+ if (&EICUD13 == eicup) {
+ nvicDisableVector(STM32_TIM13_NUMBER);
+ rccDisableTIM13(FALSE);
+ }
+#endif
+#if STM32_EICU_USE_TIM14
+ if (&EICUD14 == eicup) {
+ nvicDisableVector(STM32_TIM14_NUMBER);
+ rccDisableTIM14(FALSE);
+ }
+#endif
}
/**
diff --git a/os/hal/ports/STM32/LLD/eicu_lld.h b/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.h
index 4f10893..3c95720 100644
--- a/os/hal/ports/STM32/LLD/eicu_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.h
@@ -17,7 +17,11 @@
Rewritten by Emil Fresk (1/5 - 2014) for extended input capture
functionality. And fix for spurious callbacks in the interrupt handler.
*/
-
+/*
+ Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of
+ 32-bit timers and timers with single capture/compare channels.
+*/
+
#ifndef __EICU_LLD_H
#define __EICU_LLD_H
@@ -164,6 +168,34 @@
#if !defined(STM32_EICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EICU_TIM12_IRQ_PRIORITY 7
#endif
+
+/**
+ * @brief EICUD10 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM10_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD11 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM11_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD13 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM13_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief EICUD14 interrupt priority level setting.
+ */
+#if !defined(STM32_EICU_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EICU_TIM14_IRQ_PRIORITY 7
+#endif
/** @} */
/*===========================================================================*/
@@ -202,53 +234,91 @@
#error "TIM12 not present in the selected device"
#endif
-#if !STM32_EICU_USE_TIM1 && !STM32_EICU_USE_TIM2 && \
- !STM32_EICU_USE_TIM3 && !STM32_EICU_USE_TIM4 && \
- !STM32_EICU_USE_TIM5 && !STM32_EICU_USE_TIM8 && \
- !STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12
+#if STM32_EICU_USE_TIM10 && !STM32_HAS_TIM10
+#error "TIM10 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM11 && !STM32_HAS_TIM11
+#error "TIM11 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM13 && !STM32_HAS_TIM13
+#error "TIM13 not present in the selected device"
+#endif
+
+#if STM32_EICU_USE_TIM14 && !STM32_HAS_TIM14
+#error "TIM14 not present in the selected device"
+#endif
+
+#if !STM32_EICU_USE_TIM1 && !STM32_EICU_USE_TIM2 && \
+ !STM32_EICU_USE_TIM3 && !STM32_EICU_USE_TIM4 && \
+ !STM32_EICU_USE_TIM5 && !STM32_EICU_USE_TIM8 && \
+ !STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12 && \
+ !STM32_EICU_USE_TIM10 && !STM32_EICU_USE_TIM11 && \
+ !STM32_EICU_USE_TIM13 && !STM32_EICU_USE_TIM14
#error "EICU driver activated but no TIM peripheral assigned"
#endif
-#if STM32_EICU_USE_TIM1 && \
+#if STM32_EICU_USE_TIM1 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM1"
#endif
-#if STM32_EICU_USE_TIM2 && \
+#if STM32_EICU_USE_TIM2 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM2"
#endif
-#if STM32_EICU_USE_TIM3 && \
+#if STM32_EICU_USE_TIM3 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM3"
#endif
-#if STM32_EICU_USE_TIM4 && \
+#if STM32_EICU_USE_TIM4 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM4"
#endif
-#if STM32_EICU_USE_TIM5 && \
+#if STM32_EICU_USE_TIM5 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM5_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM5"
#endif
-#if STM32_EICU_USE_TIM8 && \
+#if STM32_EICU_USE_TIM8 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM8_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM8"
#endif
-#if STM32_EICU_USE_TIM9 && \
+#if STM32_EICU_USE_TIM9 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM9_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM9"
#endif
-#if STM32_EICU_USE_TIM12 && \
+#if STM32_EICU_USE_TIM12 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM12_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM12"
#endif
+#if STM32_EICU_USE_TIM10 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM10_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM10"
+#endif
+
+#if STM32_EICU_USE_TIM11 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM11_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM11"
+#endif
+
+#if STM32_EICU_USE_TIM13 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM13_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM13"
+#endif
+
+#if STM32_EICU_USE_TIM14 && \
+ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM14_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to TIM14"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -282,6 +352,14 @@ typedef enum {
} eicucapturemode_t;
/**
+ * @brief Timer registers width in bits.
+ */
+typedef enum {
+ EICU_WIDTH_16,
+ EICU_WIDTH_32
+} eicutimerwidth_t;
+
+/**
* @brief EICU frequency type.
*/
typedef uint32_t eicufreq_t;
@@ -391,6 +469,14 @@ struct EICUDriver {
*/
uint32_t clock;
/**
+ * @brief Number of available capture compare channels in timer.
+ */
+ size_t channels;
+ /**
+ * @brief Timer registers width in bits.
+ */
+ eicutimerwidth_t width;
+ /**
* @brief Pointer to configuration for the driver.
*/
const EICUConfig *config;
@@ -435,6 +521,22 @@ extern EICUDriver EICUD9;
extern EICUDriver EICUD12;
#endif
+#if STM32_EICU_USE_TIM10 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD10;
+#endif
+
+#if STM32_EICU_USE_TIM11 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD11;
+#endif
+
+#if STM32_EICU_USE_TIM13 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD13;
+#endif
+
+#if STM32_EICU_USE_TIM14 && !defined(__DOXYGEN__)
+extern EICUDriver EICUD14;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk
index cd25988..598807e 100644
--- a/os/hal/ports/STM32/STM32F4xx/platform.mk
+++ b/os/hal/ports/STM32/STM32F4xx/platform.mk
@@ -3,8 +3,9 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/platform.mk
PLATFORMSRC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c \
- ${CHIBIOS}/community/os/hal/ports/STM32/LLD/eicu_lld.c \
+ ${CHIBIOS}/community/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c \
${CHIBIOS}/community/os/hal/src/fsmc_sdram.c
PLATFORMINC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1 \
+ ${CHIBIOS}/community/os/hal/ports/STM32/LLD/TIMv1 \
${CHIBIOS}/community/os/hal/ports/STM32/LLD
diff --git a/os/hal/src/eicu.c b/os/hal/src/eicu.c
index 6088b8f..102b346 100644
--- a/os/hal/src/eicu.c
+++ b/os/hal/src/eicu.c
@@ -17,6 +17,10 @@
Rewritten by Emil Fresk (1/5 - 2014) for extended input capture
functionality. And fix for spurious callbacks in the interrupt handler.
*/
+/*
+ Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of
+ 32-bit timers and timers with single capture/compare channels.
+*/
/*
* Hardware Abstraction Layer for Extended Input Capture Unit
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-23 10:41:11 +0000