diff options
Diffstat (limited to 'sdram.vhd')
| -rw-r--r-- | sdram.vhd | 30 |
1 files changed, 28 insertions, 2 deletions
@@ -26,6 +26,17 @@ end entity; architecture rtl of sdram is +component pll50125 IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; + + component sdram_mcu is port ( @@ -81,12 +92,24 @@ signal b_rd_n : std_logic; signal b_wr_n : std_logic; signal b_wait_n : std_logic; +signal pll_reset : std_logic; +signal clock_100 : std_logic; +signal pll_locked : std_logic; + +signal global_reset_n : std_logic; + + begin + pll: pll50125 port map ( + pll_reset, + clock_50, + clock_100, + pll_locked ); u0 : component sdram_mcu port map ( clk_clk => clock_50, -- clk.clk - reset_reset_n => reset_n, -- reset.reset_n + reset_reset_n => global_reset_n, -- reset.reset_n pio_0_d_export => seven_seg, -- pio_0_d.export ebb_0_cs_n => b_cs_n, -- ebb_0.cs_n ebb_0_rd_n => b_rd_n, -- .rd_n @@ -99,7 +122,7 @@ begin sdram_ctrl0: sdram_ctrl port map ( clock_50, - reset_n, + global_reset_n, b_cs_n, b_rd_n, @@ -124,5 +147,8 @@ begin sdram_dq, sdram_dqm ); + + pll_reset <= '0'; + global_reset_n <= reset_n and pll_locked; end architecture; |