From 4ca3e92e5896b1b8fec43c73e14c9c7ec72a8324 Mon Sep 17 00:00:00 2001
From: the great greene arkleseizure <root@e6230.(none)>
Date: Thu, 10 Oct 2013 10:40:53 +0100
Subject: hardware
---
hardware/.gitignore | 2 +
hardware/DM9000A/dm9000a_hw.tcl | 141 +++++++++++++++++
hardware/DM9000A/hdl/DM9000A_IF.v | 85 ++++++++++
hardware/GPU/gpu_hw.tcl | 138 ++++++++++++++++
hardware/GPU/hdl/GPU_IF.v | 219 +++++++++++++++++++++++++
hardware/pll.v | 326 ++++++++++++++++++++++++++++++++++++++
hardware/pong3.pin | 274 ++++++++++++++++++++++++++++++++
hardware/pong3.qpf | 30 ++++
hardware/pong3.qsf | 151 ++++++++++++++++++
hardware/pong3.v | 112 +++++++++++++
10 files changed, 1478 insertions(+)
create mode 100644 hardware/.gitignore
create mode 100644 hardware/DM9000A/dm9000a_hw.tcl
create mode 100644 hardware/DM9000A/hdl/DM9000A_IF.v
create mode 100644 hardware/GPU/gpu_hw.tcl
create mode 100644 hardware/GPU/hdl/GPU_IF.v
create mode 100644 hardware/pll.v
create mode 100644 hardware/pong3.pin
create mode 100644 hardware/pong3.qpf
create mode 100644 hardware/pong3.qsf
create mode 100644 hardware/pong3.v
diff --git a/hardware/.gitignore b/hardware/.gitignore
new file mode 100644
index 0000000..7f7563f
--- /dev/null
+++ b/hardware/.gitignore
@@ -0,0 +1,2 @@
+db
+pong3.qws
diff --git a/hardware/DM9000A/dm9000a_hw.tcl b/hardware/DM9000A/dm9000a_hw.tcl
new file mode 100644
index 0000000..ea89ec5
--- /dev/null
+++ b/hardware/DM9000A/dm9000a_hw.tcl
@@ -0,0 +1,141 @@
+# TCL File Generated by Component Editor 12.0
+# Thu Sep 12 21:20:16 CST 2013
+# DO NOT MODIFY
+
+
+#
+# dm9000a "dm9000a" v1.0
+# null 2013.09.12.21:20:16
+#
+#
+
+#
+# request TCL package from ACDS 12.0
+#
+package require -exact qsys 12.0
+
+
+#
+# module dm9000a
+#
+set_module_property NAME dm9000a
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP my_lib
+set_module_property DISPLAY_NAME dm9000a
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property ANALYZE_HDL AUTO
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL DM9000A_IF
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file DM9000A_IF.v VERILOG PATH hdl/DM9000A_IF.v
+
+add_fileset SIM_VHDL SIM_VHDL "" ""
+set_fileset_property SIM_VHDL TOP_LEVEL DM9000A_IF
+set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file dm9000a_hw.tcl OTHER PATH dm9000a_hw.tcl
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point avalon_slave_0
+#
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressAlignment DYNAMIC
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock_sink
+set_interface_property avalon_slave_0 associatedReset clock_sink_reset
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 1
+set_interface_property avalon_slave_0 isMemoryDevice false
+set_interface_property avalon_slave_0 isNonVolatileStorage false
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 printableDevice false
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitStates 4
+set_interface_property avalon_slave_0 readWaitTime 4
+set_interface_property avalon_slave_0 setupTime 1
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitStates 4
+set_interface_property avalon_slave_0 writeWaitTime 4
+set_interface_property avalon_slave_0 ENABLED true
+
+add_interface_port avalon_slave_0 iDATA writedata Input 32
+add_interface_port avalon_slave_0 iCMD address Input 1
+add_interface_port avalon_slave_0 iRD_N read_n Input 1
+add_interface_port avalon_slave_0 iWR_N write_n Input 1
+add_interface_port avalon_slave_0 iCS_N chipselect_n Input 1
+add_interface_port avalon_slave_0 oDATA readdata Output 32
+
+
+#
+# connection point clock_sink
+#
+add_interface clock_sink clock end
+set_interface_property clock_sink clockRate 0
+set_interface_property clock_sink ENABLED true
+
+add_interface_port clock_sink iCLK clk Input 1
+
+
+#
+# connection point clock_sink_reset
+#
+add_interface clock_sink_reset reset end
+set_interface_property clock_sink_reset associatedClock clock_sink
+set_interface_property clock_sink_reset synchronousEdges DEASSERT
+set_interface_property clock_sink_reset ENABLED true
+
+add_interface_port clock_sink_reset iRST_N reset_n Input 1
+
+
+#
+# connection point conduit_end
+#
+add_interface conduit_end conduit end
+set_interface_property conduit_end associatedClock ""
+set_interface_property conduit_end associatedReset ""
+set_interface_property conduit_end ENABLED true
+
+add_interface_port conduit_end iOSC_50 export Input 1
+add_interface_port conduit_end ENET_DATA export Bidir 16
+add_interface_port conduit_end ENET_CMD export Output 1
+add_interface_port conduit_end ENET_RD_N export Output 1
+add_interface_port conduit_end ENET_WR_N export Output 1
+add_interface_port conduit_end ENET_CS_N export Output 1
+add_interface_port conduit_end ENET_RST_N export Output 1
+add_interface_port conduit_end ENET_INT export Input 1
+add_interface_port conduit_end ENET_CLK export Output 1
+
+
+#
+# connection point interrupt_sender
+#
+add_interface interrupt_sender interrupt end
+set_interface_property interrupt_sender associatedAddressablePoint avalon_slave_0
+set_interface_property interrupt_sender associatedClock clock_sink
+set_interface_property interrupt_sender associatedReset clock_sink_reset
+set_interface_property interrupt_sender ENABLED true
+
+add_interface_port interrupt_sender oINT irq Output 1
+
diff --git a/hardware/DM9000A/hdl/DM9000A_IF.v b/hardware/DM9000A/hdl/DM9000A_IF.v
new file mode 100644
index 0000000..3fd22e0
--- /dev/null
+++ b/hardware/DM9000A/hdl/DM9000A_IF.v
@@ -0,0 +1,85 @@
+module DM9000A_IF( // HOST Side
+ iDATA,
+ oDATA,
+ iCMD,
+ iRD_N,
+ iWR_N,
+ iCS_N,
+ iRST_N,
+ iCLK,
+ iOSC_50,
+ oINT,
+ // DM9000A Side
+ ENET_DATA,
+ ENET_CMD,
+ ENET_RD_N,
+ ENET_WR_N,
+ ENET_CS_N,
+ ENET_RST_N,
+ ENET_INT,
+ ENET_CLK );
+// HOST Side
+input [31:0] iDATA;
+input iCMD;
+input iRD_N;
+input iWR_N;
+input iCS_N;
+input iRST_N;
+input iCLK;
+input iOSC_50;
+output [31:0] oDATA;
+output oINT;
+// DM9000A Side
+inout [15:0] ENET_DATA;
+output ENET_CMD;
+output ENET_RD_N;
+output ENET_WR_N;
+output ENET_CS_N;
+output ENET_RST_N;
+output ENET_CLK;
+input ENET_INT;
+
+reg [15:0] TMP_DATA;
+reg ENET_CMD;
+reg ENET_RD_N;
+reg ENET_WR_N;
+reg ENET_CS_N;
+reg ENET_CLK;
+reg [31:0] oDATA;
+reg oINT;
+
+assign ENET_DATA = ENET_WR_N ? 16'hzzzz : TMP_DATA;
+
+always@(posedge iCLK or negedge iRST_N)
+begin
+ if(!iRST_N)
+ begin
+ TMP_DATA <= 0;
+ ENET_CMD <= 0;
+ ENET_RD_N <= 1;
+ ENET_WR_N <= 1;
+ ENET_CS_N <= 1;
+ oDATA <= 0;
+ oINT <= 0;
+ end
+ else
+ begin
+ oDATA <= ENET_DATA;
+ oINT <= ENET_INT;
+ TMP_DATA <= iDATA;
+ ENET_CMD <= iCMD;
+ ENET_CS_N <= iCS_N;
+ ENET_RD_N <= iRD_N;
+ ENET_WR_N <= iWR_N;
+ end
+end
+
+always@(posedge iOSC_50)
+ENET_CLK <= ~ENET_CLK;
+
+assign ENET_RST_N = iRST_N;
+
+endmodule
+
+
+
diff --git a/hardware/GPU/gpu_hw.tcl b/hardware/GPU/gpu_hw.tcl
new file mode 100644
index 0000000..5eae01e
--- /dev/null
+++ b/hardware/GPU/gpu_hw.tcl
@@ -0,0 +1,138 @@
+# TCL File Generated by Component Editor 13.0sp1
+# Wed Oct 09 17:56:27 BST 2013
+# DO NOT MODIFY
+
+
+#
+# gpu "gpu" v1.0
+# 2013.10.09.17:56:27
+#
+#
+
+#
+# request TCL package from ACDS 13.1
+#
+package require -exact qsys 13.1
+
+
+#
+# module gpu
+#
+set_module_property DESCRIPTION ""
+set_module_property NAME gpu
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP my_lib
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME gpu
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property ANALYZE_HDL AUTO
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL gpuv2
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file GPU_IF.v VERILOG PATH hdl/GPU_IF.v
+
+add_fileset SIM_VHDL SIM_VHDL "" ""
+set_fileset_property SIM_VHDL TOP_LEVEL gpuv2
+set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file gpu_hw.tcl OTHER PATH gpu_hw.tcl
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point clock
+#
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+#
+# connection point reset
+#
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset rst_n reset_n Input 1
+
+
+#
+# connection point vga
+#
+add_interface vga conduit end
+set_interface_property vga associatedClock ""
+set_interface_property vga associatedReset ""
+set_interface_property vga ENABLED true
+set_interface_property vga EXPORT_OF ""
+set_interface_property vga PORT_NAME_MAP ""
+set_interface_property vga SVD_ADDRESS_GROUP ""
+
+add_interface_port vga vga_red export Output 3
+add_interface_port vga vga_green export Output 3
+add_interface_port vga vga_blue export Output 3
+add_interface_port vga vga_hs export Output 1
+add_interface_port vga vga_vs export Output 1
+add_interface_port vga vga_clk export Input 1
+
+
+#
+# connection point avalon_slave
+#
+add_interface avalon_slave avalon end
+set_interface_property avalon_slave addressUnits WORDS
+set_interface_property avalon_slave associatedClock clock
+set_interface_property avalon_slave associatedReset reset
+set_interface_property avalon_slave bitsPerSymbol 8
+set_interface_property avalon_slave burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave burstcountUnits WORDS
+set_interface_property avalon_slave explicitAddressSpan 0
+set_interface_property avalon_slave holdTime 0
+set_interface_property avalon_slave linewrapBursts false
+set_interface_property avalon_slave maximumPendingReadTransactions 0
+set_interface_property avalon_slave readLatency 0
+set_interface_property avalon_slave readWaitTime 1
+set_interface_property avalon_slave setupTime 0
+set_interface_property avalon_slave timingUnits Cycles
+set_interface_property avalon_slave writeWaitTime 0
+set_interface_property avalon_slave ENABLED true
+set_interface_property avalon_slave EXPORT_OF ""
+set_interface_property avalon_slave PORT_NAME_MAP ""
+set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave cs_n chipselect_n Input 1
+add_interface_port avalon_slave address address Input 7
+add_interface_port avalon_slave data writedata Input 32
+add_interface_port avalon_slave wr_n write_n Input 1
+set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
+
diff --git a/hardware/GPU/hdl/GPU_IF.v b/hardware/GPU/hdl/GPU_IF.v
new file mode 100644
index 0000000..f32de1e
--- /dev/null
+++ b/hardware/GPU/hdl/GPU_IF.v
@@ -0,0 +1,219 @@
+// gpuv2.v
+
+// This file was auto-generated as a prototype implementation of a module
+// created in component editor. It ties off all outputs to ground and
+// ignores all inputs. It needs to be edited to make it do something
+// useful.
+//
+// This file will not be automatically regenerated. You should check it in
+// to your version control system if you want to keep it.
+
+`timescale 1 ps / 1 ps
+module gpuv2 #(
+ parameter AUTO_CLOCK_CLOCK_RATE = "-1"
+ ) (
+ input wire clk, // clock.clk
+ input wire rst_n, // reset.reset_n
+ input wire vga_clk, // vga_out.export
+ output reg [2:0] vga_red, // .export
+ output reg [2:0] vga_green, // .export
+ output reg [2:0] vga_blue, // .export
+ output reg vga_hs, // .export
+ output reg vga_vs, // .export
+ input wire [31:0] data, // avalon_slave.writedata
+ input wire wr_n, // .write_n
+ input wire cs_n, // .chipselect_n
+ input wire [6:0] address // .address
+ );
+
+
+ reg [9:0] ball_x;
+ reg [8:0] ball_y;
+ reg [8:0] bat0_y;
+ reg [8:0] bat1_y;
+
+ reg [15:0] sprite[0:15];
+
+ wire [4:0] reg_addr;
+
+ assign reg_addr = address[6:2];
+
+
+ reg [2:0] sprite_red;
+ reg [2:0] sprite_green;
+ reg [2:0] sprite_blue;
+
+ always @(posedge clk or negedge rst_n)
+ begin
+ if (rst_n == 0) begin
+ ball_x <= 10'd127;
+ ball_y <= 10'd127;
+ bat0_y <= 10'd100;
+ bat1_y <= 10'd200;
+
+ sprite[0]=16'b1111111111111111;
+ sprite[1]=16'b1000000000000001;
+ sprite[2]=16'b1000000000000001;
+ sprite[3]=16'b1000000000000001;
+ sprite[4]=16'b1000000000000001;
+ sprite[5]=16'b1000000000000001;
+ sprite[6]=16'b1000000000000001;
+ sprite[7]=16'b1000000000000001;
+ sprite[8]=16'b1000000000000001;
+ sprite[9]=16'b1000000000000001;
+ sprite[10]=16'b1000000000000001;
+ sprite[11]=16'b1000000000000001;
+ sprite[12]=16'b1000000000000001;
+ sprite[13]=16'b1000000000000001;
+ sprite[14]=16'b1000000000000001;
+ sprite[15]=16'b1111111111111111;
+
+ sprite_red[2:0]=3'b111;
+ sprite_green[2:0]=3'b000;
+ sprite_blue[2:0]=3'b111;
+
+ end else if (~cs_n && ~wr_n) begin
+ if (reg_addr[4]) begin
+ sprite[reg_addr[3:0]]<=data[15:0];
+ end else begin
+ case (reg_addr[2:0])
+ 3'b000:
+ ball_x <= data[9:0];
+ 3'b001:
+ ball_y <= data[8:0];
+ 3'b010:
+ bat0_y <= data[8:0];
+ 3'b011:
+ bat1_y <= data[8:0];
+ 3'b100:
+ begin
+ sprite_red <= data[8:6];
+ sprite_green <= data[5:3];
+ sprite_blue <= data[2:0];
+ end
+ endcase
+ end
+ end
+ end
+
+
+ reg trig_25M;
+ always @ (posedge vga_clk)
+ begin
+ if(!rst_n)
+ trig_25M <= 1'b0;
+ else
+ trig_25M <= ~trig_25M;
+ end
+
+ reg [9:0] vector_x;
+ always @ (posedge vga_clk or negedge rst_n)
+ begin
+ if(!rst_n)
+ vector_x <= 10'd0;
+ else if(trig_25M)
+ begin
+ if(vector_x != 10'd799)
+ vector_x <= vector_x + 1'b1;
+ else
+ vector_x <= 10'd0;
+ end
+ end
+
+ reg [9:0] vector_y;
+ always @ (posedge vga_clk or negedge rst_n)
+ begin
+ if(!rst_n)
+ vector_y <= 10'd0;
+ else if(trig_25M)
+ begin
+ if(vector_x == 10'd799)
+ begin
+ if(vector_y != 10'd524)
+ vector_y <= vector_y + 1'b1;
+ else
+ vector_y <= 10'd0;
+ end
+ end
+ end
+
+ always @ (posedge vga_clk or negedge rst_n)
+ begin
+ if(!rst_n)
+ vga_hs <= 1'b0;
+ else if(trig_25M)
+ begin
+ if(vector_x >= 10'd656 && vector_x < 10'd752)
+ vga_hs <= 1'b0;
+ else
+ vga_hs <= 1'b1;
+ end
+ end
+
+ always @ (posedge vga_clk or negedge rst_n)
+ begin
+ if(!rst_n)
+ vga_vs <= 1'b0;
+ else if(trig_25M)
+ begin
+ if(vector_y >= 10'd490 && vector_y < 10'd492)
+ vga_vs <= 1'b0;
+ else
+ vga_vs <= 1'b1;
+ end
+ end
+
+
+
+ reg [2:0] index;
+ always @ (posedge vga_clk or negedge rst_n)
+ begin
+ if(!rst_n)
+ index <= 3'b000;
+ else if(trig_25M)
+ begin
+ if(vector_x < 10'd640 && vector_y < 10'd480)
+ if(vector_x >= (ball_x - 8 )&& vector_x <=( ball_x + 7 )
+ && vector_y >= (ball_y - 8) && vector_y <= (ball_y + 7)) begin
+ if (sprite[(vector_y - (ball_y - 8)) & 15 ][(vector_x - (ball_x -8))& 15 ])
+ index <= 3'b001;
+ else
+ index <= 3'b000;
+ end else if (vector_x < 10'd4)
+ if (vector_y >=( bat0_y - 20 ) && vector_y <= (bat0_y + 20) )
+ index <= 3'b111;
+ else
+ index <= 3'b000;
+ else if (vector_x >= 10'd318 && vector_x < 10'd322)
+ index <= {3{vector_y[3]}};
+ else if (vector_x >= 10'd636 && vector_x < 10'd640)
+ if (vector_y >=( bat1_y - 20 ) && vector_y <= (bat1_y + 20) )
+ index <= 3'b111;
+ else
+ index <= 3'b000;
+ else
+ index <= 3'b000;
+ else
+ index <= 3'b000;
+ end
+ end
+
+ always begin
+ if (index == 3'b000) begin
+ vga_red = 3'b000;
+ vga_green = 3'b000;
+ vga_blue = 3'b000;
+ end else if (index == 3'b001) begin
+ vga_red = sprite_red;
+ vga_green= sprite_green;
+ vga_blue = sprite_blue;
+ end else begin
+ vga_red= 3'b111;
+ vga_green=3'b111;
+ vga_blue=3'b111;
+ end
+
+
+ end
+
+endmodule
diff --git a/hardware/pll.v b/hardware/pll.v
new file mode 100644
index 0000000..7dc9ba3
--- /dev/null
+++ b/hardware/pll.v
@@ -0,0 +1,326 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 12.0 Build 178 05/31/2012 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2012 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+ inclk0,
+ c0,
+ c1);
+
+ input inclk0;
+ output c0;
+ output c1;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire5 = 1'h0;
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire sub_wire3 = inclk0;
+ wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+ altpll altpll_component (
+ .inclk (sub_wire4),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 5,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 8,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 5,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 8,
+ altpll_component.clk1_phase_shift = "-3000",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "80.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "80.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/hardware/pong3.pin b/hardware/pong3.pin
new file mode 100644
index 0000000..163704a
--- /dev/null
+++ b/hardware/pong3.pin
@@ -0,0 +1,274 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+CHIP "dm9000a_nios" ASSIGNED TO AN: EP2C8Q208C8
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+~ASDO~ / RESERVED_INPUT : 1 : input : 3.3-V LVTTL : : 1 : N
+~nCSO~ / RESERVED_INPUT : 2 : input : 3.3-V LVTTL : : 1 : N
+GND* : 3 : : : : 1 :
+GND* : 4 : : : : 1 :
+GND* : 5 : : : : 1 :
+GND* : 6 : : : : 1 :
+VCCIO1 : 7 : power : : 3.3V : 1 :
+GND* : 8 : : : : 1 :
+GND : 9 : gnd : : : :
+GND* : 10 : : : : 1 :
+GND* : 11 : : : : 1 :
+GND* : 12 : : : : 1 :
+GND* : 13 : : : : 1 :
+seven_seg[7] : 14 : output : 3.3-V LVTTL : : 1 : N
+GND* : 15 : : : : 1 :
+altera_reserved_tdo : 16 : output : 3.3-V LVTTL : : 1 : N
+altera_reserved_tms : 17 : input : 3.3-V LVTTL : : 1 : N
+altera_reserved_tck : 18 : input : 3.3-V LVTTL : : 1 : N
+altera_reserved_tdi : 19 : input : 3.3-V LVTTL : : 1 : N
+DATA0 : 20 : input : : : 1 :
+DCLK : 21 : : : : 1 :
+nCE : 22 : : : : 1 :
+clk : 23 : input : 3.3-V LVTTL : : 1 : Y
+GND+ : 24 : : : : 1 :
+GND : 25 : gnd : : : :
+nCONFIG : 26 : : : : 1 :
+rst_n : 27 : input : 3.3-V LVTTL : : 1 : Y
+GND+ : 28 : : : : 1 :
+VCCIO1 : 29 : power : : 3.3V : 1 :
+seven_seg[2] : 30 : output : 3.3-V LVTTL : : 1 : N
+GND* : 31 : : : : 1 :
+VCCINT : 32 : power : : 1.2V : :
+GND* : 33 : : : : 1 :
+GND* : 34 : : : : 1 :
+GND* : 35 : : : : 1 :
+GND : 36 : gnd : : : :
+GND* : 37 : : : : 1 :
+GND : 38 : gnd : : : :
+GND* : 39 : : : : 1 :
+GND* : 40 : : : : 1 :
+GND* : 41 : : : : 1 :
+VCCIO1 : 42 : power : : 3.3V : 1 :
+seven_seg[0] : 43 : output : 3.3-V LVTTL : : 1 : N
+GND* : 44 : : : : 1 :
+sdram_cs_n : 45 : output : 3.3-V LVTTL : : 1 : Y
+sdram_cke : 46 : output : 3.3-V LVTTL : : 1 : Y
+sdram_clk : 47 : output : 3.3-V LVTTL : : 1 : Y
+GND* : 48 : : : : 1 :
+GND : 49 : gnd : : : :
+GND_PLL1 : 50 : gnd : : : :
+VCCD_PLL1 : 51 : power : : 1.2V : :
+GND_PLL1 : 52 : gnd : : : :
+VCCA_PLL1 : 53 : power : : 1.2V : :
+GNDA_PLL1 : 54 : gnd : : : :
+GND : 55 : gnd : : : :
+sdram_dqm[0] : 56 : output : 3.3-V LVTTL : : 4 : Y
+sdram_dq[7] : 57 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[6] : 58 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[5] : 59 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[4] : 60 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[3] : 61 : bidir : 3.3-V LVTTL : : 4 : Y
+VCCIO4 : 62 : power : : 3.3V : 4 :
+sdram_dq[2] : 63 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[1] : 64 : bidir : 3.3-V LVTTL : : 4 : Y
+GND : 65 : gnd : : : :
+VCCINT : 66 : power : : 1.2V : :
+sdram_dq[0] : 67 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_we_n : 68 : output : 3.3-V LVTTL : : 4 : Y
+sdram_cas_n : 69 : output : 3.3-V LVTTL : : 4 : Y
+sdram_ras_n : 70 : output : 3.3-V LVTTL : : 4 : Y
+VCCIO4 : 71 : power : : 3.3V : 4 :
+sdram_ba[0] : 72 : output : 3.3-V LVTTL : : 4 : Y
+GND : 73 : gnd : : : :
+sdram_ba[1] : 74 : output : 3.3-V LVTTL : : 4 : Y
+sdram_addr[10] : 75 : output : 3.3-V LVTTL : : 4 : Y
+sdram_addr[0] : 76 : output : 3.3-V LVTTL : : 4 : Y
+sdram_addr[1] : 77 : output : 3.3-V LVTTL : : 4 : Y
+GND : 78 : gnd : : : :
+VCCINT : 79 : power : : 1.2V : :
+sdram_addr[2] : 80 : output : 3.3-V LVTTL : : 4 : Y
+sdram_addr[3] : 81 : output : 3.3-V LVTTL : : 4 : Y
+sdram_addr[4] : 82 : output : 3.3-V LVTTL : : 4 : Y
+VCCIO4 : 83 : power : : 3.3V : 4 :
+sdram_addr[5] : 84 : output : 3.3-V LVTTL : : 4 : Y
+GND : 85 : gnd : : : :
+sdram_addr[6] : 86 : output : 3.3-V LVTTL : : 4 : Y
+sdram_addr[7] : 87 : output : 3.3-V LVTTL : : 4 : Y
+sdram_addr[8] : 88 : output : 3.3-V LVTTL : : 4 : Y
+sdram_addr[9] : 89 : output : 3.3-V LVTTL : : 4 : Y
+sdram_addr[11] : 90 : output : 3.3-V LVTTL : : 4 : Y
+VCCIO4 : 91 : power : : 3.3V : 4 :
+sdram_addr[12] : 92 : output : 3.3-V LVTTL : : 4 : Y
+GND : 93 : gnd : : : :
+sdram_dq[15] : 94 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[14] : 95 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[13] : 96 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[12] : 97 : bidir : 3.3-V LVTTL : : 4 : Y
+VCCIO4 : 98 : power : : 3.3V : 4 :
+sdram_dq[11] : 99 : bidir : 3.3-V LVTTL : : 4 : Y
+GND : 100 : gnd : : : :
+sdram_dq[10] : 101 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[9] : 102 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dq[8] : 103 : bidir : 3.3-V LVTTL : : 4 : Y
+sdram_dqm[1] : 104 : output : 3.3-V LVTTL : : 4 : Y
+GND* : 105 : : : : 3 :
+GND* : 106 : : : : 3 :
+GND* : 107 : : : : 3 :
+vga_red[0] : 108 : output : 3.3-V LVTTL : : 3 : Y
+VCCIO3 : 109 : power : : 3.3V : 3 :
+GND* : 110 : : : : 3 :
+GND : 111 : gnd : : : :
+vga_red[2] : 112 : output : 3.3-V LVTTL : : 3 : Y
+vga_red[1] : 113 : output : 3.3-V LVTTL : : 3 : Y
+vga_green[1] : 114 : output : 3.3-V LVTTL : : 3 : Y
+vga_green[0] : 115 : output : 3.3-V LVTTL : : 3 : Y
+vga_blue[0] : 116 : output : 3.3-V LVTTL : : 3 : Y
+vga_green[2] : 117 : output : 3.3-V LVTTL : : 3 : Y
+vga_blue[2] : 118 : output : 3.3-V LVTTL : : 3 : Y
+GND : 119 : gnd : : : :
+VCCINT : 120 : power : : 1.2V : :
+nSTATUS : 121 : : : : 3 :
+VCCIO3 : 122 : power : : 3.3V : 3 :
+CONF_DONE : 123 : : : : 3 :
+GND : 124 : gnd : : : :
+MSEL1 : 125 : : : : 3 :
+MSEL0 : 126 : : : : 3 :
+vga_blue[1] : 127 : output : 3.3-V LVTTL : : 3 : Y
+vga_hs : 128 : output : 3.3-V LVTTL : : 3 : Y
+GND+ : 129 : : : : 3 :
+GND+ : 130 : : : : 3 :
+GND+ : 131 : : : : 3 :
+GND+ : 132 : : : : 3 :
+vga_vs : 133 : output : 3.3-V LVTTL : : 3 : Y
+dm9000_data[6] : 134 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[7] : 135 : bidir : 3.3-V LVTTL : : 3 : Y
+VCCIO3 : 136 : power : : 3.3V : 3 :
+dm9000_data[4] : 137 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[5] : 138 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[2] : 139 : bidir : 3.3-V LVTTL : : 3 : Y
+GND : 140 : gnd : : : :
+dm9000_data[3] : 141 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[0] : 142 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[1] : 143 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[15] : 144 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[14] : 145 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[13] : 146 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[12] : 147 : bidir : 3.3-V LVTTL : : 3 : Y
+VCCIO3 : 148 : power : : 3.3V : 3 :
+dm9000_data[11] : 149 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[10] : 150 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[9] : 151 : bidir : 3.3-V LVTTL : : 3 : Y
+dm9000_data[8] : 152 : bidir : 3.3-V LVTTL : : 3 : Y
+GND : 153 : gnd : : : :
+GND_PLL2 : 154 : gnd : : : :
+VCCD_PLL2 : 155 : power : : 1.2V : :
+GND_PLL2 : 156 : gnd : : : :
+VCCA_PLL2 : 157 : power : : 1.2V : :
+GNDA_PLL2 : 158 : gnd : : : :
+GND : 159 : gnd : : : :
+dm9000_cmd : 160 : output : 3.3-V LVTTL : : 2 : Y
+dm9000_int : 161 : input : 3.3-V LVTTL : : 2 : Y
+dm9000_rd_n : 162 : output : 3.3-V LVTTL : : 2 : Y
+dm9000_wr_n : 163 : output : 3.3-V LVTTL : : 2 : Y
+dm9000_rst_n : 164 : output : 3.3-V LVTTL : : 2 : Y
+dm9000_cs_n : 165 : output : 3.3-V LVTTL : : 2 : Y
+VCCIO2 : 166 : power : : 3.3V : 2 :
+GND : 167 : gnd : : : :
+GND* : 168 : : : : 2 :
+GND* : 169 : : : : 2 :
+GND* : 170 : : : : 2 :
+GND* : 171 : : : : 2 :
+VCCIO2 : 172 : power : : 3.3V : 2 :
+GND* : 173 : : : : 2 :
+GND : 174 : gnd : : : :
+GND* : 175 : : : : 2 :
+GND* : 176 : : : : 2 :
+GND : 177 : gnd : : : :
+VCCINT : 178 : power : : 1.2V : :
+GND* : 179 : : : : 2 :
+GND* : 180 : : : : 2 :
+GND* : 181 : : : : 2 :
+GND* : 182 : : : : 2 :
+VCCIO2 : 183 : power : : 3.3V : 2 :
+GND : 184 : gnd : : : :
+GND* : 185 : : : : 2 :
+GND : 186 : gnd : : : :
+seven_seg[5] : 187 : output : 3.3-V LVTTL : : 2 : N
+GND* : 188 : : : : 2 :
+GND* : 189 : : : : 2 :
+VCCINT : 190 : power : : 1.2V : :
+GND* : 191 : : : : 2 :
+GND* : 192 : : : : 2 :
+seven_seg[1] : 193 : output : 3.3-V LVTTL : : 2 : N
+VCCIO2 : 194 : power : : 3.3V : 2 :
+seven_seg[4] : 195 : output : 3.3-V LVTTL : : 2 : N
+GND : 196 : gnd : : : :
+GND* : 197 : : : : 2 :
+GND* : 198 : : : : 2 :
+seven_seg[6] : 199 : output : 3.3-V LVTTL : : 2 : N
+GND* : 200 : : : : 2 :
+GND* : 201 : : : : 2 :
+VCCIO2 : 202 : power : : 3.3V : 2 :
+GND* : 203 : : : : 2 :
+GND : 204 : gnd : : : :
+GND* : 205 : : : : 2 :
+GND* : 206 : : : : 2 :
+seven_seg[3] : 207 : output : 3.3-V LVTTL : : 2 : N
+GND* : 208 : : : : 2 :
diff --git a/hardware/pong3.qpf b/hardware/pong3.qpf
new file mode 100644
index 0000000..f9a4fa2
--- /dev/null
+++ b/hardware/pong3.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Web Edition
+# Date created = 21:48:38 September 12, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.0"
+DATE = "21:48:38 September 12, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "pong3"
diff --git a/hardware/pong3.qsf b/hardware/pong3.qsf
new file mode 100644
index 0000000..0523c4d
--- /dev/null
+++ b/hardware/pong3.qsf
@@ -0,0 +1,151 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Web Edition
+# Date created = 21:48:38 September 12, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# pong3.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C8Q208C8
+set_global_assignment -name TOP_LEVEL_ENTITY pong3
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:48:38 SEPTEMBER 12, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 208
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_location_assignment PIN_40 -to seg[6]
+set_location_assignment PIN_37 -to seg[5]
+set_location_assignment PIN_43 -to seg[4]
+set_location_assignment PIN_44 -to seg[3]
+set_location_assignment PIN_39 -to seg[2]
+set_location_assignment PIN_35 -to seg[1]
+set_location_assignment PIN_34 -to seg[0]
+set_location_assignment PIN_23 -to clk
+set_location_assignment PIN_27 -to rst_n
+set_location_assignment PIN_92 -to sdram_addr[12]
+set_location_assignment PIN_90 -to sdram_addr[11]
+set_location_assignment PIN_75 -to sdram_addr[10]
+set_location_assignment PIN_89 -to sdram_addr[9]
+set_location_assignment PIN_88 -to sdram_addr[8]
+set_location_assignment PIN_87 -to sdram_addr[7]
+set_location_assignment PIN_86 -to sdram_addr[6]
+set_location_assignment PIN_84 -to sdram_addr[5]
+set_location_assignment PIN_82 -to sdram_addr[4]
+set_location_assignment PIN_81 -to sdram_addr[3]
+set_location_assignment PIN_80 -to sdram_addr[2]
+set_location_assignment PIN_77 -to sdram_addr[1]
+set_location_assignment PIN_76 -to sdram_addr[0]
+set_location_assignment PIN_74 -to sdram_ba[1]
+set_location_assignment PIN_72 -to sdram_ba[0]
+set_location_assignment PIN_69 -to sdram_cas_n
+set_location_assignment PIN_46 -to sdram_cke
+set_location_assignment PIN_47 -to sdram_clk
+set_location_assignment PIN_45 -to sdram_cs_n
+set_location_assignment PIN_94 -to sdram_dq[15]
+set_location_assignment PIN_95 -to sdram_dq[14]
+set_location_assignment PIN_96 -to sdram_dq[13]
+set_location_assignment PIN_97 -to sdram_dq[12]
+set_location_assignment PIN_99 -to sdram_dq[11]
+set_location_assignment PIN_101 -to sdram_dq[10]
+set_location_assignment PIN_102 -to sdram_dq[9]
+set_location_assignment PIN_103 -to sdram_dq[8]
+set_location_assignment PIN_57 -to sdram_dq[7]
+set_location_assignment PIN_58 -to sdram_dq[6]
+set_location_assignment PIN_59 -to sdram_dq[5]
+set_location_assignment PIN_60 -to sdram_dq[4]
+set_location_assignment PIN_61 -to sdram_dq[3]
+set_location_assignment PIN_63 -to sdram_dq[2]
+set_location_assignment PIN_64 -to sdram_dq[1]
+set_location_assignment PIN_67 -to sdram_dq[0]
+set_location_assignment PIN_104 -to sdram_dqm[1]
+set_location_assignment PIN_56 -to sdram_dqm[0]
+set_location_assignment PIN_70 -to sdram_ras_n
+set_location_assignment PIN_68 -to sdram_we_n
+set_location_assignment PIN_41 -to seg[7]
+set_location_assignment PIN_160 -to dm9000_cmd
+set_location_assignment PIN_165 -to dm9000_cs_n
+set_location_assignment PIN_144 -to dm9000_data[15]
+set_location_assignment PIN_145 -to dm9000_data[14]
+set_location_assignment PIN_146 -to dm9000_data[13]
+set_location_assignment PIN_147 -to dm9000_data[12]
+set_location_assignment PIN_149 -to dm9000_data[11]
+set_location_assignment PIN_150 -to dm9000_data[10]
+set_location_assignment PIN_151 -to dm9000_data[9]
+set_location_assignment PIN_152 -to dm9000_data[8]
+set_location_assignment PIN_135 -to dm9000_data[7]
+set_location_assignment PIN_134 -to dm9000_data[6]
+set_location_assignment PIN_138 -to dm9000_data[5]
+set_location_assignment PIN_137 -to dm9000_data[4]
+set_location_assignment PIN_141 -to dm9000_data[3]
+set_location_assignment PIN_139 -to dm9000_data[2]
+set_location_assignment PIN_143 -to dm9000_data[1]
+set_location_assignment PIN_142 -to dm9000_data[0]
+set_location_assignment PIN_162 -to dm9000_rd_n
+set_location_assignment PIN_163 -to dm9000_wr_n
+set_location_assignment PIN_164 -to dm9000_rst_n
+set_location_assignment PIN_161 -to dm9000_int
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SEARCH_PATH db/ip/my_sys/ -tag from_archive
+set_global_assignment -name SEARCH_PATH db/ip/my_sys/submodules/ -tag from_archive
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_108 -to vga_red[0]
+set_location_assignment PIN_113 -to vga_red[1]
+set_location_assignment PIN_112 -to vga_red[2]
+set_location_assignment PIN_128 -to vga_hs
+set_location_assignment PIN_115 -to vga_green[0]
+set_location_assignment PIN_114 -to vga_green[1]
+set_location_assignment PIN_117 -to vga_green[2]
+set_location_assignment PIN_116 -to vga_blue[0]
+set_location_assignment PIN_127 -to vga_blue[1]
+set_location_assignment PIN_118 -to vga_blue[2]
+set_location_assignment PIN_133 -to vga_vs
+
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+
+set_global_assignment -name VERILOG_FILE DM9000A/hdl/DM9000A_IF.v
+set_global_assignment -name VERILOG_FILE GPU/hdl/GPU_IF.v
+set_global_assignment -name PIN_FILE pong3.pin
+set_global_assignment -name VERILOG_FILE pong3.v
+set_global_assignment -name QSYS_FILE my_sys.qsys
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/hardware/pong3.v b/hardware/pong3.v
new file mode 100644
index 0000000..0328dcc
--- /dev/null
+++ b/hardware/pong3.v
@@ -0,0 +1,112 @@
+module pong3(
+ clk,
+ rst_n,
+
+ sdram_clk ,//connected to the CLK port of SDRAM
+ sdram_cke ,//connected to the CKE port of SDRAM
+ sdram_cs_n ,//connected to the CS_n port of SDRAM
+ sdram_ras_n ,//connected to the RAS_n port of SDRAM
+ sdram_cas_n ,//connected to the CAS_n port of SDRAM
+ sdram_we_n ,//connected to the WE_n port of SDRAM
+ sdram_ba ,//connected to the BA port of SDRAM
+ sdram_addr ,//connected to the ADDR port of SDRAM
+ sdram_dqm ,//connected to the DQM port of SDRAM
+ sdram_dq ,//connected to the DQ port of SDRAM
+
+ dm9000_int ,
+ dm9000_rst_n,
+ dm9000_cs_n ,
+ dm9000_cmd ,
+ dm9000_rd_n ,
+ dm9000_wr_n ,
+ dm9000_data ,
+
+ vga_hs,
+ vga_vs,
+ vga_red,
+ vga_green,
+ vga_blue,
+
+ seven_seg
+ );
+
+ input clk;
+ input rst_n;
+
+ output sdram_clk ;
+ output sdram_cke ;
+ output sdram_cs_n ;
+ output sdram_ras_n;
+ output sdram_cas_n;
+ output sdram_we_n ;
+ output [ 1 : 0] sdram_ba ;
+ output [12 : 0] sdram_addr ;
+ output [ 1 : 0] sdram_dqm ;
+ inout [15 : 0] sdram_dq ;
+
+ input dm9000_int ;
+ output dm9000_rst_n;
+ output dm9000_cs_n ;
+ output dm9000_cmd ;
+ output dm9000_rd_n ;
+ output dm9000_wr_n ;
+ inout [15:0] dm9000_data ;
+
+ output [ 7:0] seven_seg;
+
+
+ output vga_hs;
+ output vga_vs;
+ output [2:0] vga_red;
+ output [2:0] vga_green;
+ output [2:0] vga_blue;
+
+
+ wire sclk;
+
+
+ pll u_pll(
+ .inclk0(clk ),
+ .c0 (sclk ),
+ .c1 (sdram_clk)
+ );
+
+
+
+ my_sys u_my_sys(
+ .reset_reset_n (rst_n ),
+ .clk_clk (sclk ),
+ .sdram_0_wire_addr (sdram_addr ),
+ .sdram_0_wire_ba (sdram_ba ),
+ .sdram_0_wire_cas_n(sdram_cas_n),
+ .sdram_0_wire_cke (sdram_cke ),
+ .sdram_0_wire_cs_n (sdram_cs_n ),
+ .sdram_0_wire_dq (sdram_dq ),
+ .sdram_0_wire_dqm (sdram_dqm ),
+ .sdram_0_wire_ras_n(sdram_ras_n),
+ .sdram_0_wire_we_n (sdram_we_n ),
+ .pio_0_d_export (SEG ),
+
+
+ .gpu_0_vga_red(vga_red),
+ .gpu_0_vga_green(vga_green),
+ .gpu_0_vga_blue(vga_blue),
+ .gpu_0_vga_hs(vga_hs),
+ .gpu_0_vga_vs(vga_vs),
+ .gpu_0_vga_clk(clk),
+
+ .dm9000a_0_conduit_end_iOSC_50 ( ),
+ .dm9000a_0_conduit_end_ENET_DATA (dm9000_data ),
+ .dm9000a_0_conduit_end_ENET_CMD (dm9000_cmd ),
+ .dm9000a_0_conduit_end_ENET_RD_N (dm9000_rd_n ),
+ .dm9000a_0_conduit_end_ENET_WR_N (dm9000_wr_n ),
+ .dm9000a_0_conduit_end_ENET_CS_N (dm9000_cs_n ),
+ .dm9000a_0_conduit_end_ENET_RST_N(dm9000_rst_n),
+ .dm9000a_0_conduit_end_ENET_INT (dm9000_int ),
+ .dm9000a_0_conduit_end_ENET_CLK ( )
+ );
+
+
+
+
+endmodule
--
cgit v1.2.3