From fb7925518f22199dd55fb3e204fb609affe7f4cd Mon Sep 17 00:00:00 2001 From: Keir Fraser Date: Tue, 29 Sep 2009 11:27:53 +0100 Subject: vmx: add the support of XSAVE/XRSTOR to VMX guest XSAVE/XRSTOR manages the existing and future processor extended states on x86 architecture. The XSAVE/XRSTOR infrastructure is defined in Intel SDMs: http://www.intel.com/products/processor/manuals/ The patch uses the classical CR0.TS based algorithm to manage the states on context switch. At present, we know 3 bits in the XFEATURE_ENABLED_MASK: FPU, SSE and YMM. YMM is defined in Intel AVX Programming Reference: http://software.intel.com/sites/avx/ Signed-off-by: Dexuan Cui --- xen/include/asm-x86/hvm/vcpu.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'xen/include/asm-x86/hvm/vcpu.h') diff --git a/xen/include/asm-x86/hvm/vcpu.h b/xen/include/asm-x86/hvm/vcpu.h index cd24177232..cc97de490a 100644 --- a/xen/include/asm-x86/hvm/vcpu.h +++ b/xen/include/asm-x86/hvm/vcpu.h @@ -47,6 +47,15 @@ struct hvm_vcpu { */ unsigned long hw_cr[5]; + /* + * The save area for Processor Extended States and the bitmask of the + * XSAVE/XRSTOR features. They are used by: 1) when a vcpu (which has + * dirtied FPU/SSE) is scheduled out we XSAVE the states here; 2) in + * #NM handler, we XRSTOR the states we XSAVE-ed; + */ + void *xsave_area; + uint64_t xfeature_mask; + struct vlapic vlapic; s64 cache_tsc_offset; u64 guest_time; -- cgit v1.2.3