From 4b272d61e8ac507ec98d075d41b56eb9ff83b596 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 3 Sep 2013 16:00:52 +0200 Subject: pl011: preserve RTS and DTR signal on UART init Although we do not support hardware flow control in the Xen driver for the PL011 UART, the other end may be configured to use it. In this case it waits in vain for the RTS signal to be asserted by the host and will never transmit any characters. So we leave RTS and DTR as they had been setup before. This fixes the UART input on Calxeda Midway, which uses hardware flow control for the serial-over-LAN functionality. Signed-off-by: Andre Przywara Acked-by: Ian Campbell --- xen/drivers/char/pl011.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'xen/drivers') diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 3ec6e109d7..3386e2bc28 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -85,6 +85,7 @@ static void __init pl011_init_preirq(struct serial_port *port) { struct pl011 *uart = port->uart; unsigned int divisor; + unsigned int cr; /* No interrupts, please. */ pl011_write(uart, IMSC, 0); @@ -120,8 +121,10 @@ static void __init pl011_init_preirq(struct serial_port *port) pl011_write(uart, IMSC, 0); pl011_write(uart, ICR, ALLI); - /* Enable the UART for RX and TX; no flow ctrl */ - pl011_write(uart, CR, RXE | TXE | UARTEN); + /* Enable the UART for RX and TX; keep RTS and DTR */ + cr = pl011_read(uart, CR); + cr &= RTS | DTR; + pl011_write(uart, CR, cr | RXE | TXE | UARTEN); } static void __init pl011_init_postirq(struct serial_port *port) -- cgit v1.2.3