From b8131747e2e39cc5ab147586b70a5464bd1c8ed5 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Mon, 26 Aug 2013 12:48:01 +0200 Subject: x86: correct public header's documentation of PAT MSR settings The first (PAT6) column was wrong across the board, and the column for PAT7 was missing altogether. Signed-off-by: Jan Beulich Acked-by: Keir Fraser master commit: 3829655bd3ad2b1150bd94955fc6988dec6b98f2 master date: 2013-08-23 09:23:24 +0200 --- xen/include/public/xen.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index b2f6c507b9..5f40e6002c 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -276,15 +276,15 @@ DEFINE_XEN_GUEST_HANDLE(xen_pfn_t); * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of * pages instead of using MTRRs. * - * The PAT MSR is as follow (it is a 64-bit value, each entry is 8 bits): - * PAT4 PAT0 - * +---+----+----+----+-----+----+----+ - * WC | WC | WB | UC | UC- | WC | WB | <= Linux - * +---+----+----+----+-----+----+----+ - * WC | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) - * +---+----+----+----+-----+----+----+ - * WC | WP | WC | UC | UC- | WT | WB | <= Xen - * +---+----+----+----+-----+----+----+ + * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): + * PAT4 PAT0 + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) + * +-----+-----+----+----+----+-----+----+----+ + * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen + * +-----+-----+----+----+----+-----+----+----+ * * The lookup of this index table translates to looking up * Bit 7, Bit 4, and Bit 3 of val entry: -- cgit v1.2.3