From 28f9c24f07eb2077210c80fbb36952df1b25966b Mon Sep 17 00:00:00 2001 From: Yang Zhang Date: Thu, 8 Aug 2013 10:36:22 +0200 Subject: Nested VMX: Flush TLBs and Caches if paging mode changed According to SDM, if paging mode is changed, then whole TLBs and caches will be flushed. This is missed in nested handle logic. Also this fixed the issue that 64 bits windows cannot boot up on top of L1 kvm. Signed-off-by: Yang Zhang Acked-by: Keir Fraser master commit: e1ab5c77b44b7bd835a2c032fa4963b36545fdb3 master date: 2013-08-06 17:22:35 +0200 --- xen/arch/x86/mm/paging.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c index ca879f971f..37429757d4 100644 --- a/xen/arch/x86/mm/paging.c +++ b/xen/arch/x86/mm/paging.c @@ -828,6 +828,7 @@ void paging_update_nestedmode(struct vcpu *v) else /* TODO: shadow-on-shadow */ v->arch.paging.nestedmode = NULL; + hvm_asid_flush_vcpu(v); } void paging_write_p2m_entry(struct p2m_domain *p2m, unsigned long gfn, -- cgit v1.2.3