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* x86/hvm: mark save/restore registration code __initJan Beulich2012-09-141-1/+2
| | | | | Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* In most of the codebase, use CONFIG_X86 in place of __i386__||__x86_64__Keir Fraser2012-09-121-1/+1
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* xen: Remove x86_32 build target.Keir Fraser2012-09-121-1/+1
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* remove ia64Jan Beulich2012-04-031-2/+0
| | | | | | | | | | | It retains IA64-specific bits in code imported from elsewhere (e.g. ACPI, EFI) as well as in the public headers. It also doesn't touch the tools, mini-os, and unmodified_drivers sub-trees. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* amd iommu: Add iommu emulation for hvm guestWei Wang2012-01-121-0/+1
| | | | | | | | | | | | | | ATS device driver that support PASID [1] and PRI [2] capabilites needs to work with iommu driver in guest OS. We have to expose iommu functionality to HVM guest, if we want assign ATS device to it. A new hypervisor mmio handler is added to intercept iommu mmio accesses from guest. Signed-off-by: Wei Wang <wei.wang2@amd.com> [1] http://www.pcisig.com/specifications/pciexpress/specifications/ECN-PASID-ATS-2011-03-31.pdf [2] http://www.pcisig.com/members/downloads/specifications/iov/ats_r1.1_26Jan09.pdf Committed-by: Jan Beulich <jbeulich@suse.com>
* replace d->nr_pirqs sized arrays with radix treeJan Beulich2011-06-231-14/+23
| | | | | | | | | | | | | | | With this it is questionable whether retaining struct domain's nr_pirqs is actually necessary - the value now only serves for bounds checking, and this boundary could easily be nr_irqs. Note that ia64, the build of which is broken currently anyway, is only being partially fixed up. v2: adjustments for split setup/teardown of translation data v3: re-sync with radix tree implementation changes Signed-off-by: Jan Beulich <jbeulich@novell.com>
* Rename inj_msi -> inject_msiKeir Fraser2011-05-261-1/+1
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* x86: Add a new operation in HVMOP to inject emulated MSI.Wei Liu2011-05-261-0/+2
| | | | | | | | | | | The original vmsi_deliver is renamed to vmsi_deliver_pirq. New vmsi_deliver is dedicated to the actually delivering. Original HVMOP number is unchanged. New operation is numbered 16 and enclosed by (__XEN__) and (__XEN_TOOLS__). Signed-off-by: Wei Liu <liuw@liuw.name> Signed-off-by: Keir Fraser <keir@xen.org>
* x86: fix macro names typo in VMSI code (GLFAGS->GFLAGS)Wei Liu2011-05-261-2/+2
| | | | Signed-off-by: Wei Liu <liuw@liuw.name>
* xen: Include headers that are actually needed, drop everything else.Christoph Egger2011-05-201-1/+1
| | | | Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* Revert 23295:4891f1f41ba5 and 23296:24346f749826Keir Fraser2011-05-021-25/+14
| | | | | | Fails current lock checking mechanism in spinlock.c in debug=y builds. Signed-off-by: Keir Fraser <keir@xen.org>
* replace d->nr_pirqs sized arrays with radix treeJan Beulich2011-05-011-14/+25
| | | | | | | | | | | | | | | With this it is questionable whether retaining struct domain's nr_pirqs is actually necessary - the value now only serves for bounds checking, and this boundary could easily be nr_irqs. Another thing to consider is whether it's worth storing the pirq number in struct pirq, to avoid passing the number and a pointer to quite a number of functions. Note that ia64, the build of which is broken currently anyway, is only partially fixed up. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* hvm: infrastructure for backwards-compatible loadingGeorge Dunlap2011-04-061-6/+12
| | | | | | | | | | | | | | | | | | | | | | The hvm_save code is used to save and restore hypervisor-related hvm state, either for classic save/restore, or for migration (including remus). This is meant to be backwards-compatible across some hypervisor versions; but if it does change, there is no way to handle the old format as well as the new. This patch introduces the infrastructure to allow a single older version ("compat") of any given "save type" to be defined, along with a function to turn the "old" version into the "new" version. If the size check fails for the "normal" version, it will check the "compat" version, and if it matches, will read the old entry and call the conversion function. This patch involves some preprocessor hackery, but I'm only extending the hackery that's already there. Signed-off-by: George Dunlap <george.dunlap@eu.citrix.com> Acked-by: Tim Deegan <Tim.Deegan@citrix.com> Committed-by: Tim Deegan <Tim.Deegan@citrix.com>
* hvm save: Introduce hvm_load_entry_zeroextend().Keir Fraser2010-12-151-6/+11
| | | | | | | | | | In certain cases this will allow us to load old HVM save images where an HVM saved chunk has subsequently been extended with new fields. Rather than fail to load the chunk, we can pad the extended structure with zeroes, if the caller knows how to handle that. Signed-off-by: Keir Fraser <keir@xen.org> Acked-by: Tim Deegan <Tim.Deegan@citrix.com>
* hvm save: Move some inline functions into common/hvm/save.cKeir Fraser2010-12-151-62/+24
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* Move tasklet implementation into its own source files.Keir Fraser2010-04-191-1/+1
| | | | | | | | This is preparation for implementing tasklets in vcpu context rather than softirq context. There is no change to the implementation of tasklets in this patch. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: Revert Cset 20334:dcc5d5d954e9Keir Fraser2010-01-261-3/+1
| | | | | | | Recording old MSI info doesn't solve all the corner cases when guest's irq migration occurs. Signed-off-by : Xiantao Zhang <xiantao.zhang@intel.com>
* VT-d: improve RMRR region handlingKeir Fraser2009-12-221-0/+7
| | | | | | | | | | | | | | | | | | This patch improves RMRR regions handling as follows: 1) Get rid of duplicated RMRR mapping: different devices may share the same RMRR regions, when they are assigned to the same guest, it only need to map the same RMRR region once because RMRR region must be identity mapped. Add an array of mapped RMRRs to achieve this. 2) Needn't call domain_context_mapping to map the device again in iommu_prepare_rmrr_dev, and change iommu_prepare_rmrr_dev to rmrr_identity_mapping which is more suitable. 3) A device may have more than one RMRR regions, remove "break" in intel_iommu_add_device to let it map all RMRR regions of the device. Signed-off-by: Weidong Han <Weidong.han@intel.com>
* VT-d: per-iommu domain-idKeir Fraser2009-12-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, xen uses shared iommu domain-id across all the VT-d units in the platform. The number of iommu domain-ids (NR_DID, e.g. 256) supported by each VT-d unit is reported in Capability register. The limitation of current implementation is it only can support at most NR_DID domains with VT-d in the entire platform, even though the platform can support N * NR_DID (where N is the number of VT-d units). Imagine a platform with several SR_IOV NICs, and each NIC supports 128 VFs. It possibly beyond the NR_DID. This patch implements iommu domain-id management per iommu (VT-d unit), hence solves above limitation. It removes the global domain-id bitmap, instead use domain-id bitmap in struct iommu, and also involve an array to map guest domain-id and iommu domain-id, which is used to iommu domain-id when flush context cache or IOTLB. When a device is assigned to a guest, choose an available iommu domain-id from the device's iommu, and map guest domain id to the domain-id mapping array. When a device is deassigned from a guest, clear the domain-id bit in domain-id bitmap and clear the corresponding entry in domain-id map array if there is no other devices under the same iommu owned by the guest. Signed-off-by: Weidong Han <weidong.han@intel.com>
* Miscellaneous data placement adjustmentsKeir Fraser2009-10-281-1/+1
| | | | | | | Make various data items const or __read_mostly where possible/reasonable. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: vMSI: Fix msi irq affinity issue for hvm guest.Keir Fraser2009-10-191-1/+3
| | | | | | | | | | | There is a race between guest setting new vector and doing EOI on old vector. Once guest sets new vector before its doing EOI on vector, when guest does eoi, hypervisor may fail to find the related pirq, and hypervisor may miss to EOI real vector and leads to system hang. We may need to add a timer for each pirq interrupt source to avoid host hang, but this is another topic, and will be addressed later. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
* ia64: Fix build for xen/ia64Keir Fraser2009-09-251-0/+10
| | | | | | | Define the related dummy functions and move the macros as public to fix the build issue. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
* x86: Make assigned devices' interrupts delivery to right vcpu.Keir Fraser2009-09-251-0/+1
| | | | | | | | | | | | | | | | | | | | This patch targets for reducing IPIs when delivery VT-d's devices' intrs to target vcpus. According to the experiments leveraging 10G Oplin NIC card, CPU utilization can reduce 5%-6% and NIC's bandwidth keeps unchanged through testings. And this patch can always benefit UP guests with MSI-capable devices assigned and SMP guests whose lapic's destination mode is physical mode. And also it can benefit SMP guests whose lapic's dest_mode is logical mode but only one destination is specified. So it should cover major cases in real environment. Currenlty, this patch intercepts the programming for MSI intr status, and caculate the destination id for the pirq when do the programming in advance. When vcpu migratio n occurs or guest re-programe MSI status, it checks that whether needs to set the corresponding pirq's affinity of assigned devices and make vcpu's affinity and pirq's consistent to reduce the IPIs eventually. Signed-off-by : Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com>
* iommu: Fix pirq conflict issue when guest adopts per-cpu vector.Keir Fraser2009-09-181-1/+0
| | | | | | | | | | | Latest Linux and Windows may adopt per-cpu vector instead of global vector, so same vector in different vcpu may correspond to different interrupt sources. That is to say, vector and pirq should be 1:n mapping, and the array msi_gvec_pirq can't meet the mapping requirement, so need to improve the related logic, otherwise it may introduce strange issues. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
* amd iommu: Remove a useless flag and fix I/O page fault for hvmKeir Fraser2009-09-071-1/+0
| | | | | | passthru devices. Signed-off-by: Wei Wang <wei.wang2@amd.com>
* x86: Change Xen hypervisor's interrupt infrastructureKeir Fraser2009-08-191-1/+1
| | | | | | | | | | | | | | from vector-based to IRQ-based. In per-cpu vector environment, vector space changes to multi-demension resource, so vector number is not appropriate to index irq_desc which stands for unique interrupt source. As Linux does, irq number is chosen to index irq_desc. This patch changes vector-based interrupt infrastructure to irq-based one. Mostly, it follows upstream linux's changes, and some parts are adapted for Xen. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
* passthrough: use tasklet to deliver interruptsKeir Fraser2009-07-281-2/+2
| | | | | | | | | This patch enables delivery of interrupts even if the VCPU#0 is halted. Note: the changes to softirq.{ch} are needed for ia64 build. Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
* x86: eliminate hard-coded NR_IRQSKeir Fraser2009-05-271-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... splitting it into global nr_irqs (determined at boot time) and per- domain nr_pirqs (derived from nr_irqs and a possibly command line specified value, which probably should later become a per-domain config setting). This has the (desirable imo) side effect of reducing the size of struct hvm_irq_dpci from requiring an order-3 page to order-2 (on x86-64), which nevertheless still is too large. However, there is now a variable size bit array on the stack in pt_irq_time_out() - while for the moment this probably is okay, it certainly doesn't look nice. However, replacing this with a static (pre-)allocation also seems less than ideal, because that would require at least min(d->nr_pirqs, NR_VECTORS) bit arrays of d->nr_pirqs bits, since this bit array is used outside of the serialized code region in that function, and keeping the domain's event lock acquired across pirq_guest_eoi() doesn't look like a good idea either. The IRQ- and vector-indexed arrays hanging off struct hvm_irq_dpci could in fact be changed further to dynamically use the smaller of the two ranges for indexing, since there are other assumptions about a one-to-one relationship between IRQs and vectors here and elsewhere. Additionally, it seems to me that struct hvm_mirq_dpci_mapping's digl_list and gmsi fields could really be overlayed, which would yield significant savings since this structure gets always instanciated in form of d->nr_pirqs (as per the above could also be the smaller of this and NR_VECTORS) dimensioned arrays. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* passthrough: allow pass-through devices to share virtual GSIKeir Fraser2009-03-111-2/+2
| | | | | | | | | | | | | | Allow multiple pass-through devices to use the same guest_gsi. The motivation for this is: * Allow multi-function devices to be passed through as multi-function devices * Allow more than two pass-through devices. - This will place more contention on the GSI-space, and allocation becomes a lot simpler if GSI sharing is allowed. Signed-off-by: Simon Horman <horms@verge.net.au>
* Add a new domctl to get a single record from the HVM save contextKeir Fraser2009-02-051-0/+2
| | | | Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* AMD IOMMU: Allocate I/O pagetable from domheap instead of xenheapKeir Fraser2009-01-091-1/+1
| | | | Signed-off-by: Wei Wang <wei.wang2@amd.com>
* passthrough: MSI-INTx translation for HVMKeir Fraser2009-01-081-1/+10
| | | | | | | | The patch adds a new type of pt_irq: PT_IRQ_TYPE_MSI_TRANSLATE. With it, guest dpci irq can now use msi as the underlying pirq while injected as INTx irq. Signed-off-by: Qing He <qing.he@intel.com>
* Remove NR_PIRQS definition -- always use NR_IRQS.Keir Fraser2008-11-141-1/+1
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* Use hvm_dirq_assist() to replace {vmx,svm}_dirq_assist().Keir Fraser2008-10-211-0/+1
| | | | | | | Do not compile some IA64 MSI-related parts. Signed-off-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* Add a new file xen/include/xen/hvm/irq.h to share common definitions.Keir Fraser2008-10-201-0/+98
| | | | | Signed-off-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* iommu: Cleanups to some header files.Keir Fraser2008-10-131-9/+3
| | | | | Signed-off-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* PCI device register/unregister + pci_dev cleanupsKeir Fraser2008-07-041-5/+0
| | | | | | | | | | Move pci_dev lists from hvm to arch_domain Move the pci_dev list from hvm to arch_domain since PCI devs are no longer hvm specific. Also removed locking for pci_dev lists. Will reintroduce them later. Signed-off-by: Espen Skoglund <espen.skoglund@netronome.com>
* VT-d: flush iotlb of selective iommu when a domain's VT-d table is changedKeir Fraser2008-05-261-0/+1
| | | | | | | When a domain's VT-d table is changed, only the iommus under which the domain has assigned devices need to be flushed. Signed-off-by: Yang, Xiaowei <xiaowei.yang@intel.com>
* Enable IOMMU for PV guestsKeir Fraser2008-05-241-0/+3
| | | | | | | | | Introduce 'iommu_pv' boot parameter (default off). Added a need_iommu flag which is set if guest has PCI devices assigned. IOMMU page tables are populated with current guest memory when IOMMU is first enabled for the guest. Signed-off-by: Espen Skoglund <espen.skoglund@netronome.com>
* VT-d: Allocates page table pgd, root_entry, iremap and qinval fromKeir Fraser2008-04-101-1/+1
| | | | | | | domheap rather than xenheap, and get rid of structure page_info in iommu.c. Signed-off-by: Weidong Han <weidong.han@intel.com>
* AMD IOMMU: Defer IO pagetable construction until device assignmentKeir Fraser2008-04-041-1/+2
| | | | | | | | | | During HVM domain creation, I/O page tables are filled by coping p2m entries from p2m table, which is a useless step for non-passthru domain. This patch defers I/O page table construction until the moment of device assignment. In case that pci devices are never assigned or hot plugged, the unnecessary duplication will be avoided. Signed-off-by: Wei Wang <wei.wang2@amd.com>
* Revert all usages of gcc's __extension__ keyword, and instead assertKeir Fraser2008-03-311-0/+1
| | | | | | | | | | | that our headers are not built with __GNUC__ and __STRICT_ANSI__. __extension__ had some weird (and buggy) behaviours when nested which make it a risky proposition for general usage in our header files. Better to disallow -ansi, -std=c99, and similar gcc options when building against Xen headers. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* Move iommu code to arch-generic locations, and also clean up some VT-d code.Keir Fraser2008-03-171-0/+56
| | | | Signed-off-by: Weidong Han <weidong.han@intel.com>
* hvm: Clean up buf_ioreq handling.Keir Fraser2007-11-081-2/+2
| | | | | | Also, disable stdvga caching on hvm save/restore, as the shadow vga state is not preserved. Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: Split save.c into arch generic/specific part.Keir Fraser2007-10-181-0/+5
| | | | | | | struct hvm_save_header is arch specific so that arch specific part of hvm_save()/hvm_load() are moved into arch_hvm_save()/acrh_hvm_load() Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
* Split asm-x86/hvm/support into arch generic part and x86 specific part.Keir Fraser2007-10-181-0/+156
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
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