aboutsummaryrefslogtreecommitdiffstats
path: root/xen/include/asm-x86/io_apic.h
Commit message (Collapse)AuthorAgeFilesLines
* IOMMU: properly check whether interrupt remapping is enabledJan Beulich2013-03-251-1/+1
| | | | | | | | | | | | | | | | ... rather than the IOMMU as a whole. That in turn required to make sure iommu_intremap gets properly cleared when the respective initialization fails (or isn't being done at all). Along with making sure interrupt remapping doesn't get inconsistently enabled on some IOMMUs and not on others in the VT-d code, this in turn allowed quite a bit of cleanup on the VT-d side (if desired, that cleanup could of course be broken out into a separate patch). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: "Zhang, Xiantao" <xiantao.zhang@intel.com>
* x86: Remove unused 'sis_apic_bug' variable. It was only used on x86_32.Keir Fraser2012-09-121-5/+0
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* xen: Remove x86_32 build target.Keir Fraser2012-09-121-4/+0
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* IO-APIC: Prevent using EOI broadcast suppression if user specified ↵Andrew Cooper2012-02-231-0/+1
| | | | | | | | | | | | | | | ioapic_ack=new on the command line. Currently, if EOI broadcast suppression is advertised on the BSP LAPIC, Xen will discard any user specified option regarding IO-APIC ack mode. This patch introduces a check which prevents EOI Broadcast suppression from forcing the IO-APIC ack mode to old if the user has explicitly asked for the new ack mode on the command line. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Committed-by: Keir Fraser <keir@xen.org>
* VT-d: bind IRQs to CPUs local to the node the IOMMU is onJan Beulich2011-12-131-3/+0
| | | | | | | | | | | | | This extends create_irq() to take a node parameter, allowing the resulting IRQ to have its destination set to a CPU on that node right away, which is more natural than having to post-adjust this (and get e.g. a new IRQ vector assigned despite a fresh one was just obtained). All other callers of create_irq() pass NUMA_NO_NODE for the time being. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* IRQ Cleanup: rename nr_ioapic_registers to nr_ioapic_entriesKeir Fraser2011-09-301-1/+1
| | | | | | | | The name "nr_ioapic_registers" is wrong and actively misleading. The variable holds the number of redirection entries for each apic, which is two registers fewer than the total number of registers. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* IRQ: IO-APIC support End Of Interrupt for older IO-APICsAndrew Cooper2011-09-131-5/+0
| | | | | | | | | | | | | | | The old io_apic_eoi() function using the EOI register only works for IO-APICs with a version of 0x20. Older IO-APICs do not have an EOI register so line level interrupts have to be EOI'd by flipping the mode to edge and back, which clears the IRR and Delivery Status bits. This patch replaces the current io_apic_eoi() function with one which takes into account the version of the IO-APIC and EOI's appropriately. v2: make recursive call to __io_apic_eoi() to reduce code size. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* passthrough: don't use open coded IO-APIC accessesJan Beulich2011-08-161-0/+6
| | | | | | | | | | | | | This makes the respective functions quite a bit more legible. Since this requires fiddling with __ioapic_{read,write}_entry() anyway, make them and their wrappers have their argument types match those of __io_apic_{read,write}() (int -> unsigned int). No functional change intended. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* xen: remove extern function declarations from C files.Tim Deegan2011-05-261-0/+5
| | | | | | | | Move all extern declarations into appropriate header files. This also fixes up a few places where the caller and the definition had different signatures. Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
* x86: IO-APIC cleanupJan Beulich2011-03-091-1/+2
| | | | | | | | Remove unused and pointless bits from IO-APIC handling code. Move whatever possible into .init.*, and some data items into .data.read_mostly. Adjust some types. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: cleanup mpparse.cJan Beulich2011-03-091-0/+2
| | | | | | | | Remove unused and pointless bits from mpparse.c (and other files where they are related to it). Of what remains, move whatever possible into .init.*, and some data items into .data.read_mostly. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* Use bool_t for various boolean variablesKeir Fraser2010-12-241-1/+1
| | | | | | | | | | | ... decreasing cache footprint. As a prerequisite this requires making cmdline_parse() a little more flexible. Also remove a few variables altogether, and adjust sections annotations for several others. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Keir Fraser <keir@xen.org>
* x86: adjust other interrupt related section placementKeir Fraser2010-12-151-1/+0
| | | | | | | ... and remove some variables the value of which is never used altogether. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: delete not really used ioapic_renumber_irq variableKeir Fraser2010-10-241-1/+0
| | | | Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x2APIC: improve enabling logicKeir Fraser2010-07-051-0/+6
| | | | | | | | | | | | | | This patch masks PIC and IOAPIC RTE's before x2APIC enabling, unmask and restore them after x2APIC enabling. It also really enables interrupt remapping before x2APIC enabling instead of just checking interrupt remapping setting. This patch also handles all x2APIC configuration including BIOS settings and command line settings. Especially, it handles that BIOS hands over in x2APIC mode (when there is apic id > 255). It checks if x2APIC is already enabled by BIOS. If already enabled, it will disable interrupt remapping and queued invalidation first, then enable them again. Signed-off-by: Weidong Han <weidong.han@intel.com>
* iommu: Actually clear IO-APIC pins on boot and shutdown when used with an IOMMUKeir Fraser2009-12-161-3/+13
| | | | | | | | | | | | | | | | | | When booted with iommu=on, io_apic_read/write functions call into the interrupt remapping code to update the IRTEs. Unfortunately, on boot and shutdown, we really want clear_IO_APIC() to sanitize the actual IOAPIC RTE, and not just the bits that are active when interrupt remapping is enabled. This is particularly a problem on older versions of Xen which used the IOAPIC RTE as the canonical source for the IRTE index. In that case, clear_IO_APIC() actually causes whatever happens to be stored in the RTEs to be used as an IRTE index, which can come back and bite us in ioapic_guest_write() if we attempt to remove an interrupt that didn't actually exist. Current upstream appears less susceptible to errors since the IRTE index is stored in an array, but it's still a good idea to sanitize the IOAPIC state. Signed-off-by: Alex Williamson <alex.williamson@hp.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: enable directed EOIKeir Fraser2009-11-231-0/+5
| | | | | | | | | | | | This patch enables directed EOI on latest processor. With this, the broadcast of EOI would be suppressed upon LAPIC EOI, so VMM is required to perform a directed EOI to the IOxAPIC generating the interrupt by writting to its EOI register.(Pls. refer SDM 3A 10.5.5) This is useful for ioapic_ack_old to avoid the spurious interrupt storm, which is the reason why ioapic_ack_new is used. Signed-Off-By: Zhai Edwin <edwin.zhai@intel.com>
* x86: IRQ Migration logic enhancement.Keir Fraser2009-10-261-0/+9
| | | | | | | | | | | To programme MSI's addr/vector safely, delay irq migration operation before acking next interrupt. In this way, it should avoid inconsistent interrupts generation due to non-atomic writing addr and data registers about MSI. Port the logic from Linux and tailor it for Xen. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
* Scattered code arrangement cleanups.Keir Fraser2009-10-071-9/+0
| | | | | | | | - remove redundant declarations - add/move prototypes to headers - move things where they belong to Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
* vt-d: use 32-bit Destination ID when Interrupt Remapping with EIM isKeir Fraser2009-09-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enabled When x2APIC and Interrupt Remapping(IR) with EIM are enabled, we should use 32-bit Destination ID for IOAPIC and MSI. We implemented the IR support in xen by hooking the functions like io_apic_write(),io_apic_modify(), write_msi_message(), and as a result, in the hook functions in intremap.c, we can only see the 8-bit dest id rather the 32-bit id, so we can't set IR table Entry that requires a 32-bit dest id. To solve the issue throughly, we need find every place in io_apic.c and msi.c that could write ioapic RTE and and device's msi message and explicitly handle the 32-bit dest id carefully (namely, when genapic is x2apic, cpu_mask_to_apic could return a 32-bit value); and we have to change the iommu_ops->{.update_ire_from_apic, .update_ire_from_msi} interfaces. We may have to write an over-1000-LOC patch for this. Instead, we could use a workround: 1) for ioapic, in the struct IO_APIC_route_entry, we could use a new "dest32" to refer to the dest field; 2) for msi, in the struct msi_msg, we could add a new "u32 dest". And in intremap.c, if x2apic_enabled, we use the new names to refer to the dest fields. We can improve this in future. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* IOMMU: Add two generic functions to vendor neutral interfaceKeir Fraser2009-06-191-1/+1
| | | | | | | | | | | | Add 2 generic functions into the vendor neutral iommu interface, The reason is that from changeset 19732, there is only one global flag "iommu_enabled" that controls iommu enablement for both vtd and amd systems, so we need different code paths for vtd and amd iommu systems if this flag has been turned on. Also, the early checking of "iommu_enabled" in iommu_setup() is removed to prevent iommu functionalities from been disabled on amd systems. Signed-off-by: Wei Wang <wei.wang2@amd.com>
* x86: eliminate hard-coded NR_IRQSKeir Fraser2009-05-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... splitting it into global nr_irqs (determined at boot time) and per- domain nr_pirqs (derived from nr_irqs and a possibly command line specified value, which probably should later become a per-domain config setting). This has the (desirable imo) side effect of reducing the size of struct hvm_irq_dpci from requiring an order-3 page to order-2 (on x86-64), which nevertheless still is too large. However, there is now a variable size bit array on the stack in pt_irq_time_out() - while for the moment this probably is okay, it certainly doesn't look nice. However, replacing this with a static (pre-)allocation also seems less than ideal, because that would require at least min(d->nr_pirqs, NR_VECTORS) bit arrays of d->nr_pirqs bits, since this bit array is used outside of the serialized code region in that function, and keeping the domain's event lock acquired across pirq_guest_eoi() doesn't look like a good idea either. The IRQ- and vector-indexed arrays hanging off struct hvm_irq_dpci could in fact be changed further to dynamically use the smaller of the two ranges for indexing, since there are other assumptions about a one-to-one relationship between IRQs and vectors here and elsewhere. Additionally, it seems to me that struct hvm_mirq_dpci_mapping's digl_list and gmsi fields could really be overlayed, which would yield significant savings since this structure gets always instanciated in form of d->nr_pirqs (as per the above could also be the smaller of this and NR_VECTORS) dimensioned arrays. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: some assorted irq related cleanupsKeir Fraser2009-05-201-7/+0
| | | | Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86, ioapic: Fix S3 suspend error.Keir Fraser2009-03-011-4/+4
| | | | | | | Invoke ioapic_pm_state_alloc() earlier, thus avoiding check_lock() BUG_ON() in spin_lock(). Signed-off-by: Guanqun Lu <guanqun.lu@intel.com>
* Define a macro IO_APIC_ID() for x86.Keir Fraser2008-10-201-0/+2
| | | | | Signed-off-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* x86: Free MSI vector when a pirq is unmapped.Keir Fraser2008-10-081-0/+1
| | | | | Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* vtd: Fix check for interrupt remapping of ioapic RTEKeir Fraser2008-09-261-3/+6
| | | | | | | | | | | For IOAPIC interrupt remapping, it only needs to remap ioapci RTE, should not remap other IOAPIC registers, which are IOAPIC ID, VERSION and Arbitration ID. This patch adds the check for this and only remap ioapci RTE. Signed-off-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: Remove MSI boot parameter -- now always on.Keir Fraser2008-09-101-2/+0
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* vtd: Fix ioapic interrupt remappingKeir Fraser2008-08-261-1/+3
| | | | | | | | | | | | | Besides io_apic_write(), io_apic_modify() also writes to io apic RTE. This patch adds an intercept to remap interrupt in io_apic_modify(). In io_apic_read_remap_rte(), 'mask' value of RTE should not affect the return value, so remove its checking. Finally, remove panic() when index overflows. Instead, print error messages and report back the failure to upper level. Signed-off-by: Weidong Han <weidong.han@intel.com>
* x86: rename MSI optionKeir Fraser2008-07-241-0/+2
| | | | | | Also rename the variable and move its declaration to a header. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* iommu: make interrupt remapping more genericKeir Fraser2008-07-111-2/+2
| | | | Signed-off-by: Wei Wang <wei.wang2@amd.com>
* Move iommu code to arch-generic locations, and also clean up some VT-d code.Keir Fraser2008-03-171-1/+1
| | | | Signed-off-by: Weidong Han <weidong.han@intel.com>
* vt-d: Remap interrupt for passthru device if such HW is detected on VT-d ↵Keir Fraser2008-02-111-0/+5
| | | | | | platforms. Signed-off-by: Allen Kay <allen.m.kay@intel.com>
* x86: allow pv guests to disable TSC for applicationsKeir Fraser2007-10-291-1/+2
| | | | | | | | | | | | | | | | | Linux, under CONFIG_SECCOMP, has been capable of hiding the TSC from processes for quite a while. This patch enables this to actually work for pv kernels, by allowing them to control CR4.TSD (and, as a simple thing to do at the same time, CR4.DE). Applies cleanly only on top of the previously submitted debug register handling patch. Signed-off-by: Jan Beulich <jbeulich@novell.com> Also clean up CR4 and EFER handling, and hack-n-slash header file inclusion madness to get the tree building again. Signed-off-by: Keir Fraser <keir@xensource.com>
* Add suspend/resume to devices owned by Xen.kfraser@localhost.localdomain2007-06-111-0/+4
| | | | | | Signed-off-by: Ke Yu <ke.yu@intel.com> Signed-off-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Keir Fraser <keir@xensource.com>
* [XEN] Upgrade some platform files to Linux 2.6.17.13.kfraser@localhost.localdomain2006-09-191-0/+1
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* Propagate information about bad (or good) REGSEL registerkaf24@firebug.cl.cam.ac.uk2006-04-211-1/+5
| | | | | | | | | of chipset IO-APICs to Xen. If REGSEL is bad (some old SiS chipsets) then we have a slower read-modify-write routine. Loosely based on an original patch from Jan Beulich. Signed-off-by: Keir Fraser <keir@xensource.com>
* bitkeeper revision 1.1691.1.13 (42a767bfQ0_UVkV0FEMxkQeSluJPmA)kaf24@firebug.cl.cam.ac.uk2005-06-081-38/+0
| | | | | | | More irq changes: moving towards addressing irqs by vector rather than 'irq index'. Signed-off-by: Keir Fraser <keir@xensource.com>
* bitkeeper revision 1.1389.15.5 (4280e522q2MiQniUbfWd_2b5yEMlkA)kaf24@firebug.cl.cam.ac.uk2005-05-101-2/+0
| | | | | | | | Fix acknowledgement of level-triggered IOAPIC interrupts. This is a second checkin, after disentangling from aborted and utterly broken PCI-MSI changes. Signed-off-by: Keir Fraser <keir@xensource.com>
* bitkeeper revision 1.1389.15.4 (4280e2e1TW-3Y8iE13utT8fyuaozWA)kaf24@firebug.cl.cam.ac.uk2005-05-101-0/+38
| | | | | Cset exclude: kaf24@firebug.cl.cam.ac.uk|ChangeSet|20050510144837|42684
* bitkeeper revision 1.1389.15.2 (4280c9c5w05qWQmSXarelhI1f8FZkQ)kaf24@firebug.cl.cam.ac.uk2005-05-101-38/+0
| | | | | | | | | Fix level-triggered IOAPIC acknowledgement. Also a first pass at supporting PCI-MSI notifications in Xen. I think we can support these better with some interface changes in Xen. It's currently rather a kludge. Signed-off-by: Keir Fraser <keir@xensource.com>
* bitkeeper revision 1.1389.10.1 (427fa2d3ZV92f_ErvLuIzWbV1f67QA)kaf24@firebug.cl.cam.ac.uk2005-05-091-52/+96
| | | | | | | Phase 1 of upgrading platform code to be derived from Linux 2.6.11 rather than 2.4.x. Signed-off-by: Keir Fraser <keir@xensource.com>
* bitkeeper revision 1.1389.1.34 (42778a6aQ30Jj7E2TxzCF9ZtVpGMtw)kaf24@firebug.cl.cam.ac.uk2005-05-031-0/+2
| | | | | | | | | | | | | | | | | | | | | Move PCI device scanning to dom0. Enable ACPI in dom0. This should greatly reduce the complexity of xen and move the complexity of dealing with hardware bugs and workarounds etc to dom0. The ioapic local apic (and hence all the vectors) are owned by the hypervisor. Dom0 enables the ACPI interpreter, handles PCI and ACPI based interrupt routing. New hypercalls to assign vectors and for accessing the ioapic. Functionality not yet provided: o acpi=off to support machines with broken or no acpi support. o support for driver domains Signed-off-by: Arun Sharma <arun.sharma@intel.com> Signed-off-by: Asit Mallick <asit.k.mallick@intel.com>
* bitkeeper revision 1.1041.4.1 (40e49f12Fj3pygWG3LxLQ2tcwBx24A)kaf24@scramble.cl.cam.ac.uk2004-07-011-0/+1
| | | | | | Fix common files when compiled without CONFIG_SMP (some x86-specific files still don't work).
* bitkeeper revision 1.985 (40d54212AaOKN_5U41AzX44kVS3-7w)kaf24@scramble.cl.cam.ac.uk2004-06-201-1/+1
| | | | | Allow compilation of Xen with debug symbols.
* bitkeeper revision 1.952 (40c8935a3XSRdQfnx5RoO7XgaggvOQ)kaf24@scramble.cl.cam.ac.uk2004-06-101-0/+167
Towards x86_64 support. Merged a bunch of the existing x86_64 stuff back into a generic 'x86' architecture. Aim is to share as much as possible between 32- and 64-bit worlds.
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 06:17:34 +0000