| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | pl011: preserve RTS and DTR signal on UART init | Andre Przywara | 2013-09-03 | 1 | -0/+4 |
| | | | | | | | | | | | | | | Although we do not support hardware flow control in the Xen driver for the PL011 UART, the other end may be configured to use it. In this case it waits in vain for the RTS signal to be asserted by the host and will never transmit any characters. So we leave RTS and DTR as they had been setup before. This fixes the UART input on Calxeda Midway, which uses hardware flow control for the serial-over-LAN functionality. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Acked-by: Ian Campbell <ian.campbell@citrix.com> | ||||
| * | xen/arm: Use define instead of hardcoded value in debug-pl011 | Julien Grall | 2013-08-05 | 1 | -0/+1 |
| | | | | | | Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org> | ||||
| * | pl011: Move registers' definition in a separate file | Julien Grall | 2013-08-05 | 1 | -0/+80 |
| Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Tim Deegan <tim@xen.org> | |||||
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