| Commit message (Collapse) | Author | Age | Files | Lines |
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Checking the stored version doesn't tell us anything about the need to
apply the update (during resume, what is stored doesn't necessarily
match what is loaded).
Note that the check can be removed altogether because once switched to
use what was read from the CPU (uci->cpu_sig.rev, as used in the
subsequent pr_debug()), it would become redundant with the checks that
lead to microcode_update_match() returning the indication that an
update should be applied.
Note further that this was not an issue on APs since they start with
uci->mc.mc_intel being NULL.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Tested-by: Ben Guthro <ben@guthro.net>
Acked-by: Keir Fraser <keir@xen.org>
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Performance is not an issue with printk(), so let the function do
minimally more work and instead save a byte per affected format
specifier.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
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- memory was leaked on a CPU offline/online cycle (including S3)
- memory was leaked on AMD systems when microcode_update() ran a 2nd
time with the same data that was used on the first run
- microcode never got restored on APs during S3 resume (or post-boot
onlining of a CPU that was also online when microcode_update() first
ran [in the event the prior microcode update got lost intermediately,
which supposedly shouldn't happen]); this will still be the case when
no other online CPU has an identical signature (which however is now
consistent with bringing up such a CPU the very first time)
- resume was unimplemented in the AMD case
- there was a race between microcode_update_cpu() and
microcode_resume_cpu()
This also moves vendor specific type declarations to the vendor source
file and sets the stage for boot time microcode loading (i.e. without
Dom0 involvement).
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
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Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
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Make various data items const or __read_mostly where
possible/reasonable.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
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Signed-off-by: Jan Beulich <jbeulich@novell.com>
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When wakeup from S3, use per cpu microcode image to update cpu
microcode.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
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It's possible the data file has multiple matching ucode, we needn't to
update multiple times, just keep searching the latest version, and
update once.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
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Update microcode logic:
1. separate microcode_fini_cpu() into 2 level to avoid deadlock (when
fail at microcode_update_cpu);
2. cancel redundant collect_cpu_info at microcode.c level, use
relative function at microcode driver level;
3. separate microcode_resume_cpu from microcode_update_cpu, because
it's redundant (should only be called when S3 wakeup) and will block newer
microcode update when user update newer microcode.dat from user level
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
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Cancel redundant input parameter 'uci', since it can get from another
input parameter 'cpu' as index.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
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- Container header file holding the patches changed. Update to new
format.
- in cpu_request_microcode() move heap re-allocation & copy out of the
loop.
Side-effect: Remove limitation in only supporting fixed sized
microcode patches. Also simplifies code a lot.
- cleanup: use rdmsr and wrmsrl instead of inlined assembler
- pass ucode_cpu_info as arguments. Improves reentrancy.
- cleanup: simplify struct ucode_cpu_info and remove
get_matching_microcode hook. Side-effect: reduces kernel size.
- bugfix: fix xen kernel memory leak in error path. equiv_cpu_table
was not freed.
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
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Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
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(until allocations in irq context are fixed).
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
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Microcode update support for AMD CPUs Family10h and Family11h.
It is based on a patch for Linux which is on its way for 2.6.28.
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
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