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* x86 hvm: suspend platform timer emulation while its IRQ is maskedKeir Fraser2009-09-161-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of a timer which IRQ is masked from vcpu's timer list. It reduces the overhead of VM EXIT and context switch of vm. Also fixes a potential bug. (1) VCPU#0: mask the IRQ of a timer. (ex. vioapic.redir[2].mask=1) (2) VCPU#1: pt_timer_fn() is invoked by expiration of the timer. (3) VCPU#1: pt_update_irq() is called but does nothing by pt_irq_masked()==1. (4) VCPU#1: sleep by halt. (5) VCPU#0: unmask the IRQ of the timer. After that, no one wakes up the VCPU#1. IRQ of ISA is masked by: - PIC's IMR - IOAPIC's redir[0] - IOAPIC's redir[N].mask - LAPIC's LVT0 - LAPIC enabled/disabled IRQ of LAPIC timer is masked by: - LAPIC's LVTT - LAPIC disabled When above stuffs are changed, the corresponding vcpu is kicked and suspended timer emulation is resumed. In addition, a small bug fix in pt_adjust_global_vcpu_target(). Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
* x86 hvm: Allow delivery of legacy 8259 interrupts to VCPUs != 0.Keir Fraser2009-07-011-5/+3
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86_64: allow more vCPU-s per guestKeir Fraser2009-06-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Since the shared info layout is fixed, guests are required to use VCPUOP_register_vcpu_info prior to booting any vCPU beyond the traditional limit of 32. MAX_VIRT_CPUS, being an implemetation detail of the hypervisor, is no longer being exposed in the public headers. The tools changes are clearly incomplete (and done only so things would build again), and the current state of the tools (using scalar variables all over the place to represent vCPU bitmaps) very likely doesn't permit booting DomU-s with more than the traditional number of vCPU-s. Testing of the extended functionality was done with Dom0 (96 vCPU-s, as well as 128 vCPU-s out of which the kernel elected - by way of a simple kernel side patch - to use only some, resulting in a sparse bitmap). ia64 changes only to make things build, and build-tested only (and the tools part only as far as the build would go without encountering unrelated problems in the blktap code). Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86, hvm: gcc44 build fix.Keir Fraser2009-03-011-1/+1
| | | | | | | | | Broken constrain in inline asm. Bytewise access works with a, b, c, d registers only, thus "r" is wrong, it must be "q". gcc 4.4 tries to use the si register, which doesn't work and thus fails the build. From: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86 hvm: Xen interface and implementation for virtual S3Keir Fraser2008-05-201-3/+10
| | | | | | | Signed-off-by: Tian Kevin <kevin.tian@intel.com> Signed-off-by: Yu Ke <ke.yu@intel.com> Signed-off-by: Ke Liping <liping.ke@intel.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86, hvm: I/O emulation handlers return X86EMUL_* return codes.Keir Fraser2008-04-151-8/+4
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* hvm: Clean out save/restore debug tracing.Keir Fraser2008-04-091-28/+0
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86 vmx: Remove vmxassist.Keir Fraser2008-02-061-5/+0
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* hvm: Improve in-Xen PIO emulation to better handle string PIOKeir Fraser2008-01-121-37/+16
| | | | | instructions. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86, hvm: Config option to allow vmxassist to be disabled.Keir Fraser2007-11-241-1/+1
| | | | | | | | | hvmloader is modified to dynamically detect this, allowing possibility of optional full vmxassist replacement in 3.2 stable branch in future. Currently 'vmxassist=y' is not much use since no replacement is implemented. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* vt-d: Do dpci eoi outside of irq_lock.Keir Fraser2007-10-301-7/+7
| | | | | | | | | | | | | | | Deadlock may occur if do hvm_dpci_eoi() inside of irq_lock on MP platform. For example, there are two physical cpus. If interrupt is injected on cpu0, but vcpu is migrated to cpu1 and it does eoi inside of irq_lock, then IPI will be issued to cpu0. At the same time, cpu0 may have disabled irq and is acquiring the same irq_lock. In addition, current code cannot guarantee do hvm_dpci_eoi() inside of irq_lock when timeout. This patch does hvm_dpci_eoi() outside of irq_lock, and solves above problems. Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com> Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: Keir Fraser <keir@xensource.com>
* vt-d: Allow pass-through of shared interrupts.Keir Fraser2007-10-191-1/+2
| | | | | Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com> Signed-off-by: Kevin Tian <kevin.tian@intel.com>
* hvm: Re-jig event delivery logic to better integrate TPR management.Keir Fraser2007-10-011-1/+1
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* IRQ injection changes for HVM PCI passthru.kfraser@localhost.localdomain2007-09-181-2/+6
| | | | | Signed-off-by: Allen Kay <allen.m.kay@intel.com> Signed-off-by: Guy Zana <guy@neocleus.com>
* hvm: Support injection of virtual NMIs and clean up ExtInt handling in general.kfraser@localhost.localdomain2007-06-201-2/+1
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: Respect irqbase set by protected mode in mode switching with VMXAssist.kfraser@localhost.localdomain2007-06-081-1/+7
| | | | | | | | RHEL4U4 PAE SMP guest currently crashes, and we found changeset 15214 introduced it. This patch fixes it. Signed-off-by: Xin Li <xin.b.li@intel.com> Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* hvm vpic: Fix IRQ priority calculation in 8259 device model.kfraser@localhost.localdomain2007-03-161-2/+2
| | | | | | | The priority shift should be a right-rotation, not a left-rotation. From: Trolle Selander <trolle.selander@gmail.com> Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] Save/restore: dynamically calculate the size of the save bufferTim Deegan2007-02-071-1/+1
| | | | Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] Save/restore: clean up marshalling codeTim Deegan2007-01-311-12/+27
| | | | | | | | | | | | - All entries are now defined as structs and saved/restored in self-contained operations. - Save/restore operations are type-safe, to tie each entry's typecode to a particular struct and its length. - Save/restore handlers are registered once per host instead of per domain. - Detect buffer overrun before it happens and abort. Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] Save/restore cleanups 03: IRQTim Deegan2007-01-201-59/+25
| | | | | IRQ, PIC, IOAPIC and LAPIC Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] save restore: save restore dev in HVTim Deegan2007-01-181-0/+83
| | | | | | Signed-off-by: Zhai Edwin <edwin.zhai@intel.com> save/restore all dev state in HV such as PIT/PIC/APIC
* [HVM] Enable more than one platform timer (PIT/RTC/HPET)kfraser@localhost.localdomain2006-12-201-16/+0
| | | | | | | | | | | programmed as periodic timer and adds them to abstract layer, which keeps track of pending_intr_nr to avoid time interrupt lost and sync'ed timer with TSC. It also makes some cleanup to the time related code. Signed-off-by: Xiaowei Yang <xiaowei.yang@intel.com> Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
* [HVM] Fix 8259 ELCR masks.kfraser@localhost.localdomain2006-11-271-1/+1
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] Update VPIC device model for new interrupt delivery code.kaf24@localhost.localdomain2006-11-261-0/+463
Move BSP VLAPIC initialisation to hvmloader. Remove callback_irq update hack from Linux unmodified drivers. Signed-off-by: Keir Fraser <keir@xensource.com>
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