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* x86/HVM: Call vlapic_set_irq() to delivery virtual interruptYang Zhang2013-04-181-2/+1
| | | | | | | | | Move kick_vcpu into vlapic_set_irq. And call it to deliver virtual interrupt instead set vIRR directly. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: George Dunlap <george.dunlap@eu.citrix.com> (from a release perspective)
* CONFIG: remove #ifdef __ia64__ from the x86 arch treeAndrew Cooper2012-02-091-5/+1
| | | | | | | | | | | | | | | | | | | | | | __ia64__ really really should not be defined in the x86 arch subtree, so remove it from xen/include/public/arch-x86/hvm/save.h This in turn allows the removal of VIOAPIC_IS_IOSAPIC, as x86 does not use streamlined {IO,L}APICs, allowing for the removal of more code from the x86 tree. Changes since v2: * Leave the EOI register write protected by VIOAPIC_VERSION_ID >= 0x20. Currently, only version 0x11 is emulated, but leave this correct code in place in case a decision is make to emulate the newer version. Changes since v1: * Refresh patch following the decision not to try emulating a version 0x20 IOAPIC Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Committed-by: Keir Fraser <keir@xen.org>
* x86/vioapic: clear remote IRR when switching RTE to edge triggered modeJan Beulich2011-11-211-2/+3
| | | | | | | | | Xen itself (as much as Linux) relies on this behavior, so it should also emulate it properly. Not doing so reportedly gets in the way of kexec inside a HVM guest. Signed-off-by: Jan Beulich <jbeulich@suse.com> Tested-by: Olaf Hering <olaf@aepfle.de>
* x86: split struct domainJan Beulich2011-04-051-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is accomplished by converting a couple of embedded arrays (in one case a structure containing an array) into separately allocated pointers, and (just as for struct arch_vcpu in a prior patch) overlaying some PV-only fields with HVM-only ones. One particularly noteworthy change in the opposite direction is that of PITState - this field so far lived in the HVM-only portion, but is being used by PV guests too, and hence needed to be moved out of struct hvm_domain. The change to XENMEM_set_memory_map (and hence libxl__build_pre() and the movement of the E820 related pieces to struct pv_domain) are subject to a positive response to a query sent to xen-devel regarding the need for this to happen for HVM guests (see http://lists.xensource.com/archives/html/xen-devel/2011-03/msg01848.html). The protection of arch.hvm_domain.irq.dpci accesses by is_hvm_domain() is subject to confirmation that the field is used for HVM guests only (see http://lists.xensource.com/archives/html/xen-devel/2011-03/msg02004.html). In the absence of any reply to these queries, and given the early state of 4.2 development, I think it should be acceptable to take the risk of having to later undo/redo some of this. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86: Do not include apic.h/io_apic.h from asm/smp.hKeir Fraser2010-06-111-0/+1
| | | | | | ...and fix up the ensuing fall-out of implicit dependencies Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86: vioapic: fix remote irr bit setting for level triggered interruptsKeir Fraser2009-10-281-31/+18
| | | | | | | Clear all entries' remote irr bits once the RTE entries' vector field match with EOI message's vector. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
* Miscellaneous data placement adjustmentsKeir Fraser2009-10-281-1/+1
| | | | | | | Make various data items const or __read_mostly where possible/reasonable. Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86 hvm: suspend platform timer emulation while its IRQ is maskedKeir Fraser2009-09-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of a timer which IRQ is masked from vcpu's timer list. It reduces the overhead of VM EXIT and context switch of vm. Also fixes a potential bug. (1) VCPU#0: mask the IRQ of a timer. (ex. vioapic.redir[2].mask=1) (2) VCPU#1: pt_timer_fn() is invoked by expiration of the timer. (3) VCPU#1: pt_update_irq() is called but does nothing by pt_irq_masked()==1. (4) VCPU#1: sleep by halt. (5) VCPU#0: unmask the IRQ of the timer. After that, no one wakes up the VCPU#1. IRQ of ISA is masked by: - PIC's IMR - IOAPIC's redir[0] - IOAPIC's redir[N].mask - LAPIC's LVT0 - LAPIC enabled/disabled IRQ of LAPIC timer is masked by: - LAPIC's LVTT - LAPIC disabled When above stuffs are changed, the corresponding vcpu is kicked and suspended timer emulation is resumed. In addition, a small bug fix in pt_adjust_global_vcpu_target(). Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
* x86 hvm: Clean up vlapic/vioapic/vmsi delivery.Keir Fraser2009-08-191-83/+23
| | | | | | | In particular, avoid intermediate delivery bitmaps which restrict number of vcpus supported. Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86 hvm: Allow delivery of legacy 8259 interrupts to VCPUs != 0.Keir Fraser2009-07-011-7/+10
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86_64: allow more vCPU-s per guestKeir Fraser2009-06-181-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Since the shared info layout is fixed, guests are required to use VCPUOP_register_vcpu_info prior to booting any vCPU beyond the traditional limit of 32. MAX_VIRT_CPUS, being an implemetation detail of the hypervisor, is no longer being exposed in the public headers. The tools changes are clearly incomplete (and done only so things would build again), and the current state of the tools (using scalar variables all over the place to represent vCPU bitmaps) very likely doesn't permit booting DomU-s with more than the traditional number of vCPU-s. Testing of the extended functionality was done with Dom0 (96 vCPU-s, as well as 128 vCPU-s out of which the kernel elected - by way of a simple kernel side patch - to use only some, resulting in a sparse bitmap). ia64 changes only to make things build, and build-tested only (and the tools part only as far as the build would go without encountering unrelated problems in the blktap code). Signed-off-by: Jan Beulich <jbeulich@novell.com>
* x86, hvm: Implement interrupt routing to least priority processor.Keir Fraser2008-11-181-2/+2
| | | | | | | | | | Instead of round robin the vcpu with the lowest processor priority is selected for the interrupt. If multiple vcpus share the same low priority then interrupts are distributed between those round robin. Signed-off-by: Juergen Gross <juergen.gross@fujitsu-siemens.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86 hvm: Xen interface and implementation for virtual S3Keir Fraser2008-05-201-8/+12
| | | | | | | Signed-off-by: Tian Kevin <kevin.tian@intel.com> Signed-off-by: Yu Ke <ke.yu@intel.com> Signed-off-by: Ke Liping <liping.ke@intel.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86, hvm: I/O emulation handlers return X86EMUL_* return codes.Keir Fraser2008-04-151-9/+12
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* hvm: Clean out save/restore debug tracing.Keir Fraser2008-04-091-31/+2
| | | | Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* x86 iommu: Define vendor-neutral interface for access to IOMMU.Keir Fraser2008-02-141-1/+1
| | | | | Signed-off-by: Wei Wang <wei.wang2@amd.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* hvm: Fix destroy_periodic_time() to not race destruction of one-shot timers.Keir Fraser2007-12-121-1/+1
| | | | | | This bug was tracked down by Dexuan Cui <dexuan.cui@intel.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
* vt-d: Do dpci eoi outside of irq_lock.Keir Fraser2007-10-301-0/+4
| | | | | | | | | | | | | | | Deadlock may occur if do hvm_dpci_eoi() inside of irq_lock on MP platform. For example, there are two physical cpus. If interrupt is injected on cpu0, but vcpu is migrated to cpu1 and it does eoi inside of irq_lock, then IPI will be issued to cpu0. At the same time, cpu0 may have disabled irq and is acquiring the same irq_lock. In addition, current code cannot guarantee do hvm_dpci_eoi() inside of irq_lock when timeout. This patch does hvm_dpci_eoi() outside of irq_lock, and solves above problems. Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com> Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: Keir Fraser <keir@xensource.com>
* vt-d: Allow pass-through of shared interrupts.Keir Fraser2007-10-191-1/+1
| | | | | Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com> Signed-off-by: Kevin Tian <kevin.tian@intel.com>
* hvm: More changes to reduce size of domain structure.Keir Fraser2007-10-031-7/+20
| | | | | It is now smaller than a page (4kB) on x86/32 and x86/64. Signed-off-by: Keir Fraser <keir@xensource.com>
* IRQ injection changes for HVM PCI passthru.kfraser@localhost.localdomain2007-09-181-0/+4
| | | | | Signed-off-by: Allen Kay <allen.m.kay@intel.com> Signed-off-by: Guy Zana <guy@neocleus.com>
* hvm: Remove hvm-specific NMI flag and use generic flag instead.kfraser@localhost.localdomain2007-09-061-1/+1
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* hvm: More cleanups, particularly to %cr4 handling.kfraser@localhost.localdomain2007-08-081-4/+0
| | | | | Signed-off-by: Keir Fraser <keir@xensource.com> Signed-off-by: Xin Li <xin.b.li@intel.com>
* hvm: Support injection of virtual NMIs and clean up ExtInt handling in general.kfraser@localhost.localdomain2007-06-201-15/+19
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* x86/hvm: HVM_DBG_LOG() cleanupkfraser@localhost.localdomain2007-05-151-13/+10
| | | | | | | | - make log levels used consistent in a few places - remove trailing newlines, dots, and commas - remove explictly specified function names from message text Signed-off-by: Jan Beulich <jbeulich@novell.com>
* [HVM] Save/restore: dynamically calculate the size of the save bufferTim Deegan2007-02-071-1/+1
| | | | Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] Save/restore: tidy up IRQsTim Deegan2007-02-051-56/+2
| | | | | | | - don't save PV state - recalculate IRQ assert counts instead of saving them Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] Save/restore: clean up marshalling codeTim Deegan2007-01-311-19/+27
| | | | | | | | | | | | - All entries are now defined as structs and saved/restored in self-contained operations. - Save/restore operations are type-safe, to tie each entry's typecode to a particular struct and its length. - Save/restore handlers are registered once per host instead of per domain. - Detect buffer overrun before it happens and abort. Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] Save/restore cleanups 03: IRQTim Deegan2007-01-201-78/+35
| | | | | IRQ, PIC, IOAPIC and LAPIC Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] Save/restore cleanups 01: PITTim Deegan2007-01-201-1/+1
| | | | | | | Define public structure for the saved PIT data and use it instead of a series of explicit loads and stores. Don't save ephemeral Xen timer structs; rebuild them instead. Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] Save/Restore: Various structures have changedTim Deegan2007-01-181-6/+10
| | | | Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] save restore: save restore dev in HVTim Deegan2007-01-181-0/+128
| | | | | | Signed-off-by: Zhai Edwin <edwin.zhai@intel.com> save/restore all dev state in HV such as PIT/PIC/APIC
* [HVM] Fix timer interrupt delivery on x64 Vista.kfraser@localhost.localdomain2007-01-121-2/+9
| | | | | | | | | | | | x64 SMP Vista HVM guest uses HPET as the main system timer, and it uses physical destination mode with broadcast to deliver the interrupts generated by HPET. In current code, timer interrupts are injected only to VCPU0 in vioapic.c, but this doesn't satisfy x64 SMP Vista -- when it boots, it complains "a clock interrupt was not received on a secondary processor within the allocated time interval" with Bug Check 0x101. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
* [HVM] Fix assumptions that ISA IRQ 0 connects to GSI 0.kaf24@localhost.localdomain2006-12-281-2/+2
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] Reworked interrupt distribution logic.kfraser@localhost.localdomain2006-11-211-172/+95
| | | | | | | | | | | | | TODO: 1. Fix IO-APIC ID to not conflict with LAPIC IDS. 2. Fix i8259 device model (seems to work already though!). 3. Add INTSRC overrides in MPBIOS and ACPI tables so that PCI legacy IRQ routing always ends up at an IO-APIC input with level trigger. Restricting link routing to {5,6,10,11} and setting overrides for all four of those would work. Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] Decouple the RTC from the PIT periodic timerTim Deegan2006-11-161-2/+2
| | | | Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
* [HVM] Simplify apic dest-matching code. Refactorkfraser@localhost.localdomain2006-11-101-36/+1
| | | | | | across vlapic/vioapic source files to reduce code duplication. Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] Remove a duplicated range checking in vioapic_set_irq.kfraser@localhost.localdomain2006-11-101-14/+12
| | | | | | | Since irq range checking has already been done at the beginning of this function. Signed-off-by: Xin Li <xin.b.li@intel.com>
* [HVM] Change vlapic printk()s into appropriate gdprintk()s.kfraser@localhost.localdomain2006-11-091-1/+1
| | | | | Simplify apic_round_robin(). Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] Avoid long delay between setting IRQ for PV drivers andkaf24@firebug.cl.cam.ac.uk2006-11-091-0/+2
| | | | | servicing it. Should call service_ioapic() synchronously. Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] Simplify relationship between VIOAPIC and VLAPICs.kfraser@localhost.localdomain2006-11-081-76/+39
| | | | | | It's not really dynamic since there is always exactly one VLAPIC per VCPU. Signed-off-by: Keir Fraser <keir@xensource.com>
* [XEN] Fix 64-bit build.kaf24@localhost.localdomain2006-11-071-3/+4
| | | | | | | | | This required fiddling the asm constraints of the atomic bitops. It seems gcc isn't entirely happy with "+m": the manual says that the '+' modifier should be used only when a register constraint is available. Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] VIOAPIC and VPIC cleanups.kfraser@localhost.localdomain2006-11-071-333/+304
| | | | Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] VLAPIC cleanups. vlapic tsruct is statically containedkfraser@localhost.localdomain2006-11-071-3/+2
| | | | | inside the vcpu structure. Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] Replace shared-memory PIC state with a set-irq-level hypercall.kfraser@localhost.localdomain2006-11-071-21/+3
| | | | | | | | | | | | | | This simplifies the IRQ logic significantly and avoids the bogus hvm_pic_assist() on domain resume path. There is more work to be done here. At least: 1. set-irq-level should really be set-interrupt-wire-level. Wire state needs to be distinguished from PIC (in particular, PIC IRR) state. 2. Hypercalls can be batched in qemu and pushed down in one multicall. Signed-off-by: Keir Fraser <keir@xensource.com>
* [XEN] Replace hvm_setup_platform() with hvm_domain_initialise()kaf24@localhost.localdomain2006-11-051-11/+1
| | | | | | | | and extra code in hvm_vcpu_initialise(). Remove 'apic' config option -- HVM CPUs will always have an APIC (which should be set up in virtual wire mode for backward compatibility, just as in a real system). Signed-off-by: Keir Fraser <keir@xensource.com>
* [XEN] Some cleanups to the log-level stuff. Largely thiskaf24@localhost.localdomain2006-10-271-4/+2
| | | | | | | | is a rename and slight interface change to DPRINTK (now replaced by dprintk() and gdprintk()). Also shuffle some log-level definitions around and tweak the semantics of the upper threshold. Signed-off-by: Keir Fraser <keir@xensource.com>
* [HVM] Ensure that, if AP is blocked, it is woken by interrupt delivered by ↵kaf24@localhost.localdomain2006-10-271-3/+7
| | | | | | | | | IOAPIC. This fixes 64-bit SMP Windows 2k3 boot. Signed-off-by: Xiaowei Yang <xiaowei.yang@intel.com> Signed-off-by: Xin Li <xin.b.li@intel.com>
* Workaround for bigsmp APIC mode SMP linux guests - we cannot correctly dealSteven Hand2006-10-201-17/+34
| | | | | | | | | | with timer interrupts being delivered to VCPUs other than 0, so spit a warning and then subsequently ignore the target. This fixes the recent issues Intel reported when booting SMP FC5 and FC6 kernels. Needs a better fix at some point. Signed-off-by: Steven Hand <steven@xensource.com>
* [XEN][HVM] Make sure that the interrupt which event channel events come inSteven Smith2006-09-291-1/+21
| | | | | | | | | | | | | on is level triggered rather than edge triggered, since it's a PCI device. This is complicated by the possibility that another PCI device could be on the same interrupt; the workaround is to have two irr registers for the PIC and APIC, and have qemu and Xen generated interrupts go into different ones. This broke the alt_irq stuff. Fortunately, nobody uses that anymore, so I've removed it. Signed-off-by: Steven Smith <sos22@cam.ac.uk>
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