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* x86: make hvm_cpuid() tolerate NULL pointersJan Beulich2013-10-041-4/+4
| | | | | | | | | | | Now that other HVM code started making more extensive use of hvm_cpuid(), let's not force every caller to declare dummy variables for output not cared about. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Acked-by: Jun Nakajima <jun.nakajima@intel.com>
* hvm/vpmu: Prevent dump handlers from incorrectly mutating stateAndrew Cooper2013-09-161-6/+6
| | | | | | | | | | | | | | | | | | Discovered by Coverity, CID 1055181 core2_vpmu_dump() was incorrectly setting VPMU_CONTEXT_LOADED when it was intending to check for it. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> This would have been avoided if the dump function declared all its pointers "const" - doing this now (also in SVM). Also fixing some indentation issues at once. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
* x86: Introduce and use GLOBAL() in asm codeAndrew Cooper2013-09-091-2/+1
| | | | | | Also clean up some cases of misused/opencoded ENTRY() Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* SVM: streamline entry.S codeJan Beulich2013-09-092-37/+26
| | | | | | | | | | | | | - fix a bogus "test" with zero immediate - move stuff easily/better done in C into C code - re-arrange code paths so that no redundant GET_CURRENT() would remain on the fast paths - move long latency operations earlier - slightly defer disabling global interrupts on the VM entry path Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Tim Deegan <tim@xen.org>
* x86/AMD: Inject #GP instead of #UD when unable to map vmcbSuravee Suthikulpanit2013-08-131-10/+14
| | | | | | | | | | According to AMD Programmer's Manual vol2, vmrun, vmsave and vmload should inject #GP instead of #UD when unable to access memory location for vmcb. Also, the code should make sure that L1 guest EFER.SVME is not zero. Otherwise, #UD should be injected. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Reviewed-by: Tim Deegan <tim@xen.org>
* x86/AMD: Fix nested svm crash due to assertion in __virt_to_maddrSuravee Suthikulpanit2013-08-131-9/+43
| | | | | | | | | Fix assertion in __virt_to_maddr when starting nested SVM guest in debug mode. Investigation has shown that svm_vmsave/svm_vmload make use of __pa() with invalid address. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Reviewed-by: Tim Deegan <tim@xen.org>
* x86: Special case __HYPERVISOR_iret rather more when writing hypercall pagesAndrew Cooper2013-07-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | In all cases when a hypercall page is written, __HYPERVISOR_iret is first written as a regular hypercall, then subsequently rewritten in its special case. For VMX and SVM, this means that following the ud2a instruction is 3 bytes of an imm32 parameter. For a ring3 kernel, this means that following the syscall instruction is the second half of 'pop %r11'. For a ring1 kernel, the iret case ends up as the same number of bytes as the rest of the hypercalls, but it is pointless writing it twice, and is changed for consistency. Therefore, skip the loop iteration which would write the incorrect __HYPERVISOR_iret hypercall. This removes junk machine code from the tail and makes disassemblers rather more happy when looking at the hypercall page. Also, a miscellaneous whitespace fix in the comment for ring3 kernel. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
* x86/HVM: key handler registration functions can be __initJan Beulich2013-07-101-1/+1
| | | | | | | This applies to both SVM and VMX. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: fix XCR0 handlingJan Beulich2013-06-041-1/+2
| | | | | | | | | | | | | | - both VMX and SVM ignored the ECX input to XSETBV - both SVM and VMX used the full 64-bit RAX when calculating the input mask to XSETBV - faults on XSETBV did not get recovered from Also consolidate the handling for PV and HVM into a single function, and make the per-CPU variable "xcr0" static to xstate.c. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org> Acked-by: George Dunlap <george.dunlap@eu.citrix.com>
* x86: handle paged gfn in wrmsr_hypervisor_regsOlaf Hering2013-05-071-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If xenpaging is started very early for a guest the gfn for the hypercall page may be paged-out already. This leads to a guest crash: ... (XEN) HVM10: Allocated Xen hypercall page at 169ff000 (XEN) traps.c:654:d10 Bad GMFN 169ff (MFN 3e900000000) to MSR 40000000 (XEN) HVM10: Detected Xen v4.3 (XEN) io.c:201:d10 MMIO emulation failed @ 0008:c2c2c2c2: 18 7c 55 6d 03 83 ff ff 10 7c (XEN) hvm.c:1253:d10 Triple fault on VCPU0 - invoking HVM shutdown action 1. (XEN) HVM11: HVM Loader ... Update return codes of wrmsr_hypervisor_regs, update callers to deal with the new return codes: 0: not handled 1: handled -EAGAIN: retry Currently wrmsr_hypervisor_regs will not return the following error, it will be added in a separate patch: -EINVAL: error during handling Also update the gdprintk to handle a page value of NULL to avoid printing a bogus MFN value. Update also computing of MSR value in gdprintk, the idx was always zero. Signed-off-by: Olaf Hering <olaf@aepfle.de> Acked-by: Keir Fraser <keir@xen.org>
* x86/HVM: move per-vendor function tables into .init.dataJan Beulich2013-04-291-2/+2
| | | | | | | | | | | | | | | hvm_enable() copies the table contents rather than storing the pointer, so there's no need to keep these tables post-boot. Also constify the return values of the per-vendor initialization functions, making clear that once the per-vendor initialization is complete, the vendor specific tables won't get modified anymore. Finally, in hvm_enable(), use the returned pointer for all read accesses as being more efficient than global variable accesses. Writes of course still need to go to the global variable. Signed-off-by: Jan Beulich <jbeulich@suse.com>
* x86/AMD: Dump AMD VPMU infoBoris Ostrovsky2013-04-151-1/+41
| | | | | | Dump VPMU registers on AMD in the 'q' keyhandler. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
* x86/AMD: Clean up context_update() in AMD VPMU codeBoris Ostrovsky2013-04-151-11/+17
| | | | | | | | | | Clean up context_update() in AMD VPMU code. Rename restore routine to "load" to be consistent with Intel code and with arch_vpmu_ops names Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
* x86/VPMU: Save/restore VPMU only when necessaryBoris Ostrovsky2013-04-152-9/+45
| | | | | | | | | | | | | VPMU doesn't need to always be saved during context switch. If we are comming back to the same processor and no other VPCU has run here we can simply continue running. This is especailly useful on Intel processors where Global Control MSR is stored in VMCS, thus not requiring us to stop the counters during save operation. On AMD we need to explicitly stop the counters but we don't need to save them. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com> Tested-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
* x86/VPMU: Factor out VPMU common codeBoris Ostrovsky2013-04-151-37/+0
| | | | | | | | | Factor out common code from SVM amd VMX into VPMU. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com> Tested-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com> Acked-by: Jun Nakajima <jun.nakajima@intel.com>
* x86/AMD: Stop counters on VPMU saveBoris Ostrovsky2013-04-151-16/+6
| | | | | | | | | | | | Stop the counters during VPMU save operation since they shouldn't be running when VPCU that controls them is not. This also makes it unnecessary to check for overflow in context_restore() Set LVTPC vector before loading the context during vpmu_restore(). Otherwise it is possible to trigger an interrupt without proper vector. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
* x86/AMD: Load context when attempting to read VPMU MSRsBoris Ostrovsky2013-04-151-1/+20
| | | | | | | | | | | | | | | | Load context (and mark it as LOADED) on any MSR access. This will allow us to always read the most up-to-date value of an MSR: guest may write into an MSR without enabling it (thus not marking the context as RUNNING) and then be migrated. Without first loading the context reading this MSR from HW will not match the pervious write since registers will not be loaded into HW in amd_vpmu_load(). In addition, we should be saving the context when it is LOADED, not RUNNING --- otherwise we need to save it any time it becomes non-RUNNING, which may be a frequent occurrence. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
* x86/AMD: Do not intercept access to performance counters MSRsBoris Ostrovsky2013-04-152-1/+44
| | | | | | | | Access to performance counters and reads of event selects don't need to always be intercepted. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
* x86/AMD: Allow more fine-grained control of VMCB MSR Permission MapBoris Ostrovsky2013-04-151-8/+7
| | | | | | | | | Currently VMCB's MSRPM can be updated to either intercept both reads and writes to an MSR or not intercept neither. In some cases we may want to be more selective and intercept one but not the other. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
* vpmu intel: Add cpuid handling when vpmu disabledDietmar Hahn2013-03-261-0/+4
| | | | | | | | | | | | | | | | | Even though vpmu is disabled in the hypervisor in the HVM guest the call of cpuid(0xa) returns informations about usable performance counters. This may confuse guest software when trying to use the counters and nothing happens. This patch clears most bits in registers eax and edx of cpuid(0xa) instruction for the guest when vpmu is disabled: - version ID of architectural performance counting - number of general pmu registers - width of general pmu registers - number of fixed pmu registers - width of ixed pmu registers Signed-off-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: don't rely on __softirq_pending to be the first field in irq_cpustat_tJan Beulich2013-03-041-4/+4
| | | | | | | | | | | | | This is even more so as the field doesn't have a comment to that effect in the structure definition. Once modifying the respective assembly code, also convert the IRQSTAT_shift users to do a 32-bit shift only (as we won't support 48M CPUs any time soon) and use "cmpl" instead of "testl" when checking the field (both reducing code size). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* Fix emacs local variable block to use correct C style variable.David Vrabel2013-02-216-6/+6
| | | | | | | The emacs variable to set the C style from a local variable block is c-file-style, not c-set-style. Signed-off-by: David Vrabel <david.vrabel@citrix.com
* x86: Add Xenoprofile support for AMD Family16hSuravee Suthikulpanit2013-02-121-0/+2
| | | | | | | | | Add Xenoprofile support for AMD Family16h. The corresponded OProfile patch has already been submitted to OProfile mailing list. (http://marc.info/?l=oprofile-list&m=136036136017302&w=2 ). Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86: properly use map_domain_page() in nested HVM codeJan Beulich2013-01-231-7/+8
| | | | | | | | | | | | | | This eliminates a couple of incorrect/inconsistent uses of map_domain_page() from VT-x code. Note that this does _not_ add error handling where none was present before, even though I think NULL returns from any of the mapping operations touched here need to properly be handled. I just don't know this code well enough to figure out what the right action in each case would be. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* nEPT: Use minimal permission for nested p2mZhang Xiantao2013-01-151-1/+1
| | | | | | | | | | | | Emulate permission check for the nested p2m. Current solution is to use minimal permission, and once meet permission violation in L0, then determin whether it is caused by guest EPT or host EPT Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Acked-by: Tim Deegan <tim@xen.org> Acked-by: Jun Nakajima <jun.nakajima@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* nestedhap: Change nested p2m's walker to vendor-specificZhang Xiantao2013-01-152-0/+31
| | | | | | | | | | | EPT and NPT adopts differnt formats for each-level entry, so change the walker functions to vendor-specific. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Acked-by: Tim Deegan <tim@xen.org> Acked-by: Jun Nakajima <jun.nakajima@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* nestedhap: Change hostcr3 and p2m->cr3 to meaningful wordsZhang Xiantao2013-01-151-1/+1
| | | | | | | | | | | VMX doesn't have the concept about host cr3 for nested p2m, and only SVM has, so change it to netural words. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Acked-by: Tim Deegan <tim@xen.org> Acked-by: Jun Nakajima <jun.nakajima@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86/hvm: Remove 32-/64-bit abstraction macros from asm files.Keir Fraser2013-01-141-50/+44
| | | | | | Not needed now we target 64-bit only. Signed-off-by: Keir Fraser <keir@xen.org>
* x86: Assert !in_atomic() before exiting to guest context.Keir Fraser2013-01-141-0/+1
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* x86/IST: Create set_ist() helper functionAndrew Cooper2012-12-111-6/+6
| | | | | | | | ... to save using open-coded bitwise operations, and update all IST manipulation sites to use the function. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86: mark certain items staticJan Beulich2012-12-072-2/+2
| | | | | | | ..., and at once constify the data items among them. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* nestedsvm: fix VMEXIT emulationChristoph Egger2012-10-231-6/+11
| | | | | | | | | Values in regs can be newer than those in the shadow vmcb (e.g. due to an instruction emulation right before). So use the values from regs. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Acked-by: Tim Deegan <tim@xen.org> Committed-by: Jan Beulich <jbeulich@suse.com>
* nestedsvm: fix memory leak on shutdown/crashChristoph Egger2012-10-231-0/+9
| | | | | | | | | Fix memory leak of l1 vmcb page when destroying a vcpu while l2 guest is running. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Acked-by: Tim Deegan <tim@xen.org> Committed-by: Jan Beulich <jbeulich@suse.com>
* x86/nested-svm: Update the paging mode on VMRUN and VMEXIT emulation.Tim Deegan2012-10-041-0/+8
| | | | | | | | | | | | This allows Xen to walk the l1 hypervisor's shadow pagetable correctly. Not needed for hap-on-hap guests because they are handled at lookup time. Problem found with 64bit Win7 and 32bit XPMode where Win7 switches forth and back between long mode and PAE legacy pagetables. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> [Adjusted to update in all cases where the l1 vmm uses shadows] Signed-off-by: Tim Deegan <tim@xen.org> Committed-by: Tim Deegan <tim@xen.org>
* x86: enable VIA CPU supportJan Beulich2012-09-211-3/+0
| | | | | | | | | | | | | Newer VIA CPUs have both 64-bit and VMX support. Enable them to be recognized for these purposes, at once stripping off any 32-bit CPU only bits from the respective CPU support file, and adding 64-bit ones found in recent Linux. This particularly implies untying the VMX == Intel assumption in a few places. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* printk: prefer %#x et at over 0x%xJan Beulich2012-09-214-34/+33
| | | | | | | | | Performance is not an issue with printk(), so let the function do minimally more work and instead save a byte per affected format specifier. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/hvm: constify static data where possibleJan Beulich2012-09-142-15/+15
| | | | | | | | In a few cases this also extends to making them static in the first place. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86/hvm: don't use indirect calls without needJan Beulich2012-09-141-17/+7
| | | | | | | | Direct calls perform better, so we should prefer them and use indirect ones only when there indeed is a need for indirection. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Keir Fraser <keir@xen.org>
* x86: We can assume CONFIG_PAGING_LEVELS==4.Keir Fraser2012-09-121-2/+1
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* xen: Remove x86_32 build target.Keir Fraser2012-09-123-39/+0
| | | | Signed-off-by: Keir Fraser <keir@xen.org>
* nestedsvm: fix interrupt handlingChristoph Egger2012-08-311-0/+10
| | | | | | | | | | Give the l2 guest a chance to finish the delivery of the last injected interrupt or exception before we emulate a VMEXIT. For example after a NPF handled by the host there can be an interrupt for the l1 guest. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Keir Fraser <keir@xen.org>
* nestedsvm: fix DRn handlingChristoph Egger2012-07-091-6/+7
| | | | | | | | | Always use l1 vmcb to handle DRn access. This avoids to interfere with l1 hypervisor's DRn handling when it doesn't intercept DRn. Fixes Hyper-V hang. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Keir Fraser <keir@xen.org>
* Fix check if guest enabled nested paging.Christoph Egger2012-06-251-0/+3
| | | | | | | Fixes crashes with Windows guests when shadow-on-nested is used. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Acked-by: Tim Deegan <tim@xen.org>
* SVM: fix performance decrease with asid assignmentChristoph Egger2012-06-131-1/+2
| | | | | | | | Do not clear asid cleanbit unconditionally. This shaves off 100 cycles from the VMRUN instruction. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* xen: Define new struct hvm_trap and cleanup vmx exceptionKeir Fraser2012-05-303-41/+45
| | | | | | | | | | Define new struct hvm_trap to represent information of trap, and renames hvm_inject_exception to hvm_inject_trap, then define a couple of wrappers around that function for existing callers. Signed-off-by: Keir Fraser <keir@xen.org> Signed-off-by: Xudong Hao <xudong.hao@intel.com> Committed-by: Keir Fraser <keir@xen.org>
* x86/hvm/svm: used unlocked p2m lookups in trace and error paths.Andres Lagar-Cavilla2012-05-171-4/+2
| | | | Signed-off-by: Andres Lagar-Cavilla <andres@lagarcavilla.org>
* x86/hvm: Use get_page_from_gfn() instead of get_gfn()/put_gfn.Tim Deegan2012-05-171-8/+6
| | | | | Signed-off-by: Tim Deegan <tim@xen.org> Signed-off-by: Andres Lagar-Cavilla <andres@lagarcavilla.org>
* x86/hvm: Add get_shadow_gs_base() wrapper functionAravindh Puthiyaparambil2012-04-271-0/+6
| | | | | | | | Add a wrapper function to the HVM function table that returns the shadow GS base. Signed-off-by: Aravindh Puthiyaparambil <aravindh@virtuata.com> Committed-by: Jan Beulich <jbeulich@suse.com>
* svm: Do not intercept RDTSC(P) when TSC scaling is supported by hardwareBoris Ostrovsky2012-04-251-1/+8
| | | | | | | | | | | When running in TSC_MODE_ALWAYS_EMULATE mode on processors that support TSC scaling we don't need to intercept RDTSC/RDTSCP instructions. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> Acked-by: Wei Huang <wei.huang2@amd.com> Tested-by: Wei Huang <wei.huang2@amd.com> Committed-by: Keir Fraser <keir@xen.org>
* Fix save/restore of guest PAT table in HAP paging mode.Gianluca Guida2012-04-171-0/+24
| | | | | | | | | | | | | | HAP paging mode guests use direct MSR read/write into the VMCS/VMCB for the guest PAT table, while the current save/restore code was accessing only the pat_cr field in hvm_vcpu, used when intercepting the MSR mostly in shadow mode (the Intel scenario is a bit more complicated). This patch fixes this issue creating a new couple of hvm_funcs, get/set_guest_pat, that access the right PAT table based on the paging mode and guest configuration. Signed-off-by: Gianluca Guida <gianluca.guida@citrix.com> Acked-by: Tim Deegan <tim@xen.org> Committed-by: Keir Fraser <keir@xen.org>
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