[HVM] Shadow: don't shadow the p2m table.

For HVM vcpus with paging disabled, we used to shadow the p2m table,
and skip the p2m lookup to go from gfn to mfn.  Instead, we now
provide a simple pagetable that gives a one-to-one mapping of 4GB, and
shadow that, making the translations from gfn to mfn via the p2m.
This removes the paging-disabled special-case code from the shadow
fault handler, and allows us to expand the p2m interface, since all HVM
translations now go through the same p2m lookups.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>

1 files changed, 0 insertions, 16 deletions

diff --git a/xen/include/asm-x86/paging.h b/xen/include/asm-x86/paging.h
index 35067b289b..842c4c7134 100644
--- a/xen/include/asm-x86/paging.h
+++ b/xen/include/asm-x86/paging.h
@@ -66,19 +66,6 @@
 /* flags used for paging debug */
 #define PAGING_DEBUG_LOGDIRTY 0
 
-/******************************************************************************
- * The equivalent for a particular vcpu of a shadowed domain. */
-
-/* Is this vcpu using the P2M table to translate between GFNs and MFNs?
- *
- * This is true of translated HVM domains on a vcpu which has paging
- * enabled.  (HVM vcpus with paging disabled are using the p2m table as
- * its paging table, so no translation occurs in this case.)
- * It is also true for all vcpus of translated PV domains. */
-#define paging_vcpu_mode_translate(_v) ((_v)->arch.paging.translate_enabled)
-
-
-
 /*****************************************************************************
  * Mode-specific entry points into the shadow code.  
  *
@@ -222,9 +209,6 @@ static inline int paging_invlpg(struct vcpu *v, unsigned long va)
 #define INVALID_GFN (-1UL)
 static inline unsigned long paging_gva_to_gfn(struct vcpu *v, unsigned long va)
 {
-    if ( unlikely(!paging_vcpu_mode_translate(v)) )
-        return va >> PAGE_SHIFT;
-
     return v->arch.paging.mode->gva_to_gfn(v, va);
 }