diff options
| author | Keir Fraser <keir.fraser@citrix.com> | 2010-07-30 11:36:34 +0100 |
|---|---|---|
| committer | Keir Fraser <keir.fraser@citrix.com> | 2010-07-30 11:36:34 +0100 |
| commit | d4a2c8df0ac4cc35e86971ff80d4c4e01d2fd15a (patch) | |
| tree | 5f8a889944aa31f1b7028a739266d51497f751ce /xen/include/asm-x86/msr-index.h | |
| parent | 116fe7eac5cda05e693e167700b0a8156bb3f57a (diff) | |
| download | xen-d4a2c8df0ac4cc35e86971ff80d4c4e01d2fd15a.tar.gz xen-d4a2c8df0ac4cc35e86971ff80d4c4e01d2fd15a.tar.bz2 xen-d4a2c8df0ac4cc35e86971ff80d4c4e01d2fd15a.zip | |
x86: unmask CPUID levels on Intel CPUs
If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to
make all CPUID information available. This is required for some
features to work, such as MWAIT in cpuidle, get cpu topology, XSAVE,
etc.
Signed-off-by: Wei Gang <gang.wei@intel.com>
Diffstat (limited to 'xen/include/asm-x86/msr-index.h')
| -rw-r--r-- | xen/include/asm-x86/msr-index.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 150e19154f..813531bd8e 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -324,6 +324,7 @@ #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11) #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12) #define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18) +#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22) #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23) /* Intel Model 6 */ |