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| author | Yang Zhang <yang.z.zhang@Intel.com> | 2013-10-04 12:30:09 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2013-10-04 12:30:09 +0200 |
| commit | c6f92aed0e209df823d2cb5780dbb1ea12fc6d4a (patch) | |
| tree | ef9f8adf44914b86a82888afe50adf23a04260c2 /xen/include/asm-x86/cpufeature.h | |
| parent | 1332d0e907fd5b6075241d36257f8faef5ec97a7 (diff) | |
| download | xen-c6f92aed0e209df823d2cb5780dbb1ea12fc6d4a.tar.gz xen-c6f92aed0e209df823d2cb5780dbb1ea12fc6d4a.tar.bz2 xen-c6f92aed0e209df823d2cb5780dbb1ea12fc6d4a.zip | |
Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation
Currently, it use hardcode value for IA32_VMX_CR4_FIXED1. This is wrong.
We should check guest's cpuid to know which bits are writeable in CR4 by guest
and allow the guest to set the corresponding bit only when guest has the feature.
Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
Cleanup.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Jun Nakajima <jun.nakajima@intel.com>
Diffstat (limited to 'xen/include/asm-x86/cpufeature.h')
| -rw-r--r-- | xen/include/asm-x86/cpufeature.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 065c2652a8..1cfaf948b2 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -148,6 +148,7 @@ #define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */ #define X86_FEATURE_RTM (7*32+11) /* Restricted Transactional Memory */ #define X86_FEATURE_NO_FPU_SEL (7*32+13) /* FPU CS/DS stored as zero */ +#define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) |