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| author | Mark Langsdorf <mark.langsdorf@amd.com> | 2011-11-12 16:15:19 +0000 |
|---|---|---|
| committer | Mark Langsdorf <mark.langsdorf@amd.com> | 2011-11-12 16:15:19 +0000 |
| commit | fbd80674b0ed69a3aca34b244dab1aa4e5897cf6 (patch) | |
| tree | 73535ba2cd72f35b52a00cb0585ce1e4604690e5 | |
| parent | 584df17dd943eac6c17ee56346f7d1a2ea045436 (diff) | |
| download | xen-fbd80674b0ed69a3aca34b244dab1aa4e5897cf6.tar.gz xen-fbd80674b0ed69a3aca34b244dab1aa4e5897cf6.tar.bz2 xen-fbd80674b0ed69a3aca34b244dab1aa4e5897cf6.zip | |
x86/amd: Eliminate cache flushing when entering C3 on select AMD processors
AMD Fam15h processors have a shared cache. It does not need=
to be be flushed when entering C3 and doing so causes reduces
performance. Modify acpi_processor_power_init_bm_check to
prevent these processors from flushing when entering C3.
Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
xen-unstable changeset: 23511:450f1d198e1e
xen-unstable date: Tue Jun 14 12:46:29 2011 +0100
Committed-by: Keir Fraser <keir@xen.org>
| -rw-r--r-- | xen/arch/x86/acpi/cpu_idle.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index ce5cfa3b27..5fbbbcdd5f 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -549,7 +549,8 @@ static void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flag flags->bm_check = 0; if ( num_online_cpus() == 1 ) flags->bm_check = 1; - else if ( c->x86_vendor == X86_VENDOR_INTEL ) + else if ( (c->x86_vendor == X86_VENDOR_INTEL) || + ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 0x15)) ) { /* * Today all MP CPUs that support C3 share cache. |