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authorAndrew Cooper <andrew.cooper3@citrix.com>2011-09-13 10:39:25 +0100
committerAndrew Cooper <andrew.cooper3@citrix.com>2011-09-13 10:39:25 +0100
commitefc3f8041aa441a01fb93cd32029886c625ba14e (patch)
tree32bce84892797c7ef1adff5dc3e94eaf979f351f
parentc8dc5e7b2537bc06790d7ba61521c11fe5f9bc7f (diff)
downloadxen-efc3f8041aa441a01fb93cd32029886c625ba14e.tar.gz
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IRQ: IO-APIC support End Of Interrupt for older IO-APICs
The old io_apic_eoi() function using the EOI register only works for IO-APICs with a version of 0x20. Older IO-APICs do not have an EOI register so line level interrupts have to be EOI'd by flipping the mode to edge and back, which clears the IRR and Delivery Status bits. This patch replaces the current io_apic_eoi() function with one which takes into account the version of the IO-APIC and EOI's appropriately. v2: make recursive call to __io_apic_eoi() to reduce code size. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> xen-unstable changeset: 23833:ffe8e65f6687 xen-unstable date: Tue Sep 13 10:33:10 2011 +0100
-rw-r--r--xen/arch/x86/io_apic.c111
-rw-r--r--xen/include/asm-x86/io_apic.h5
2 files changed, 109 insertions, 7 deletions
diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index 8b883dafe9..c72a26a1d3 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -70,6 +70,13 @@ int disable_timer_pin_1 __initdata;
#define MAX_PLUS_SHARED_IRQS nr_irqs_gsi
#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + nr_irqs_gsi)
+
+#define ioapic_has_eoi_reg(apic) (mp_ioapics[(apic)].mpc_apicver >= 0x20)
+
+#define io_apic_eoi_vector(apic, vector) io_apic_eoi((apic), (vector), -1)
+#define io_apic_eoi_pin(apic, pin) io_apic_eoi((apic), -1, (pin))
+
+
/*
* This is performance-critical, we want to do it O(1)
*
@@ -205,6 +212,105 @@ static void ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_
spin_unlock_irqrestore(&ioapic_lock, flags);
}
+/* EOI an IO-APIC entry. One of vector or pin may be -1, indicating that
+ * it should be worked out using the other. This function expect that the
+ * ioapic_lock is taken, and interrupts are disabled (or there is a good reason
+ * not to), and that if both pin and vector are passed, that they refer to the
+ * same redirection entry in the IO-APIC. */
+static void __io_apic_eoi(unsigned int apic, unsigned int vector, unsigned int pin)
+{
+ /* Ensure some useful information is passed in */
+ BUG_ON( (vector == -1 && pin == -1) );
+
+ /* Prefer the use of the EOI register if available */
+ if ( ioapic_has_eoi_reg(apic) )
+ {
+ /* If vector is unknown, read it from the IO-APIC */
+ if ( vector == -1 )
+ vector = __ioapic_read_entry(apic, pin, TRUE).vector;
+
+ *(IO_APIC_BASE(apic)+16) = vector;
+ }
+ else
+ {
+ /* Else fake an EOI by switching to edge triggered mode
+ * and back */
+ struct IO_APIC_route_entry entry;
+ bool_t need_to_unmask = 0;
+
+ /* If pin is unknown, search for it */
+ if ( pin == -1 )
+ {
+ unsigned int p;
+ for ( p = 0; p < nr_ioapic_registers[apic]; ++p )
+ {
+ entry = __ioapic_read_entry(apic, p, TRUE);
+ if ( entry.vector == vector )
+ {
+ pin = p;
+ /* break; */
+
+ /* Here should be a break out of the loop, but at the
+ * Xen code doesn't actually prevent multiple IO-APIC
+ * entries being assigned the same vector, so EOI all
+ * pins which have the correct vector.
+ *
+ * Remove the following code when the above assertion
+ * is fulfilled. */
+ __io_apic_eoi(apic, vector, p);
+ }
+ }
+
+ /* If search fails, nothing to do */
+
+ /* if ( pin == -1 ) */
+
+ /* Because the loop wasn't broken out of (see comment above),
+ * all relevant pins have been EOI, so we can always return.
+ *
+ * Re-instate the if statement above when the Xen logic has been
+ * fixed.*/
+
+ return;
+ }
+
+ entry = __ioapic_read_entry(apic, pin, TRUE);
+
+ if ( ! entry.mask )
+ {
+ /* If entry is not currently masked, mask it and make
+ * a note to unmask it later */
+ entry.mask = 1;
+ __ioapic_write_entry(apic, pin, TRUE, entry);
+ need_to_unmask = 1;
+ }
+
+ /* Flip the trigger mode to edge and back */
+ entry.trigger = 0;
+ __ioapic_write_entry(apic, pin, TRUE, entry);
+ entry.trigger = 1;
+ __ioapic_write_entry(apic, pin, TRUE, entry);
+
+ if ( need_to_unmask )
+ {
+ /* Unmask if neccesary */
+ entry.mask = 0;
+ __ioapic_write_entry(apic, pin, TRUE, entry);
+ }
+ }
+}
+
+/* EOI an IO-APIC entry. One of vector or pin may be -1, indicating that
+ * it should be worked out using the other. This function disables interrupts
+ * and takes the ioapic_lock */
+static void io_apic_eoi(unsigned int apic, unsigned int vector, unsigned int pin)
+{
+ unsigned int flags;
+ spin_lock_irqsave(&ioapic_lock, flags);
+ __io_apic_eoi(apic, vector, pin);
+ spin_unlock_irqrestore(&ioapic_lock, flags);
+}
+
/*
* Saves all the IO-APIC RTE's
*/
@@ -354,7 +460,7 @@ static void __eoi_IO_APIC_irq(unsigned int irq)
pin = entry->pin;
if (pin == -1)
break;
- io_apic_eoi(entry->apic, vector);
+ __io_apic_eoi(entry->apic, vector, pin);
if (!entry->next)
break;
entry = irq_2_pin + entry->next;
@@ -1705,7 +1811,7 @@ static void end_level_ioapic_irq (unsigned int irq, u8 vector)
{
int ioapic;
for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
- io_apic_eoi(ioapic, i);
+ io_apic_eoi_vector(ioapic, i);
}
v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
@@ -2559,3 +2665,4 @@ void __init init_ioapic_mappings(void)
if (nr_irqs > MAX_NR_IRQS)
nr_irqs = MAX_NR_IRQS;
}
+
diff --git a/xen/include/asm-x86/io_apic.h b/xen/include/asm-x86/io_apic.h
index fcbb557325..f1703abaa5 100644
--- a/xen/include/asm-x86/io_apic.h
+++ b/xen/include/asm-x86/io_apic.h
@@ -157,11 +157,6 @@ static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned i
__io_apic_write(apic, reg, value);
}
-static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
-{
- *(IO_APIC_BASE(apic)+16) = vector;
-}
-
/*
* Re-write a value: to be used for read-modify-write
* cycles where the read already set up the index register.