xen: arm: introduce Cortex-A7 support

Introduce Cortex-A7 with a scalable proc_info_list which including cpu id
and cpu initialize function.
In head.S, search cpu specific MIDR in procinfo and call such initialize
function. Currently, support Cortex-A7 and Cortex-A15.

Signed-off-by: Bamvor Jian Zhang <bjzhang@suse.com>
Acked-by: Tim Deegan <tim@xen.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>

10 files changed, 128 insertions, 34 deletions

diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile
index b903803a58..18522dca20 100644
--- a/xen/arch/arm/arm32/Makefile
+++ b/xen/arch/arm/arm32/Makefile
@@ -2,7 +2,7 @@ subdir-y += lib
 
 obj-y += entry.o
 obj-y += mode_switch.o
-obj-y += proc-ca15.o
+obj-y += proc-v7.o
 
 obj-y += traps.o
 obj-y += domain.o
diff --git a/xen/arch/arm/arm32/asm-offsets.c b/xen/arch/arm/arm32/asm-offsets.c
index 776c974bff..263fff3c57 100644
--- a/xen/arch/arm/arm32/asm-offsets.c
+++ b/xen/arch/arm/arm32/asm-offsets.c
@@ -11,6 +11,7 @@
 #include <xen/bitops.h>
 #include <public/xen.h>
 #include <asm/current.h>
+#include <asm/procinfo.h>
 
 #define DEFINE(_sym, _val) \
     __asm__ __volatile__ ( "\n->" #_sym " %0 " #_val : : "i" (_val) )
@@ -62,6 +63,12 @@ void __dummy__(void)
    DEFINE(CPUINFO_sizeof, sizeof(struct cpu_info));
 
    OFFSET(VCPU_arch_saved_context, struct vcpu, arch.saved_context);
+
+   BLANK();
+   DEFINE(PROCINFO_sizeof, sizeof(struct proc_info_list));
+   OFFSET(PROCINFO_cpu_val, struct proc_info_list, cpu_val);
+   OFFSET(PROCINFO_cpu_mask, struct proc_info_list, cpu_mask);
+   OFFSET(PROCINFO_cpu_init, struct proc_info_list, cpu_init);
 }
 
 /*
diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index 0588d54709..b8334e2d74 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -20,6 +20,7 @@
 #include <asm/config.h>
 #include <asm/page.h>
 #include <asm/processor-ca15.h>
+#include <asm/processor-ca7.h>
 #include <asm/asm_defns.h>
 
 #define ZIMAGE_MAGIC_NUMBER 0x016f2818
@@ -185,18 +186,36 @@ hyp:
         blo   1b
 
 skip_bss:
-
         PRINT("- Setting up control registers -\r\n")
 
-        /* Read CPU ID */
-        mrc   CP32(r0, MIDR)
-        ldr   r1, =(MIDR_MASK)
-        and   r0, r0, r1
-        /* Is this a Cortex A15? */
-        ldr   r1, =(CORTEX_A15_ID)
-        teq   r0, r1
-        bleq  cortex_a15_init
+        /* Get processor specific proc info into r1 */
+        mrc   CP32(r0, MIDR)                /* r0 := our cpu id */
+        ldr   r1, = __proc_info_start
+        add   r1, r1, r10                   /* r1 := paddr of table (start) */
+        ldr   r2, = __proc_info_end
+        add   r2, r2, r10                   /* r2 := paddr of table (end) */
+1:      ldr   r3, [r1, #PROCINFO_cpu_mask]
+        and   r4, r0, r3                    /* r4 := our cpu id with mask */
+        ldr   r3, [r1, #PROCINFO_cpu_val]   /* r3 := cpu val in current proc info */
+        teq   r4, r3
+        beq   2f                            /* Match => exit, or try next proc info */
+        add   r1, r1, #PROCINFO_sizeof
+        cmp   r1, r2
+        blo   1b
+        mov   r4, r0
+        PRINT("- Missing processor info: ")
+        mov   r0, r4
+        bl    putn
+        PRINT(" -\r\n")
+        b     fail
+
+2:
+        /* Jump to cpu_init */
+        ldr   r1, [r1, #PROCINFO_cpu_init]  /* r1 := vaddr(init func) */
+        adr   lr, cpu_init_done             /* Save return address */
+        add   pc, r1, r10                   /* Call paddr(init func) */
 
+cpu_init_done:
         /* Set up memory attribute type tables */
         ldr   r0, =MAIR0VAL
         ldr   r1, =MAIR1VAL
diff --git a/xen/arch/arm/arm32/proc-v7.S b/xen/arch/arm/arm32/proc-v7.S
new file mode 100644
index 0000000000..0ab3845a73
--- /dev/null
+++ b/xen/arch/arm/arm32/proc-v7.S
@@ -0,0 +1,52 @@
+/*
+ * xen/arch/arm/proc-v7.S
+ *
+ * rename from xen/arch/arm/proc-ca15.S
+ * arm v7 specific initializations
+ *
+ * Copyright (c) 2011 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/asm_defns.h>
+#include <asm/arm32/processor.h>
+
+.globl v7_init
+v7_init:
+        /* Set up the SMP bit in ACTLR */
+        mrc   CP32(r0, ACTLR)
+        orr   r0, r0, #(ACTLR_V7_SMP) /* enable SMP bit */
+        mcr   CP32(r0, ACTLR)
+        mov   pc, lr
+
+        .section ".init.proc.info", #alloc, #execinstr
+        .type __v7_ca15mp_proc_info, #object
+__v7_ca15mp_proc_info:
+        .long 0x410FC0F0             /* Cortex-A15 */
+        .long 0xFF0FFFF0             /* Mask */
+        .long v7_init
+        .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
+
+        .section ".init.proc.info", #alloc, #execinstr
+        .type __v7_ca7mp_proc_info, #object
+__v7_ca7mp_proc_info:
+        .long 0x410FC070             /* Cortex-A7 */
+        .long 0xFF0FFFF0             /* Mask */
+        .long v7_init
+        .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
+
+/*
+ * Local variables:
+ * mode: ASM
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S
index 3b60668178..e8b4f47f7b 100644
--- a/xen/arch/arm/xen.lds.S
+++ b/xen/arch/arm/xen.lds.S
@@ -116,6 +116,11 @@ SECTIONS
        *(.init.setup)
        __setup_end = .;
   } :text
+  .init.proc.info : {
+       __proc_info_start = .;
+       *(.init.proc.info)
+       __proc_info_end = .;
+  } :text
   .initcall.init : {
        __initcall_start = .;
        *(.initcallpresmp.init)
diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h
index d26fc85645..b26625291d 100644
--- a/xen/include/asm-arm/arm32/processor.h
+++ b/xen/include/asm-arm/arm32/processor.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ARM_ARM32_PROCESSOR_H
 #define __ASM_ARM_ARM32_PROCESSOR_H
 
+#define ACTLR_V7_SMP    (1<<6)
+
 #ifndef __ASSEMBLY__
 /* On stack VCPU state */
 struct cpu_user_regs
diff --git a/xen/include/asm-arm/processor-ca15.h b/xen/include/asm-arm/processor-ca15.h
index 06cdbdd214..f65f40a32c 100644
--- a/xen/include/asm-arm/processor-ca15.h
+++ b/xen/include/asm-arm/processor-ca15.h
@@ -1,9 +1,6 @@
 #ifndef __ASM_ARM_PROCESSOR_CA15_H
 #define __ASM_ARM_PROCESSOR_CA15_H
 
-
-#define CORTEX_A15_ID     (0x410FC0F0)
-
 /* ACTLR Auxiliary Control Register, Cortex A15 */
 #define ACTLR_CA15_SNOOP_DELAYED      (1<<31)
 #define ACTLR_CA15_MAIN_CLOCK         (1<<30)
diff --git a/xen/include/asm-arm/processor-ca7.h b/xen/include/asm-arm/processor-ca7.h
new file mode 100644
index 0000000000..5048a95ff4
--- /dev/null
+++ b/xen/include/asm-arm/processor-ca7.h
@@ -0,0 +1,20 @@
+#ifndef __ASM_ARM_PROCESSOR_CA7_H
+#define __ASM_ARM_PROCESSOR_CA7_H
+
+/* ACTLR Auxiliary Control Register, Cortex A7 */
+#define ACTLR_CA7_DDI                 (1<<28)
+#define ACTLR_CA7_DDVM                (1<<15)
+#define ACTLR_CA7_L1RADIS             (1<<12)
+#define ACTLR_CA7_L2RADIS             (1<<11)
+#define ACTLR_CA7_DODMBS              (1<<10)
+#define ACTLR_CA7_SMP                 (1<<6)
+
+#endif /* __ASM_ARM_PROCESSOR_CA7_H */
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 1c9d7932d9..263bd0328d 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -3,9 +3,6 @@
 
 #include <asm/cpregs.h>
 
-/* MIDR Main ID Register */
-#define MIDR_MASK    0xff0ffff0
-
 /* TTBCR Translation Table Base Control Register */
 #define TTBCR_EAE    0x80000000
 #define TTBCR_N_MASK 0x07
diff --git a/xen/arch/arm/arm32/proc-ca15.S b/xen/include/asm-arm/procinfo.h
index dcdd42e09e..9d3feb7d0a 100644
--- a/xen/arch/arm/arm32/proc-ca15.S
+++ b/xen/include/asm-arm/procinfo.h
@@ -1,9 +1,11 @@
 /*
- * xen/arch/arm/proc-ca15.S
+ * include/asm-arm/procinfo.h
  *
- * Cortex A15 specific initializations
+ * Bamvor Jian Zhang <bjzhang@suse.com>
+ * Copyright (c) 2013 SUSE
  *
- * Copyright (c) 2011 Citrix Systems.
+ * base on linux/arch/arm/include/asm/procinfo.h
+ * Copyright (C) 1996-1999 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,20 +18,13 @@
  * GNU General Public License for more details.
  */
 
-#include <asm/asm_defns.h>
-#include <asm/processor-ca15.h>
+#ifndef __ASM_ARM_PROCINFO_H
+#define __ASM_ARM_PROCINFO_H
 
-.globl cortex_a15_init
-cortex_a15_init:
-        /* Set up the SMP bit in ACTLR */
-        mrc   CP32(r0, ACTLR)
-        orr   r0, r0, #(ACTLR_CA15_SMP) /* enable SMP bit */
-        mcr   CP32(r0, ACTLR)
-        mov   pc, lr
+struct proc_info_list {
+	unsigned int		cpu_val;
+	unsigned int		cpu_mask;
+    void                (*cpu_init)(void);
+};
 
-/*
- * Local variables:
- * mode: ASM
- * indent-tabs-mode: nil
- * End:
- */
+#endif