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| author | Jan Beulich <jbeulich@suse.com> | 2013-08-26 12:46:54 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2013-08-26 12:46:54 +0200 |
| commit | 1a6662a795a7205c8b30eb18d4477305adb171bb (patch) | |
| tree | 61436c18dd43957c8c029f66a8255745f64a2c6a | |
| parent | fa20320edac4666c5214892db5cf216738ac02da (diff) | |
| download | xen-1a6662a795a7205c8b30eb18d4477305adb171bb.tar.gz xen-1a6662a795a7205c8b30eb18d4477305adb171bb.tar.bz2 xen-1a6662a795a7205c8b30eb18d4477305adb171bb.zip | |
x86: correct public header's documentation of PAT MSR settings
The first (PAT6) column was wrong across the board, and the column for
PAT7 was missing altogether.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
master commit: 3829655bd3ad2b1150bd94955fc6988dec6b98f2
master date: 2013-08-23 09:23:24 +0200
| -rw-r--r-- | xen/include/public/xen.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index 3cab74f18e..fe179b9ca2 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -277,15 +277,15 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t); * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of * pages instead of using MTRRs. * - * The PAT MSR is as follow (it is a 64-bit value, each entry is 8 bits): - * PAT4 PAT0 - * +---+----+----+----+-----+----+----+ - * WC | WC | WB | UC | UC- | WC | WB | <= Linux - * +---+----+----+----+-----+----+----+ - * WC | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) - * +---+----+----+----+-----+----+----+ - * WC | WP | WC | UC | UC- | WT | WB | <= Xen - * +---+----+----+----+-----+----+----+ + * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): + * PAT4 PAT0 + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux + * +-----+-----+----+----+----+-----+----+----+ + * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) + * +-----+-----+----+----+----+-----+----+----+ + * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen + * +-----+-----+----+----+----+-----+----+----+ * * The lookup of this index table translates to looking up * Bit 7, Bit 4, and Bit 3 of val entry: |